HWACCMR0.cpp@ 12227

Last change on this file since 12227 was 12225, checked in by vboxsync, 16 years ago
VMM: X86_DR7_ENABLED_MASK should not include GD, because it isn't a breakpoint and including it will break assumptions in CPUMRecalcHyperDRx (DBGFBpGetDR7 always returns GD).
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 46.0 KB

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1	/* $Id: HWACCMR0.cpp 12225 2008-09-08 12:59:59Z vboxsync $ */
2	/** @file
3	* HWACCM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_vmx.h>
32	#include <VBox/hwacc_svm.h>
33	#include <VBox/pgm.h>
34	#include <VBox/pdm.h>
35	#include <VBox/err.h>
36	#include <VBox/log.h>
37	#include <VBox/selm.h>
38	#include <VBox/iom.h>
39	#include <iprt/param.h>
40	#include <iprt/assert.h>
41	#include <iprt/asm.h>
42	#include <iprt/string.h>
43	#include <iprt/memobj.h>
44	#include <iprt/cpuset.h>
45	#include "HWVMXR0.h"
46	#include "HWSVMR0.h"
47
48	/*******************************************************************************
49	* Internal Functions *
50	*******************************************************************************/
51	static DECLCALLBACK(void) HWACCMR0EnableCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) HWACCMR0DisableCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static int hwaccmr0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu);
55
56	/*******************************************************************************
57	* Local Variables *
58	*******************************************************************************/
59
60	static struct
61	{
62	HWACCM_CPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
63
64	/** Ring 0 handlers for VT-x and AMD-V. */
65	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PHWACCM_CPUINFO pCpu));
66	DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM));
67	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM));
68	DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, CPUMCTX *pCtx));
69	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, CPUMCTX *pCtx));
70	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
71	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
72	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
73	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
74	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVM pVM));
75
76	struct
77	{
78	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
79	bool fSupported;
80
81	/** Host CR4 value (set by ring-0 VMX init) */
82	uint64_t hostCR4;
83
84	/** VMX MSR values */
85	struct
86	{
87	uint64_t feature_ctrl;
88	uint64_t vmx_basic_info;
89	VMX_CAPABILITY vmx_pin_ctls;
90	VMX_CAPABILITY vmx_proc_ctls;
91	VMX_CAPABILITY vmx_proc_ctls2;
92	VMX_CAPABILITY vmx_exit;
93	VMX_CAPABILITY vmx_entry;
94	uint64_t vmx_misc;
95	uint64_t vmx_cr0_fixed0;
96	uint64_t vmx_cr0_fixed1;
97	uint64_t vmx_cr4_fixed0;
98	uint64_t vmx_cr4_fixed1;
99	uint64_t vmx_vmcs_enum;
100	uint64_t vmx_eptcaps;
101	} msr;
102	/* Last instruction error */
103	uint32_t ulLastInstrError;
104	} vmx;
105	struct
106	{
107	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
108	bool fSupported;
109
110	/** SVM revision. */
111	uint32_t u32Rev;
112
113	/** Maximum ASID allowed. */
114	uint32_t u32MaxASID;
115
116	/** SVM feature bits from cpuid 0x8000000a */
117	uint32_t u32Features;
118	} svm;
119	/** Saved error from detection */
120	int32_t lLastError;
121
122	struct
123	{
124	uint32_t u32AMDFeatureECX;
125	uint32_t u32AMDFeatureEDX;
126	} cpuid;
127
128	HWACCMSTATE enmHwAccmState;
129	} HWACCMR0Globals;
130
131
132
133	/**
134	* Does global Ring-0 HWACCM initialization.
135	*
136	* @returns VBox status code.
137	*/
138	HWACCMR0DECL(int) HWACCMR0Init()
139	{
140	int rc;
141
142	memset(&HWACCMR0Globals, 0, sizeof(HWACCMR0Globals));
143	HWACCMR0Globals.enmHwAccmState = HWACCMSTATE_UNINITIALIZED;
144	for (unsigned i = 0; i < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); i++)
145	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
146
147	/* Fill in all callbacks with placeholders. */
148	HWACCMR0Globals.pfnEnterSession = HWACCMR0DummyEnter;
149	HWACCMR0Globals.pfnLeaveSession = HWACCMR0DummyLeave;
150	HWACCMR0Globals.pfnSaveHostState = HWACCMR0DummySaveHostState;
151	HWACCMR0Globals.pfnLoadGuestState = HWACCMR0DummyLoadGuestState;
152	HWACCMR0Globals.pfnRunGuestCode = HWACCMR0DummyRunGuestCode;
153	HWACCMR0Globals.pfnEnableCpu = HWACCMR0DummyEnableCpu;
154	HWACCMR0Globals.pfnDisableCpu = HWACCMR0DummyDisableCpu;
155	HWACCMR0Globals.pfnInitVM = HWACCMR0DummyInitVM;
156	HWACCMR0Globals.pfnTermVM = HWACCMR0DummyTermVM;
157	HWACCMR0Globals.pfnSetupVM = HWACCMR0DummySetupVM;
158
159	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL /* paranoia */
160
161	/*
162	* Check for VT-x and AMD-V capabilities
163	*/
164	if (ASMHasCpuId())
165	{
166	uint32_t u32FeaturesECX;
167	uint32_t u32Dummy;
168	uint32_t u32FeaturesEDX;
169	uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
170
171	ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
172	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
173	/* Query AMD features. */
174	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy, &HWACCMR0Globals.cpuid.u32AMDFeatureECX, &HWACCMR0Globals.cpuid.u32AMDFeatureEDX);
175
176	if ( u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
177	&& u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
178	&& u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX
179	)
180	{
181	/*
182	* Read all VMX MSRs if VMX is available. (same goes for RDMSR/WRMSR)
183	* We also assume all VMX-enabled CPUs support fxsave/fxrstor.
184	*/
185	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
186	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
187	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
188	)
189	{
190	int aRc[RTCPUSET_MAX_CPUS];
191	RTCPUID idCpu = 0;
192
193	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
194
195	/* We need to check if VT-x has been properly initialized on all CPUs. Some BIOSes do a lousy job. */
196	memset(aRc, 0, sizeof(aRc));
197	HWACCMR0Globals.lLastError = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
198
199	/* Check the return code of all invocations. */
200	if (VBOX_SUCCESS(HWACCMR0Globals.lLastError))
201	HWACCMR0Globals.lLastError = hwaccmr0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
202
203	if (VBOX_SUCCESS(HWACCMR0Globals.lLastError))
204	{
205	/* Reread in case we've changed it. */
206	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
207
208	if ( (HWACCMR0Globals.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
209	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
210	{
211	RTR0MEMOBJ pScatchMemObj;
212	void *pvScatchPage;
213	RTHCPHYS pScatchPagePhys;
214
215	HWACCMR0Globals.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
216	HWACCMR0Globals.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
217	HWACCMR0Globals.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
218	HWACCMR0Globals.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
219	HWACCMR0Globals.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
220	HWACCMR0Globals.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
221	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
222	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
223	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
224	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
225	HWACCMR0Globals.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
226
227	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
228	{
229	HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
230	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT\|VMX_VMCS_CTRL_PROC_EXEC2_VPID))
231	HWACCMR0Globals.vmx.msr.vmx_eptcaps = ASMRdMsr(MSR_IA32_VMX_EPT_CAPS);
232	}
233
234	HWACCMR0Globals.vmx.hostCR4 = ASMGetCR4();
235
236	rc = RTR0MemObjAllocCont(&pScatchMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
237	if (RT_FAILURE(rc))
238	return rc;
239
240	pvScatchPage = RTR0MemObjAddress(pScatchMemObj);
241	pScatchPagePhys = RTR0MemObjGetPagePhysAddr(pScatchMemObj, 0);
242	memset(pvScatchPage, 0, PAGE_SIZE);
243
244	/* Set revision dword at the beginning of the structure. */
245	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(HWACCMR0Globals.vmx.msr.vmx_basic_info);
246
247	/* Make sure we don't get rescheduled to another cpu during this probe. */
248	RTCCUINTREG fFlags = ASMIntDisableFlags();
249
250	/*
251	* Check CR4.VMXE
252	*/
253	if (!(HWACCMR0Globals.vmx.hostCR4 & X86_CR4_VMXE))
254	{
255	/* In theory this bit could be cleared behind our back. Which would cause #UD faults when we
256	* try to execute the VMX instructions...
257	*/
258	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4 \| X86_CR4_VMXE);
259	}
260
261	/* Enter VMX Root Mode */
262	rc = VMXEnable(pScatchPagePhys);
263	if (VBOX_FAILURE(rc))
264	{
265	/* KVM leaves the CPU in VMX root mode. Not only is this not allowed, it will crash the host when we enter raw mode, because
266	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify this bit)
267	* (b) turning off paging causes a #GP (unavoidable when switching from long to 32 bits mode or 32 bits to PAE)
268	*
269	* They should fix their code, but until they do we simply refuse to run.
270	*/
271	HWACCMR0Globals.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
272	}
273	else
274	{
275	HWACCMR0Globals.vmx.fSupported = true;
276	VMXDisable();
277	}
278
279	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it wasn't so before (some software could incorrectly think it's in VMX mode) */
280	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4);
281	ASMSetFlags(fFlags);
282
283	RTR0MemObjFree(pScatchMemObj, false);
284	if (VBOX_FAILURE(HWACCMR0Globals.lLastError))
285	return HWACCMR0Globals.lLastError;
286	}
287	else
288	{
289	AssertFailed(); /* can't hit this case anymore */
290	HWACCMR0Globals.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
291	}
292	}
293	#ifdef LOG_ENABLED
294	else
295	SUPR0Printf("HWACCMR0InitCPU failed with rc=%d\n", HWACCMR0Globals.lLastError);
296	#endif
297	}
298	else
299	HWACCMR0Globals.lLastError = VERR_VMX_NO_VMX;
300	}
301	else
302	if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
303	&& u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
304	&& u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX
305	)
306	{
307	/*
308	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
309	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
310	*/
311	if ( (HWACCMR0Globals.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
312	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
313	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
314	)
315	{
316	int aRc[RTCPUSET_MAX_CPUS];
317	RTCPUID idCpu = 0;
318
319	/* We need to check if AMD-V has been properly initialized on all CPUs. Some BIOSes might do a poor job. */
320	memset(aRc, 0, sizeof(aRc));
321	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
322	AssertRC(rc);
323
324	/* Check the return code of all invocations. */
325	if (VBOX_SUCCESS(rc))
326	rc = hwaccmr0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
327
328	AssertMsg(VBOX_SUCCESS(rc), ("HWACCMR0InitCPU failed for cpu %d with rc=%d\n", idCpu, rc));
329
330	if (VBOX_SUCCESS(rc))
331	{
332	/* Query AMD features. */
333	ASMCpuId(0x8000000A, &HWACCMR0Globals.svm.u32Rev, &HWACCMR0Globals.svm.u32MaxASID, &u32Dummy, &HWACCMR0Globals.svm.u32Features);
334
335	HWACCMR0Globals.svm.fSupported = true;
336	}
337	else
338	HWACCMR0Globals.lLastError = rc;
339	}
340	else
341	HWACCMR0Globals.lLastError = VERR_SVM_NO_SVM;
342	}
343	else
344	HWACCMR0Globals.lLastError = VERR_HWACCM_UNKNOWN_CPU;
345	}
346	else
347	HWACCMR0Globals.lLastError = VERR_HWACCM_NO_CPUID;
348
349	#endif /* !VBOX_WITH_HYBIRD_32BIT_KERNEL */
350
351	if (HWACCMR0Globals.vmx.fSupported)
352	{
353	HWACCMR0Globals.pfnEnterSession = VMXR0Enter;
354	HWACCMR0Globals.pfnLeaveSession = VMXR0Leave;
355	HWACCMR0Globals.pfnSaveHostState = VMXR0SaveHostState;
356	HWACCMR0Globals.pfnLoadGuestState = VMXR0LoadGuestState;
357	HWACCMR0Globals.pfnRunGuestCode = VMXR0RunGuestCode;
358	HWACCMR0Globals.pfnEnableCpu = VMXR0EnableCpu;
359	HWACCMR0Globals.pfnDisableCpu = VMXR0DisableCpu;
360	HWACCMR0Globals.pfnInitVM = VMXR0InitVM;
361	HWACCMR0Globals.pfnTermVM = VMXR0TermVM;
362	HWACCMR0Globals.pfnSetupVM = VMXR0SetupVM;
363	}
364	else
365	if (HWACCMR0Globals.svm.fSupported)
366	{
367	HWACCMR0Globals.pfnEnterSession = SVMR0Enter;
368	HWACCMR0Globals.pfnLeaveSession = SVMR0Leave;
369	HWACCMR0Globals.pfnSaveHostState = SVMR0SaveHostState;
370	HWACCMR0Globals.pfnLoadGuestState = SVMR0LoadGuestState;
371	HWACCMR0Globals.pfnRunGuestCode = SVMR0RunGuestCode;
372	HWACCMR0Globals.pfnEnableCpu = SVMR0EnableCpu;
373	HWACCMR0Globals.pfnDisableCpu = SVMR0DisableCpu;
374	HWACCMR0Globals.pfnInitVM = SVMR0InitVM;
375	HWACCMR0Globals.pfnTermVM = SVMR0TermVM;
376	HWACCMR0Globals.pfnSetupVM = SVMR0SetupVM;
377	}
378
379	return VINF_SUCCESS;
380	}
381
382
383	/**
384	* Checks the error code array filled in for each cpu in the system.
385	*
386	* @returns VBox status code.
387	* @param paRc Error code array
388	* @param cErrorCodes Array size
389	* @param pidCpu Value of the first cpu that set an error (out)
390	*/
391	static int hwaccmr0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu)
392	{
393	int rc = VINF_SUCCESS;
394
395	Assert(cErrorCodes == RTCPUSET_MAX_CPUS);
396
397	for (unsigned i=0;i<cErrorCodes;i++)
398	{
399	if (RTMpIsCpuOnline(i))
400	{
401	if (VBOX_FAILURE(paRc[i]))
402	{
403	rc = paRc[i];
404	*pidCpu = i;
405	break;
406	}
407	}
408	}
409	return rc;
410	}
411
412	/**
413	* Does global Ring-0 HWACCM termination.
414	*
415	* @returns VBox status code.
416	*/
417	HWACCMR0DECL(int) HWACCMR0Term()
418	{
419	int aRc[RTCPUSET_MAX_CPUS];
420
421	memset(aRc, 0, sizeof(aRc));
422	int rc = RTMpOnAll(HWACCMR0DisableCPU, aRc, NULL);
423	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
424
425	/* Free the per-cpu pages used for VT-x and AMD-V */
426	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
427	{
428	AssertMsg(VBOX_SUCCESS(aRc[i]), ("HWACCMR0DisableCPU failed for cpu %d with rc=%d\n", i, aRc[i]));
429	if (HWACCMR0Globals.aCpuInfo[i].pMemObj != NIL_RTR0MEMOBJ)
430	{
431	RTR0MemObjFree(HWACCMR0Globals.aCpuInfo[i].pMemObj, false);
432	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
433	}
434	}
435	return rc;
436	}
437
438
439	/**
440	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
441	* is to be called on the target cpus.
442	*
443	* @param idCpu The identifier for the CPU the function is called on.
444	* @param pvUser1 The 1st user argument.
445	* @param pvUser2 The 2nd user argument.
446	*/
447	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
448	{
449	unsigned u32VendorEBX = (uintptr_t)pvUser1;
450	int paRc = (int )pvUser2;
451	uint64_t val;
452
453	#ifdef LOG_ENABLED
454	SUPR0Printf("HWACCMR0InitCPU cpu %d\n", idCpu);
455	#endif
456	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
457
458	if (u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX)
459	{
460	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
461
462	/*
463	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
464	* Once the lock bit is set, this MSR can no longer be modified.
465	*/
466	if (!(val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK)))
467	{
468	/* MSR is not yet locked; we can change it ourselves here */
469	ASMWrMsr(MSR_IA32_FEATURE_CONTROL, HWACCMR0Globals.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
470	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
471	}
472	if ( (val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
473	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
474	paRc[idCpu] = VINF_SUCCESS;
475	else
476	paRc[idCpu] = VERR_VMX_MSR_LOCKED_OR_DISABLED;
477	}
478	else
479	if (u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX)
480	{
481	/* Check if SVM is disabled */
482	val = ASMRdMsr(MSR_K8_VM_CR);
483	if (!(val & MSR_K8_VM_CR_SVM_DISABLE))
484	{
485	/* Turn on SVM in the EFER MSR. */
486	val = ASMRdMsr(MSR_K6_EFER);
487	if (!(val & MSR_K6_EFER_SVME))
488	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
489
490	/* Paranoia. */
491	val = ASMRdMsr(MSR_K6_EFER);
492	if (val & MSR_K6_EFER_SVME)
493	paRc[idCpu] = VINF_SUCCESS;
494	else
495	paRc[idCpu] = VERR_SVM_ILLEGAL_EFER_MSR;
496	}
497	else
498	paRc[idCpu] = HWACCMR0Globals.lLastError = VERR_SVM_DISABLED;
499	}
500	else
501	AssertFailed(); /* can't happen */
502	return;
503	}
504
505
506	/**
507	* Sets up HWACCM on all cpus.
508	*
509	* @returns VBox status code.
510	* @param pVM The VM to operate on.
511	* @param enmNewHwAccmState New hwaccm state
512	*
513	*/
514	HWACCMR0DECL(int) HWACCMR0EnableAllCpus(PVM pVM, HWACCMSTATE enmNewHwAccmState)
515	{
516	Assert(sizeof(HWACCMR0Globals.enmHwAccmState) == sizeof(uint32_t));
517	if (ASMAtomicCmpXchgU32((volatile uint32_t *)&HWACCMR0Globals.enmHwAccmState, enmNewHwAccmState, HWACCMSTATE_UNINITIALIZED))
518	{
519	int aRc[RTCPUSET_MAX_CPUS];
520	RTCPUID idCpu = 0;
521
522	/* Don't setup hwaccm as that might not work (vt-x & 64 bits raw mode) */
523	if (enmNewHwAccmState == HWACCMSTATE_DISABLED)
524	return VINF_SUCCESS;
525
526	memset(aRc, 0, sizeof(aRc));
527
528	/* Allocate one page per cpu for the global vt-x and amd-v pages */
529	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
530	{
531	Assert(!HWACCMR0Globals.aCpuInfo[i].pMemObj);
532
533	/** @todo this is rather dangerous if cpus can be taken offline; we don't care for now */
534	if (RTMpIsCpuOnline(i))
535	{
536	int rc = RTR0MemObjAllocCont(&HWACCMR0Globals.aCpuInfo[i].pMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
537	AssertRC(rc);
538	if (RT_FAILURE(rc))
539	return rc;
540
541	void *pvR0 = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[i].pMemObj);
542	Assert(pvR0);
543	ASMMemZeroPage(pvR0);
544
545	#ifdef LOG_ENABLED
546	SUPR0Printf("address %x phys %x\n", pvR0, (uint32_t)RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[i].pMemObj, 0));
547	#endif
548	}
549	}
550	/* First time, so initialize each cpu/core */
551	int rc = RTMpOnAll(HWACCMR0EnableCPU, (void *)pVM, aRc);
552
553	/* Check the return code of all invocations. */
554	if (VBOX_SUCCESS(rc))
555	rc = hwaccmr0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
556
557	AssertMsg(VBOX_SUCCESS(rc), ("HWACCMR0EnableAllCpus failed for cpu %d with rc=%d\n", idCpu, rc));
558	return rc;
559	}
560
561	if (HWACCMR0Globals.enmHwAccmState == enmNewHwAccmState)
562	return VINF_SUCCESS;
563
564	/* Request to change the mode is not allowed */
565	return VERR_ACCESS_DENIED;
566	}
567
568	/**
569	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
570	* is to be called on the target cpus.
571	*
572	* @param idCpu The identifier for the CPU the function is called on.
573	* @param pvUser1 The 1st user argument.
574	* @param pvUser2 The 2nd user argument.
575	*/
576	static DECLCALLBACK(void) HWACCMR0EnableCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
577	{
578	PVM pVM = (PVM)pvUser1;
579	int paRc = (int )pvUser2;
580	void *pvPageCpu;
581	RTHCPHYS pPageCpuPhys;
582	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
583
584	Assert(pVM);
585	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
586	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
587
588	pCpu->idCpu = idCpu;
589
590	/* Make sure we start with a clean TLB. */
591	pCpu->fFlushTLB = true;
592
593	/* Should never happen */
594	if (!HWACCMR0Globals.aCpuInfo[idCpu].pMemObj)
595	{
596	AssertFailed();
597	paRc[idCpu] = VERR_INTERNAL_ERROR;
598	return;
599	}
600
601	pvPageCpu = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[idCpu].pMemObj);
602	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[idCpu].pMemObj, 0);
603
604	paRc[idCpu] = HWACCMR0Globals.pfnEnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
605	AssertRC(paRc[idCpu]);
606	if (VBOX_SUCCESS(paRc[idCpu]))
607	HWACCMR0Globals.aCpuInfo[idCpu].fConfigured = true;
608
609	return;
610	}
611
612	/**
613	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
614	* is to be called on the target cpus.
615	*
616	* @param idCpu The identifier for the CPU the function is called on.
617	* @param pvUser1 The 1st user argument.
618	* @param pvUser2 The 2nd user argument.
619	*/
620	static DECLCALLBACK(void) HWACCMR0DisableCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
621	{
622	void *pvPageCpu;
623	RTHCPHYS pPageCpuPhys;
624	int paRc = (int )pvUser1;
625
626	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
627	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
628
629	if (!HWACCMR0Globals.aCpuInfo[idCpu].pMemObj)
630	return;
631
632	pvPageCpu = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[idCpu].pMemObj);
633	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[idCpu].pMemObj, 0);
634
635	paRc[idCpu] = HWACCMR0Globals.pfnDisableCpu(&HWACCMR0Globals.aCpuInfo[idCpu], pvPageCpu, pPageCpuPhys);
636	AssertRC(paRc[idCpu]);
637	HWACCMR0Globals.aCpuInfo[idCpu].fConfigured = false;
638	return;
639	}
640
641
642	/**
643	* Does Ring-0 per VM HWACCM initialization.
644	*
645	* This is mainly to check that the Host CPU mode is compatible
646	* with VMX.
647	*
648	* @returns VBox status code.
649	* @param pVM The VM to operate on.
650	*/
651	HWACCMR0DECL(int) HWACCMR0InitVM(PVM pVM)
652	{
653	AssertReturn(pVM, VERR_INVALID_PARAMETER);
654
655	#ifdef LOG_ENABLED
656	SUPR0Printf("HWACCMR0InitVM: %p\n", pVM);
657	#endif
658
659	pVM->hwaccm.s.vmx.fSupported = HWACCMR0Globals.vmx.fSupported;
660	pVM->hwaccm.s.svm.fSupported = HWACCMR0Globals.svm.fSupported;
661
662	pVM->hwaccm.s.vmx.msr.feature_ctrl = HWACCMR0Globals.vmx.msr.feature_ctrl;
663	pVM->hwaccm.s.vmx.hostCR4 = HWACCMR0Globals.vmx.hostCR4;
664	pVM->hwaccm.s.vmx.msr.vmx_basic_info = HWACCMR0Globals.vmx.msr.vmx_basic_info;
665	pVM->hwaccm.s.vmx.msr.vmx_pin_ctls = HWACCMR0Globals.vmx.msr.vmx_pin_ctls;
666	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls = HWACCMR0Globals.vmx.msr.vmx_proc_ctls;
667	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2 = HWACCMR0Globals.vmx.msr.vmx_proc_ctls2;
668	pVM->hwaccm.s.vmx.msr.vmx_exit = HWACCMR0Globals.vmx.msr.vmx_exit;
669	pVM->hwaccm.s.vmx.msr.vmx_entry = HWACCMR0Globals.vmx.msr.vmx_entry;
670	pVM->hwaccm.s.vmx.msr.vmx_misc = HWACCMR0Globals.vmx.msr.vmx_misc;
671	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0;
672	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1;
673	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0;
674	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1;
675	pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum = HWACCMR0Globals.vmx.msr.vmx_vmcs_enum;
676	pVM->hwaccm.s.vmx.msr.vmx_eptcaps = HWACCMR0Globals.vmx.msr.vmx_eptcaps;
677	pVM->hwaccm.s.svm.u32Rev = HWACCMR0Globals.svm.u32Rev;
678	pVM->hwaccm.s.svm.u32MaxASID = HWACCMR0Globals.svm.u32MaxASID;
679	pVM->hwaccm.s.svm.u32Features = HWACCMR0Globals.svm.u32Features;
680	pVM->hwaccm.s.cpuid.u32AMDFeatureECX = HWACCMR0Globals.cpuid.u32AMDFeatureECX;
681	pVM->hwaccm.s.cpuid.u32AMDFeatureEDX = HWACCMR0Globals.cpuid.u32AMDFeatureEDX;
682	pVM->hwaccm.s.lLastError = HWACCMR0Globals.lLastError;
683	#ifdef VBOX_STRICT
684	pVM->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
685	#endif
686
687	/* Init a VT-x or AMD-V VM. */
688	return HWACCMR0Globals.pfnInitVM(pVM);
689	}
690
691
692	/**
693	* Does Ring-0 per VM HWACCM termination.
694	*
695	* @returns VBox status code.
696	* @param pVM The VM to operate on.
697	*/
698	HWACCMR0DECL(int) HWACCMR0TermVM(PVM pVM)
699	{
700	AssertReturn(pVM, VERR_INVALID_PARAMETER);
701
702	#ifdef LOG_ENABLED
703	SUPR0Printf("HWACCMR0TermVM: %p\n", pVM);
704	#endif
705
706	/* Terminate a VT-x or AMD-V VM. */
707	return HWACCMR0Globals.pfnTermVM(pVM);
708	}
709
710
711	/**
712	* Sets up a VT-x or AMD-V session
713	*
714	* @returns VBox status code.
715	* @param pVM The VM to operate on.
716	*/
717	HWACCMR0DECL(int) HWACCMR0SetupVM(PVM pVM)
718	{
719	AssertReturn(pVM, VERR_INVALID_PARAMETER);
720
721	#ifdef LOG_ENABLED
722	SUPR0Printf("HWACCMR0SetupVM: %p\n", pVM);
723	#endif
724
725	/* Setup VT-x or AMD-V. */
726	return HWACCMR0Globals.pfnSetupVM(pVM);
727	}
728
729
730	/**
731	* Enters the VT-x or AMD-V session
732	*
733	* @returns VBox status code.
734	* @param pVM The VM to operate on.
735	*/
736	HWACCMR0DECL(int) HWACCMR0Enter(PVM pVM)
737	{
738	CPUMCTX *pCtx;
739	int rc;
740	RTCPUID idCpu = RTMpCpuId();
741
742	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
743	if (VBOX_FAILURE(rc))
744	return rc;
745
746	/* Always load the guest's FPU/XMM state on-demand. */
747	CPUMDeactivateGuestFPUState(pVM);
748
749	#ifdef VBOX_WITH_HWACCM_DEBUG_REGISTER_SUPPORT
750	/*
751	* Check if host debug registers are armed. All context switches set DR7 back to 0x400.
752	*/
753	uint64_t u64DR7 = ASMGetDR7();
754	if (u64DR7 & (X86_DR7_ENABLED_MASK \| X86_DR7_GD))
755	{
756	pVM->hwaccm.s.savedhoststate.dr7 = u64DR7;
757	pVM->hwaccm.s.savedhoststate.fHostDR7Saved = true;
758	}
759	else
760	pVM->hwaccm.s.savedhoststate.fHostDR7Saved = false;
761	#endif
762
763	/* Always reload the host context and the guest's CR0 register. (!!!!) */
764	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0 \| HWACCM_CHANGED_HOST_CONTEXT;
765
766	/* Setup the register and mask according to the current execution mode. */
767	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
768	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFFFFFFFFFF);
769	else
770	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFF);
771
772	rc = HWACCMR0Globals.pfnEnterSession(pVM, &HWACCMR0Globals.aCpuInfo[idCpu]);
773	AssertRC(rc);
774	/* We must save the host context here (VT-x) as we might be rescheduled on a different cpu after a long jump back to ring 3. */
775	rc \|= HWACCMR0Globals.pfnSaveHostState(pVM);
776	AssertRC(rc);
777	rc \|= HWACCMR0Globals.pfnLoadGuestState(pVM, pCtx);
778	AssertRC(rc);
779
780	#ifdef VBOX_STRICT
781	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
782	if (RT_SUCCESS(rc))
783	{
784	AssertMsg(pVM->hwaccm.s.idEnteredCpu == NIL_RTCPUID, ("%d", (int)pVM->hwaccm.s.idEnteredCpu));
785	pVM->hwaccm.s.idEnteredCpu = idCpu;
786	}
787	#endif
788	return rc;
789	}
790
791
792	/**
793	* Leaves the VT-x or AMD-V session
794	*
795	* @returns VBox status code.
796	* @param pVM The VM to operate on.
797	*/
798	HWACCMR0DECL(int) HWACCMR0Leave(PVM pVM)
799	{
800	CPUMCTX *pCtx;
801	int rc;
802
803	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
804	if (VBOX_FAILURE(rc))
805	return rc;
806
807	/** @note It's rather tricky with longjmps done by e.g. Log statements or the page fault handler. */
808	/* We must restore the host FPU here to make absolutely sure we don't leave the guest FPU state active
809	* or trash somebody else's FPU state.
810	*/
811	/* Save the guest FPU and XMM state if necessary. */
812	if (CPUMIsGuestFPUStateActive(pVM))
813	{
814	Log2(("CPUMR0SaveGuestFPU\n"));
815	CPUMR0SaveGuestFPU(pVM, pCtx);
816
817	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
818	}
819
820	#ifdef VBOX_WITH_HWACCM_DEBUG_REGISTER_SUPPORT
821	/* Restore the host debug registers. First dr0-3, then dr6 and only then dr7! */
822	if (pVM->hwaccm.s.savedhoststate.fHostDebugRegsSaved)
823	{
824	ASMSetDR0(pVM->hwaccm.s.savedhoststate.dr0);
825	ASMSetDR1(pVM->hwaccm.s.savedhoststate.dr1);
826	ASMSetDR2(pVM->hwaccm.s.savedhoststate.dr2);
827	ASMSetDR3(pVM->hwaccm.s.savedhoststate.dr3);
828	ASMSetDR6(pVM->hwaccm.s.savedhoststate.dr6);
829	pVM->hwaccm.s.savedhoststate.fHostDebugRegsSaved = false;
830	}
831	if (pVM->hwaccm.s.savedhoststate.fHostDR7Saved)
832	{
833	ASMSetDR7(pVM->hwaccm.s.savedhoststate.dr7);
834	pVM->hwaccm.s.savedhoststate.fHostDR7Saved = false;
835	}
836	#endif
837
838	/* Resync the debug register on the next entry. */
839	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_DEBUG;
840	rc = HWACCMR0Globals.pfnLeaveSession(pVM);
841
842	#ifdef VBOX_STRICT
843	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
844	RTCPUID idCpu = RTMpCpuId();
845	AssertMsg(pVM->hwaccm.s.idEnteredCpu == idCpu, ("owner is %d, I'm %d", (int)pVM->hwaccm.s.idEnteredCpu, (int)idCpu));
846	pVM->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
847	#endif
848
849	return rc;
850	}
851
852	/**
853	* Runs guest code in a hardware accelerated VM.
854	*
855	* @returns VBox status code.
856	* @param pVM The VM to operate on.
857	*/
858	HWACCMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM)
859	{
860	CPUMCTX *pCtx;
861	int rc;
862	RTCPUID idCpu = RTMpCpuId(); NOREF(idCpu);
863
864	Assert(!VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL));
865	Assert(HWACCMR0Globals.aCpuInfo[idCpu].fConfigured);
866
867	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
868	if (VBOX_FAILURE(rc))
869	return rc;
870
871	return HWACCMR0Globals.pfnRunGuestCode(pVM, pCtx);
872	}
873
874	/**
875	* Returns the cpu structure for the current cpu.
876	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
877	*
878	* @returns cpu structure pointer
879	* @param pVM The VM to operate on.
880	*/
881	HWACCMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu()
882	{
883	RTCPUID idCpu = RTMpCpuId();
884
885	return &HWACCMR0Globals.aCpuInfo[idCpu];
886	}
887
888	#ifdef VBOX_STRICT
889	#include <iprt/string.h>
890	/**
891	* Dumps a descriptor.
892	*
893	* @param pDesc Descriptor to dump.
894	* @param Sel Selector number.
895	* @param pszMsg Message to prepend the log entry with.
896	*/
897	HWACCMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
898	{
899	/*
900	* Make variable description string.
901	*/
902	static struct
903	{
904	unsigned cch;
905	const char *psz;
906	} const aTypes[32] =
907	{
908	#define STRENTRY(str) { sizeof(str) - 1, str }
909
910	/* system */
911	#if HC_ARCH_BITS == 64
912	STRENTRY("Reserved0 "), /* 0x00 */
913	STRENTRY("Reserved1 "), /* 0x01 */
914	STRENTRY("LDT "), /* 0x02 */
915	STRENTRY("Reserved3 "), /* 0x03 */
916	STRENTRY("Reserved4 "), /* 0x04 */
917	STRENTRY("Reserved5 "), /* 0x05 */
918	STRENTRY("Reserved6 "), /* 0x06 */
919	STRENTRY("Reserved7 "), /* 0x07 */
920	STRENTRY("Reserved8 "), /* 0x08 */
921	STRENTRY("TSS64Avail "), /* 0x09 */
922	STRENTRY("ReservedA "), /* 0x0a */
923	STRENTRY("TSS64Busy "), /* 0x0b */
924	STRENTRY("Call64 "), /* 0x0c */
925	STRENTRY("ReservedD "), /* 0x0d */
926	STRENTRY("Int64 "), /* 0x0e */
927	STRENTRY("Trap64 "), /* 0x0f */
928	#else
929	STRENTRY("Reserved0 "), /* 0x00 */
930	STRENTRY("TSS16Avail "), /* 0x01 */
931	STRENTRY("LDT "), /* 0x02 */
932	STRENTRY("TSS16Busy "), /* 0x03 */
933	STRENTRY("Call16 "), /* 0x04 */
934	STRENTRY("Task "), /* 0x05 */
935	STRENTRY("Int16 "), /* 0x06 */
936	STRENTRY("Trap16 "), /* 0x07 */
937	STRENTRY("Reserved8 "), /* 0x08 */
938	STRENTRY("TSS32Avail "), /* 0x09 */
939	STRENTRY("ReservedA "), /* 0x0a */
940	STRENTRY("TSS32Busy "), /* 0x0b */
941	STRENTRY("Call32 "), /* 0x0c */
942	STRENTRY("ReservedD "), /* 0x0d */
943	STRENTRY("Int32 "), /* 0x0e */
944	STRENTRY("Trap32 "), /* 0x0f */
945	#endif
946	/* non system */
947	STRENTRY("DataRO "), /* 0x10 */
948	STRENTRY("DataRO Accessed "), /* 0x11 */
949	STRENTRY("DataRW "), /* 0x12 */
950	STRENTRY("DataRW Accessed "), /* 0x13 */
951	STRENTRY("DataDownRO "), /* 0x14 */
952	STRENTRY("DataDownRO Accessed "), /* 0x15 */
953	STRENTRY("DataDownRW "), /* 0x16 */
954	STRENTRY("DataDownRW Accessed "), /* 0x17 */
955	STRENTRY("CodeEO "), /* 0x18 */
956	STRENTRY("CodeEO Accessed "), /* 0x19 */
957	STRENTRY("CodeER "), /* 0x1a */
958	STRENTRY("CodeER Accessed "), /* 0x1b */
959	STRENTRY("CodeConfEO "), /* 0x1c */
960	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
961	STRENTRY("CodeConfER "), /* 0x1e */
962	STRENTRY("CodeConfER Accessed ") /* 0x1f */
963	#undef SYSENTRY
964	};
965	#define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
966	char szMsg[128];
967	char *psz = &szMsg[0];
968	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
969	memcpy(psz, aTypes[i].psz, aTypes[i].cch);
970	psz += aTypes[i].cch;
971
972	if (pDesc->Gen.u1Present)
973	ADD_STR(psz, "Present ");
974	else
975	ADD_STR(psz, "Not-Present ");
976	#if HC_ARCH_BITS == 64
977	if (pDesc->Gen.u1Long)
978	ADD_STR(psz, "64-bit ");
979	else
980	ADD_STR(psz, "Comp ");
981	#else
982	if (pDesc->Gen.u1Granularity)
983	ADD_STR(psz, "Page ");
984	if (pDesc->Gen.u1DefBig)
985	ADD_STR(psz, "32-bit ");
986	else
987	ADD_STR(psz, "16-bit ");
988	#endif
989	#undef ADD_STR
990	*psz = '\0';
991
992	/*
993	* Limit and Base and format the output.
994	*/
995	uint32_t u32Limit = X86DESC_LIMIT(*pDesc);
996	if (pDesc->Gen.u1Granularity)
997	u32Limit = u32Limit << PAGE_SHIFT \| PAGE_OFFSET_MASK;
998
999	#if HC_ARCH_BITS == 64
1000	uint64_t u32Base = X86DESC64_BASE(*pDesc);
1001
1002	Log(("%s %04x - %VX64 %VX64 - base=%VX64 limit=%08x dpl=%d %s\n", pszMsg,
1003	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1004	#else
1005	uint32_t u32Base = X86DESC_BASE(*pDesc);
1006
1007	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1008	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1009	#endif
1010	}
1011
1012	/**
1013	* Formats a full register dump.
1014	*
1015	* @param pVM The VM to operate on.
1016	* @param pCtx The context to format.
1017	*/
1018	HWACCMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx)
1019	{
1020	/*
1021	* Format the flags.
1022	*/
1023	static struct
1024	{
1025	const char pszSet; const char pszClear; uint32_t fFlag;
1026	} aFlags[] =
1027	{
1028	{ "vip",NULL, X86_EFL_VIP },
1029	{ "vif",NULL, X86_EFL_VIF },
1030	{ "ac", NULL, X86_EFL_AC },
1031	{ "vm", NULL, X86_EFL_VM },
1032	{ "rf", NULL, X86_EFL_RF },
1033	{ "nt", NULL, X86_EFL_NT },
1034	{ "ov", "nv", X86_EFL_OF },
1035	{ "dn", "up", X86_EFL_DF },
1036	{ "ei", "di", X86_EFL_IF },
1037	{ "tf", NULL, X86_EFL_TF },
1038	{ "nt", "pl", X86_EFL_SF },
1039	{ "nz", "zr", X86_EFL_ZF },
1040	{ "ac", "na", X86_EFL_AF },
1041	{ "po", "pe", X86_EFL_PF },
1042	{ "cy", "nc", X86_EFL_CF },
1043	};
1044	char szEFlags[80];
1045	char *psz = szEFlags;
1046	uint32_t efl = pCtx->eflags.u32;
1047	for (unsigned i = 0; i < RT_ELEMENTS(aFlags); i++)
1048	{
1049	const char *pszAdd = aFlags[i].fFlag & efl ? aFlags[i].pszSet : aFlags[i].pszClear;
1050	if (pszAdd)
1051	{
1052	strcpy(psz, pszAdd);
1053	psz += strlen(pszAdd);
1054	*psz++ = ' ';
1055	}
1056	}
1057	psz[-1] = '\0';
1058
1059
1060	/*
1061	* Format the registers.
1062	*/
1063	if (CPUMIsGuestIn64BitCode(pVM, CPUMCTX2CORE(pCtx)))
1064	{
1065	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1066	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1067	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1068	"r14=%016RX64 r15=%016RX64\n"
1069	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1070	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1071	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1072	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1073	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1074	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1075	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1076	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1077	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1078	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1079	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1080	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1081	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1082	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1083	,
1084	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1085	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1086	pCtx->r14, pCtx->r15,
1087	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1088	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1089	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1090	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1091	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1092	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1093	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1094	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1095	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3,
1096	pCtx->dr4, pCtx->dr5, pCtx->dr6, pCtx->dr7,
1097	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1098	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1099	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1100	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1101	}
1102	else
1103	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1104	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1105	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1106	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1107	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1108	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1109	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1110	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1111	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1112	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1113	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1114	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1115	,
1116	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1117	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1118	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr0, pCtx->dr1,
1119	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr2, pCtx->dr3,
1120	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr4, pCtx->dr5,
1121	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr6, pCtx->dr7,
1122	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0, pCtx->cr2,
1123	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3, pCtx->cr4,
1124	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1125	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1126	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1127	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1128
1129	Log(("FPU:\n"
1130	"FCW=%04x FSW=%04x FTW=%02x\n"
1131	"res1=%02x FOP=%04x FPUIP=%08x CS=%04x Rsvrd1=%04x\n"
1132	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1133	,
1134	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
1135	pCtx->fpu.huh1, pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsvrd1,
1136	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
1137	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
1138
1139
1140	Log(("MSR:\n"
1141	"EFER =%016RX64\n"
1142	"PAT =%016RX64\n"
1143	"STAR =%016RX64\n"
1144	"CSTAR =%016RX64\n"
1145	"LSTAR =%016RX64\n"
1146	"SFMASK =%016RX64\n"
1147	"KERNELGSBASE =%016RX64\n",
1148	pCtx->msrEFER,
1149	pCtx->msrPAT,
1150	pCtx->msrSTAR,
1151	pCtx->msrCSTAR,
1152	pCtx->msrLSTAR,
1153	pCtx->msrSFMASK,
1154	pCtx->msrKERNELGSBASE));
1155
1156	}
1157	#endif
1158
1159	/* Dummy callback handlers. */
1160	HWACCMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PHWACCM_CPUINFO pCpu)
1161	{
1162	return VINF_SUCCESS;
1163	}
1164
1165	HWACCMR0DECL(int) HWACCMR0DummyLeave(PVM pVM)
1166	{
1167	return VINF_SUCCESS;
1168	}
1169
1170	HWACCMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1171	{
1172	return VINF_SUCCESS;
1173	}
1174
1175	HWACCMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1176	{
1177	return VINF_SUCCESS;
1178	}
1179
1180	HWACCMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM)
1181	{
1182	return VINF_SUCCESS;
1183	}
1184
1185	HWACCMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM)
1186	{
1187	return VINF_SUCCESS;
1188	}
1189
1190	HWACCMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM)
1191	{
1192	return VINF_SUCCESS;
1193	}
1194
1195	HWACCMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, CPUMCTX *pCtx)
1196	{
1197	return VINF_SUCCESS;
1198	}
1199
1200	HWACCMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM)
1201	{
1202	return VINF_SUCCESS;
1203	}
1204
1205	HWACCMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, CPUMCTX *pCtx)
1206	{
1207	return VINF_SUCCESS;
1208	}

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp@ 12227

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