HWACCMR0.cpp@ 13263

Last change on this file since 13263 was 13025, checked in by vboxsync, 16 years ago
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1	/* $Id: HWACCMR0.cpp 13025 2008-10-07 07:28:54Z vboxsync $ */
2	/** @file
3	* HWACCM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_vmx.h>
32	#include <VBox/hwacc_svm.h>
33	#include <VBox/pgm.h>
34	#include <VBox/pdm.h>
35	#include <VBox/err.h>
36	#include <VBox/log.h>
37	#include <VBox/selm.h>
38	#include <VBox/iom.h>
39	#include <iprt/param.h>
40	#include <iprt/assert.h>
41	#include <iprt/asm.h>
42	#include <iprt/string.h>
43	#include <iprt/memobj.h>
44	#include <iprt/cpuset.h>
45	#include "HWVMXR0.h"
46	#include "HWSVMR0.h"
47
48	/*******************************************************************************
49	* Internal Functions *
50	*******************************************************************************/
51	static DECLCALLBACK(void) HWACCMR0EnableCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) HWACCMR0DisableCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static int hwaccmR0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu);
55
56	/*******************************************************************************
57	* Global Variables *
58	*******************************************************************************/
59
60	static struct
61	{
62	HWACCM_CPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
63
64	/** Ring 0 handlers for VT-x and AMD-V. */
65	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PHWACCM_CPUINFO pCpu));
66	DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM, CPUMCTX *pCtx));
67	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM));
68	DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, CPUMCTX *pCtx));
69	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, CPUMCTX *pCtx));
70	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
71	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
72	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
73	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
74	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVM pVM));
75
76	/** Maximum ASID allowed. */
77	uint32_t uMaxASID;
78
79	struct
80	{
81	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
82	bool fSupported;
83
84	/** Host CR4 value (set by ring-0 VMX init) */
85	uint64_t hostCR4;
86
87	/** VMX MSR values */
88	struct
89	{
90	uint64_t feature_ctrl;
91	uint64_t vmx_basic_info;
92	VMX_CAPABILITY vmx_pin_ctls;
93	VMX_CAPABILITY vmx_proc_ctls;
94	VMX_CAPABILITY vmx_proc_ctls2;
95	VMX_CAPABILITY vmx_exit;
96	VMX_CAPABILITY vmx_entry;
97	uint64_t vmx_misc;
98	uint64_t vmx_cr0_fixed0;
99	uint64_t vmx_cr0_fixed1;
100	uint64_t vmx_cr4_fixed0;
101	uint64_t vmx_cr4_fixed1;
102	uint64_t vmx_vmcs_enum;
103	uint64_t vmx_eptcaps;
104	} msr;
105	/* Last instruction error */
106	uint32_t ulLastInstrError;
107	} vmx;
108	struct
109	{
110	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
111	bool fSupported;
112
113	/** SVM revision. */
114	uint32_t u32Rev;
115
116	/** SVM feature bits from cpuid 0x8000000a */
117	uint32_t u32Features;
118	} svm;
119	/** Saved error from detection */
120	int32_t lLastError;
121
122	struct
123	{
124	uint32_t u32AMDFeatureECX;
125	uint32_t u32AMDFeatureEDX;
126	} cpuid;
127
128	HWACCMSTATE enmHwAccmState;
129	} HWACCMR0Globals;
130
131
132
133	/**
134	* Does global Ring-0 HWACCM initialization.
135	*
136	* @returns VBox status code.
137	*/
138	VMMR0DECL(int) HWACCMR0Init(void)
139	{
140	int rc;
141
142	memset(&HWACCMR0Globals, 0, sizeof(HWACCMR0Globals));
143	HWACCMR0Globals.enmHwAccmState = HWACCMSTATE_UNINITIALIZED;
144	for (unsigned i = 0; i < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); i++)
145	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
146
147	/* Fill in all callbacks with placeholders. */
148	HWACCMR0Globals.pfnEnterSession = HWACCMR0DummyEnter;
149	HWACCMR0Globals.pfnLeaveSession = HWACCMR0DummyLeave;
150	HWACCMR0Globals.pfnSaveHostState = HWACCMR0DummySaveHostState;
151	HWACCMR0Globals.pfnLoadGuestState = HWACCMR0DummyLoadGuestState;
152	HWACCMR0Globals.pfnRunGuestCode = HWACCMR0DummyRunGuestCode;
153	HWACCMR0Globals.pfnEnableCpu = HWACCMR0DummyEnableCpu;
154	HWACCMR0Globals.pfnDisableCpu = HWACCMR0DummyDisableCpu;
155	HWACCMR0Globals.pfnInitVM = HWACCMR0DummyInitVM;
156	HWACCMR0Globals.pfnTermVM = HWACCMR0DummyTermVM;
157	HWACCMR0Globals.pfnSetupVM = HWACCMR0DummySetupVM;
158
159	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL /* paranoia */
160
161	/*
162	* Check for VT-x and AMD-V capabilities
163	*/
164	if (ASMHasCpuId())
165	{
166	uint32_t u32FeaturesECX;
167	uint32_t u32Dummy;
168	uint32_t u32FeaturesEDX;
169	uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
170
171	ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
172	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
173	/* Query AMD features. */
174	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy, &HWACCMR0Globals.cpuid.u32AMDFeatureECX, &HWACCMR0Globals.cpuid.u32AMDFeatureEDX);
175
176	if ( u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
177	&& u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
178	&& u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX
179	)
180	{
181	/*
182	* Read all VMX MSRs if VMX is available. (same goes for RDMSR/WRMSR)
183	* We also assume all VMX-enabled CPUs support fxsave/fxrstor.
184	*/
185	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
186	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
187	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
188	)
189	{
190	int aRc[RTCPUSET_MAX_CPUS];
191	RTCPUID idCpu = 0;
192
193	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
194
195	/* We need to check if VT-x has been properly initialized on all CPUs. Some BIOSes do a lousy job. */
196	memset(aRc, 0, sizeof(aRc));
197	HWACCMR0Globals.lLastError = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
198
199	/* Check the return code of all invocations. */
200	if (VBOX_SUCCESS(HWACCMR0Globals.lLastError))
201	HWACCMR0Globals.lLastError = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
202
203	if (VBOX_SUCCESS(HWACCMR0Globals.lLastError))
204	{
205	/* Reread in case we've changed it. */
206	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
207
208	if ( (HWACCMR0Globals.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
209	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
210	{
211	RTR0MEMOBJ pScatchMemObj;
212	void *pvScatchPage;
213	RTHCPHYS pScatchPagePhys;
214
215	HWACCMR0Globals.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
216	HWACCMR0Globals.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
217	HWACCMR0Globals.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
218	HWACCMR0Globals.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
219	HWACCMR0Globals.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
220	HWACCMR0Globals.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
221	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
222	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
223	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
224	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
225	HWACCMR0Globals.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
226	/* VPID 16 bits ASID. */
227	HWACCMR0Globals.uMaxASID = 0x10000; /* exclusive */
228
229	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
230	{
231	HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
232	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT\|VMX_VMCS_CTRL_PROC_EXEC2_VPID))
233	HWACCMR0Globals.vmx.msr.vmx_eptcaps = ASMRdMsr(MSR_IA32_VMX_EPT_CAPS);
234	}
235
236	HWACCMR0Globals.vmx.hostCR4 = ASMGetCR4();
237
238	rc = RTR0MemObjAllocCont(&pScatchMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
239	if (RT_FAILURE(rc))
240	return rc;
241
242	pvScatchPage = RTR0MemObjAddress(pScatchMemObj);
243	pScatchPagePhys = RTR0MemObjGetPagePhysAddr(pScatchMemObj, 0);
244	memset(pvScatchPage, 0, PAGE_SIZE);
245
246	/* Set revision dword at the beginning of the structure. */
247	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(HWACCMR0Globals.vmx.msr.vmx_basic_info);
248
249	/* Make sure we don't get rescheduled to another cpu during this probe. */
250	RTCCUINTREG fFlags = ASMIntDisableFlags();
251
252	/*
253	* Check CR4.VMXE
254	*/
255	if (!(HWACCMR0Globals.vmx.hostCR4 & X86_CR4_VMXE))
256	{
257	/* In theory this bit could be cleared behind our back. Which would cause #UD faults when we
258	* try to execute the VMX instructions...
259	*/
260	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4 \| X86_CR4_VMXE);
261	}
262
263	/* Enter VMX Root Mode */
264	rc = VMXEnable(pScatchPagePhys);
265	if (VBOX_FAILURE(rc))
266	{
267	/* KVM leaves the CPU in VMX root mode. Not only is this not allowed, it will crash the host when we enter raw mode, because
268	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify this bit)
269	* (b) turning off paging causes a #GP (unavoidable when switching from long to 32 bits mode or 32 bits to PAE)
270	*
271	* They should fix their code, but until they do we simply refuse to run.
272	*/
273	HWACCMR0Globals.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
274	}
275	else
276	{
277	HWACCMR0Globals.vmx.fSupported = true;
278	VMXDisable();
279	}
280
281	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it wasn't so before (some software could incorrectly think it's in VMX mode) */
282	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4);
283	ASMSetFlags(fFlags);
284
285	RTR0MemObjFree(pScatchMemObj, false);
286	if (VBOX_FAILURE(HWACCMR0Globals.lLastError))
287	return HWACCMR0Globals.lLastError;
288	}
289	else
290	{
291	AssertFailed(); /* can't hit this case anymore */
292	HWACCMR0Globals.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
293	}
294	}
295	#ifdef LOG_ENABLED
296	else
297	SUPR0Printf("HWACCMR0InitCPU failed with rc=%d\n", HWACCMR0Globals.lLastError);
298	#endif
299	}
300	else
301	HWACCMR0Globals.lLastError = VERR_VMX_NO_VMX;
302	}
303	else
304	if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
305	&& u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
306	&& u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX
307	)
308	{
309	/*
310	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
311	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
312	*/
313	if ( (HWACCMR0Globals.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
314	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
315	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
316	)
317	{
318	int aRc[RTCPUSET_MAX_CPUS];
319	RTCPUID idCpu = 0;
320
321	/* We need to check if AMD-V has been properly initialized on all CPUs. Some BIOSes might do a poor job. */
322	memset(aRc, 0, sizeof(aRc));
323	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
324	AssertRC(rc);
325
326	/* Check the return code of all invocations. */
327	if (VBOX_SUCCESS(rc))
328	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
329
330	AssertMsgRC(rc, ("HWACCMR0InitCPU failed for cpu %d with rc=%d\n", idCpu, rc));
331
332	if (VBOX_SUCCESS(rc))
333	{
334	/* Query AMD features. */
335	ASMCpuId(0x8000000A, &HWACCMR0Globals.svm.u32Rev, &HWACCMR0Globals.uMaxASID, &u32Dummy, &HWACCMR0Globals.svm.u32Features);
336
337	HWACCMR0Globals.svm.fSupported = true;
338	}
339	else
340	HWACCMR0Globals.lLastError = rc;
341	}
342	else
343	HWACCMR0Globals.lLastError = VERR_SVM_NO_SVM;
344	}
345	else
346	HWACCMR0Globals.lLastError = VERR_HWACCM_UNKNOWN_CPU;
347	}
348	else
349	HWACCMR0Globals.lLastError = VERR_HWACCM_NO_CPUID;
350
351	#endif /* !VBOX_WITH_HYBIRD_32BIT_KERNEL */
352
353	if (HWACCMR0Globals.vmx.fSupported)
354	{
355	HWACCMR0Globals.pfnEnterSession = VMXR0Enter;
356	HWACCMR0Globals.pfnLeaveSession = VMXR0Leave;
357	HWACCMR0Globals.pfnSaveHostState = VMXR0SaveHostState;
358	HWACCMR0Globals.pfnLoadGuestState = VMXR0LoadGuestState;
359	HWACCMR0Globals.pfnRunGuestCode = VMXR0RunGuestCode;
360	HWACCMR0Globals.pfnEnableCpu = VMXR0EnableCpu;
361	HWACCMR0Globals.pfnDisableCpu = VMXR0DisableCpu;
362	HWACCMR0Globals.pfnInitVM = VMXR0InitVM;
363	HWACCMR0Globals.pfnTermVM = VMXR0TermVM;
364	HWACCMR0Globals.pfnSetupVM = VMXR0SetupVM;
365	}
366	else
367	if (HWACCMR0Globals.svm.fSupported)
368	{
369	HWACCMR0Globals.pfnEnterSession = SVMR0Enter;
370	HWACCMR0Globals.pfnLeaveSession = SVMR0Leave;
371	HWACCMR0Globals.pfnSaveHostState = SVMR0SaveHostState;
372	HWACCMR0Globals.pfnLoadGuestState = SVMR0LoadGuestState;
373	HWACCMR0Globals.pfnRunGuestCode = SVMR0RunGuestCode;
374	HWACCMR0Globals.pfnEnableCpu = SVMR0EnableCpu;
375	HWACCMR0Globals.pfnDisableCpu = SVMR0DisableCpu;
376	HWACCMR0Globals.pfnInitVM = SVMR0InitVM;
377	HWACCMR0Globals.pfnTermVM = SVMR0TermVM;
378	HWACCMR0Globals.pfnSetupVM = SVMR0SetupVM;
379	}
380
381	return VINF_SUCCESS;
382	}
383
384
385	/**
386	* Checks the error code array filled in for each cpu in the system.
387	*
388	* @returns VBox status code.
389	* @param paRc Error code array
390	* @param cErrorCodes Array size
391	* @param pidCpu Value of the first cpu that set an error (out)
392	*/
393	static int hwaccmR0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu)
394	{
395	int rc = VINF_SUCCESS;
396
397	Assert(cErrorCodes == RTCPUSET_MAX_CPUS);
398
399	for (unsigned i=0;i<cErrorCodes;i++)
400	{
401	if (RTMpIsCpuOnline(i))
402	{
403	if (VBOX_FAILURE(paRc[i]))
404	{
405	rc = paRc[i];
406	*pidCpu = i;
407	break;
408	}
409	}
410	}
411	return rc;
412	}
413
414	/**
415	* Does global Ring-0 HWACCM termination.
416	*
417	* @returns VBox status code.
418	*/
419	VMMR0DECL(int) HWACCMR0Term(void)
420	{
421	int aRc[RTCPUSET_MAX_CPUS];
422
423	memset(aRc, 0, sizeof(aRc));
424	int rc = RTMpOnAll(HWACCMR0DisableCPU, aRc, NULL);
425	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
426
427	/* Free the per-cpu pages used for VT-x and AMD-V */
428	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
429	{
430	AssertMsgRC(aRc[i], ("HWACCMR0DisableCPU failed for cpu %d with rc=%d\n", i, aRc[i]));
431	if (HWACCMR0Globals.aCpuInfo[i].pMemObj != NIL_RTR0MEMOBJ)
432	{
433	RTR0MemObjFree(HWACCMR0Globals.aCpuInfo[i].pMemObj, false);
434	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
435	}
436	}
437	return rc;
438	}
439
440
441	/**
442	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
443	* is to be called on the target cpus.
444	*
445	* @param idCpu The identifier for the CPU the function is called on.
446	* @param pvUser1 The 1st user argument.
447	* @param pvUser2 The 2nd user argument.
448	*/
449	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
450	{
451	unsigned u32VendorEBX = (uintptr_t)pvUser1;
452	int paRc = (int )pvUser2;
453	uint64_t val;
454
455	#ifdef LOG_ENABLED
456	SUPR0Printf("HWACCMR0InitCPU cpu %d\n", idCpu);
457	#endif
458	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
459
460	if (u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX)
461	{
462	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
463
464	/*
465	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
466	* Once the lock bit is set, this MSR can no longer be modified.
467	*/
468	if (!(val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK)))
469	{
470	/* MSR is not yet locked; we can change it ourselves here */
471	ASMWrMsr(MSR_IA32_FEATURE_CONTROL, HWACCMR0Globals.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
472	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
473	}
474	if ( (val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
475	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
476	paRc[idCpu] = VINF_SUCCESS;
477	else
478	paRc[idCpu] = VERR_VMX_MSR_LOCKED_OR_DISABLED;
479	}
480	else
481	if (u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX)
482	{
483	/* Check if SVM is disabled */
484	val = ASMRdMsr(MSR_K8_VM_CR);
485	if (!(val & MSR_K8_VM_CR_SVM_DISABLE))
486	{
487	/* Turn on SVM in the EFER MSR. */
488	val = ASMRdMsr(MSR_K6_EFER);
489	if (!(val & MSR_K6_EFER_SVME))
490	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
491
492	/* Paranoia. */
493	val = ASMRdMsr(MSR_K6_EFER);
494	if (val & MSR_K6_EFER_SVME)
495	paRc[idCpu] = VINF_SUCCESS;
496	else
497	paRc[idCpu] = VERR_SVM_ILLEGAL_EFER_MSR;
498	}
499	else
500	paRc[idCpu] = HWACCMR0Globals.lLastError = VERR_SVM_DISABLED;
501	}
502	else
503	AssertFailed(); /* can't happen */
504	return;
505	}
506
507
508	/**
509	* Sets up HWACCM on all cpus.
510	*
511	* @returns VBox status code.
512	* @param pVM The VM to operate on.
513	* @param enmNewHwAccmState New hwaccm state
514	*
515	*/
516	VMMR0DECL(int) HWACCMR0EnableAllCpus(PVM pVM, HWACCMSTATE enmNewHwAccmState)
517	{
518	Assert(sizeof(HWACCMR0Globals.enmHwAccmState) == sizeof(uint32_t));
519	if (ASMAtomicCmpXchgU32((volatile uint32_t *)&HWACCMR0Globals.enmHwAccmState, enmNewHwAccmState, HWACCMSTATE_UNINITIALIZED))
520	{
521	int aRc[RTCPUSET_MAX_CPUS];
522	RTCPUID idCpu = 0;
523
524	/* Don't setup hwaccm as that might not work (vt-x & 64 bits raw mode) */
525	if (enmNewHwAccmState == HWACCMSTATE_DISABLED)
526	return VINF_SUCCESS;
527
528	memset(aRc, 0, sizeof(aRc));
529
530	/* Allocate one page per cpu for the global vt-x and amd-v pages */
531	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
532	{
533	Assert(!HWACCMR0Globals.aCpuInfo[i].pMemObj);
534
535	/** @todo this is rather dangerous if cpus can be taken offline; we don't care for now */
536	if (RTMpIsCpuOnline(i))
537	{
538	int rc = RTR0MemObjAllocCont(&HWACCMR0Globals.aCpuInfo[i].pMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
539	AssertRC(rc);
540	if (RT_FAILURE(rc))
541	return rc;
542
543	void *pvR0 = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[i].pMemObj);
544	Assert(pvR0);
545	ASMMemZeroPage(pvR0);
546
547	#ifdef LOG_ENABLED
548	SUPR0Printf("address %x phys %x\n", pvR0, (uint32_t)RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[i].pMemObj, 0));
549	#endif
550	}
551	}
552	/* First time, so initialize each cpu/core */
553	int rc = RTMpOnAll(HWACCMR0EnableCPU, (void *)pVM, aRc);
554
555	/* Check the return code of all invocations. */
556	if (VBOX_SUCCESS(rc))
557	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
558
559	AssertMsgRC(rc, ("HWACCMR0EnableAllCpus failed for cpu %d with rc=%d\n", idCpu, rc));
560	return rc;
561	}
562
563	if (HWACCMR0Globals.enmHwAccmState == enmNewHwAccmState)
564	return VINF_SUCCESS;
565
566	/* Request to change the mode is not allowed */
567	return VERR_ACCESS_DENIED;
568	}
569
570	/**
571	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
572	* is to be called on the target cpus.
573	*
574	* @param idCpu The identifier for the CPU the function is called on.
575	* @param pvUser1 The 1st user argument.
576	* @param pvUser2 The 2nd user argument.
577	*/
578	static DECLCALLBACK(void) HWACCMR0EnableCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
579	{
580	PVM pVM = (PVM)pvUser1;
581	int paRc = (int )pvUser2;
582	void *pvPageCpu;
583	RTHCPHYS pPageCpuPhys;
584	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
585
586	Assert(pVM);
587	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
588	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
589
590	pCpu->idCpu = idCpu;
591
592	/* Make sure we start with a clean TLB. */
593	pCpu->fFlushTLB = true;
594
595	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
596	pCpu->cTLBFlushes = 0;
597
598	/* Should never happen */
599	if (!pCpu->pMemObj)
600	{
601	AssertFailed();
602	paRc[idCpu] = VERR_INTERNAL_ERROR;
603	return;
604	}
605
606	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
607	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
608
609	paRc[idCpu] = HWACCMR0Globals.pfnEnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
610	AssertRC(paRc[idCpu]);
611	if (VBOX_SUCCESS(paRc[idCpu]))
612	pCpu->fConfigured = true;
613
614	return;
615	}
616
617	/**
618	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
619	* is to be called on the target cpus.
620	*
621	* @param idCpu The identifier for the CPU the function is called on.
622	* @param pvUser1 The 1st user argument.
623	* @param pvUser2 The 2nd user argument.
624	*/
625	static DECLCALLBACK(void) HWACCMR0DisableCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
626	{
627	void *pvPageCpu;
628	RTHCPHYS pPageCpuPhys;
629	int paRc = (int )pvUser1;
630	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
631
632	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
633	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
634
635	if (!pCpu->pMemObj)
636	return;
637
638	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
639	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
640
641	paRc[idCpu] = HWACCMR0Globals.pfnDisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
642	AssertRC(paRc[idCpu]);
643	HWACCMR0Globals.aCpuInfo[idCpu].fConfigured = false;
644
645	pCpu->uCurrentASID = 0;
646
647	return;
648	}
649
650
651	/**
652	* Does Ring-0 per VM HWACCM initialization.
653	*
654	* This is mainly to check that the Host CPU mode is compatible
655	* with VMX.
656	*
657	* @returns VBox status code.
658	* @param pVM The VM to operate on.
659	*/
660	VMMR0DECL(int) HWACCMR0InitVM(PVM pVM)
661	{
662	AssertReturn(pVM, VERR_INVALID_PARAMETER);
663
664	#ifdef LOG_ENABLED
665	SUPR0Printf("HWACCMR0InitVM: %p\n", pVM);
666	#endif
667
668	pVM->hwaccm.s.vmx.fSupported = HWACCMR0Globals.vmx.fSupported;
669	pVM->hwaccm.s.svm.fSupported = HWACCMR0Globals.svm.fSupported;
670
671	pVM->hwaccm.s.vmx.msr.feature_ctrl = HWACCMR0Globals.vmx.msr.feature_ctrl;
672	pVM->hwaccm.s.vmx.hostCR4 = HWACCMR0Globals.vmx.hostCR4;
673	pVM->hwaccm.s.vmx.msr.vmx_basic_info = HWACCMR0Globals.vmx.msr.vmx_basic_info;
674	pVM->hwaccm.s.vmx.msr.vmx_pin_ctls = HWACCMR0Globals.vmx.msr.vmx_pin_ctls;
675	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls = HWACCMR0Globals.vmx.msr.vmx_proc_ctls;
676	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2 = HWACCMR0Globals.vmx.msr.vmx_proc_ctls2;
677	pVM->hwaccm.s.vmx.msr.vmx_exit = HWACCMR0Globals.vmx.msr.vmx_exit;
678	pVM->hwaccm.s.vmx.msr.vmx_entry = HWACCMR0Globals.vmx.msr.vmx_entry;
679	pVM->hwaccm.s.vmx.msr.vmx_misc = HWACCMR0Globals.vmx.msr.vmx_misc;
680	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0;
681	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1;
682	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0;
683	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1;
684	pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum = HWACCMR0Globals.vmx.msr.vmx_vmcs_enum;
685	pVM->hwaccm.s.vmx.msr.vmx_eptcaps = HWACCMR0Globals.vmx.msr.vmx_eptcaps;
686	pVM->hwaccm.s.svm.u32Rev = HWACCMR0Globals.svm.u32Rev;
687	pVM->hwaccm.s.svm.u32Features = HWACCMR0Globals.svm.u32Features;
688	pVM->hwaccm.s.cpuid.u32AMDFeatureECX = HWACCMR0Globals.cpuid.u32AMDFeatureECX;
689	pVM->hwaccm.s.cpuid.u32AMDFeatureEDX = HWACCMR0Globals.cpuid.u32AMDFeatureEDX;
690	pVM->hwaccm.s.lLastError = HWACCMR0Globals.lLastError;
691	#ifdef VBOX_STRICT
692	pVM->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
693	#endif
694
695	pVM->hwaccm.s.uMaxASID = HWACCMR0Globals.uMaxASID;
696
697	/* Invalidate the last cpu we were running on. */
698	pVM->hwaccm.s.idLastCpu = NIL_RTCPUID;
699
700	/* we'll aways increment this the first time (host uses ASID 0) */
701	pVM->hwaccm.s.uCurrentASID = 0;
702
703	/* Init a VT-x or AMD-V VM. */
704	return HWACCMR0Globals.pfnInitVM(pVM);
705	}
706
707
708	/**
709	* Does Ring-0 per VM HWACCM termination.
710	*
711	* @returns VBox status code.
712	* @param pVM The VM to operate on.
713	*/
714	VMMR0DECL(int) HWACCMR0TermVM(PVM pVM)
715	{
716	AssertReturn(pVM, VERR_INVALID_PARAMETER);
717
718	#ifdef LOG_ENABLED
719	SUPR0Printf("HWACCMR0TermVM: %p\n", pVM);
720	#endif
721
722	/* Terminate a VT-x or AMD-V VM. */
723	return HWACCMR0Globals.pfnTermVM(pVM);
724	}
725
726
727	/**
728	* Sets up a VT-x or AMD-V session
729	*
730	* @returns VBox status code.
731	* @param pVM The VM to operate on.
732	*/
733	VMMR0DECL(int) HWACCMR0SetupVM(PVM pVM)
734	{
735	AssertReturn(pVM, VERR_INVALID_PARAMETER);
736
737	#ifdef LOG_ENABLED
738	SUPR0Printf("HWACCMR0SetupVM: %p\n", pVM);
739	#endif
740
741	/* Setup VT-x or AMD-V. */
742	return HWACCMR0Globals.pfnSetupVM(pVM);
743	}
744
745
746	/**
747	* Enters the VT-x or AMD-V session
748	*
749	* @returns VBox status code.
750	* @param pVM The VM to operate on.
751	*/
752	VMMR0DECL(int) HWACCMR0Enter(PVM pVM)
753	{
754	CPUMCTX *pCtx;
755	int rc;
756	RTCPUID idCpu = RTMpCpuId();
757
758	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
759	if (VBOX_FAILURE(rc))
760	return rc;
761
762	/* Always load the guest's FPU/XMM state on-demand. */
763	CPUMDeactivateGuestFPUState(pVM);
764
765	/* Always load the guest's debug state on-demand. */
766	CPUMDeactivateGuestDebugState(pVM);
767
768	/* Always reload the host context and the guest's CR0 register. (!!!!) */
769	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0 \| HWACCM_CHANGED_HOST_CONTEXT;
770
771	/* Setup the register and mask according to the current execution mode. */
772	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
773	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFFFFFFFFFF);
774	else
775	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFF);
776
777	rc = HWACCMR0Globals.pfnEnterSession(pVM, &HWACCMR0Globals.aCpuInfo[idCpu]);
778	AssertRC(rc);
779	/* We must save the host context here (VT-x) as we might be rescheduled on a different cpu after a long jump back to ring 3. */
780	rc \|= HWACCMR0Globals.pfnSaveHostState(pVM);
781	AssertRC(rc);
782	rc \|= HWACCMR0Globals.pfnLoadGuestState(pVM, pCtx);
783	AssertRC(rc);
784
785	#ifdef VBOX_STRICT
786	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
787	if (RT_SUCCESS(rc))
788	{
789	AssertMsg(pVM->hwaccm.s.idEnteredCpu == NIL_RTCPUID, ("%d", (int)pVM->hwaccm.s.idEnteredCpu));
790	pVM->hwaccm.s.idEnteredCpu = idCpu;
791	}
792	#endif
793	return rc;
794	}
795
796
797	/**
798	* Leaves the VT-x or AMD-V session
799	*
800	* @returns VBox status code.
801	* @param pVM The VM to operate on.
802	*/
803	VMMR0DECL(int) HWACCMR0Leave(PVM pVM)
804	{
805	CPUMCTX *pCtx;
806	int rc;
807
808	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
809	if (VBOX_FAILURE(rc))
810	return rc;
811
812	/* Note: It's rather tricky with longjmps done by e.g. Log statements or the page fault handler.
813	* We must restore the host FPU here to make absolutely sure we don't leave the guest FPU state active
814	* or trash somebody else's FPU state.
815	*/
816	/* Save the guest FPU and XMM state if necessary. */
817	if (CPUMIsGuestFPUStateActive(pVM))
818	{
819	Log2(("CPUMR0SaveGuestFPU\n"));
820	CPUMR0SaveGuestFPU(pVM, pCtx);
821
822	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
823	}
824
825	rc = HWACCMR0Globals.pfnLeaveSession(pVM, pCtx);
826
827	#ifdef VBOX_STRICT
828	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
829	RTCPUID idCpu = RTMpCpuId();
830	AssertMsg(pVM->hwaccm.s.idEnteredCpu == idCpu, ("owner is %d, I'm %d", (int)pVM->hwaccm.s.idEnteredCpu, (int)idCpu));
831	pVM->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
832	#endif
833
834	return rc;
835	}
836
837	/**
838	* Runs guest code in a hardware accelerated VM.
839	*
840	* @returns VBox status code.
841	* @param pVM The VM to operate on.
842	*/
843	VMMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM)
844	{
845	CPUMCTX *pCtx;
846	int rc;
847	RTCPUID idCpu = RTMpCpuId(); NOREF(idCpu);
848
849	Assert(!VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL));
850	Assert(HWACCMR0Globals.aCpuInfo[idCpu].fConfigured);
851
852	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
853	if (VBOX_FAILURE(rc))
854	return rc;
855
856	return HWACCMR0Globals.pfnRunGuestCode(pVM, pCtx);
857	}
858
859	/**
860	* Returns the cpu structure for the current cpu.
861	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
862	*
863	* @returns cpu structure pointer
864	* @param pVM The VM to operate on.
865	*/
866	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu()
867	{
868	RTCPUID idCpu = RTMpCpuId();
869
870	return &HWACCMR0Globals.aCpuInfo[idCpu];
871	}
872
873	#ifdef VBOX_STRICT
874	# include <iprt/string.h>
875	/**
876	* Dumps a descriptor.
877	*
878	* @param pDesc Descriptor to dump.
879	* @param Sel Selector number.
880	* @param pszMsg Message to prepend the log entry with.
881	*/
882	VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
883	{
884	/*
885	* Make variable description string.
886	*/
887	static struct
888	{
889	unsigned cch;
890	const char *psz;
891	} const aTypes[32] =
892	{
893	# define STRENTRY(str) { sizeof(str) - 1, str }
894
895	/* system */
896	# if HC_ARCH_BITS == 64
897	STRENTRY("Reserved0 "), /* 0x00 */
898	STRENTRY("Reserved1 "), /* 0x01 */
899	STRENTRY("LDT "), /* 0x02 */
900	STRENTRY("Reserved3 "), /* 0x03 */
901	STRENTRY("Reserved4 "), /* 0x04 */
902	STRENTRY("Reserved5 "), /* 0x05 */
903	STRENTRY("Reserved6 "), /* 0x06 */
904	STRENTRY("Reserved7 "), /* 0x07 */
905	STRENTRY("Reserved8 "), /* 0x08 */
906	STRENTRY("TSS64Avail "), /* 0x09 */
907	STRENTRY("ReservedA "), /* 0x0a */
908	STRENTRY("TSS64Busy "), /* 0x0b */
909	STRENTRY("Call64 "), /* 0x0c */
910	STRENTRY("ReservedD "), /* 0x0d */
911	STRENTRY("Int64 "), /* 0x0e */
912	STRENTRY("Trap64 "), /* 0x0f */
913	# else
914	STRENTRY("Reserved0 "), /* 0x00 */
915	STRENTRY("TSS16Avail "), /* 0x01 */
916	STRENTRY("LDT "), /* 0x02 */
917	STRENTRY("TSS16Busy "), /* 0x03 */
918	STRENTRY("Call16 "), /* 0x04 */
919	STRENTRY("Task "), /* 0x05 */
920	STRENTRY("Int16 "), /* 0x06 */
921	STRENTRY("Trap16 "), /* 0x07 */
922	STRENTRY("Reserved8 "), /* 0x08 */
923	STRENTRY("TSS32Avail "), /* 0x09 */
924	STRENTRY("ReservedA "), /* 0x0a */
925	STRENTRY("TSS32Busy "), /* 0x0b */
926	STRENTRY("Call32 "), /* 0x0c */
927	STRENTRY("ReservedD "), /* 0x0d */
928	STRENTRY("Int32 "), /* 0x0e */
929	STRENTRY("Trap32 "), /* 0x0f */
930	# endif
931	/* non system */
932	STRENTRY("DataRO "), /* 0x10 */
933	STRENTRY("DataRO Accessed "), /* 0x11 */
934	STRENTRY("DataRW "), /* 0x12 */
935	STRENTRY("DataRW Accessed "), /* 0x13 */
936	STRENTRY("DataDownRO "), /* 0x14 */
937	STRENTRY("DataDownRO Accessed "), /* 0x15 */
938	STRENTRY("DataDownRW "), /* 0x16 */
939	STRENTRY("DataDownRW Accessed "), /* 0x17 */
940	STRENTRY("CodeEO "), /* 0x18 */
941	STRENTRY("CodeEO Accessed "), /* 0x19 */
942	STRENTRY("CodeER "), /* 0x1a */
943	STRENTRY("CodeER Accessed "), /* 0x1b */
944	STRENTRY("CodeConfEO "), /* 0x1c */
945	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
946	STRENTRY("CodeConfER "), /* 0x1e */
947	STRENTRY("CodeConfER Accessed ") /* 0x1f */
948	# undef SYSENTRY
949	};
950	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
951	char szMsg[128];
952	char *psz = &szMsg[0];
953	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
954	memcpy(psz, aTypes[i].psz, aTypes[i].cch);
955	psz += aTypes[i].cch;
956
957	if (pDesc->Gen.u1Present)
958	ADD_STR(psz, "Present ");
959	else
960	ADD_STR(psz, "Not-Present ");
961	# if HC_ARCH_BITS == 64
962	if (pDesc->Gen.u1Long)
963	ADD_STR(psz, "64-bit ");
964	else
965	ADD_STR(psz, "Comp ");
966	# else
967	if (pDesc->Gen.u1Granularity)
968	ADD_STR(psz, "Page ");
969	if (pDesc->Gen.u1DefBig)
970	ADD_STR(psz, "32-bit ");
971	else
972	ADD_STR(psz, "16-bit ");
973	# endif
974	# undef ADD_STR
975	*psz = '\0';
976
977	/*
978	* Limit and Base and format the output.
979	*/
980	uint32_t u32Limit = X86DESC_LIMIT(*pDesc);
981	if (pDesc->Gen.u1Granularity)
982	u32Limit = u32Limit << PAGE_SHIFT \| PAGE_OFFSET_MASK;
983
984	# if HC_ARCH_BITS == 64
985	uint64_t u32Base = X86DESC64_BASE(*pDesc);
986
987	Log(("%s %04x - %VX64 %VX64 - base=%VX64 limit=%08x dpl=%d %s\n", pszMsg,
988	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
989	# else
990	uint32_t u32Base = X86DESC_BASE(*pDesc);
991
992	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
993	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
994	# endif
995	}
996
997	/**
998	* Formats a full register dump.
999	*
1000	* @param pVM The VM to operate on.
1001	* @param pCtx The context to format.
1002	*/
1003	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx)
1004	{
1005	/*
1006	* Format the flags.
1007	*/
1008	static struct
1009	{
1010	const char pszSet; const char pszClear; uint32_t fFlag;
1011	} aFlags[] =
1012	{
1013	{ "vip",NULL, X86_EFL_VIP },
1014	{ "vif",NULL, X86_EFL_VIF },
1015	{ "ac", NULL, X86_EFL_AC },
1016	{ "vm", NULL, X86_EFL_VM },
1017	{ "rf", NULL, X86_EFL_RF },
1018	{ "nt", NULL, X86_EFL_NT },
1019	{ "ov", "nv", X86_EFL_OF },
1020	{ "dn", "up", X86_EFL_DF },
1021	{ "ei", "di", X86_EFL_IF },
1022	{ "tf", NULL, X86_EFL_TF },
1023	{ "nt", "pl", X86_EFL_SF },
1024	{ "nz", "zr", X86_EFL_ZF },
1025	{ "ac", "na", X86_EFL_AF },
1026	{ "po", "pe", X86_EFL_PF },
1027	{ "cy", "nc", X86_EFL_CF },
1028	};
1029	char szEFlags[80];
1030	char *psz = szEFlags;
1031	uint32_t efl = pCtx->eflags.u32;
1032	for (unsigned i = 0; i < RT_ELEMENTS(aFlags); i++)
1033	{
1034	const char *pszAdd = aFlags[i].fFlag & efl ? aFlags[i].pszSet : aFlags[i].pszClear;
1035	if (pszAdd)
1036	{
1037	strcpy(psz, pszAdd);
1038	psz += strlen(pszAdd);
1039	*psz++ = ' ';
1040	}
1041	}
1042	psz[-1] = '\0';
1043
1044
1045	/*
1046	* Format the registers.
1047	*/
1048	if (CPUMIsGuestIn64BitCode(pVM, CPUMCTX2CORE(pCtx)))
1049	{
1050	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1051	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1052	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1053	"r14=%016RX64 r15=%016RX64\n"
1054	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1055	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1056	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1057	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1058	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1059	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1060	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1061	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1062	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1063	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1064	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1065	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1066	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1067	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1068	,
1069	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1070	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1071	pCtx->r14, pCtx->r15,
1072	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1073	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1074	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1075	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1076	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1077	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1078	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1079	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1080	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1081	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1082	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1083	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1084	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1085	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1086	}
1087	else
1088	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1089	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1090	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1091	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1092	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1093	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1094	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1095	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1096	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1097	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1098	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1099	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1100	,
1101	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1102	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1103	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr[0], pCtx->dr[1],
1104	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr[2], pCtx->dr[3],
1105	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr[4], pCtx->dr[5],
1106	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr[6], pCtx->dr[7],
1107	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0, pCtx->cr2,
1108	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3, pCtx->cr4,
1109	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1110	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1111	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1112	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1113
1114	Log(("FPU:\n"
1115	"FCW=%04x FSW=%04x FTW=%02x\n"
1116	"res1=%02x FOP=%04x FPUIP=%08x CS=%04x Rsvrd1=%04x\n"
1117	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1118	,
1119	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
1120	pCtx->fpu.huh1, pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsvrd1,
1121	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
1122	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
1123
1124
1125	Log(("MSR:\n"
1126	"EFER =%016RX64\n"
1127	"PAT =%016RX64\n"
1128	"STAR =%016RX64\n"
1129	"CSTAR =%016RX64\n"
1130	"LSTAR =%016RX64\n"
1131	"SFMASK =%016RX64\n"
1132	"KERNELGSBASE =%016RX64\n",
1133	pCtx->msrEFER,
1134	pCtx->msrPAT,
1135	pCtx->msrSTAR,
1136	pCtx->msrCSTAR,
1137	pCtx->msrLSTAR,
1138	pCtx->msrSFMASK,
1139	pCtx->msrKERNELGSBASE));
1140
1141	}
1142	#endif /* VBOX_STRICT */
1143
1144	/* Dummy callback handlers. */
1145	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PHWACCM_CPUINFO pCpu)
1146	{
1147	return VINF_SUCCESS;
1148	}
1149
1150	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PCPUMCTX pCtx)
1151	{
1152	return VINF_SUCCESS;
1153	}
1154
1155	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1156	{
1157	return VINF_SUCCESS;
1158	}
1159
1160	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1161	{
1162	return VINF_SUCCESS;
1163	}
1164
1165	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM)
1166	{
1167	return VINF_SUCCESS;
1168	}
1169
1170	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM)
1171	{
1172	return VINF_SUCCESS;
1173	}
1174
1175	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM)
1176	{
1177	return VINF_SUCCESS;
1178	}
1179
1180	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, CPUMCTX *pCtx)
1181	{
1182	return VINF_SUCCESS;
1183	}
1184
1185	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM)
1186	{
1187	return VINF_SUCCESS;
1188	}
1189
1190	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, CPUMCTX *pCtx)
1191	{
1192	return VINF_SUCCESS;
1193	}

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp@ 13263

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