HWACCMR0.cpp@ 23570

Last change on this file since 23570 was 23566, checked in by vboxsync, 15 years ago
Fixed assertion
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File size: 64.1 KB

Line
1	/* $Id: HWACCMR0.cpp 23566 2009-10-05 16:07:34Z vboxsync $ */
2	/** @file
3	* HWACCM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_vmx.h>
32	#include <VBox/hwacc_svm.h>
33	#include <VBox/pgm.h>
34	#include <VBox/pdm.h>
35	#include <VBox/err.h>
36	#include <VBox/log.h>
37	#include <VBox/selm.h>
38	#include <VBox/iom.h>
39	#include <iprt/assert.h>
40	#include <iprt/asm.h>
41	#include <iprt/cpuset.h>
42	#include <iprt/memobj.h>
43	#include <iprt/param.h>
44	#include <iprt/power.h>
45	#include <iprt/string.h>
46	#include <iprt/thread.h>
47	#include "HWVMXR0.h"
48	#include "HWSVMR0.h"
49
50	/*******************************************************************************
51	* Internal Functions *
52	*******************************************************************************/
53	static DECLCALLBACK(void) hwaccmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hwaccmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
55	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
56	static int hwaccmR0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu);
57	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
58
59	/*******************************************************************************
60	* Global Variables *
61	*******************************************************************************/
62
63	static struct
64	{
65	HWACCM_CPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
66
67	/** Ring 0 handlers for VT-x and AMD-V. */
68	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu));
69	DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
70	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
71	DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
72	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
73	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
74	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
75	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
76	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
77	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVM pVM));
78
79	/** Maximum ASID allowed. */
80	uint32_t uMaxASID;
81
82	struct
83	{
84	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
85	bool fSupported;
86	/** Whether we're using SUPR0EnableVTx or not. */
87	bool fUsingSUPR0EnableVTx;
88
89	/** Host CR4 value (set by ring-0 VMX init) */
90	uint64_t hostCR4;
91
92	/** VMX MSR values */
93	struct
94	{
95	uint64_t feature_ctrl;
96	uint64_t vmx_basic_info;
97	VMX_CAPABILITY vmx_pin_ctls;
98	VMX_CAPABILITY vmx_proc_ctls;
99	VMX_CAPABILITY vmx_proc_ctls2;
100	VMX_CAPABILITY vmx_exit;
101	VMX_CAPABILITY vmx_entry;
102	uint64_t vmx_misc;
103	uint64_t vmx_cr0_fixed0;
104	uint64_t vmx_cr0_fixed1;
105	uint64_t vmx_cr4_fixed0;
106	uint64_t vmx_cr4_fixed1;
107	uint64_t vmx_vmcs_enum;
108	uint64_t vmx_eptcaps;
109	} msr;
110	/* Last instruction error */
111	uint32_t ulLastInstrError;
112	} vmx;
113	struct
114	{
115	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
116	bool fSupported;
117
118	/** SVM revision. */
119	uint32_t u32Rev;
120
121	/** SVM feature bits from cpuid 0x8000000a */
122	uint32_t u32Features;
123	} svm;
124	/** Saved error from detection */
125	int32_t lLastError;
126
127	struct
128	{
129	uint32_t u32AMDFeatureECX;
130	uint32_t u32AMDFeatureEDX;
131	} cpuid;
132
133	HWACCMSTATE enmHwAccmState;
134
135	bool fGlobalInit;
136	volatile bool fSuspended;
137	} HWACCMR0Globals;
138
139
140
141	/**
142	* Does global Ring-0 HWACCM initialization.
143	*
144	* @returns VBox status code.
145	*/
146	VMMR0DECL(int) HWACCMR0Init(void)
147	{
148	int rc;
149
150	memset(&HWACCMR0Globals, 0, sizeof(HWACCMR0Globals));
151	HWACCMR0Globals.enmHwAccmState = HWACCMSTATE_UNINITIALIZED;
152	for (unsigned i = 0; i < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); i++)
153	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
154
155	/* Fill in all callbacks with placeholders. */
156	HWACCMR0Globals.pfnEnterSession = HWACCMR0DummyEnter;
157	HWACCMR0Globals.pfnLeaveSession = HWACCMR0DummyLeave;
158	HWACCMR0Globals.pfnSaveHostState = HWACCMR0DummySaveHostState;
159	HWACCMR0Globals.pfnLoadGuestState = HWACCMR0DummyLoadGuestState;
160	HWACCMR0Globals.pfnRunGuestCode = HWACCMR0DummyRunGuestCode;
161	HWACCMR0Globals.pfnEnableCpu = HWACCMR0DummyEnableCpu;
162	HWACCMR0Globals.pfnDisableCpu = HWACCMR0DummyDisableCpu;
163	HWACCMR0Globals.pfnInitVM = HWACCMR0DummyInitVM;
164	HWACCMR0Globals.pfnTermVM = HWACCMR0DummyTermVM;
165	HWACCMR0Globals.pfnSetupVM = HWACCMR0DummySetupVM;
166
167	/* Default is global VT-x/AMD-V init */
168	HWACCMR0Globals.fGlobalInit = true;
169
170	/*
171	* Check for VT-x and AMD-V capabilities
172	*/
173	if (ASMHasCpuId())
174	{
175	uint32_t u32FeaturesECX;
176	uint32_t u32Dummy;
177	uint32_t u32FeaturesEDX;
178	uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
179
180	ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
181	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
182	/* Query AMD features. */
183	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy, &HWACCMR0Globals.cpuid.u32AMDFeatureECX, &HWACCMR0Globals.cpuid.u32AMDFeatureEDX);
184
185	if ( u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
186	&& u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
187	&& u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX
188	)
189	{
190	/*
191	* Read all VMX MSRs if VMX is available. (same goes for RDMSR/WRMSR)
192	* We also assume all VMX-enabled CPUs support fxsave/fxrstor.
193	*/
194	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
195	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
196	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
197	)
198	{
199	int aRc[RTCPUSET_MAX_CPUS];
200	RTCPUID idCpu = 0;
201
202	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
203
204	/*
205	* First try use native kernel API for controlling VT-x.
206	* (This is only supported by some Mac OS X kernels atm.)
207	*/
208	HWACCMR0Globals.lLastError = rc = SUPR0EnableVTx(true /* fEnable */);
209	if (rc != VERR_NOT_SUPPORTED)
210	{
211	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
212	HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx = true;
213	if (RT_SUCCESS(rc))
214	{
215	HWACCMR0Globals.vmx.fSupported = true;
216	rc = SUPR0EnableVTx(false /* fEnable */);
217	AssertRC(rc);
218	}
219	}
220	else
221	{
222	HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx = false;
223
224	/* We need to check if VT-x has been properly initialized on all CPUs. Some BIOSes do a lousy job. */
225	memset(aRc, 0, sizeof(aRc));
226	HWACCMR0Globals.lLastError = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
227
228	/* Check the return code of all invocations. */
229	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
230	HWACCMR0Globals.lLastError = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
231	}
232	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
233	{
234	/* Reread in case we've changed it. */
235	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
236
237	if ( (HWACCMR0Globals.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
238	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
239	{
240	RTR0MEMOBJ pScatchMemObj;
241	void *pvScatchPage;
242	RTHCPHYS pScatchPagePhys;
243
244	HWACCMR0Globals.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
245	HWACCMR0Globals.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
246	HWACCMR0Globals.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
247	HWACCMR0Globals.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
248	HWACCMR0Globals.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
249	HWACCMR0Globals.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
250	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
251	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
252	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
253	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
254	HWACCMR0Globals.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
255	/* VPID 16 bits ASID. */
256	HWACCMR0Globals.uMaxASID = 0x10000; /* exclusive */
257
258	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
259	{
260	HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
261	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT\|VMX_VMCS_CTRL_PROC_EXEC2_VPID))
262	HWACCMR0Globals.vmx.msr.vmx_eptcaps = ASMRdMsr(MSR_IA32_VMX_EPT_CAPS);
263	}
264
265	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
266	{
267	HWACCMR0Globals.vmx.hostCR4 = ASMGetCR4();
268
269	rc = RTR0MemObjAllocCont(&pScatchMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
270	if (RT_FAILURE(rc))
271	return rc;
272
273	pvScatchPage = RTR0MemObjAddress(pScatchMemObj);
274	pScatchPagePhys = RTR0MemObjGetPagePhysAddr(pScatchMemObj, 0);
275	memset(pvScatchPage, 0, PAGE_SIZE);
276
277	/* Set revision dword at the beginning of the structure. */
278	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(HWACCMR0Globals.vmx.msr.vmx_basic_info);
279
280	/* Make sure we don't get rescheduled to another cpu during this probe. */
281	RTCCUINTREG fFlags = ASMIntDisableFlags();
282
283	/*
284	* Check CR4.VMXE
285	*/
286	if (!(HWACCMR0Globals.vmx.hostCR4 & X86_CR4_VMXE))
287	{
288	/* In theory this bit could be cleared behind our back. Which would cause #UD faults when we
289	* try to execute the VMX instructions...
290	*/
291	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4 \| X86_CR4_VMXE);
292	}
293
294	/* Enter VMX Root Mode */
295	rc = VMXEnable(pScatchPagePhys);
296	if (RT_FAILURE(rc))
297	{
298	/* KVM leaves the CPU in VMX root mode. Not only is this not allowed, it will crash the host when we enter raw mode, because
299	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify this bit)
300	* (b) turning off paging causes a #GP (unavoidable when switching from long to 32 bits mode or 32 bits to PAE)
301	*
302	* They should fix their code, but until they do we simply refuse to run.
303	*/
304	HWACCMR0Globals.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
305	}
306	else
307	{
308	HWACCMR0Globals.vmx.fSupported = true;
309	VMXDisable();
310	}
311
312	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it wasn't so before (some software could incorrectly think it's in VMX mode) */
313	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4);
314	ASMSetFlags(fFlags);
315
316	RTR0MemObjFree(pScatchMemObj, false);
317	if (RT_FAILURE(HWACCMR0Globals.lLastError))
318	return HWACCMR0Globals.lLastError;
319	}
320	}
321	else
322	{
323	AssertFailed(); /* can't hit this case anymore */
324	HWACCMR0Globals.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
325	}
326	}
327	#ifdef LOG_ENABLED
328	else
329	SUPR0Printf("HWACCMR0InitCPU failed with rc=%d\n", HWACCMR0Globals.lLastError);
330	#endif
331	}
332	else
333	HWACCMR0Globals.lLastError = VERR_VMX_NO_VMX;
334	}
335	else
336	if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
337	&& u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
338	&& u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX
339	)
340	{
341	/*
342	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
343	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
344	*/
345	if ( (HWACCMR0Globals.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
346	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
347	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
348	)
349	{
350	int aRc[RTCPUSET_MAX_CPUS];
351	RTCPUID idCpu = 0;
352
353	/* We need to check if AMD-V has been properly initialized on all CPUs. Some BIOSes might do a poor job. */
354	memset(aRc, 0, sizeof(aRc));
355	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
356	AssertRC(rc);
357
358	/* Check the return code of all invocations. */
359	if (RT_SUCCESS(rc))
360	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
361
362	AssertMsgRC(rc, ("HWACCMR0InitCPU failed for cpu %d with rc=%d\n", idCpu, rc));
363
364	if (RT_SUCCESS(rc))
365	{
366	/* Query AMD features. */
367	ASMCpuId(0x8000000A, &HWACCMR0Globals.svm.u32Rev, &HWACCMR0Globals.uMaxASID, &u32Dummy, &HWACCMR0Globals.svm.u32Features);
368
369	HWACCMR0Globals.svm.fSupported = true;
370	}
371	else
372	HWACCMR0Globals.lLastError = rc;
373	}
374	else
375	HWACCMR0Globals.lLastError = VERR_SVM_NO_SVM;
376	}
377	else
378	HWACCMR0Globals.lLastError = VERR_HWACCM_UNKNOWN_CPU;
379	}
380	else
381	HWACCMR0Globals.lLastError = VERR_HWACCM_NO_CPUID;
382
383	if (HWACCMR0Globals.vmx.fSupported)
384	{
385	HWACCMR0Globals.pfnEnterSession = VMXR0Enter;
386	HWACCMR0Globals.pfnLeaveSession = VMXR0Leave;
387	HWACCMR0Globals.pfnSaveHostState = VMXR0SaveHostState;
388	HWACCMR0Globals.pfnLoadGuestState = VMXR0LoadGuestState;
389	HWACCMR0Globals.pfnRunGuestCode = VMXR0RunGuestCode;
390	HWACCMR0Globals.pfnEnableCpu = VMXR0EnableCpu;
391	HWACCMR0Globals.pfnDisableCpu = VMXR0DisableCpu;
392	HWACCMR0Globals.pfnInitVM = VMXR0InitVM;
393	HWACCMR0Globals.pfnTermVM = VMXR0TermVM;
394	HWACCMR0Globals.pfnSetupVM = VMXR0SetupVM;
395	}
396	else
397	if (HWACCMR0Globals.svm.fSupported)
398	{
399	HWACCMR0Globals.pfnEnterSession = SVMR0Enter;
400	HWACCMR0Globals.pfnLeaveSession = SVMR0Leave;
401	HWACCMR0Globals.pfnSaveHostState = SVMR0SaveHostState;
402	HWACCMR0Globals.pfnLoadGuestState = SVMR0LoadGuestState;
403	HWACCMR0Globals.pfnRunGuestCode = SVMR0RunGuestCode;
404	HWACCMR0Globals.pfnEnableCpu = SVMR0EnableCpu;
405	HWACCMR0Globals.pfnDisableCpu = SVMR0DisableCpu;
406	HWACCMR0Globals.pfnInitVM = SVMR0InitVM;
407	HWACCMR0Globals.pfnTermVM = SVMR0TermVM;
408	HWACCMR0Globals.pfnSetupVM = SVMR0SetupVM;
409	}
410
411	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
412	{
413	rc = RTPowerNotificationRegister(hwaccmR0PowerCallback, 0);
414	AssertRC(rc);
415	}
416
417	return VINF_SUCCESS;
418	}
419
420
421	/**
422	* Checks the error code array filled in for each cpu in the system.
423	*
424	* @returns VBox status code.
425	* @param paRc Error code array
426	* @param cErrorCodes Array size
427	* @param pidCpu Value of the first cpu that set an error (out)
428	*/
429	static int hwaccmR0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu)
430	{
431	int rc = VINF_SUCCESS;
432
433	Assert(cErrorCodes == RTCPUSET_MAX_CPUS);
434
435	for (unsigned i=0;i<cErrorCodes;i++)
436	{
437	if (RTMpIsCpuOnline(i))
438	{
439	if (RT_FAILURE(paRc[i]))
440	{
441	rc = paRc[i];
442	*pidCpu = i;
443	break;
444	}
445	}
446	}
447	return rc;
448	}
449
450	/**
451	* Does global Ring-0 HWACCM termination.
452	*
453	* @returns VBox status code.
454	*/
455	VMMR0DECL(int) HWACCMR0Term(void)
456	{
457	int rc;
458	if ( HWACCMR0Globals.vmx.fSupported
459	&& HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
460	{
461	Assert(HWACCMR0Globals.fGlobalInit);
462	rc = SUPR0EnableVTx(false /* fEnable */);
463	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); iCpu++)
464	{
465	HWACCMR0Globals.aCpuInfo[iCpu].fConfigured = false;
466	Assert(HWACCMR0Globals.aCpuInfo[iCpu].pMemObj == NIL_RTR0MEMOBJ);
467	}
468	}
469	else
470	{
471	Assert(!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
472	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
473	{
474	rc = RTPowerNotificationDeregister(hwaccmR0PowerCallback, 0);
475	Assert(RT_SUCCESS(rc));
476	}
477
478	/* Only disable VT-x/AMD-V on all CPUs if we enabled it before. */
479	if (HWACCMR0Globals.fGlobalInit)
480	{
481	int aRc[RTCPUSET_MAX_CPUS];
482
483	memset(aRc, 0, sizeof(aRc));
484	rc = RTMpOnAll(hwaccmR0DisableCpuCallback, aRc, NULL);
485	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
486	#ifdef VBOX_STRICT
487	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
488	AssertMsgRC(aRc[i], ("hwaccmR0DisableCpuCallback failed for cpu %d with rc=%d\n", i, aRc[i]));
489	#endif
490	}
491
492	/* Free the per-cpu pages used for VT-x and AMD-V */
493	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
494	{
495	if (HWACCMR0Globals.aCpuInfo[i].pMemObj != NIL_RTR0MEMOBJ)
496	{
497	RTR0MemObjFree(HWACCMR0Globals.aCpuInfo[i].pMemObj, false);
498	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
499	}
500	}
501	}
502	return rc;
503	}
504
505
506	/**
507	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
508	* is to be called on the target cpus.
509	*
510	* @param idCpu The identifier for the CPU the function is called on.
511	* @param pvUser1 The 1st user argument.
512	* @param pvUser2 The 2nd user argument.
513	*/
514	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
515	{
516	unsigned u32VendorEBX = (uintptr_t)pvUser1;
517	int paRc = (int )pvUser2;
518	uint64_t val;
519
520	#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
521	SUPR0Printf("HWACCMR0InitCPU cpu %d\n", idCpu);
522	#endif
523	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
524
525	if (u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX)
526	{
527	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
528
529	/*
530	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
531	* Once the lock bit is set, this MSR can no longer be modified.
532	*/
533	if ( !(val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
534	\|\| ((val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK)) == MSR_IA32_FEATURE_CONTROL_VMXON) /* Some BIOSes forget to set the locked bit. */
535	)
536	{
537	/* MSR is not yet locked; we can change it ourselves here */
538	ASMWrMsr(MSR_IA32_FEATURE_CONTROL, HWACCMR0Globals.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
539	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
540	}
541	if ( (val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
542	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
543	paRc[idCpu] = VINF_SUCCESS;
544	else
545	paRc[idCpu] = VERR_VMX_MSR_LOCKED_OR_DISABLED;
546	}
547	else
548	if (u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX)
549	{
550	/* Check if SVM is disabled */
551	val = ASMRdMsr(MSR_K8_VM_CR);
552	if (!(val & MSR_K8_VM_CR_SVM_DISABLE))
553	{
554	/* Turn on SVM in the EFER MSR. */
555	val = ASMRdMsr(MSR_K6_EFER);
556	if (!(val & MSR_K6_EFER_SVME))
557	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
558
559	/* Paranoia. */
560	val = ASMRdMsr(MSR_K6_EFER);
561	if (val & MSR_K6_EFER_SVME)
562	{
563	/* Restore previous value. */
564	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
565	paRc[idCpu] = VINF_SUCCESS;
566	}
567	else
568	paRc[idCpu] = VERR_SVM_ILLEGAL_EFER_MSR;
569	}
570	else
571	paRc[idCpu] = HWACCMR0Globals.lLastError = VERR_SVM_DISABLED;
572	}
573	else
574	AssertFailed(); /* can't happen */
575	return;
576	}
577
578
579	/**
580	* Sets up HWACCM on all cpus.
581	*
582	* @returns VBox status code.
583	* @param pVM The VM to operate on.
584	*
585	*/
586	VMMR0DECL(int) HWACCMR0EnableAllCpus(PVM pVM)
587	{
588	AssertCompile(sizeof(HWACCMR0Globals.enmHwAccmState) == sizeof(uint32_t));
589
590	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
591	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
592	return VERR_HWACCM_SUSPEND_PENDING;
593
594	if (ASMAtomicCmpXchgU32((volatile uint32_t *)&HWACCMR0Globals.enmHwAccmState, HWACCMSTATE_ENABLED, HWACCMSTATE_UNINITIALIZED))
595	{
596	int rc;
597
598	HWACCMR0Globals.fGlobalInit = pVM->hwaccm.s.fGlobalInit;
599
600	if ( HWACCMR0Globals.vmx.fSupported
601	&& HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
602	{
603	rc = SUPR0EnableVTx(true /* fEnable */);
604	if (RT_SUCCESS(rc))
605	{
606	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); iCpu++)
607	{
608	HWACCMR0Globals.aCpuInfo[iCpu].fConfigured = true;
609	Assert(HWACCMR0Globals.aCpuInfo[iCpu].pMemObj == NIL_RTR0MEMOBJ);
610	}
611	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
612	HWACCMR0Globals.fGlobalInit = pVM->hwaccm.s.fGlobalInit = true;
613	}
614	else
615	AssertMsgFailed(("HWACCMR0EnableAllCpus/SUPR0EnableVTx: rc=%Rrc\n", rc));
616	}
617	else
618	{
619	int aRc[RTCPUSET_MAX_CPUS];
620	RTCPUID idCpu = 0;
621
622	memset(aRc, 0, sizeof(aRc));
623
624	/* Allocate one page per cpu for the global vt-x and amd-v pages */
625	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
626	{
627	Assert(!HWACCMR0Globals.aCpuInfo[i].pMemObj);
628
629	/** @todo this is rather dangerous if cpus can be taken offline; we don't care for now */
630	if (RTMpIsCpuOnline(i))
631	{
632	rc = RTR0MemObjAllocCont(&HWACCMR0Globals.aCpuInfo[i].pMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
633	AssertRC(rc);
634	if (RT_FAILURE(rc))
635	return rc;
636
637	void *pvR0 = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[i].pMemObj);
638	Assert(pvR0);
639	ASMMemZeroPage(pvR0);
640
641	#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
642	SUPR0Printf("address %x phys %x\n", pvR0, (uint32_t)RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[i].pMemObj, 0));
643	#endif
644	}
645	}
646	if (HWACCMR0Globals.fGlobalInit)
647	{
648	/* First time, so initialize each cpu/core */
649	rc = RTMpOnAll(hwaccmR0EnableCpuCallback, (void *)pVM, aRc);
650
651	/* Check the return code of all invocations. */
652	if (RT_SUCCESS(rc))
653	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
654	AssertMsgRC(rc, ("HWACCMR0EnableAllCpus failed for cpu %d with rc=%d\n", idCpu, rc));
655	}
656	else
657	rc = VINF_SUCCESS;
658	}
659
660	return rc;
661	}
662	return VINF_SUCCESS;
663	}
664
665	/**
666	* Disable VT-x or AMD-V on the current CPU
667	*
668	* @returns VBox status code.
669	* @param pVM VM handle (can be 0!)
670	* @param idCpu The identifier for the CPU the function is called on.
671	*/
672	static int hwaccmR0EnableCpu(PVM pVM, RTCPUID idCpu)
673	{
674	void *pvPageCpu;
675	RTHCPHYS pPageCpuPhys;
676	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
677
678	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
679	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
680	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
681	Assert(!pCpu->fConfigured);
682	Assert(!HWACCMR0Globals.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
683
684	pCpu->idCpu = idCpu;
685
686	/* Make sure we start with a clean TLB. */
687	pCpu->fFlushTLB = true;
688
689	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
690	pCpu->cTLBFlushes = 0;
691
692	/* Should never happen */
693	if (!pCpu->pMemObj)
694	{
695	AssertFailed();
696	return VERR_INTERNAL_ERROR;
697	}
698
699	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
700	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
701
702	int rc = HWACCMR0Globals.pfnEnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
703	AssertRC(rc);
704	if (RT_SUCCESS(rc))
705	pCpu->fConfigured = true;
706
707	return rc;
708	}
709
710
711	/**
712	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
713	* is to be called on the target cpus.
714	*
715	* @param idCpu The identifier for the CPU the function is called on.
716	* @param pvUser1 The 1st user argument.
717	* @param pvUser2 The 2nd user argument.
718	*/
719	static DECLCALLBACK(void) hwaccmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
720	{
721	PVM pVM = (PVM)pvUser1; /* can be NULL! */
722	int paRc = (int )pvUser2;
723
724	paRc[idCpu] = hwaccmR0EnableCpu(pVM, idCpu);
725	}
726
727
728	/**
729	* Disable VT-x or AMD-V on the current CPU
730	*
731	* @returns VBox status code.
732	* @param idCpu The identifier for the CPU the function is called on.
733	*/
734	static int hwaccmR0DisableCpu(RTCPUID idCpu)
735	{
736	void *pvPageCpu;
737	RTHCPHYS pPageCpuPhys;
738	int rc;
739	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
740
741	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
742	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
743	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
744	Assert(!HWACCMR0Globals.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
745	Assert(!pCpu->fConfigured \|\| pCpu->pMemObj);
746
747	if (!pCpu->pMemObj)
748	return (pCpu->fConfigured) ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
749
750	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
751	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
752
753	if (pCpu->fConfigured)
754	{
755	rc = HWACCMR0Globals.pfnDisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
756	AssertRC(rc);
757	pCpu->fConfigured = false;
758	}
759	else
760	rc = VINF_SUCCESS; /* nothing to do */
761
762	pCpu->uCurrentASID = 0;
763	return rc;
764	}
765
766	/**
767	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
768	* is to be called on the target cpus.
769	*
770	* @param idCpu The identifier for the CPU the function is called on.
771	* @param pvUser1 The 1st user argument.
772	* @param pvUser2 The 2nd user argument.
773	*/
774	static DECLCALLBACK(void) hwaccmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
775	{
776	int paRc = (int )pvUser1;
777
778	paRc[idCpu] = hwaccmR0DisableCpu(idCpu);
779	}
780
781	/**
782	* Called whenever a system power state change occurs.
783	*
784	* @param enmEvent Power event
785	* @param pvUser User argument
786	*/
787	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
788	{
789	NOREF(pvUser);
790	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
791
792	#ifdef LOG_ENABLED
793	if (enmEvent == RTPOWEREVENT_SUSPEND)
794	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
795	else
796	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_RESUME\n");
797	#endif
798
799	if (enmEvent == RTPOWEREVENT_SUSPEND)
800	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, true);
801
802	if ( HWACCMR0Globals.enmHwAccmState == HWACCMSTATE_ENABLED
803	&& HWACCMR0Globals.fGlobalInit)
804	{
805	int aRc[RTCPUSET_MAX_CPUS];
806	int rc;
807	RTCPUID idCpu;
808
809	memset(aRc, 0, sizeof(aRc));
810	if (enmEvent == RTPOWEREVENT_SUSPEND)
811	{
812	/* Turn off VT-x or AMD-V on all CPUs. */
813	rc = RTMpOnAll(hwaccmR0DisableCpuCallback, aRc, NULL);
814	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
815	}
816	else
817	{
818	/* Reinit the CPUs from scratch as the suspend state has messed with the MSRs. */
819	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)((HWACCMR0Globals.vmx.fSupported) ? X86_CPUID_VENDOR_INTEL_EBX : X86_CPUID_VENDOR_AMD_EBX), aRc);
820	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
821
822	if (RT_SUCCESS(rc))
823	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
824	#ifdef LOG_ENABLED
825	if (RT_FAILURE(rc))
826	SUPR0Printf("hwaccmR0PowerCallback HWACCMR0InitCPU failed with %d\n", rc);
827	#endif
828
829	/* Turn VT-x or AMD-V back on on all CPUs. */
830	rc = RTMpOnAll(hwaccmR0EnableCpuCallback, NULL, aRc);
831	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
832	}
833	}
834	if (enmEvent == RTPOWEREVENT_RESUME)
835	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, false);
836	}
837
838
839	/**
840	* Does Ring-0 per VM HWACCM initialization.
841	*
842	* This is mainly to check that the Host CPU mode is compatible
843	* with VMX.
844	*
845	* @returns VBox status code.
846	* @param pVM The VM to operate on.
847	*/
848	VMMR0DECL(int) HWACCMR0InitVM(PVM pVM)
849	{
850	int rc;
851
852	AssertReturn(pVM, VERR_INVALID_PARAMETER);
853
854	#ifdef LOG_ENABLED
855	SUPR0Printf("HWACCMR0InitVM: %p\n", pVM);
856	#endif
857
858	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
859	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
860	return VERR_HWACCM_SUSPEND_PENDING;
861
862	pVM->hwaccm.s.vmx.fSupported = HWACCMR0Globals.vmx.fSupported;
863	pVM->hwaccm.s.svm.fSupported = HWACCMR0Globals.svm.fSupported;
864
865	pVM->hwaccm.s.vmx.msr.feature_ctrl = HWACCMR0Globals.vmx.msr.feature_ctrl;
866	pVM->hwaccm.s.vmx.hostCR4 = HWACCMR0Globals.vmx.hostCR4;
867	pVM->hwaccm.s.vmx.msr.vmx_basic_info = HWACCMR0Globals.vmx.msr.vmx_basic_info;
868	pVM->hwaccm.s.vmx.msr.vmx_pin_ctls = HWACCMR0Globals.vmx.msr.vmx_pin_ctls;
869	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls = HWACCMR0Globals.vmx.msr.vmx_proc_ctls;
870	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2 = HWACCMR0Globals.vmx.msr.vmx_proc_ctls2;
871	pVM->hwaccm.s.vmx.msr.vmx_exit = HWACCMR0Globals.vmx.msr.vmx_exit;
872	pVM->hwaccm.s.vmx.msr.vmx_entry = HWACCMR0Globals.vmx.msr.vmx_entry;
873	pVM->hwaccm.s.vmx.msr.vmx_misc = HWACCMR0Globals.vmx.msr.vmx_misc;
874	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0;
875	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1;
876	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0;
877	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1;
878	pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum = HWACCMR0Globals.vmx.msr.vmx_vmcs_enum;
879	pVM->hwaccm.s.vmx.msr.vmx_eptcaps = HWACCMR0Globals.vmx.msr.vmx_eptcaps;
880	pVM->hwaccm.s.svm.u32Rev = HWACCMR0Globals.svm.u32Rev;
881	pVM->hwaccm.s.svm.u32Features = HWACCMR0Globals.svm.u32Features;
882	pVM->hwaccm.s.cpuid.u32AMDFeatureECX = HWACCMR0Globals.cpuid.u32AMDFeatureECX;
883	pVM->hwaccm.s.cpuid.u32AMDFeatureEDX = HWACCMR0Globals.cpuid.u32AMDFeatureEDX;
884	pVM->hwaccm.s.lLastError = HWACCMR0Globals.lLastError;
885
886	pVM->hwaccm.s.uMaxASID = HWACCMR0Globals.uMaxASID;
887
888
889	if (!pVM->hwaccm.s.cMaxResumeLoops) /* allow ring-3 overrides */
890	{
891	pVM->hwaccm.s.cMaxResumeLoops = 1024;
892	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
893	if (RTThreadPreemptIsPendingTrusty())
894	pVM->hwaccm.s.cMaxResumeLoops = 8192;
895	#endif
896	}
897
898	for (VMCPUID i = 0; i < pVM->cCpus; i++)
899	{
900	PVMCPU pVCpu = &pVM->aCpus[i];
901
902	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
903
904	/* Invalidate the last cpu we were running on. */
905	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
906
907	/* we'll aways increment this the first time (host uses ASID 0) */
908	pVCpu->hwaccm.s.uCurrentASID = 0;
909	}
910
911	RTCCUINTREG fFlags = ASMIntDisableFlags();
912	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
913
914	/* Note: Not correct as we can be rescheduled to a different cpu, but the fInUse case is mostly for debugging. */
915	ASMAtomicWriteBool(&pCpu->fInUse, true);
916	ASMSetFlags(fFlags);
917
918	/* Init a VT-x or AMD-V VM. */
919	rc = HWACCMR0Globals.pfnInitVM(pVM);
920
921	ASMAtomicWriteBool(&pCpu->fInUse, false);
922	return rc;
923	}
924
925
926	/**
927	* Does Ring-0 per VM HWACCM termination.
928	*
929	* @returns VBox status code.
930	* @param pVM The VM to operate on.
931	*/
932	VMMR0DECL(int) HWACCMR0TermVM(PVM pVM)
933	{
934	int rc;
935
936	AssertReturn(pVM, VERR_INVALID_PARAMETER);
937
938	#ifdef LOG_ENABLED
939	SUPR0Printf("HWACCMR0TermVM: %p\n", pVM);
940	#endif
941
942	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
943	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
944
945	/* @note Not correct as we can be rescheduled to a different cpu, but the fInUse case is mostly for debugging. */
946	RTCCUINTREG fFlags = ASMIntDisableFlags();
947	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
948
949	ASMAtomicWriteBool(&pCpu->fInUse, true);
950	ASMSetFlags(fFlags);
951
952	/* Terminate a VT-x or AMD-V VM. */
953	rc = HWACCMR0Globals.pfnTermVM(pVM);
954
955	ASMAtomicWriteBool(&pCpu->fInUse, false);
956	return rc;
957	}
958
959
960	/**
961	* Sets up a VT-x or AMD-V session
962	*
963	* @returns VBox status code.
964	* @param pVM The VM to operate on.
965	*/
966	VMMR0DECL(int) HWACCMR0SetupVM(PVM pVM)
967	{
968	int rc;
969	RTCPUID idCpu = RTMpCpuId();
970	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
971
972	AssertReturn(pVM, VERR_INVALID_PARAMETER);
973
974	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
975	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
976
977	#ifdef LOG_ENABLED
978	SUPR0Printf("HWACCMR0SetupVM: %p\n", pVM);
979	#endif
980
981	ASMAtomicWriteBool(&pCpu->fInUse, true);
982
983	for (VMCPUID i = 0; i < pVM->cCpus; i++)
984	{
985	/* On first entry we'll sync everything. */
986	pVM->aCpus[i].hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
987	}
988
989	/* Enable VT-x or AMD-V if local init is required. */
990	if (!HWACCMR0Globals.fGlobalInit)
991	{
992	rc = hwaccmR0EnableCpu(pVM, idCpu);
993	AssertRC(rc);
994	}
995
996	/* Setup VT-x or AMD-V. */
997	rc = HWACCMR0Globals.pfnSetupVM(pVM);
998
999	/* Disable VT-x or AMD-V if local init was done before. */
1000	if (!HWACCMR0Globals.fGlobalInit)
1001	{
1002	rc = hwaccmR0DisableCpu(idCpu);
1003	AssertRC(rc);
1004	}
1005
1006	ASMAtomicWriteBool(&pCpu->fInUse, false);
1007
1008	return rc;
1009	}
1010
1011
1012	/**
1013	* Enters the VT-x or AMD-V session
1014	*
1015	* @returns VBox status code.
1016	* @param pVM The VM to operate on.
1017	* @param pVCpu VMCPUD id.
1018	*/
1019	VMMR0DECL(int) HWACCMR0Enter(PVM pVM, PVMCPU pVCpu)
1020	{
1021	PCPUMCTX pCtx;
1022	int rc;
1023	RTCPUID idCpu = RTMpCpuId();
1024	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1025
1026	/* Make sure we can't enter a session after we've disabled hwaccm in preparation of a suspend. */
1027	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1028	ASMAtomicWriteBool(&pCpu->fInUse, true);
1029
1030	AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == NIL_RTCPUID, ("%d", (int)pVCpu->hwaccm.s.idEnteredCpu));
1031	pVCpu->hwaccm.s.idEnteredCpu = idCpu;
1032
1033	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1034
1035	/* Always load the guest's FPU/XMM state on-demand. */
1036	CPUMDeactivateGuestFPUState(pVCpu);
1037
1038	/* Always load the guest's debug state on-demand. */
1039	CPUMDeactivateGuestDebugState(pVCpu);
1040
1041	/* Always reload the host context and the guest's CR0 register. (!!!!) */
1042	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0 \| HWACCM_CHANGED_HOST_CONTEXT;
1043
1044	/* Setup the register and mask according to the current execution mode. */
1045	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1046	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFFFFFFFFFF);
1047	else
1048	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFF);
1049
1050	/* Enable VT-x or AMD-V if local init is required. */
1051	if (!HWACCMR0Globals.fGlobalInit)
1052	{
1053	rc = hwaccmR0EnableCpu(pVM, idCpu);
1054	AssertRC(rc);
1055	}
1056
1057	rc = HWACCMR0Globals.pfnEnterSession(pVM, pVCpu, pCpu);
1058	AssertRC(rc);
1059	/* We must save the host context here (VT-x) as we might be rescheduled on a different cpu after a long jump back to ring 3. */
1060	rc \|= HWACCMR0Globals.pfnSaveHostState(pVM, pVCpu);
1061	AssertRC(rc);
1062	rc \|= HWACCMR0Globals.pfnLoadGuestState(pVM, pVCpu, pCtx);
1063	AssertRC(rc);
1064
1065	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1066	if (RT_SUCCESS(rc))
1067	{
1068	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1069	PGMDynMapMigrateAutoSet(pVCpu);
1070	#endif
1071	}
1072	else
1073	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1074	return rc;
1075	}
1076
1077
1078	/**
1079	* Leaves the VT-x or AMD-V session
1080	*
1081	* @returns VBox status code.
1082	* @param pVM The VM to operate on.
1083	* @param pVCpu VMCPUD id.
1084	*/
1085	VMMR0DECL(int) HWACCMR0Leave(PVM pVM, PVMCPU pVCpu)
1086	{
1087	PCPUMCTX pCtx;
1088	int rc;
1089	RTCPUID idCpu = RTMpCpuId();
1090	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1091
1092	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1093
1094	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1095
1096	/* Note: It's rather tricky with longjmps done by e.g. Log statements or the page fault handler.
1097	* We must restore the host FPU here to make absolutely sure we don't leave the guest FPU state active
1098	* or trash somebody else's FPU state.
1099	*/
1100	/* Save the guest FPU and XMM state if necessary. */
1101	if (CPUMIsGuestFPUStateActive(pVCpu))
1102	{
1103	Log2(("CPUMR0SaveGuestFPU\n"));
1104	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
1105
1106	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1107	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1108	}
1109
1110	rc = HWACCMR0Globals.pfnLeaveSession(pVM, pVCpu, pCtx);
1111
1112	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1113	#ifdef RT_STRICT
1114	if (RT_UNLIKELY( pVCpu->hwaccm.s.idEnteredCpu != idCpu
1115	&& RT_FAILURE(rc)))
1116	{
1117	AssertMsgFailed(("Owner is %d, I'm %d", (int)pVCpu->hwaccm.s.idEnteredCpu, (int)idCpu));
1118	rc = VERR_INTERNAL_ERROR;
1119	}
1120	#endif
1121	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1122
1123	/* Disable VT-x or AMD-V if local init was done before. */
1124	if (!HWACCMR0Globals.fGlobalInit)
1125	{
1126	rc = hwaccmR0DisableCpu(idCpu);
1127	AssertRC(rc);
1128
1129	/* Reset these to force a TLB flush for the next entry. (-> EXPENSIVE) */
1130	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
1131	pVCpu->hwaccm.s.uCurrentASID = 0;
1132	}
1133
1134	ASMAtomicWriteBool(&pCpu->fInUse, false);
1135	return rc;
1136	}
1137
1138	/**
1139	* Runs guest code in a hardware accelerated VM.
1140	*
1141	* @returns VBox status code.
1142	* @param pVM The VM to operate on.
1143	* @param pVCpu VMCPUD id.
1144	*/
1145	VMMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1146	{
1147	CPUMCTX *pCtx;
1148	int rc;
1149	#ifdef VBOX_STRICT
1150	RTCPUID idCpu = RTMpCpuId(); NOREF(idCpu);
1151	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1152	#endif
1153
1154	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1155	Assert(HWACCMR0Globals.aCpuInfo[idCpu].fConfigured);
1156	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1157	Assert(ASMAtomicReadBool(&pCpu->fInUse) == true);
1158
1159	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1160	PGMDynMapStartAutoSet(pVCpu);
1161	#endif
1162
1163	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1164
1165	rc = HWACCMR0Globals.pfnRunGuestCode(pVM, pVCpu, pCtx);
1166
1167	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1168	PGMDynMapReleaseAutoSet(pVCpu);
1169	#endif
1170	return rc;
1171	}
1172
1173
1174	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1175	/**
1176	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1177	*
1178	* @returns VBox status code.
1179	* @param pVM VM handle.
1180	* @param pVCpu VMCPU handle.
1181	* @param pCtx CPU context
1182	*/
1183	VMMR0DECL(int) HWACCMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1184	{
1185	if (pVM->hwaccm.s.vmx.fSupported)
1186	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1187
1188	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1189	}
1190
1191	/**
1192	* Save guest debug state (64 bits guest mode & 32 bits host only)
1193	*
1194	* @returns VBox status code.
1195	* @param pVM VM handle.
1196	* @param pVCpu VMCPU handle.
1197	* @param pCtx CPU context
1198	*/
1199	VMMR0DECL(int) HWACCMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1200	{
1201	if (pVM->hwaccm.s.vmx.fSupported)
1202	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1203
1204	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1205	}
1206
1207	/**
1208	* Test the 32->64 bits switcher
1209	*
1210	* @returns VBox status code.
1211	* @param pVM VM handle.
1212	*/
1213	VMMR0DECL(int) HWACCMR0TestSwitcher3264(PVM pVM)
1214	{
1215	PVMCPU pVCpu = &pVM->aCpus[0];
1216	CPUMCTX *pCtx;
1217	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1218	int rc;
1219
1220	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1221
1222	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1223	if (pVM->hwaccm.s.vmx.fSupported)
1224	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1225	else
1226	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1227	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1228	return rc;
1229	}
1230
1231	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1232
1233	/**
1234	* Returns suspend status of the host
1235	*
1236	* @returns Suspend pending or not
1237	*/
1238	VMMR0DECL(bool) HWACCMR0SuspendPending()
1239	{
1240	return ASMAtomicReadBool(&HWACCMR0Globals.fSuspended);
1241	}
1242
1243	/**
1244	* Returns the cpu structure for the current cpu.
1245	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1246	*
1247	* @returns cpu structure pointer
1248	*/
1249	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu()
1250	{
1251	RTCPUID idCpu = RTMpCpuId();
1252
1253	return &HWACCMR0Globals.aCpuInfo[idCpu];
1254	}
1255
1256	/**
1257	* Returns the cpu structure for the current cpu.
1258	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1259	*
1260	* @returns cpu structure pointer
1261	* @param idCpu id of the VCPU
1262	*/
1263	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu)
1264	{
1265	return &HWACCMR0Globals.aCpuInfo[idCpu];
1266	}
1267
1268	/**
1269	* Returns the VMCPU of the current EMT thread.
1270	*
1271	* @param pVM The VM to operate on.
1272	*/
1273	VMMR0DECL(PVMCPU) HWACCMR0GetVMCPU(PVM pVM)
1274	{
1275	/* RTMpCpuId had better be cheap. */
1276	RTCPUID idHostCpu = RTMpCpuId();
1277
1278	/** @todo optimize for large number of VCPUs when that becomes more common. */
1279	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1280	{
1281	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1282
1283	if (pVCpu->hwaccm.s.idEnteredCpu == idHostCpu)
1284	return pVCpu;
1285	}
1286	return NULL;
1287	}
1288
1289	/**
1290	* Returns the VMCPU id of the current EMT thread.
1291	*
1292	* @param pVM The VM to operate on.
1293	*/
1294	VMMR0DECL(VMCPUID) HWACCMR0GetVMCPUId(PVM pVM)
1295	{
1296	PVMCPU pVCpu = HWACCMR0GetVMCPU(pVM);
1297	if (pVCpu)
1298	return pVCpu->idCpu;
1299
1300	return 0;
1301	}
1302
1303	/**
1304	* Save a pending IO read.
1305	*
1306	* @param pVCpu The VMCPU to operate on.
1307	* @param GCPtrRip Address of IO instruction
1308	* @param GCPtrRipNext Address of the next instruction
1309	* @param uPort Port address
1310	* @param uAndVal And mask for saving the result in eax
1311	* @param cbSize Read size
1312	*/
1313	VMMR0DECL(void) HWACCMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1314	{
1315	pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_PORT_READ;
1316	pVCpu->hwaccm.s.PendingIO.GCPtrRip = GCPtrRip;
1317	pVCpu->hwaccm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1318	pVCpu->hwaccm.s.PendingIO.s.Port.uPort = uPort;
1319	pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal = uAndVal;
1320	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize = cbSize;
1321	return;
1322	}
1323
1324	/**
1325	* Save a pending IO write.
1326	*
1327	* @param pVCpu The VMCPU to operate on.
1328	* @param GCPtrRIP Address of IO instruction
1329	* @param uPort Port address
1330	* @param uAndVal And mask for fetching the result from eax
1331	* @param cbSize Read size
1332	*/
1333	VMMR0DECL(void) HWACCMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1334	{
1335	pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_PORT_WRITE;
1336	pVCpu->hwaccm.s.PendingIO.GCPtrRip = GCPtrRip;
1337	pVCpu->hwaccm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1338	pVCpu->hwaccm.s.PendingIO.s.Port.uPort = uPort;
1339	pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal = uAndVal;
1340	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize = cbSize;
1341	return;
1342	}
1343
1344	/**
1345	* Disable VT-x if it's active and the current switcher turns off paging
1346	*
1347	* @returns VBox status code.
1348	* @param pVM VM handle.
1349	* @param pfVTxDisabled VT-x was disabled or not (out)
1350	*/
1351	VMMR0DECL(int) HWACCMR0EnterSwitcher(PVM pVM, bool *pfVTxDisabled)
1352	{
1353	Assert(!(ASMGetFlags() & X86_EFL_IF));
1354
1355	*pfVTxDisabled = false;
1356
1357	if ( HWACCMR0Globals.enmHwAccmState != HWACCMSTATE_ENABLED
1358	\|\| !HWACCMR0Globals.vmx.fSupported /* no such issues with AMD-V */
1359	\|\| !pVM->hwaccm.s.fGlobalInit /* Local init implies the CPU is currently not in VMX root mode. */)
1360	return VINF_SUCCESS; /* nothing to do */
1361
1362	switch(VMMGetSwitcher(pVM))
1363	{
1364	case VMMSWITCHER_32_TO_32:
1365	case VMMSWITCHER_PAE_TO_PAE:
1366	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1367
1368	case VMMSWITCHER_32_TO_PAE:
1369	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1370	case VMMSWITCHER_AMD64_TO_32:
1371	case VMMSWITCHER_AMD64_TO_PAE:
1372	break; /* unsafe switchers */
1373
1374	default:
1375	AssertFailed();
1376	return VERR_INTERNAL_ERROR;
1377	}
1378
1379	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1380	void *pvPageCpu;
1381	RTHCPHYS pPageCpuPhys;
1382
1383	AssertReturn(pCpu && pCpu->pMemObj, VERR_INTERNAL_ERROR);
1384	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
1385	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
1386
1387	*pfVTxDisabled = true;
1388	return VMXR0DisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
1389	}
1390
1391	/**
1392	* Reeable VT-x if was active and the current switcher turned off paging
1393	*
1394	* @returns VBox status code.
1395	* @param pVM VM handle.
1396	* @param fVTxDisabled VT-x was disabled or not
1397	*/
1398	VMMR0DECL(int) HWACCMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1399	{
1400	Assert(!(ASMGetFlags() & X86_EFL_IF));
1401
1402	if (!fVTxDisabled)
1403	return VINF_SUCCESS; /* nothing to do */
1404
1405	Assert( HWACCMR0Globals.enmHwAccmState == HWACCMSTATE_ENABLED
1406	&& HWACCMR0Globals.vmx.fSupported
1407	&& pVM->hwaccm.s.fGlobalInit);
1408
1409	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1410	void *pvPageCpu;
1411	RTHCPHYS pPageCpuPhys;
1412
1413	AssertReturn(pCpu && pCpu->pMemObj, VERR_INTERNAL_ERROR);
1414	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
1415	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
1416
1417	return VMXR0EnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
1418	}
1419
1420	#ifdef VBOX_STRICT
1421	/**
1422	* Dumps a descriptor.
1423	*
1424	* @param pDesc Descriptor to dump.
1425	* @param Sel Selector number.
1426	* @param pszMsg Message to prepend the log entry with.
1427	*/
1428	VMMR0DECL(void) HWACCMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1429	{
1430	/*
1431	* Make variable description string.
1432	*/
1433	static struct
1434	{
1435	unsigned cch;
1436	const char *psz;
1437	} const s_aTypes[32] =
1438	{
1439	# define STRENTRY(str) { sizeof(str) - 1, str }
1440
1441	/* system */
1442	# if HC_ARCH_BITS == 64
1443	STRENTRY("Reserved0 "), /* 0x00 */
1444	STRENTRY("Reserved1 "), /* 0x01 */
1445	STRENTRY("LDT "), /* 0x02 */
1446	STRENTRY("Reserved3 "), /* 0x03 */
1447	STRENTRY("Reserved4 "), /* 0x04 */
1448	STRENTRY("Reserved5 "), /* 0x05 */
1449	STRENTRY("Reserved6 "), /* 0x06 */
1450	STRENTRY("Reserved7 "), /* 0x07 */
1451	STRENTRY("Reserved8 "), /* 0x08 */
1452	STRENTRY("TSS64Avail "), /* 0x09 */
1453	STRENTRY("ReservedA "), /* 0x0a */
1454	STRENTRY("TSS64Busy "), /* 0x0b */
1455	STRENTRY("Call64 "), /* 0x0c */
1456	STRENTRY("ReservedD "), /* 0x0d */
1457	STRENTRY("Int64 "), /* 0x0e */
1458	STRENTRY("Trap64 "), /* 0x0f */
1459	# else
1460	STRENTRY("Reserved0 "), /* 0x00 */
1461	STRENTRY("TSS16Avail "), /* 0x01 */
1462	STRENTRY("LDT "), /* 0x02 */
1463	STRENTRY("TSS16Busy "), /* 0x03 */
1464	STRENTRY("Call16 "), /* 0x04 */
1465	STRENTRY("Task "), /* 0x05 */
1466	STRENTRY("Int16 "), /* 0x06 */
1467	STRENTRY("Trap16 "), /* 0x07 */
1468	STRENTRY("Reserved8 "), /* 0x08 */
1469	STRENTRY("TSS32Avail "), /* 0x09 */
1470	STRENTRY("ReservedA "), /* 0x0a */
1471	STRENTRY("TSS32Busy "), /* 0x0b */
1472	STRENTRY("Call32 "), /* 0x0c */
1473	STRENTRY("ReservedD "), /* 0x0d */
1474	STRENTRY("Int32 "), /* 0x0e */
1475	STRENTRY("Trap32 "), /* 0x0f */
1476	# endif
1477	/* non system */
1478	STRENTRY("DataRO "), /* 0x10 */
1479	STRENTRY("DataRO Accessed "), /* 0x11 */
1480	STRENTRY("DataRW "), /* 0x12 */
1481	STRENTRY("DataRW Accessed "), /* 0x13 */
1482	STRENTRY("DataDownRO "), /* 0x14 */
1483	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1484	STRENTRY("DataDownRW "), /* 0x16 */
1485	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1486	STRENTRY("CodeEO "), /* 0x18 */
1487	STRENTRY("CodeEO Accessed "), /* 0x19 */
1488	STRENTRY("CodeER "), /* 0x1a */
1489	STRENTRY("CodeER Accessed "), /* 0x1b */
1490	STRENTRY("CodeConfEO "), /* 0x1c */
1491	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1492	STRENTRY("CodeConfER "), /* 0x1e */
1493	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1494	# undef SYSENTRY
1495	};
1496	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1497	char szMsg[128];
1498	char *psz = &szMsg[0];
1499	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1500	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1501	psz += s_aTypes[i].cch;
1502
1503	if (pDesc->Gen.u1Present)
1504	ADD_STR(psz, "Present ");
1505	else
1506	ADD_STR(psz, "Not-Present ");
1507	# if HC_ARCH_BITS == 64
1508	if (pDesc->Gen.u1Long)
1509	ADD_STR(psz, "64-bit ");
1510	else
1511	ADD_STR(psz, "Comp ");
1512	# else
1513	if (pDesc->Gen.u1Granularity)
1514	ADD_STR(psz, "Page ");
1515	if (pDesc->Gen.u1DefBig)
1516	ADD_STR(psz, "32-bit ");
1517	else
1518	ADD_STR(psz, "16-bit ");
1519	# endif
1520	# undef ADD_STR
1521	*psz = '\0';
1522
1523	/*
1524	* Limit and Base and format the output.
1525	*/
1526	uint32_t u32Limit = X86DESC_LIMIT(*pDesc);
1527	if (pDesc->Gen.u1Granularity)
1528	u32Limit = u32Limit << PAGE_SHIFT \| PAGE_OFFSET_MASK;
1529
1530	# if HC_ARCH_BITS == 64
1531	uint64_t u32Base = X86DESC64_BASE(*pDesc);
1532
1533	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1534	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1535	# else
1536	uint32_t u32Base = X86DESC_BASE(*pDesc);
1537
1538	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1539	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1540	# endif
1541	}
1542
1543	/**
1544	* Formats a full register dump.
1545	*
1546	* @param pVM The VM to operate on.
1547	* @param pVCpu The VMCPU to operate on.
1548	* @param pCtx The context to format.
1549	*/
1550	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1551	{
1552	/*
1553	* Format the flags.
1554	*/
1555	static struct
1556	{
1557	const char pszSet; const char pszClear; uint32_t fFlag;
1558	} aFlags[] =
1559	{
1560	{ "vip",NULL, X86_EFL_VIP },
1561	{ "vif",NULL, X86_EFL_VIF },
1562	{ "ac", NULL, X86_EFL_AC },
1563	{ "vm", NULL, X86_EFL_VM },
1564	{ "rf", NULL, X86_EFL_RF },
1565	{ "nt", NULL, X86_EFL_NT },
1566	{ "ov", "nv", X86_EFL_OF },
1567	{ "dn", "up", X86_EFL_DF },
1568	{ "ei", "di", X86_EFL_IF },
1569	{ "tf", NULL, X86_EFL_TF },
1570	{ "nt", "pl", X86_EFL_SF },
1571	{ "nz", "zr", X86_EFL_ZF },
1572	{ "ac", "na", X86_EFL_AF },
1573	{ "po", "pe", X86_EFL_PF },
1574	{ "cy", "nc", X86_EFL_CF },
1575	};
1576	char szEFlags[80];
1577	char *psz = szEFlags;
1578	uint32_t efl = pCtx->eflags.u32;
1579	for (unsigned i = 0; i < RT_ELEMENTS(aFlags); i++)
1580	{
1581	const char *pszAdd = aFlags[i].fFlag & efl ? aFlags[i].pszSet : aFlags[i].pszClear;
1582	if (pszAdd)
1583	{
1584	strcpy(psz, pszAdd);
1585	psz += strlen(pszAdd);
1586	*psz++ = ' ';
1587	}
1588	}
1589	psz[-1] = '\0';
1590
1591
1592	/*
1593	* Format the registers.
1594	*/
1595	if (CPUMIsGuestIn64BitCode(pVCpu, CPUMCTX2CORE(pCtx)))
1596	{
1597	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1598	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1599	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1600	"r14=%016RX64 r15=%016RX64\n"
1601	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1602	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1603	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1604	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1605	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1606	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1607	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1608	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1609	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1610	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1611	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1612	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1613	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1614	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1615	,
1616	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1617	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1618	pCtx->r14, pCtx->r15,
1619	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1620	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1621	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1622	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1623	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1624	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1625	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1626	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1627	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1628	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1629	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1630	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1631	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1632	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1633	}
1634	else
1635	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1636	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1637	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1638	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1639	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1640	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1641	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1642	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1643	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1644	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1645	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1646	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1647	,
1648	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1649	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1650	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr[0], pCtx->dr[1],
1651	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr[2], pCtx->dr[3],
1652	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr[4], pCtx->dr[5],
1653	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr[6], pCtx->dr[7],
1654	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0, pCtx->cr2,
1655	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3, pCtx->cr4,
1656	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1657	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1658	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1659	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1660
1661	Log(("FPU:\n"
1662	"FCW=%04x FSW=%04x FTW=%02x\n"
1663	"res1=%02x FOP=%04x FPUIP=%08x CS=%04x Rsvrd1=%04x\n"
1664	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1665	,
1666	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
1667	pCtx->fpu.huh1, pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsvrd1,
1668	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
1669	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
1670
1671
1672	Log(("MSR:\n"
1673	"EFER =%016RX64\n"
1674	"PAT =%016RX64\n"
1675	"STAR =%016RX64\n"
1676	"CSTAR =%016RX64\n"
1677	"LSTAR =%016RX64\n"
1678	"SFMASK =%016RX64\n"
1679	"KERNELGSBASE =%016RX64\n",
1680	pCtx->msrEFER,
1681	pCtx->msrPAT,
1682	pCtx->msrSTAR,
1683	pCtx->msrCSTAR,
1684	pCtx->msrLSTAR,
1685	pCtx->msrSFMASK,
1686	pCtx->msrKERNELGSBASE));
1687
1688	}
1689	#endif /* VBOX_STRICT */
1690
1691	/* Dummy callback handlers. */
1692	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
1693	{
1694	return VINF_SUCCESS;
1695	}
1696
1697	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1698	{
1699	return VINF_SUCCESS;
1700	}
1701
1702	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1703	{
1704	return VINF_SUCCESS;
1705	}
1706
1707	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1708	{
1709	return VINF_SUCCESS;
1710	}
1711
1712	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM)
1713	{
1714	return VINF_SUCCESS;
1715	}
1716
1717	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM)
1718	{
1719	return VINF_SUCCESS;
1720	}
1721
1722	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM)
1723	{
1724	return VINF_SUCCESS;
1725	}
1726
1727	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1728	{
1729	return VINF_SUCCESS;
1730	}
1731
1732	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
1733	{
1734	return VINF_SUCCESS;
1735	}
1736
1737	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1738	{
1739	return VINF_SUCCESS;
1740	}

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp@ 23570

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