HWACCMR0.cpp@ 26005

Last change on this file since 26005 was 25931, checked in by vboxsync, 15 years ago
Added VBOX_HWVIRTEX_IGNORE_SVM_IN_USE environment variable check to enable hack for disregarding VERR_SVM_IN_USE errors (quite a few BIOSes around that incorrectly set EFER.SVME).
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 65.2 KB

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1	/* $Id: HWACCMR0.cpp 25931 2010-01-20 14:05:01Z vboxsync $ */
2	/** @file
3	* HWACCM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_vmx.h>
32	#include <VBox/hwacc_svm.h>
33	#include <VBox/pgm.h>
34	#include <VBox/pdm.h>
35	#include <VBox/err.h>
36	#include <VBox/log.h>
37	#include <VBox/selm.h>
38	#include <VBox/iom.h>
39	#include <iprt/assert.h>
40	#include <iprt/asm.h>
41	#include <iprt/cpuset.h>
42	#include <iprt/memobj.h>
43	#include <iprt/param.h>
44	#include <iprt/power.h>
45	#include <iprt/string.h>
46	#include <iprt/thread.h>
47	#include "HWVMXR0.h"
48	#include "HWSVMR0.h"
49
50	/*******************************************************************************
51	* Internal Functions *
52	*******************************************************************************/
53	static DECLCALLBACK(void) hwaccmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hwaccmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
55	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
56	static int hwaccmR0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu);
57	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
58
59	/*******************************************************************************
60	* Global Variables *
61	*******************************************************************************/
62
63	static struct
64	{
65	HWACCM_CPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
66
67	/** Ring 0 handlers for VT-x and AMD-V. */
68	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu));
69	DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
70	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
71	DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
72	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
73	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
74	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
75	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
76	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
77	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVM pVM));
78
79	/** Maximum ASID allowed. */
80	uint32_t uMaxASID;
81
82	struct
83	{
84	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
85	bool fSupported;
86	/** Whether we're using SUPR0EnableVTx or not. */
87	bool fUsingSUPR0EnableVTx;
88
89	/** Host CR4 value (set by ring-0 VMX init) */
90	uint64_t hostCR4;
91
92	/** VMX MSR values */
93	struct
94	{
95	uint64_t feature_ctrl;
96	uint64_t vmx_basic_info;
97	VMX_CAPABILITY vmx_pin_ctls;
98	VMX_CAPABILITY vmx_proc_ctls;
99	VMX_CAPABILITY vmx_proc_ctls2;
100	VMX_CAPABILITY vmx_exit;
101	VMX_CAPABILITY vmx_entry;
102	uint64_t vmx_misc;
103	uint64_t vmx_cr0_fixed0;
104	uint64_t vmx_cr0_fixed1;
105	uint64_t vmx_cr4_fixed0;
106	uint64_t vmx_cr4_fixed1;
107	uint64_t vmx_vmcs_enum;
108	uint64_t vmx_eptcaps;
109	} msr;
110	/* Last instruction error */
111	uint32_t ulLastInstrError;
112	} vmx;
113	struct
114	{
115	/* HWCR msr (for diagnostics) */
116	uint64_t msrHWCR;
117
118	/** SVM revision. */
119	uint32_t u32Rev;
120
121	/** SVM feature bits from cpuid 0x8000000a */
122	uint32_t u32Features;
123
124	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
125	bool fSupported;
126	} svm;
127	/** Saved error from detection */
128	int32_t lLastError;
129
130	struct
131	{
132	uint32_t u32AMDFeatureECX;
133	uint32_t u32AMDFeatureEDX;
134	} cpuid;
135
136	HWACCMSTATE enmHwAccmState;
137
138	bool fGlobalInit;
139	volatile bool fSuspended;
140	} HWACCMR0Globals;
141
142
143
144	/**
145	* Does global Ring-0 HWACCM initialization.
146	*
147	* @returns VBox status code.
148	*/
149	VMMR0DECL(int) HWACCMR0Init(void)
150	{
151	int rc;
152	bool fAMDVPresent = false;
153
154	memset(&HWACCMR0Globals, 0, sizeof(HWACCMR0Globals));
155	HWACCMR0Globals.enmHwAccmState = HWACCMSTATE_UNINITIALIZED;
156	for (unsigned i = 0; i < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); i++)
157	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
158
159	/* Fill in all callbacks with placeholders. */
160	HWACCMR0Globals.pfnEnterSession = HWACCMR0DummyEnter;
161	HWACCMR0Globals.pfnLeaveSession = HWACCMR0DummyLeave;
162	HWACCMR0Globals.pfnSaveHostState = HWACCMR0DummySaveHostState;
163	HWACCMR0Globals.pfnLoadGuestState = HWACCMR0DummyLoadGuestState;
164	HWACCMR0Globals.pfnRunGuestCode = HWACCMR0DummyRunGuestCode;
165	HWACCMR0Globals.pfnEnableCpu = HWACCMR0DummyEnableCpu;
166	HWACCMR0Globals.pfnDisableCpu = HWACCMR0DummyDisableCpu;
167	HWACCMR0Globals.pfnInitVM = HWACCMR0DummyInitVM;
168	HWACCMR0Globals.pfnTermVM = HWACCMR0DummyTermVM;
169	HWACCMR0Globals.pfnSetupVM = HWACCMR0DummySetupVM;
170
171	/* Default is global VT-x/AMD-V init */
172	HWACCMR0Globals.fGlobalInit = true;
173
174	/*
175	* Check for VT-x and AMD-V capabilities
176	*/
177	if (ASMHasCpuId())
178	{
179	uint32_t u32FeaturesECX;
180	uint32_t u32Dummy;
181	uint32_t u32FeaturesEDX;
182	uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
183
184	ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
185	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
186	/* Query AMD features. */
187	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy, &HWACCMR0Globals.cpuid.u32AMDFeatureECX, &HWACCMR0Globals.cpuid.u32AMDFeatureEDX);
188
189	if ( u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
190	&& u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
191	&& u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX
192	)
193	{
194	/*
195	* Read all VMX MSRs if VMX is available. (same goes for RDMSR/WRMSR)
196	* We also assume all VMX-enabled CPUs support fxsave/fxrstor.
197	*/
198	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
199	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
200	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
201	)
202	{
203	int aRc[RTCPUSET_MAX_CPUS];
204	RTCPUID idCpu = 0;
205
206	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
207
208	/*
209	* First try use native kernel API for controlling VT-x.
210	* (This is only supported by some Mac OS X kernels atm.)
211	*/
212	HWACCMR0Globals.lLastError = rc = SUPR0EnableVTx(true /* fEnable */);
213	if (rc != VERR_NOT_SUPPORTED)
214	{
215	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
216	HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx = true;
217	if (RT_SUCCESS(rc))
218	{
219	HWACCMR0Globals.vmx.fSupported = true;
220	rc = SUPR0EnableVTx(false /* fEnable */);
221	AssertRC(rc);
222	}
223	}
224	else
225	{
226	HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx = false;
227
228	/* We need to check if VT-x has been properly initialized on all CPUs. Some BIOSes do a lousy job. */
229	memset(aRc, 0, sizeof(aRc));
230	HWACCMR0Globals.lLastError = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
231
232	/* Check the return code of all invocations. */
233	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
234	HWACCMR0Globals.lLastError = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
235	}
236	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
237	{
238	/* Reread in case we've changed it. */
239	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
240
241	if ( (HWACCMR0Globals.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
242	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
243	{
244	RTR0MEMOBJ pScatchMemObj;
245	void *pvScatchPage;
246	RTHCPHYS pScatchPagePhys;
247
248	HWACCMR0Globals.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
249	HWACCMR0Globals.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
250	HWACCMR0Globals.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
251	HWACCMR0Globals.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
252	HWACCMR0Globals.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
253	HWACCMR0Globals.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
254	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
255	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
256	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
257	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
258	HWACCMR0Globals.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
259	/* VPID 16 bits ASID. */
260	HWACCMR0Globals.uMaxASID = 0x10000; /* exclusive */
261
262	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
263	{
264	HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
265	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT\|VMX_VMCS_CTRL_PROC_EXEC2_VPID))
266	HWACCMR0Globals.vmx.msr.vmx_eptcaps = ASMRdMsr(MSR_IA32_VMX_EPT_CAPS);
267	}
268
269	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
270	{
271	HWACCMR0Globals.vmx.hostCR4 = ASMGetCR4();
272
273	rc = RTR0MemObjAllocCont(&pScatchMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
274	if (RT_FAILURE(rc))
275	return rc;
276
277	pvScatchPage = RTR0MemObjAddress(pScatchMemObj);
278	pScatchPagePhys = RTR0MemObjGetPagePhysAddr(pScatchMemObj, 0);
279	memset(pvScatchPage, 0, PAGE_SIZE);
280
281	/* Set revision dword at the beginning of the structure. */
282	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(HWACCMR0Globals.vmx.msr.vmx_basic_info);
283
284	/* Make sure we don't get rescheduled to another cpu during this probe. */
285	RTCCUINTREG fFlags = ASMIntDisableFlags();
286
287	/*
288	* Check CR4.VMXE
289	*/
290	if (!(HWACCMR0Globals.vmx.hostCR4 & X86_CR4_VMXE))
291	{
292	/* In theory this bit could be cleared behind our back. Which would cause #UD faults when we
293	* try to execute the VMX instructions...
294	*/
295	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4 \| X86_CR4_VMXE);
296	}
297
298	/* Enter VMX Root Mode */
299	rc = VMXEnable(pScatchPagePhys);
300	if (RT_FAILURE(rc))
301	{
302	/* KVM leaves the CPU in VMX root mode. Not only is this not allowed, it will crash the host when we enter raw mode, because
303	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify this bit)
304	* (b) turning off paging causes a #GP (unavoidable when switching from long to 32 bits mode or 32 bits to PAE)
305	*
306	* They should fix their code, but until they do we simply refuse to run.
307	*/
308	HWACCMR0Globals.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
309	}
310	else
311	{
312	HWACCMR0Globals.vmx.fSupported = true;
313	VMXDisable();
314	}
315
316	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it wasn't so before (some software could incorrectly think it's in VMX mode) */
317	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4);
318	ASMSetFlags(fFlags);
319
320	RTR0MemObjFree(pScatchMemObj, false);
321	if (RT_FAILURE(HWACCMR0Globals.lLastError))
322	return HWACCMR0Globals.lLastError;
323	}
324	}
325	else
326	{
327	AssertFailed(); /* can't hit this case anymore */
328	HWACCMR0Globals.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
329	}
330	}
331	#ifdef LOG_ENABLED
332	else
333	SUPR0Printf("HWACCMR0InitCPU failed with rc=%d\n", HWACCMR0Globals.lLastError);
334	#endif
335	}
336	else
337	HWACCMR0Globals.lLastError = VERR_VMX_NO_VMX;
338	}
339	else
340	if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
341	&& u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
342	&& u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX
343	)
344	{
345	/*
346	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
347	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
348	*/
349	if ( (HWACCMR0Globals.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
350	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
351	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
352	)
353	{
354	int aRc[RTCPUSET_MAX_CPUS];
355	RTCPUID idCpu = 0;
356
357	fAMDVPresent = true;
358
359	/* Query AMD features. */
360	ASMCpuId(0x8000000A, &HWACCMR0Globals.svm.u32Rev, &HWACCMR0Globals.uMaxASID, &u32Dummy, &HWACCMR0Globals.svm.u32Features);
361
362	/* We need to check if AMD-V has been properly initialized on all CPUs. Some BIOSes might do a poor job. */
363	memset(aRc, 0, sizeof(aRc));
364	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
365	AssertRC(rc);
366
367	/* Check the return code of all invocations. */
368	if (RT_SUCCESS(rc))
369	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
370
371	#ifndef DEBUG_bird
372	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE, ("HWACCMR0InitCPU failed for cpu %d with rc=%d\n", idCpu, rc));
373	#endif
374	if (RT_SUCCESS(rc))
375	{
376	/* Read the HWCR msr for diagnostics. */
377	HWACCMR0Globals.svm.msrHWCR = ASMRdMsr(MSR_K8_HWCR);
378	HWACCMR0Globals.svm.fSupported = true;
379	}
380	else
381	HWACCMR0Globals.lLastError = rc;
382	}
383	else
384	HWACCMR0Globals.lLastError = VERR_SVM_NO_SVM;
385	}
386	else
387	HWACCMR0Globals.lLastError = VERR_HWACCM_UNKNOWN_CPU;
388	}
389	else
390	HWACCMR0Globals.lLastError = VERR_HWACCM_NO_CPUID;
391
392	if (HWACCMR0Globals.vmx.fSupported)
393	{
394	HWACCMR0Globals.pfnEnterSession = VMXR0Enter;
395	HWACCMR0Globals.pfnLeaveSession = VMXR0Leave;
396	HWACCMR0Globals.pfnSaveHostState = VMXR0SaveHostState;
397	HWACCMR0Globals.pfnLoadGuestState = VMXR0LoadGuestState;
398	HWACCMR0Globals.pfnRunGuestCode = VMXR0RunGuestCode;
399	HWACCMR0Globals.pfnEnableCpu = VMXR0EnableCpu;
400	HWACCMR0Globals.pfnDisableCpu = VMXR0DisableCpu;
401	HWACCMR0Globals.pfnInitVM = VMXR0InitVM;
402	HWACCMR0Globals.pfnTermVM = VMXR0TermVM;
403	HWACCMR0Globals.pfnSetupVM = VMXR0SetupVM;
404	}
405	else
406	if (fAMDVPresent)
407	{
408	HWACCMR0Globals.pfnEnterSession = SVMR0Enter;
409	HWACCMR0Globals.pfnLeaveSession = SVMR0Leave;
410	HWACCMR0Globals.pfnSaveHostState = SVMR0SaveHostState;
411	HWACCMR0Globals.pfnLoadGuestState = SVMR0LoadGuestState;
412	HWACCMR0Globals.pfnRunGuestCode = SVMR0RunGuestCode;
413	HWACCMR0Globals.pfnEnableCpu = SVMR0EnableCpu;
414	HWACCMR0Globals.pfnDisableCpu = SVMR0DisableCpu;
415	HWACCMR0Globals.pfnInitVM = SVMR0InitVM;
416	HWACCMR0Globals.pfnTermVM = SVMR0TermVM;
417	HWACCMR0Globals.pfnSetupVM = SVMR0SetupVM;
418	}
419
420	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
421	{
422	rc = RTPowerNotificationRegister(hwaccmR0PowerCallback, 0);
423	AssertRC(rc);
424	}
425
426	return VINF_SUCCESS;
427	}
428
429
430	/**
431	* Checks the error code array filled in for each cpu in the system.
432	*
433	* @returns VBox status code.
434	* @param paRc Error code array
435	* @param cErrorCodes Array size
436	* @param pidCpu Value of the first cpu that set an error (out)
437	*/
438	static int hwaccmR0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu)
439	{
440	int rc = VINF_SUCCESS;
441
442	Assert(cErrorCodes == RTCPUSET_MAX_CPUS);
443
444	for (unsigned i=0;i<cErrorCodes;i++)
445	{
446	if (RTMpIsCpuOnline(i))
447	{
448	if (RT_FAILURE(paRc[i]))
449	{
450	rc = paRc[i];
451	*pidCpu = i;
452	break;
453	}
454	}
455	}
456	return rc;
457	}
458
459	/**
460	* Does global Ring-0 HWACCM termination.
461	*
462	* @returns VBox status code.
463	*/
464	VMMR0DECL(int) HWACCMR0Term(void)
465	{
466	int rc;
467	if ( HWACCMR0Globals.vmx.fSupported
468	&& HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
469	{
470	Assert(HWACCMR0Globals.fGlobalInit);
471	rc = SUPR0EnableVTx(false /* fEnable */);
472	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); iCpu++)
473	{
474	HWACCMR0Globals.aCpuInfo[iCpu].fConfigured = false;
475	Assert(HWACCMR0Globals.aCpuInfo[iCpu].pMemObj == NIL_RTR0MEMOBJ);
476	}
477	}
478	else
479	{
480	Assert(!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
481	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
482	{
483	rc = RTPowerNotificationDeregister(hwaccmR0PowerCallback, 0);
484	AssertRC(rc);
485	}
486	else
487	rc = VINF_SUCCESS;
488
489	/* Only disable VT-x/AMD-V on all CPUs if we enabled it before. */
490	if (HWACCMR0Globals.fGlobalInit)
491	{
492	int aRc[RTCPUSET_MAX_CPUS];
493
494	memset(aRc, 0, sizeof(aRc));
495	rc = RTMpOnAll(hwaccmR0DisableCpuCallback, aRc, NULL);
496	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
497	#ifdef VBOX_STRICT
498	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
499	AssertMsgRC(aRc[i], ("hwaccmR0DisableCpuCallback failed for cpu %d with rc=%d\n", i, aRc[i]));
500	#endif
501	}
502
503	/* Free the per-cpu pages used for VT-x and AMD-V */
504	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
505	{
506	if (HWACCMR0Globals.aCpuInfo[i].pMemObj != NIL_RTR0MEMOBJ)
507	{
508	RTR0MemObjFree(HWACCMR0Globals.aCpuInfo[i].pMemObj, false);
509	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
510	}
511	}
512	}
513	return rc;
514	}
515
516
517	/**
518	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
519	* is to be called on the target cpus.
520	*
521	* @param idCpu The identifier for the CPU the function is called on.
522	* @param pvUser1 The 1st user argument.
523	* @param pvUser2 The 2nd user argument.
524	*/
525	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
526	{
527	unsigned u32VendorEBX = (uintptr_t)pvUser1;
528	int paRc = (int )pvUser2;
529	uint64_t val;
530
531	#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
532	SUPR0Printf("HWACCMR0InitCPU cpu %d\n", idCpu);
533	#endif
534	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
535
536	if (u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX)
537	{
538	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
539
540	/*
541	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
542	* Once the lock bit is set, this MSR can no longer be modified.
543	*/
544	if ( !(val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
545	\|\| ((val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK)) == MSR_IA32_FEATURE_CONTROL_VMXON) /* Some BIOSes forget to set the locked bit. */
546	)
547	{
548	/* MSR is not yet locked; we can change it ourselves here */
549	ASMWrMsr(MSR_IA32_FEATURE_CONTROL, HWACCMR0Globals.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
550	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
551	}
552	if ( (val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
553	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
554	paRc[idCpu] = VINF_SUCCESS;
555	else
556	paRc[idCpu] = VERR_VMX_MSR_LOCKED_OR_DISABLED;
557	}
558	else
559	if (u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX)
560	{
561	/* Check if SVM is disabled */
562	val = ASMRdMsr(MSR_K8_VM_CR);
563	if (!(val & MSR_K8_VM_CR_SVM_DISABLE))
564	{
565	/* Turn on SVM in the EFER MSR. */
566	val = ASMRdMsr(MSR_K6_EFER);
567	if (val & MSR_K6_EFER_SVME)
568	{
569	paRc[idCpu] = VERR_SVM_IN_USE;
570	}
571	else
572	{
573	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
574
575	/* Paranoia. */
576	val = ASMRdMsr(MSR_K6_EFER);
577	if (val & MSR_K6_EFER_SVME)
578	{
579	/* Restore previous value. */
580	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
581	paRc[idCpu] = VINF_SUCCESS;
582	}
583	else
584	paRc[idCpu] = VERR_SVM_ILLEGAL_EFER_MSR;
585	}
586	}
587	else
588	paRc[idCpu] = VERR_SVM_DISABLED;
589	}
590	else
591	AssertFailed(); /* can't happen */
592	return;
593	}
594
595
596	/**
597	* Sets up HWACCM on all cpus.
598	*
599	* @returns VBox status code.
600	* @param pVM The VM to operate on.
601	*
602	*/
603	VMMR0DECL(int) HWACCMR0EnableAllCpus(PVM pVM)
604	{
605	AssertCompile(sizeof(HWACCMR0Globals.enmHwAccmState) == sizeof(uint32_t));
606
607	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
608	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
609	return VERR_HWACCM_SUSPEND_PENDING;
610
611	if (ASMAtomicCmpXchgU32((volatile uint32_t *)&HWACCMR0Globals.enmHwAccmState, HWACCMSTATE_ENABLED, HWACCMSTATE_UNINITIALIZED))
612	{
613	int rc;
614
615	HWACCMR0Globals.fGlobalInit = pVM->hwaccm.s.fGlobalInit;
616
617	if ( HWACCMR0Globals.vmx.fSupported
618	&& HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
619	{
620	rc = SUPR0EnableVTx(true /* fEnable */);
621	if (RT_SUCCESS(rc))
622	{
623	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); iCpu++)
624	{
625	HWACCMR0Globals.aCpuInfo[iCpu].fConfigured = true;
626	Assert(HWACCMR0Globals.aCpuInfo[iCpu].pMemObj == NIL_RTR0MEMOBJ);
627	}
628	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
629	HWACCMR0Globals.fGlobalInit = pVM->hwaccm.s.fGlobalInit = true;
630	}
631	else
632	AssertMsgFailed(("HWACCMR0EnableAllCpus/SUPR0EnableVTx: rc=%Rrc\n", rc));
633	}
634	else
635	{
636	int aRc[RTCPUSET_MAX_CPUS];
637	RTCPUID idCpu = 0;
638
639	memset(aRc, 0, sizeof(aRc));
640
641	/* Allocate one page per cpu for the global vt-x and amd-v pages */
642	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
643	{
644	Assert(!HWACCMR0Globals.aCpuInfo[i].pMemObj);
645
646	/** @todo this is rather dangerous if cpus can be taken offline; we don't care for now */
647	if (RTMpIsCpuOnline(i))
648	{
649	rc = RTR0MemObjAllocCont(&HWACCMR0Globals.aCpuInfo[i].pMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
650	AssertRC(rc);
651	if (RT_FAILURE(rc))
652	return rc;
653
654	void *pvR0 = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[i].pMemObj);
655	Assert(pvR0);
656	ASMMemZeroPage(pvR0);
657
658	#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
659	SUPR0Printf("address %x phys %x\n", pvR0, (uint32_t)RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[i].pMemObj, 0));
660	#endif
661	}
662	}
663	if (HWACCMR0Globals.fGlobalInit)
664	{
665	/* First time, so initialize each cpu/core */
666	rc = RTMpOnAll(hwaccmR0EnableCpuCallback, (void *)pVM, aRc);
667
668	/* Check the return code of all invocations. */
669	if (RT_SUCCESS(rc))
670	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
671	AssertMsgRC(rc, ("HWACCMR0EnableAllCpus failed for cpu %d with rc=%d\n", idCpu, rc));
672	}
673	else
674	rc = VINF_SUCCESS;
675	}
676
677	return rc;
678	}
679	return VINF_SUCCESS;
680	}
681
682	/**
683	* Disable VT-x or AMD-V on the current CPU
684	*
685	* @returns VBox status code.
686	* @param pVM VM handle (can be 0!)
687	* @param idCpu The identifier for the CPU the function is called on.
688	*/
689	static int hwaccmR0EnableCpu(PVM pVM, RTCPUID idCpu)
690	{
691	void *pvPageCpu;
692	RTHCPHYS pPageCpuPhys;
693	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
694
695	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
696	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
697	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
698	Assert(!pCpu->fConfigured);
699	Assert(!HWACCMR0Globals.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
700
701	pCpu->idCpu = idCpu;
702
703	/* Make sure we start with a clean TLB. */
704	pCpu->fFlushTLB = true;
705
706	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
707	pCpu->cTLBFlushes = 0;
708
709	/* Should never happen */
710	if (!pCpu->pMemObj)
711	{
712	AssertFailed();
713	return VERR_INTERNAL_ERROR;
714	}
715
716	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
717	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
718
719	int rc = HWACCMR0Globals.pfnEnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
720	AssertRC(rc);
721	if (RT_SUCCESS(rc))
722	pCpu->fConfigured = true;
723
724	return rc;
725	}
726
727
728	/**
729	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
730	* is to be called on the target cpus.
731	*
732	* @param idCpu The identifier for the CPU the function is called on.
733	* @param pvUser1 The 1st user argument.
734	* @param pvUser2 The 2nd user argument.
735	*/
736	static DECLCALLBACK(void) hwaccmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
737	{
738	PVM pVM = (PVM)pvUser1; /* can be NULL! */
739	int paRc = (int )pvUser2;
740
741	if (!HWACCMR0Globals.fGlobalInit)
742	{
743	paRc[idCpu] = VINF_SUCCESS;
744	AssertFailed();
745	return;
746	}
747
748	paRc[idCpu] = hwaccmR0EnableCpu(pVM, idCpu);
749	}
750
751
752	/**
753	* Disable VT-x or AMD-V on the current CPU
754	*
755	* @returns VBox status code.
756	* @param idCpu The identifier for the CPU the function is called on.
757	*/
758	static int hwaccmR0DisableCpu(RTCPUID idCpu)
759	{
760	void *pvPageCpu;
761	RTHCPHYS pPageCpuPhys;
762	int rc;
763	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
764
765	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
766	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
767	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
768	Assert(!HWACCMR0Globals.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
769	Assert(!pCpu->fConfigured \|\| pCpu->pMemObj);
770
771	if (!pCpu->pMemObj)
772	return (pCpu->fConfigured) ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
773
774	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
775	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
776
777	if (pCpu->fConfigured)
778	{
779	rc = HWACCMR0Globals.pfnDisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
780	AssertRC(rc);
781	pCpu->fConfigured = false;
782	}
783	else
784	rc = VINF_SUCCESS; /* nothing to do */
785
786	pCpu->uCurrentASID = 0;
787	return rc;
788	}
789
790	/**
791	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
792	* is to be called on the target cpus.
793	*
794	* @param idCpu The identifier for the CPU the function is called on.
795	* @param pvUser1 The 1st user argument.
796	* @param pvUser2 The 2nd user argument.
797	*/
798	static DECLCALLBACK(void) hwaccmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
799	{
800	int paRc = (int )pvUser1;
801
802	if (!HWACCMR0Globals.fGlobalInit)
803	{
804	paRc[idCpu] = VINF_SUCCESS;
805	AssertFailed();
806	return;
807	}
808
809	paRc[idCpu] = hwaccmR0DisableCpu(idCpu);
810	}
811
812	/**
813	* Called whenever a system power state change occurs.
814	*
815	* @param enmEvent Power event
816	* @param pvUser User argument
817	*/
818	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
819	{
820	NOREF(pvUser);
821	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
822
823	#ifdef LOG_ENABLED
824	if (enmEvent == RTPOWEREVENT_SUSPEND)
825	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
826	else
827	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_RESUME\n");
828	#endif
829
830	if (enmEvent == RTPOWEREVENT_SUSPEND)
831	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, true);
832
833	if (HWACCMR0Globals.enmHwAccmState == HWACCMSTATE_ENABLED)
834	{
835	int aRc[RTCPUSET_MAX_CPUS];
836	int rc;
837	RTCPUID idCpu;
838
839	memset(aRc, 0, sizeof(aRc));
840	if (enmEvent == RTPOWEREVENT_SUSPEND)
841	{
842	if (HWACCMR0Globals.fGlobalInit)
843	{
844	/* Turn off VT-x or AMD-V on all CPUs. */
845	rc = RTMpOnAll(hwaccmR0DisableCpuCallback, aRc, NULL);
846	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
847	}
848	/* else nothing to do here for the local init case */
849	}
850	else
851	{
852	/* Reinit the CPUs from scratch as the suspend state might have messed with the MSRs. (lousy BIOSes as usual) */
853	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)((HWACCMR0Globals.vmx.fSupported) ? X86_CPUID_VENDOR_INTEL_EBX : X86_CPUID_VENDOR_AMD_EBX), aRc);
854	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
855
856	if (RT_SUCCESS(rc))
857	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
858	#ifdef LOG_ENABLED
859	if (RT_FAILURE(rc))
860	SUPR0Printf("hwaccmR0PowerCallback HWACCMR0InitCPU failed with %d\n", rc);
861	#endif
862
863	if (HWACCMR0Globals.fGlobalInit)
864	{
865	/* Turn VT-x or AMD-V back on on all CPUs. */
866	rc = RTMpOnAll(hwaccmR0EnableCpuCallback, NULL, aRc);
867	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
868	}
869	/* else nothing to do here for the local init case */
870	}
871	}
872	if (enmEvent == RTPOWEREVENT_RESUME)
873	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, false);
874	}
875
876
877	/**
878	* Does Ring-0 per VM HWACCM initialization.
879	*
880	* This is mainly to check that the Host CPU mode is compatible
881	* with VMX.
882	*
883	* @returns VBox status code.
884	* @param pVM The VM to operate on.
885	*/
886	VMMR0DECL(int) HWACCMR0InitVM(PVM pVM)
887	{
888	int rc;
889
890	AssertReturn(pVM, VERR_INVALID_PARAMETER);
891
892	#ifdef LOG_ENABLED
893	SUPR0Printf("HWACCMR0InitVM: %p\n", pVM);
894	#endif
895
896	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
897	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
898	return VERR_HWACCM_SUSPEND_PENDING;
899
900	pVM->hwaccm.s.vmx.fSupported = HWACCMR0Globals.vmx.fSupported;
901	pVM->hwaccm.s.svm.fSupported = HWACCMR0Globals.svm.fSupported;
902
903	pVM->hwaccm.s.vmx.msr.feature_ctrl = HWACCMR0Globals.vmx.msr.feature_ctrl;
904	pVM->hwaccm.s.vmx.hostCR4 = HWACCMR0Globals.vmx.hostCR4;
905	pVM->hwaccm.s.vmx.msr.vmx_basic_info = HWACCMR0Globals.vmx.msr.vmx_basic_info;
906	pVM->hwaccm.s.vmx.msr.vmx_pin_ctls = HWACCMR0Globals.vmx.msr.vmx_pin_ctls;
907	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls = HWACCMR0Globals.vmx.msr.vmx_proc_ctls;
908	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2 = HWACCMR0Globals.vmx.msr.vmx_proc_ctls2;
909	pVM->hwaccm.s.vmx.msr.vmx_exit = HWACCMR0Globals.vmx.msr.vmx_exit;
910	pVM->hwaccm.s.vmx.msr.vmx_entry = HWACCMR0Globals.vmx.msr.vmx_entry;
911	pVM->hwaccm.s.vmx.msr.vmx_misc = HWACCMR0Globals.vmx.msr.vmx_misc;
912	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0;
913	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1;
914	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0;
915	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1;
916	pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum = HWACCMR0Globals.vmx.msr.vmx_vmcs_enum;
917	pVM->hwaccm.s.vmx.msr.vmx_eptcaps = HWACCMR0Globals.vmx.msr.vmx_eptcaps;
918	pVM->hwaccm.s.svm.msrHWCR = HWACCMR0Globals.svm.msrHWCR;
919	pVM->hwaccm.s.svm.u32Rev = HWACCMR0Globals.svm.u32Rev;
920	pVM->hwaccm.s.svm.u32Features = HWACCMR0Globals.svm.u32Features;
921	pVM->hwaccm.s.cpuid.u32AMDFeatureECX = HWACCMR0Globals.cpuid.u32AMDFeatureECX;
922	pVM->hwaccm.s.cpuid.u32AMDFeatureEDX = HWACCMR0Globals.cpuid.u32AMDFeatureEDX;
923	pVM->hwaccm.s.lLastError = HWACCMR0Globals.lLastError;
924
925	pVM->hwaccm.s.uMaxASID = HWACCMR0Globals.uMaxASID;
926
927
928	if (!pVM->hwaccm.s.cMaxResumeLoops) /* allow ring-3 overrides */
929	{
930	pVM->hwaccm.s.cMaxResumeLoops = 1024;
931	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
932	if (RTThreadPreemptIsPendingTrusty())
933	pVM->hwaccm.s.cMaxResumeLoops = 8192;
934	#endif
935	}
936
937	for (VMCPUID i = 0; i < pVM->cCpus; i++)
938	{
939	PVMCPU pVCpu = &pVM->aCpus[i];
940
941	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
942
943	/* Invalidate the last cpu we were running on. */
944	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
945
946	/* we'll aways increment this the first time (host uses ASID 0) */
947	pVCpu->hwaccm.s.uCurrentASID = 0;
948	}
949
950	RTCCUINTREG fFlags = ASMIntDisableFlags();
951	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
952
953	/* Note: Not correct as we can be rescheduled to a different cpu, but the fInUse case is mostly for debugging. */
954	ASMAtomicWriteBool(&pCpu->fInUse, true);
955	ASMSetFlags(fFlags);
956
957	/* Init a VT-x or AMD-V VM. */
958	rc = HWACCMR0Globals.pfnInitVM(pVM);
959
960	ASMAtomicWriteBool(&pCpu->fInUse, false);
961	return rc;
962	}
963
964
965	/**
966	* Does Ring-0 per VM HWACCM termination.
967	*
968	* @returns VBox status code.
969	* @param pVM The VM to operate on.
970	*/
971	VMMR0DECL(int) HWACCMR0TermVM(PVM pVM)
972	{
973	int rc;
974
975	AssertReturn(pVM, VERR_INVALID_PARAMETER);
976
977	#ifdef LOG_ENABLED
978	SUPR0Printf("HWACCMR0TermVM: %p\n", pVM);
979	#endif
980
981	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
982	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
983
984	/* @note Not correct as we can be rescheduled to a different cpu, but the fInUse case is mostly for debugging. */
985	RTCCUINTREG fFlags = ASMIntDisableFlags();
986	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
987
988	ASMAtomicWriteBool(&pCpu->fInUse, true);
989	ASMSetFlags(fFlags);
990
991	/* Terminate a VT-x or AMD-V VM. */
992	rc = HWACCMR0Globals.pfnTermVM(pVM);
993
994	ASMAtomicWriteBool(&pCpu->fInUse, false);
995	return rc;
996	}
997
998
999	/**
1000	* Sets up a VT-x or AMD-V session
1001	*
1002	* @returns VBox status code.
1003	* @param pVM The VM to operate on.
1004	*/
1005	VMMR0DECL(int) HWACCMR0SetupVM(PVM pVM)
1006	{
1007	int rc;
1008	RTCPUID idCpu = RTMpCpuId();
1009	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1010
1011	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1012
1013	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
1014	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1015
1016	#ifdef LOG_ENABLED
1017	SUPR0Printf("HWACCMR0SetupVM: %p\n", pVM);
1018	#endif
1019
1020	ASMAtomicWriteBool(&pCpu->fInUse, true);
1021
1022	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1023	{
1024	/* On first entry we'll sync everything. */
1025	pVM->aCpus[i].hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1026	}
1027
1028	/* Enable VT-x or AMD-V if local init is required. */
1029	if (!HWACCMR0Globals.fGlobalInit)
1030	{
1031	rc = hwaccmR0EnableCpu(pVM, idCpu);
1032	AssertRCReturn(rc, rc);
1033	}
1034
1035	/* Setup VT-x or AMD-V. */
1036	rc = HWACCMR0Globals.pfnSetupVM(pVM);
1037
1038	/* Disable VT-x or AMD-V if local init was done before. */
1039	if (!HWACCMR0Globals.fGlobalInit)
1040	{
1041	rc = hwaccmR0DisableCpu(idCpu);
1042	AssertRC(rc);
1043	}
1044
1045	ASMAtomicWriteBool(&pCpu->fInUse, false);
1046
1047	return rc;
1048	}
1049
1050
1051	/**
1052	* Enters the VT-x or AMD-V session
1053	*
1054	* @returns VBox status code.
1055	* @param pVM The VM to operate on.
1056	* @param pVCpu VMCPUD id.
1057	*/
1058	VMMR0DECL(int) HWACCMR0Enter(PVM pVM, PVMCPU pVCpu)
1059	{
1060	PCPUMCTX pCtx;
1061	int rc;
1062	RTCPUID idCpu = RTMpCpuId();
1063	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1064
1065	/* Make sure we can't enter a session after we've disabled hwaccm in preparation of a suspend. */
1066	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1067	ASMAtomicWriteBool(&pCpu->fInUse, true);
1068
1069	AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == NIL_RTCPUID, ("%d", (int)pVCpu->hwaccm.s.idEnteredCpu));
1070	pVCpu->hwaccm.s.idEnteredCpu = idCpu;
1071
1072	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1073
1074	/* Always load the guest's FPU/XMM state on-demand. */
1075	CPUMDeactivateGuestFPUState(pVCpu);
1076
1077	/* Always load the guest's debug state on-demand. */
1078	CPUMDeactivateGuestDebugState(pVCpu);
1079
1080	/* Always reload the host context and the guest's CR0 register. (!!!!) */
1081	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0 \| HWACCM_CHANGED_HOST_CONTEXT;
1082
1083	/* Setup the register and mask according to the current execution mode. */
1084	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1085	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFFFFFFFFFF);
1086	else
1087	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFF);
1088
1089	/* Enable VT-x or AMD-V if local init is required. */
1090	if (!HWACCMR0Globals.fGlobalInit)
1091	{
1092	rc = hwaccmR0EnableCpu(pVM, idCpu);
1093	AssertRCReturn(rc, rc);
1094	}
1095
1096	rc = HWACCMR0Globals.pfnEnterSession(pVM, pVCpu, pCpu);
1097	AssertRC(rc);
1098	/* We must save the host context here (VT-x) as we might be rescheduled on a different cpu after a long jump back to ring 3. */
1099	rc \|= HWACCMR0Globals.pfnSaveHostState(pVM, pVCpu);
1100	AssertRC(rc);
1101	rc \|= HWACCMR0Globals.pfnLoadGuestState(pVM, pVCpu, pCtx);
1102	AssertRC(rc);
1103
1104	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1105	if (RT_SUCCESS(rc))
1106	{
1107	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1108	PGMDynMapMigrateAutoSet(pVCpu);
1109	#endif
1110	}
1111	else
1112	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1113	return rc;
1114	}
1115
1116
1117	/**
1118	* Leaves the VT-x or AMD-V session
1119	*
1120	* @returns VBox status code.
1121	* @param pVM The VM to operate on.
1122	* @param pVCpu VMCPUD id.
1123	*/
1124	VMMR0DECL(int) HWACCMR0Leave(PVM pVM, PVMCPU pVCpu)
1125	{
1126	PCPUMCTX pCtx;
1127	int rc;
1128	RTCPUID idCpu = RTMpCpuId();
1129	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1130
1131	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1132
1133	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1134
1135	/* Note: It's rather tricky with longjmps done by e.g. Log statements or the page fault handler.
1136	* We must restore the host FPU here to make absolutely sure we don't leave the guest FPU state active
1137	* or trash somebody else's FPU state.
1138	*/
1139	/* Save the guest FPU and XMM state if necessary. */
1140	if (CPUMIsGuestFPUStateActive(pVCpu))
1141	{
1142	Log2(("CPUMR0SaveGuestFPU\n"));
1143	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
1144
1145	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1146	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1147	}
1148
1149	rc = HWACCMR0Globals.pfnLeaveSession(pVM, pVCpu, pCtx);
1150
1151	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1152	#ifdef RT_STRICT
1153	if (RT_UNLIKELY( pVCpu->hwaccm.s.idEnteredCpu != idCpu
1154	&& RT_FAILURE(rc)))
1155	{
1156	AssertMsgFailed(("Owner is %d, I'm %d", (int)pVCpu->hwaccm.s.idEnteredCpu, (int)idCpu));
1157	rc = VERR_INTERNAL_ERROR;
1158	}
1159	#endif
1160	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1161
1162	/* Disable VT-x or AMD-V if local init was done before. */
1163	if (!HWACCMR0Globals.fGlobalInit)
1164	{
1165	rc = hwaccmR0DisableCpu(idCpu);
1166	AssertRC(rc);
1167
1168	/* Reset these to force a TLB flush for the next entry. (-> EXPENSIVE) */
1169	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
1170	pVCpu->hwaccm.s.uCurrentASID = 0;
1171	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1172	}
1173
1174	ASMAtomicWriteBool(&pCpu->fInUse, false);
1175	return rc;
1176	}
1177
1178	/**
1179	* Runs guest code in a hardware accelerated VM.
1180	*
1181	* @returns VBox status code.
1182	* @param pVM The VM to operate on.
1183	* @param pVCpu VMCPUD id.
1184	*/
1185	VMMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1186	{
1187	CPUMCTX *pCtx;
1188	int rc;
1189	#ifdef VBOX_STRICT
1190	RTCPUID idCpu = RTMpCpuId(); NOREF(idCpu);
1191	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1192	#endif
1193
1194	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1195	Assert(HWACCMR0Globals.aCpuInfo[idCpu].fConfigured);
1196	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1197	Assert(ASMAtomicReadBool(&pCpu->fInUse) == true);
1198
1199	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1200	PGMDynMapStartAutoSet(pVCpu);
1201	#endif
1202
1203	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1204
1205	rc = HWACCMR0Globals.pfnRunGuestCode(pVM, pVCpu, pCtx);
1206
1207	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1208	PGMDynMapReleaseAutoSet(pVCpu);
1209	#endif
1210	return rc;
1211	}
1212
1213
1214	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1215	/**
1216	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1217	*
1218	* @returns VBox status code.
1219	* @param pVM VM handle.
1220	* @param pVCpu VMCPU handle.
1221	* @param pCtx CPU context
1222	*/
1223	VMMR0DECL(int) HWACCMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1224	{
1225	if (pVM->hwaccm.s.vmx.fSupported)
1226	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1227
1228	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1229	}
1230
1231	/**
1232	* Save guest debug state (64 bits guest mode & 32 bits host only)
1233	*
1234	* @returns VBox status code.
1235	* @param pVM VM handle.
1236	* @param pVCpu VMCPU handle.
1237	* @param pCtx CPU context
1238	*/
1239	VMMR0DECL(int) HWACCMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1240	{
1241	if (pVM->hwaccm.s.vmx.fSupported)
1242	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1243
1244	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1245	}
1246
1247	/**
1248	* Test the 32->64 bits switcher
1249	*
1250	* @returns VBox status code.
1251	* @param pVM VM handle.
1252	*/
1253	VMMR0DECL(int) HWACCMR0TestSwitcher3264(PVM pVM)
1254	{
1255	PVMCPU pVCpu = &pVM->aCpus[0];
1256	CPUMCTX *pCtx;
1257	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1258	int rc;
1259
1260	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1261
1262	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1263	if (pVM->hwaccm.s.vmx.fSupported)
1264	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1265	else
1266	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1267	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1268	return rc;
1269	}
1270
1271	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1272
1273	/**
1274	* Returns suspend status of the host
1275	*
1276	* @returns Suspend pending or not
1277	*/
1278	VMMR0DECL(bool) HWACCMR0SuspendPending()
1279	{
1280	return ASMAtomicReadBool(&HWACCMR0Globals.fSuspended);
1281	}
1282
1283	/**
1284	* Returns the cpu structure for the current cpu.
1285	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1286	*
1287	* @returns cpu structure pointer
1288	*/
1289	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu()
1290	{
1291	RTCPUID idCpu = RTMpCpuId();
1292
1293	return &HWACCMR0Globals.aCpuInfo[idCpu];
1294	}
1295
1296	/**
1297	* Returns the cpu structure for the current cpu.
1298	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1299	*
1300	* @returns cpu structure pointer
1301	* @param idCpu id of the VCPU
1302	*/
1303	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu)
1304	{
1305	return &HWACCMR0Globals.aCpuInfo[idCpu];
1306	}
1307
1308	/**
1309	* Returns the VMCPU of the current EMT thread.
1310	*
1311	* @param pVM The VM to operate on.
1312	*/
1313	VMMR0DECL(PVMCPU) HWACCMR0GetVMCPU(PVM pVM)
1314	{
1315	/* RTMpCpuId had better be cheap. */
1316	RTCPUID idHostCpu = RTMpCpuId();
1317
1318	/** @todo optimize for large number of VCPUs when that becomes more common. */
1319	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1320	{
1321	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1322
1323	if (pVCpu->hwaccm.s.idEnteredCpu == idHostCpu)
1324	return pVCpu;
1325	}
1326	return NULL;
1327	}
1328
1329	/**
1330	* Returns the VMCPU id of the current EMT thread.
1331	*
1332	* @param pVM The VM to operate on.
1333	*/
1334	VMMR0DECL(VMCPUID) HWACCMR0GetVMCPUId(PVM pVM)
1335	{
1336	PVMCPU pVCpu = HWACCMR0GetVMCPU(pVM);
1337	if (pVCpu)
1338	return pVCpu->idCpu;
1339
1340	return 0;
1341	}
1342
1343	/**
1344	* Save a pending IO read.
1345	*
1346	* @param pVCpu The VMCPU to operate on.
1347	* @param GCPtrRip Address of IO instruction
1348	* @param GCPtrRipNext Address of the next instruction
1349	* @param uPort Port address
1350	* @param uAndVal And mask for saving the result in eax
1351	* @param cbSize Read size
1352	*/
1353	VMMR0DECL(void) HWACCMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1354	{
1355	pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_PORT_READ;
1356	pVCpu->hwaccm.s.PendingIO.GCPtrRip = GCPtrRip;
1357	pVCpu->hwaccm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1358	pVCpu->hwaccm.s.PendingIO.s.Port.uPort = uPort;
1359	pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal = uAndVal;
1360	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize = cbSize;
1361	return;
1362	}
1363
1364	/**
1365	* Save a pending IO write.
1366	*
1367	* @param pVCpu The VMCPU to operate on.
1368	* @param GCPtrRIP Address of IO instruction
1369	* @param uPort Port address
1370	* @param uAndVal And mask for fetching the result from eax
1371	* @param cbSize Read size
1372	*/
1373	VMMR0DECL(void) HWACCMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1374	{
1375	pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_PORT_WRITE;
1376	pVCpu->hwaccm.s.PendingIO.GCPtrRip = GCPtrRip;
1377	pVCpu->hwaccm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1378	pVCpu->hwaccm.s.PendingIO.s.Port.uPort = uPort;
1379	pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal = uAndVal;
1380	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize = cbSize;
1381	return;
1382	}
1383
1384	/**
1385	* Disable VT-x if it's active and the current switcher turns off paging
1386	*
1387	* @returns VBox status code.
1388	* @param pVM VM handle.
1389	* @param pfVTxDisabled VT-x was disabled or not (out)
1390	*/
1391	VMMR0DECL(int) HWACCMR0EnterSwitcher(PVM pVM, bool *pfVTxDisabled)
1392	{
1393	Assert(!(ASMGetFlags() & X86_EFL_IF));
1394
1395	*pfVTxDisabled = false;
1396
1397	if ( HWACCMR0Globals.enmHwAccmState != HWACCMSTATE_ENABLED
1398	\|\| !HWACCMR0Globals.vmx.fSupported /* no such issues with AMD-V */
1399	\|\| !HWACCMR0Globals.fGlobalInit /* Local init implies the CPU is currently not in VMX root mode. */)
1400	return VINF_SUCCESS; /* nothing to do */
1401
1402	switch(VMMGetSwitcher(pVM))
1403	{
1404	case VMMSWITCHER_32_TO_32:
1405	case VMMSWITCHER_PAE_TO_PAE:
1406	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1407
1408	case VMMSWITCHER_32_TO_PAE:
1409	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1410	case VMMSWITCHER_AMD64_TO_32:
1411	case VMMSWITCHER_AMD64_TO_PAE:
1412	break; /* unsafe switchers */
1413
1414	default:
1415	AssertFailed();
1416	return VERR_INTERNAL_ERROR;
1417	}
1418
1419	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1420	void *pvPageCpu;
1421	RTHCPHYS pPageCpuPhys;
1422
1423	AssertReturn(pCpu && pCpu->pMemObj, VERR_INTERNAL_ERROR);
1424	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
1425	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
1426
1427	*pfVTxDisabled = true;
1428	return VMXR0DisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
1429	}
1430
1431	/**
1432	* Reeable VT-x if was active and the current switcher turned off paging
1433	*
1434	* @returns VBox status code.
1435	* @param pVM VM handle.
1436	* @param fVTxDisabled VT-x was disabled or not
1437	*/
1438	VMMR0DECL(int) HWACCMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1439	{
1440	Assert(!(ASMGetFlags() & X86_EFL_IF));
1441
1442	if (!fVTxDisabled)
1443	return VINF_SUCCESS; /* nothing to do */
1444
1445	Assert( HWACCMR0Globals.enmHwAccmState == HWACCMSTATE_ENABLED
1446	&& HWACCMR0Globals.vmx.fSupported
1447	&& HWACCMR0Globals.fGlobalInit);
1448
1449	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1450	void *pvPageCpu;
1451	RTHCPHYS pPageCpuPhys;
1452
1453	AssertReturn(pCpu && pCpu->pMemObj, VERR_INTERNAL_ERROR);
1454	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
1455	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
1456
1457	return VMXR0EnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
1458	}
1459
1460	#ifdef VBOX_STRICT
1461	/**
1462	* Dumps a descriptor.
1463	*
1464	* @param pDesc Descriptor to dump.
1465	* @param Sel Selector number.
1466	* @param pszMsg Message to prepend the log entry with.
1467	*/
1468	VMMR0DECL(void) HWACCMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1469	{
1470	/*
1471	* Make variable description string.
1472	*/
1473	static struct
1474	{
1475	unsigned cch;
1476	const char *psz;
1477	} const s_aTypes[32] =
1478	{
1479	# define STRENTRY(str) { sizeof(str) - 1, str }
1480
1481	/* system */
1482	# if HC_ARCH_BITS == 64
1483	STRENTRY("Reserved0 "), /* 0x00 */
1484	STRENTRY("Reserved1 "), /* 0x01 */
1485	STRENTRY("LDT "), /* 0x02 */
1486	STRENTRY("Reserved3 "), /* 0x03 */
1487	STRENTRY("Reserved4 "), /* 0x04 */
1488	STRENTRY("Reserved5 "), /* 0x05 */
1489	STRENTRY("Reserved6 "), /* 0x06 */
1490	STRENTRY("Reserved7 "), /* 0x07 */
1491	STRENTRY("Reserved8 "), /* 0x08 */
1492	STRENTRY("TSS64Avail "), /* 0x09 */
1493	STRENTRY("ReservedA "), /* 0x0a */
1494	STRENTRY("TSS64Busy "), /* 0x0b */
1495	STRENTRY("Call64 "), /* 0x0c */
1496	STRENTRY("ReservedD "), /* 0x0d */
1497	STRENTRY("Int64 "), /* 0x0e */
1498	STRENTRY("Trap64 "), /* 0x0f */
1499	# else
1500	STRENTRY("Reserved0 "), /* 0x00 */
1501	STRENTRY("TSS16Avail "), /* 0x01 */
1502	STRENTRY("LDT "), /* 0x02 */
1503	STRENTRY("TSS16Busy "), /* 0x03 */
1504	STRENTRY("Call16 "), /* 0x04 */
1505	STRENTRY("Task "), /* 0x05 */
1506	STRENTRY("Int16 "), /* 0x06 */
1507	STRENTRY("Trap16 "), /* 0x07 */
1508	STRENTRY("Reserved8 "), /* 0x08 */
1509	STRENTRY("TSS32Avail "), /* 0x09 */
1510	STRENTRY("ReservedA "), /* 0x0a */
1511	STRENTRY("TSS32Busy "), /* 0x0b */
1512	STRENTRY("Call32 "), /* 0x0c */
1513	STRENTRY("ReservedD "), /* 0x0d */
1514	STRENTRY("Int32 "), /* 0x0e */
1515	STRENTRY("Trap32 "), /* 0x0f */
1516	# endif
1517	/* non system */
1518	STRENTRY("DataRO "), /* 0x10 */
1519	STRENTRY("DataRO Accessed "), /* 0x11 */
1520	STRENTRY("DataRW "), /* 0x12 */
1521	STRENTRY("DataRW Accessed "), /* 0x13 */
1522	STRENTRY("DataDownRO "), /* 0x14 */
1523	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1524	STRENTRY("DataDownRW "), /* 0x16 */
1525	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1526	STRENTRY("CodeEO "), /* 0x18 */
1527	STRENTRY("CodeEO Accessed "), /* 0x19 */
1528	STRENTRY("CodeER "), /* 0x1a */
1529	STRENTRY("CodeER Accessed "), /* 0x1b */
1530	STRENTRY("CodeConfEO "), /* 0x1c */
1531	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1532	STRENTRY("CodeConfER "), /* 0x1e */
1533	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1534	# undef SYSENTRY
1535	};
1536	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1537	char szMsg[128];
1538	char *psz = &szMsg[0];
1539	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1540	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1541	psz += s_aTypes[i].cch;
1542
1543	if (pDesc->Gen.u1Present)
1544	ADD_STR(psz, "Present ");
1545	else
1546	ADD_STR(psz, "Not-Present ");
1547	# if HC_ARCH_BITS == 64
1548	if (pDesc->Gen.u1Long)
1549	ADD_STR(psz, "64-bit ");
1550	else
1551	ADD_STR(psz, "Comp ");
1552	# else
1553	if (pDesc->Gen.u1Granularity)
1554	ADD_STR(psz, "Page ");
1555	if (pDesc->Gen.u1DefBig)
1556	ADD_STR(psz, "32-bit ");
1557	else
1558	ADD_STR(psz, "16-bit ");
1559	# endif
1560	# undef ADD_STR
1561	*psz = '\0';
1562
1563	/*
1564	* Limit and Base and format the output.
1565	*/
1566	uint32_t u32Limit = X86DESC_LIMIT(*pDesc);
1567	if (pDesc->Gen.u1Granularity)
1568	u32Limit = u32Limit << PAGE_SHIFT \| PAGE_OFFSET_MASK;
1569
1570	# if HC_ARCH_BITS == 64
1571	uint64_t u32Base = X86DESC64_BASE(*pDesc);
1572
1573	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1574	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1575	# else
1576	uint32_t u32Base = X86DESC_BASE(*pDesc);
1577
1578	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1579	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1580	# endif
1581	}
1582
1583	/**
1584	* Formats a full register dump.
1585	*
1586	* @param pVM The VM to operate on.
1587	* @param pVCpu The VMCPU to operate on.
1588	* @param pCtx The context to format.
1589	*/
1590	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1591	{
1592	/*
1593	* Format the flags.
1594	*/
1595	static struct
1596	{
1597	const char pszSet; const char pszClear; uint32_t fFlag;
1598	} aFlags[] =
1599	{
1600	{ "vip",NULL, X86_EFL_VIP },
1601	{ "vif",NULL, X86_EFL_VIF },
1602	{ "ac", NULL, X86_EFL_AC },
1603	{ "vm", NULL, X86_EFL_VM },
1604	{ "rf", NULL, X86_EFL_RF },
1605	{ "nt", NULL, X86_EFL_NT },
1606	{ "ov", "nv", X86_EFL_OF },
1607	{ "dn", "up", X86_EFL_DF },
1608	{ "ei", "di", X86_EFL_IF },
1609	{ "tf", NULL, X86_EFL_TF },
1610	{ "nt", "pl", X86_EFL_SF },
1611	{ "nz", "zr", X86_EFL_ZF },
1612	{ "ac", "na", X86_EFL_AF },
1613	{ "po", "pe", X86_EFL_PF },
1614	{ "cy", "nc", X86_EFL_CF },
1615	};
1616	char szEFlags[80];
1617	char *psz = szEFlags;
1618	uint32_t efl = pCtx->eflags.u32;
1619	for (unsigned i = 0; i < RT_ELEMENTS(aFlags); i++)
1620	{
1621	const char *pszAdd = aFlags[i].fFlag & efl ? aFlags[i].pszSet : aFlags[i].pszClear;
1622	if (pszAdd)
1623	{
1624	strcpy(psz, pszAdd);
1625	psz += strlen(pszAdd);
1626	*psz++ = ' ';
1627	}
1628	}
1629	psz[-1] = '\0';
1630
1631
1632	/*
1633	* Format the registers.
1634	*/
1635	if (CPUMIsGuestIn64BitCode(pVCpu, CPUMCTX2CORE(pCtx)))
1636	{
1637	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1638	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1639	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1640	"r14=%016RX64 r15=%016RX64\n"
1641	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1642	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1643	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1644	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1645	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1646	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1647	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1648	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1649	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1650	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1651	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1652	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1653	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1654	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1655	,
1656	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1657	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1658	pCtx->r14, pCtx->r15,
1659	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1660	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1661	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1662	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1663	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1664	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1665	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1666	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1667	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1668	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1669	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1670	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1671	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1672	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1673	}
1674	else
1675	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1676	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1677	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1678	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1679	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1680	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1681	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1682	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1683	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1684	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1685	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1686	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1687	,
1688	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1689	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1690	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr[0], pCtx->dr[1],
1691	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr[2], pCtx->dr[3],
1692	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr[4], pCtx->dr[5],
1693	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr[6], pCtx->dr[7],
1694	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0, pCtx->cr2,
1695	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3, pCtx->cr4,
1696	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1697	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1698	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1699	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1700
1701	Log(("FPU:\n"
1702	"FCW=%04x FSW=%04x FTW=%02x\n"
1703	"FOP=%04x FPUIP=%08x CS=%04x Rsvrd1=%04x\n"
1704	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1705	,
1706	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
1707	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsvrd1,
1708	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
1709	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
1710
1711
1712	Log(("MSR:\n"
1713	"EFER =%016RX64\n"
1714	"PAT =%016RX64\n"
1715	"STAR =%016RX64\n"
1716	"CSTAR =%016RX64\n"
1717	"LSTAR =%016RX64\n"
1718	"SFMASK =%016RX64\n"
1719	"KERNELGSBASE =%016RX64\n",
1720	pCtx->msrEFER,
1721	pCtx->msrPAT,
1722	pCtx->msrSTAR,
1723	pCtx->msrCSTAR,
1724	pCtx->msrLSTAR,
1725	pCtx->msrSFMASK,
1726	pCtx->msrKERNELGSBASE));
1727
1728	}
1729	#endif /* VBOX_STRICT */
1730
1731	/* Dummy callback handlers. */
1732	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
1733	{
1734	return VINF_SUCCESS;
1735	}
1736
1737	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1738	{
1739	return VINF_SUCCESS;
1740	}
1741
1742	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1743	{
1744	return VINF_SUCCESS;
1745	}
1746
1747	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1748	{
1749	return VINF_SUCCESS;
1750	}
1751
1752	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM)
1753	{
1754	return VINF_SUCCESS;
1755	}
1756
1757	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM)
1758	{
1759	return VINF_SUCCESS;
1760	}
1761
1762	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM)
1763	{
1764	return VINF_SUCCESS;
1765	}
1766
1767	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1768	{
1769	return VINF_SUCCESS;
1770	}
1771
1772	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
1773	{
1774	return VINF_SUCCESS;
1775	}
1776
1777	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1778	{
1779	return VINF_SUCCESS;
1780	}

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp@ 26005

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