HWACCMR0.cpp@ 37250

Last change on this file since 37250 was 37231, checked in by vboxsync, 14 years ago
HWACCMR0: Fixed bug in HWACCMR0EnableAllCpus, the current CPU is always possible. :-) Some nits and cleanup.
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File size: 71.1 KB

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1	/* $Id: HWACCMR0.cpp 37231 2011-05-27 11:28:52Z vboxsync $ */
2	/** @file
3	* HWACCM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HWACCM
23	#include <VBox/vmm/hwaccm.h>
24	#include <VBox/vmm/pgm.h>
25	#include "HWACCMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include <VBox/x86.h>
28	#include <VBox/vmm/hwacc_vmx.h>
29	#include <VBox/vmm/hwacc_svm.h>
30	#include <VBox/err.h>
31	#include <VBox/log.h>
32	#include <iprt/assert.h>
33	#include <iprt/asm.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/cpuset.h>
36	#include <iprt/mem.h>
37	#include <iprt/memobj.h>
38	#include <iprt/param.h>
39	#include <iprt/power.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42	#include "HWVMXR0.h"
43	#include "HWSVMR0.h"
44
45	/*******************************************************************************
46	* Internal Functions *
47	*******************************************************************************/
48	static DECLCALLBACK(void) hwaccmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
49	static DECLCALLBACK(void) hwaccmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
50	static DECLCALLBACK(void) hwaccmR0InitCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static bool hwaccmR0IsSubjectToVmxPreemptionTimerErratum(void);
52	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
53	static DECLCALLBACK(void) hwaccmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
54
55	/*******************************************************************************
56	* Global Variables *
57	*******************************************************************************/
58
59	static struct
60	{
61	HWACCM_CPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
62
63	/** Ring 0 handlers for VT-x and AMD-V. */
64	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu));
65	DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
66	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
67	DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
68	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
69	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
70	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
71	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
72	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
73	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVM pVM));
74
75	/** Maximum ASID allowed. */
76	uint32_t uMaxASID;
77
78	struct
79	{
80	/** Set to by us to indicate VMX is supported by the CPU. */
81	bool fSupported;
82	/** Whether we're using SUPR0EnableVTx or not. */
83	bool fUsingSUPR0EnableVTx;
84	/** Whether we're using the preemption timer or not. */
85	bool fUsePreemptTimer;
86	/** The shift mask employed by the VMX-Preemption timer. */
87	uint8_t cPreemptTimerShift;
88
89	/** Host CR4 value (set by ring-0 VMX init) */
90	uint64_t hostCR4;
91
92	/** Host EFER value (set by ring-0 VMX init) */
93	uint64_t hostEFER;
94
95	/** VMX MSR values */
96	struct
97	{
98	uint64_t feature_ctrl;
99	uint64_t vmx_basic_info;
100	VMX_CAPABILITY vmx_pin_ctls;
101	VMX_CAPABILITY vmx_proc_ctls;
102	VMX_CAPABILITY vmx_proc_ctls2;
103	VMX_CAPABILITY vmx_exit;
104	VMX_CAPABILITY vmx_entry;
105	uint64_t vmx_misc;
106	uint64_t vmx_cr0_fixed0;
107	uint64_t vmx_cr0_fixed1;
108	uint64_t vmx_cr4_fixed0;
109	uint64_t vmx_cr4_fixed1;
110	uint64_t vmx_vmcs_enum;
111	uint64_t vmx_eptcaps;
112	} msr;
113	/* Last instruction error */
114	uint32_t ulLastInstrError;
115	} vmx;
116	struct
117	{
118	/* HWCR msr (for diagnostics) */
119	uint64_t msrHWCR;
120
121	/** SVM revision. */
122	uint32_t u32Rev;
123
124	/** SVM feature bits from cpuid 0x8000000a */
125	uint32_t u32Features;
126
127	/** Set by us to indicate SVM is supported by the CPU. */
128	bool fSupported;
129	} svm;
130	/** Saved error from detection */
131	int32_t lLastError;
132
133	struct
134	{
135	uint32_t u32AMDFeatureECX;
136	uint32_t u32AMDFeatureEDX;
137	} cpuid;
138
139	HWACCMSTATE enmHwAccmState;
140
141	bool fGlobalInit;
142	volatile bool fSuspended;
143	} HWACCMR0Globals;
144
145
146	/**
147	* This is used to manage the status code of a RTMpOnAll in HWACCM.
148	*/
149	typedef struct HWACCMR0FIRSTRC
150	{
151	/** The status code. */
152	int32_t volatile rc;
153	/** The ID of the CPU reporting the first failure. */
154	RTCPUID volatile idCpu;
155	} HWACCMR0FIRSTRC;
156	/** Pointer to a first return code structure. */
157	typedef HWACCMR0FIRSTRC *PHWACCMR0FIRSTRC;
158
159
160	/**
161	* Initializes a first return code structure.
162	*
163	* @param pFirstRc The structure to init.
164	*/
165	static void hwaccmR0FirstRcInit(PHWACCMR0FIRSTRC pFirstRc)
166	{
167	pFirstRc->rc = VINF_SUCCESS;
168	pFirstRc->idCpu = NIL_RTCPUID;
169	}
170
171
172	/**
173	* Try se the status code (success ignored).
174	*
175	* @param pFirstRc The first return code structure.
176	* @param rc The status code.
177	*/
178	static void hwaccmR0FirstRcSetStatus(PHWACCMR0FIRSTRC pFirstRc, int rc)
179	{
180	if ( RT_FAILURE(rc)
181	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
182	pFirstRc->idCpu = RTMpCpuId();
183	}
184
185
186	/**
187	* Get the status code of a first return code structure.
188	*
189	* @returns The status code; VINF_SUCCESS or error status, no informational or
190	* warning errors.
191	* @param pFirstRc The first return code structure.
192	*/
193	static int hwaccmR0FirstRcGetStatus(PHWACCMR0FIRSTRC pFirstRc)
194	{
195	return pFirstRc->rc;
196	}
197
198
199	/**
200	* Get the CPU ID on which the failure status code was reported.
201	*
202	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
203	* @param pFirstRc The first return code structure.
204	*/
205	static RTCPUID hwaccmR0FirstRcGetCpuId(PHWACCMR0FIRSTRC pFirstRc)
206	{
207	return pFirstRc->idCpu;
208	}
209
210
211	/**
212	* Does global Ring-0 HWACCM initialization.
213	*
214	* @returns VBox status code.
215	*/
216	VMMR0DECL(int) HWACCMR0Init(void)
217	{
218	int rc;
219	bool fAMDVPresent = false;
220
221	HWACCMR0Globals.enmHwAccmState = HWACCMSTATE_UNINITIALIZED;
222	for (unsigned i = 0; i < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); i++)
223	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
224
225	/* Fill in all callbacks with placeholders. */
226	HWACCMR0Globals.pfnEnterSession = HWACCMR0DummyEnter;
227	HWACCMR0Globals.pfnLeaveSession = HWACCMR0DummyLeave;
228	HWACCMR0Globals.pfnSaveHostState = HWACCMR0DummySaveHostState;
229	HWACCMR0Globals.pfnLoadGuestState = HWACCMR0DummyLoadGuestState;
230	HWACCMR0Globals.pfnRunGuestCode = HWACCMR0DummyRunGuestCode;
231	HWACCMR0Globals.pfnEnableCpu = HWACCMR0DummyEnableCpu;
232	HWACCMR0Globals.pfnDisableCpu = HWACCMR0DummyDisableCpu;
233	HWACCMR0Globals.pfnInitVM = HWACCMR0DummyInitVM;
234	HWACCMR0Globals.pfnTermVM = HWACCMR0DummyTermVM;
235	HWACCMR0Globals.pfnSetupVM = HWACCMR0DummySetupVM;
236
237	/* Default is global VT-x/AMD-V init */
238	HWACCMR0Globals.fGlobalInit = true;
239
240	/*
241	* Make sure aCpuInfo is big enough for all the CPUs on this system.
242	*/
243	if (RTMpGetArraySize() > RT_ELEMENTS(HWACCMR0Globals.aCpuInfo))
244	{
245	LogRel(("HWACCM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(HWACCMR0Globals.aCpuInfo)));
246	return VERR_TOO_MANY_CPUS;
247	}
248
249	/*
250	* Check for VT-x and AMD-V capabilities
251	*/
252	if (ASMHasCpuId())
253	{
254	uint32_t u32FeaturesECX;
255	uint32_t u32Dummy;
256	uint32_t u32FeaturesEDX;
257	uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
258
259	ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
260	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
261	/* Query AMD features. */
262	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy, &HWACCMR0Globals.cpuid.u32AMDFeatureECX, &HWACCMR0Globals.cpuid.u32AMDFeatureEDX);
263
264	if ( u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
265	&& u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
266	&& u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX
267	)
268	{
269	/*
270	* Read all VMX MSRs if VMX is available. (same goes for RDMSR/WRMSR)
271	* We also assume all VMX-enabled CPUs support fxsave/fxrstor.
272	*/
273	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
274	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
275	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
276	)
277	{
278	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
279
280	/*
281	* First try use native kernel API for controlling VT-x.
282	* (This is only supported by some Mac OS X kernels atm.)
283	*/
284	HWACCMR0Globals.lLastError = rc = SUPR0EnableVTx(true /* fEnable */);
285	if (rc != VERR_NOT_SUPPORTED)
286	{
287	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
288	HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx = true;
289	if (RT_SUCCESS(rc))
290	{
291	HWACCMR0Globals.vmx.fSupported = true;
292	rc = SUPR0EnableVTx(false /* fEnable */);
293	AssertRC(rc);
294	}
295	}
296	else
297	{
298	HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx = false;
299
300	/* We need to check if VT-x has been properly initialized on all CPUs. Some BIOSes do a lousy job. */
301	HWACCMR0FIRSTRC FirstRc;
302	hwaccmR0FirstRcInit(&FirstRc);
303	HWACCMR0Globals.lLastError = RTMpOnAll(hwaccmR0InitCpu, (void *)(uintptr_t)u32VendorEBX, &FirstRc);
304	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
305	HWACCMR0Globals.lLastError = hwaccmR0FirstRcGetStatus(&FirstRc);
306	}
307	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
308	{
309	/* Reread in case we've changed it. */
310	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
311
312	if ( (HWACCMR0Globals.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
313	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
314	{
315	RTR0MEMOBJ pScatchMemObj;
316	void *pvScatchPage;
317	RTHCPHYS pScatchPagePhys;
318
319	HWACCMR0Globals.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
320	HWACCMR0Globals.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
321	HWACCMR0Globals.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
322	HWACCMR0Globals.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
323	HWACCMR0Globals.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
324	HWACCMR0Globals.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
325	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
326	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
327	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
328	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
329	HWACCMR0Globals.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
330	/* VPID 16 bits ASID. */
331	HWACCMR0Globals.uMaxASID = 0x10000; /* exclusive */
332
333	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
334	{
335	HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
336	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT\|VMX_VMCS_CTRL_PROC_EXEC2_VPID))
337	HWACCMR0Globals.vmx.msr.vmx_eptcaps = ASMRdMsr(MSR_IA32_VMX_EPT_CAPS);
338	}
339
340	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
341	{
342	HWACCMR0Globals.vmx.hostCR4 = ASMGetCR4();
343	HWACCMR0Globals.vmx.hostEFER = ASMRdMsr(MSR_K6_EFER);
344
345	rc = RTR0MemObjAllocCont(&pScatchMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
346	if (RT_FAILURE(rc))
347	return rc;
348
349	pvScatchPage = RTR0MemObjAddress(pScatchMemObj);
350	pScatchPagePhys = RTR0MemObjGetPagePhysAddr(pScatchMemObj, 0);
351	memset(pvScatchPage, 0, PAGE_SIZE);
352
353	/* Set revision dword at the beginning of the structure. */
354	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(HWACCMR0Globals.vmx.msr.vmx_basic_info);
355
356	/* Make sure we don't get rescheduled to another cpu during this probe. */
357	RTCCUINTREG fFlags = ASMIntDisableFlags();
358
359	/*
360	* Check CR4.VMXE
361	*/
362	if (!(HWACCMR0Globals.vmx.hostCR4 & X86_CR4_VMXE))
363	{
364	/* In theory this bit could be cleared behind our back. Which would cause #UD faults when we
365	* try to execute the VMX instructions...
366	*/
367	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4 \| X86_CR4_VMXE);
368	}
369
370	/* Enter VMX Root Mode */
371	rc = VMXEnable(pScatchPagePhys);
372	if (RT_FAILURE(rc))
373	{
374	/* KVM leaves the CPU in VMX root mode. Not only is this not allowed, it will crash the host when we enter raw mode, because
375	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify this bit)
376	* (b) turning off paging causes a #GP (unavoidable when switching from long to 32 bits mode or 32 bits to PAE)
377	*
378	* They should fix their code, but until they do we simply refuse to run.
379	*/
380	HWACCMR0Globals.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
381	}
382	else
383	{
384	HWACCMR0Globals.vmx.fSupported = true;
385	VMXDisable();
386
387	/*
388	* Check for the VMX-Preemption Timer and adjust for the
389	* "VMX-Preemption Timer Does Not Count Down at the Rate Specified" erratum.
390	*/
391	if ( HWACCMR0Globals.vmx.msr.vmx_pin_ctls.n.allowed1
392	& VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
393	{
394	HWACCMR0Globals.vmx.fUsePreemptTimer = true;
395	HWACCMR0Globals.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(HWACCMR0Globals.vmx.msr.vmx_misc);
396	if (hwaccmR0IsSubjectToVmxPreemptionTimerErratum())
397	HWACCMR0Globals.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
398	}
399	}
400
401	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it wasn't so before (some software could incorrectly think it's in VMX mode) */
402	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4);
403	ASMSetFlags(fFlags);
404
405	RTR0MemObjFree(pScatchMemObj, false);
406	if (RT_FAILURE(HWACCMR0Globals.lLastError))
407	return HWACCMR0Globals.lLastError;
408	}
409	}
410	else
411	{
412	AssertFailed(); /* can't hit this case anymore */
413	HWACCMR0Globals.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
414	}
415	}
416	#ifdef LOG_ENABLED
417	else
418	SUPR0Printf("hwaccmR0InitCpu failed with rc=%d\n", HWACCMR0Globals.lLastError);
419	#endif
420	}
421	else
422	HWACCMR0Globals.lLastError = VERR_VMX_NO_VMX;
423	}
424	else
425	if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
426	&& u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
427	&& u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX
428	)
429	{
430	/*
431	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
432	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
433	*/
434	if ( (HWACCMR0Globals.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
435	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
436	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
437	)
438	{
439	fAMDVPresent = true;
440
441	/* Query AMD features. */
442	ASMCpuId(0x8000000A, &HWACCMR0Globals.svm.u32Rev, &HWACCMR0Globals.uMaxASID, &u32Dummy, &HWACCMR0Globals.svm.u32Features);
443
444	/* We need to check if AMD-V has been properly initialized on all CPUs. Some BIOSes might do a poor job. */
445	HWACCMR0FIRSTRC FirstRc;
446	hwaccmR0FirstRcInit(&FirstRc);
447	rc = RTMpOnAll(hwaccmR0InitCpu, (void *)(uintptr_t)u32VendorEBX, &FirstRc); AssertRC(rc);
448	if (RT_SUCCESS(rc))
449	rc = hwaccmR0FirstRcGetStatus(&FirstRc);
450	#ifndef DEBUG_bird
451	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE, ("hwaccmR0InitCpu failed for cpu %d with rc=%d\n", hwaccmR0FirstRcGetCpuId(&FirstRc), rc));
452	#endif
453	if (RT_SUCCESS(rc))
454	{
455	/* Read the HWCR msr for diagnostics. */
456	HWACCMR0Globals.svm.msrHWCR = ASMRdMsr(MSR_K8_HWCR);
457	HWACCMR0Globals.svm.fSupported = true;
458	}
459	else
460	HWACCMR0Globals.lLastError = rc;
461	}
462	else
463	HWACCMR0Globals.lLastError = VERR_SVM_NO_SVM;
464	}
465	else
466	HWACCMR0Globals.lLastError = VERR_HWACCM_UNKNOWN_CPU;
467	}
468	else
469	HWACCMR0Globals.lLastError = VERR_HWACCM_NO_CPUID;
470
471	if (HWACCMR0Globals.vmx.fSupported)
472	{
473	HWACCMR0Globals.pfnEnterSession = VMXR0Enter;
474	HWACCMR0Globals.pfnLeaveSession = VMXR0Leave;
475	HWACCMR0Globals.pfnSaveHostState = VMXR0SaveHostState;
476	HWACCMR0Globals.pfnLoadGuestState = VMXR0LoadGuestState;
477	HWACCMR0Globals.pfnRunGuestCode = VMXR0RunGuestCode;
478	HWACCMR0Globals.pfnEnableCpu = VMXR0EnableCpu;
479	HWACCMR0Globals.pfnDisableCpu = VMXR0DisableCpu;
480	HWACCMR0Globals.pfnInitVM = VMXR0InitVM;
481	HWACCMR0Globals.pfnTermVM = VMXR0TermVM;
482	HWACCMR0Globals.pfnSetupVM = VMXR0SetupVM;
483	}
484	else
485	if (fAMDVPresent)
486	{
487	HWACCMR0Globals.pfnEnterSession = SVMR0Enter;
488	HWACCMR0Globals.pfnLeaveSession = SVMR0Leave;
489	HWACCMR0Globals.pfnSaveHostState = SVMR0SaveHostState;
490	HWACCMR0Globals.pfnLoadGuestState = SVMR0LoadGuestState;
491	HWACCMR0Globals.pfnRunGuestCode = SVMR0RunGuestCode;
492	HWACCMR0Globals.pfnEnableCpu = SVMR0EnableCpu;
493	HWACCMR0Globals.pfnDisableCpu = SVMR0DisableCpu;
494	HWACCMR0Globals.pfnInitVM = SVMR0InitVM;
495	HWACCMR0Globals.pfnTermVM = SVMR0TermVM;
496	HWACCMR0Globals.pfnSetupVM = SVMR0SetupVM;
497	}
498
499	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
500	{
501	rc = RTMpNotificationRegister(hwaccmR0MpEventCallback, NULL);
502	AssertRC(rc);
503
504	rc = RTPowerNotificationRegister(hwaccmR0PowerCallback, NULL);
505	AssertRC(rc);
506	}
507
508	return VINF_SUCCESS;
509	}
510
511
512	/**
513	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
514	* Down at the Rate Specified" erratum.
515	*
516	* Errata names and related steppings:
517	* - BA86 - D0.
518	* - AAX65 - C2.
519	* - AAU65 - C2, K0.
520	* - AAO95 - B1.
521	* - AAT59 - C2.
522	* - AAK139 - D0.
523	* - AAM126 - C0, C1, D0.
524	* - AAN92 - B1.
525	* - AAJ124 - C0, D0.
526	*
527	* - AAP86 - B1.
528	*
529	* Steppings: B1, C0, C1, C2, D0, K0.
530	*
531	* @returns true if subject to it, false if not.
532	*/
533	static bool hwaccmR0IsSubjectToVmxPreemptionTimerErratum(void)
534	{
535	uint32_t u = ASMCpuId_EAX(1);
536	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
537	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
538	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
539	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
540	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
541	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
542	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
543	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
544	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
545	\|\| u == UINT32_C(0x000106A0) /?321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification /
546	\|\| u == UINT32_C(0x000106A1) /?321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification /
547	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
548	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
549	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
550	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
551	)
552	return true;
553	return false;
554	}
555
556
557	/**
558	* Does global Ring-0 HWACCM termination.
559	*
560	* @returns VBox status code.
561	*/
562	VMMR0DECL(int) HWACCMR0Term(void)
563	{
564	int rc;
565	if ( HWACCMR0Globals.vmx.fSupported
566	&& HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
567	{
568	Assert(HWACCMR0Globals.fGlobalInit);
569	rc = SUPR0EnableVTx(false /* fEnable */);
570	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); iCpu++)
571	{
572	HWACCMR0Globals.aCpuInfo[iCpu].fConfigured = false;
573	Assert(HWACCMR0Globals.aCpuInfo[iCpu].pMemObj == NIL_RTR0MEMOBJ);
574	}
575	}
576	else
577	{
578	Assert(!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
579	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
580	{
581	/* Doesn't really matter if this fails. */
582	rc = RTMpNotificationDeregister(hwaccmR0MpEventCallback, NULL); AssertRC(rc);
583	rc = RTPowerNotificationDeregister(hwaccmR0PowerCallback, NULL); AssertRC(rc);
584	}
585	else
586	rc = VINF_SUCCESS;
587
588	/* Only disable VT-x/AMD-V on all CPUs if we enabled it before. */
589	if (HWACCMR0Globals.fGlobalInit)
590	{
591	HWACCMR0FIRSTRC FirstRc;
592	hwaccmR0FirstRcInit(&FirstRc);
593	rc = RTMpOnAll(hwaccmR0DisableCpuCallback, NULL, &FirstRc);
594	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
595	if (RT_SUCCESS(rc))
596	{
597	rc = hwaccmR0FirstRcGetStatus(&FirstRc);
598	AssertMsgRC(rc, ("%u: %Rrc\n", hwaccmR0FirstRcGetCpuId(&FirstRc), rc));
599	}
600	}
601
602	/* Free the per-cpu pages used for VT-x and AMD-V */
603	for (unsigned i = 0; i < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); i++)
604	{
605	if (HWACCMR0Globals.aCpuInfo[i].pMemObj != NIL_RTR0MEMOBJ)
606	{
607	RTR0MemObjFree(HWACCMR0Globals.aCpuInfo[i].pMemObj, false);
608	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
609	}
610	}
611	}
612	return rc;
613	}
614
615
616	/**
617	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
618	* is to be called on the target cpus.
619	*
620	* @param idCpu The identifier for the CPU the function is called on.
621	* @param pvUser1 The 1st user argument.
622	* @param pvUser2 The 2nd user argument.
623	*/
624	static DECLCALLBACK(void) hwaccmR0InitCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
625	{
626	unsigned u32VendorEBX = (uintptr_t)pvUser1;
627	PHWACCMR0FIRSTRC pFirstRc = (PHWACCMR0FIRSTRC)pvUser2;
628	uint64_t val;
629	int rc;
630
631	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
632
633	if (u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX)
634	{
635	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
636
637	/*
638	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
639	* Once the lock bit is set, this MSR can no longer be modified.
640	*/
641	if ( !(val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
642	\|\| ((val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK)) == MSR_IA32_FEATURE_CONTROL_VMXON) /* Some BIOSes forget to set the locked bit. */
643	)
644	{
645	/* MSR is not yet locked; we can change it ourselves here */
646	ASMWrMsr(MSR_IA32_FEATURE_CONTROL, HWACCMR0Globals.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
647	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
648	}
649	if ( (val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
650	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
651	rc = VINF_SUCCESS;
652	else
653	rc = VERR_VMX_MSR_LOCKED_OR_DISABLED;
654	}
655	else if (u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX)
656	{
657	/* Check if SVM is disabled */
658	val = ASMRdMsr(MSR_K8_VM_CR);
659	if (!(val & MSR_K8_VM_CR_SVM_DISABLE))
660	{
661	/* Turn on SVM in the EFER MSR. */
662	val = ASMRdMsr(MSR_K6_EFER);
663	if (val & MSR_K6_EFER_SVME)
664	rc = VERR_SVM_IN_USE;
665	else
666	{
667	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
668
669	/* Paranoia. */
670	val = ASMRdMsr(MSR_K6_EFER);
671	if (val & MSR_K6_EFER_SVME)
672	{
673	/* Restore previous value. */
674	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
675	rc = VINF_SUCCESS;
676	}
677	else
678	rc = VERR_SVM_ILLEGAL_EFER_MSR;
679	}
680	}
681	else
682	rc = VERR_SVM_DISABLED;
683	}
684	else
685	{
686	AssertFailed(); /* can't happen */
687	rc = VERR_INTERNAL_ERROR_5;
688	}
689
690	hwaccmR0FirstRcSetStatus(pFirstRc, rc);
691	}
692
693
694	/**
695	* Sets up HWACCM on all cpus.
696	*
697	* @returns VBox status code.
698	* @param pVM The VM to operate on.
699	*
700	*/
701	VMMR0DECL(int) HWACCMR0EnableAllCpus(PVM pVM)
702	{
703	AssertCompile(sizeof(HWACCMR0Globals.enmHwAccmState) == sizeof(uint32_t));
704
705	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
706	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
707	return VERR_HWACCM_SUSPEND_PENDING;
708
709	if (ASMAtomicCmpXchgU32((volatile uint32_t *)&HWACCMR0Globals.enmHwAccmState, HWACCMSTATE_ENABLED, HWACCMSTATE_UNINITIALIZED))
710	{
711	int rc;
712
713	HWACCMR0Globals.fGlobalInit = pVM->hwaccm.s.fGlobalInit;
714
715	if ( HWACCMR0Globals.vmx.fSupported
716	&& HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
717	{
718	rc = SUPR0EnableVTx(true /* fEnable */);
719	if (RT_SUCCESS(rc))
720	{
721	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); iCpu++)
722	{
723	HWACCMR0Globals.aCpuInfo[iCpu].fConfigured = true;
724	Assert(HWACCMR0Globals.aCpuInfo[iCpu].pMemObj == NIL_RTR0MEMOBJ);
725	}
726	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
727	HWACCMR0Globals.fGlobalInit = pVM->hwaccm.s.fGlobalInit = true;
728	}
729	else
730	AssertMsgFailed(("HWACCMR0EnableAllCpus/SUPR0EnableVTx: rc=%Rrc\n", rc));
731	}
732	else
733	{
734	/* Allocate one page per cpu for the global vt-x and amd-v pages */
735	for (unsigned i = 0; i < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); i++)
736	{
737	Assert(!HWACCMR0Globals.aCpuInfo[i].pMemObj);
738
739	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
740	{
741	rc = RTR0MemObjAllocCont(&HWACCMR0Globals.aCpuInfo[i].pMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
742	AssertRC(rc);
743	if (RT_FAILURE(rc))
744	return rc;
745
746	void *pvR0 = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[i].pMemObj);
747	Assert(pvR0);
748	ASMMemZeroPage(pvR0);
749
750	#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
751	SUPR0Printf("address %x phys %x\n", pvR0, (uint32_t)RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[i].pMemObj, 0));
752	#endif
753	}
754	HWACCMR0Globals.aCpuInfo[i].fConfigured = false;
755	}
756	if (HWACCMR0Globals.fGlobalInit)
757	{
758	/* First time, so initialize each cpu/core */
759	HWACCMR0FIRSTRC FirstRc;
760	hwaccmR0FirstRcInit(&FirstRc);
761	rc = RTMpOnAll(hwaccmR0EnableCpuCallback, (void *)pVM, &FirstRc);
762	if (RT_SUCCESS(rc))
763	rc = hwaccmR0FirstRcGetStatus(&FirstRc);
764	AssertMsgRC(rc, ("HWACCMR0EnableAllCpus failed for cpu %d with rc=%d\n", hwaccmR0FirstRcGetCpuId(&FirstRc), rc));
765	}
766	else
767	rc = VINF_SUCCESS;
768	}
769
770	return rc;
771	}
772	return VINF_SUCCESS;
773	}
774
775	/**
776	* Disable VT-x or AMD-V on the current CPU
777	*
778	* @returns VBox status code.
779	* @param pVM VM handle (can be 0!)
780	* @param idCpu The identifier for the CPU the function is called on.
781	*/
782	static int hwaccmR0EnableCpu(PVM pVM, RTCPUID idCpu)
783	{
784	void *pvPageCpu;
785	RTHCPHYS pPageCpuPhys;
786	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
787
788	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
789	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
790	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
791	Assert(!pCpu->fConfigured);
792	Assert(!HWACCMR0Globals.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
793
794	pCpu->idCpu = idCpu;
795
796	/* Make sure we start with a clean TLB. */
797	pCpu->fFlushTLB = true;
798
799	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
800	pCpu->cTLBFlushes = 0;
801
802	/* Should never happen */
803	if (!pCpu->pMemObj)
804	{
805	AssertLogRelMsgFailed(("hwaccmR0EnableCpu failed idCpu=%u.\n", idCpu));
806	return VERR_INTERNAL_ERROR;
807	}
808
809	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
810	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
811
812	int rc = HWACCMR0Globals.pfnEnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
813	AssertRC(rc);
814	if (RT_SUCCESS(rc))
815	pCpu->fConfigured = true;
816
817	return rc;
818	}
819
820
821	/**
822	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
823	* is to be called on the target cpus.
824	*
825	* @param idCpu The identifier for the CPU the function is called on.
826	* @param pvUser1 The 1st user argument.
827	* @param pvUser2 The 2nd user argument.
828	*/
829	static DECLCALLBACK(void) hwaccmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
830	{
831	PVM pVM = (PVM)pvUser1; /* can be NULL! */
832	PHWACCMR0FIRSTRC pFirstRc = (PHWACCMR0FIRSTRC)pvUser2;
833	AssertReturnVoid(HWACCMR0Globals.fGlobalInit);
834	hwaccmR0FirstRcSetStatus(pFirstRc, hwaccmR0EnableCpu(pVM, idCpu));
835	}
836
837
838	/**
839	* Disable VT-x or AMD-V on the current CPU
840	*
841	* @returns VBox status code.
842	* @param idCpu The identifier for the CPU the function is called on.
843	*/
844	static int hwaccmR0DisableCpu(RTCPUID idCpu)
845	{
846	void *pvPageCpu;
847	RTHCPHYS pPageCpuPhys;
848	int rc;
849	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
850
851	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
852	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
853	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
854	Assert(!HWACCMR0Globals.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
855	Assert(!pCpu->fConfigured \|\| pCpu->pMemObj);
856
857	if (!pCpu->pMemObj)
858	return (pCpu->fConfigured) ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
859
860	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
861	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
862
863	if (pCpu->fConfigured)
864	{
865	rc = HWACCMR0Globals.pfnDisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
866	AssertRC(rc);
867	pCpu->fConfigured = false;
868	}
869	else
870	rc = VINF_SUCCESS; /* nothing to do */
871
872	pCpu->uCurrentASID = 0;
873	return rc;
874	}
875
876	/**
877	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
878	* is to be called on the target cpus.
879	*
880	* @param idCpu The identifier for the CPU the function is called on.
881	* @param pvUser1 The 1st user argument.
882	* @param pvUser2 The 2nd user argument.
883	*/
884	static DECLCALLBACK(void) hwaccmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
885	{
886	PHWACCMR0FIRSTRC pFirstRc = (PHWACCMR0FIRSTRC)pvUser2;
887	AssertReturnVoid(HWACCMR0Globals.fGlobalInit);
888	hwaccmR0FirstRcSetStatus(pFirstRc, hwaccmR0DisableCpu(idCpu));
889	}
890
891
892	/**
893	* Callback function invoked when a cpu goes online or offline.
894	*
895	* @param enmEvent The Mp event.
896	* @param idCpu The identifier for the CPU the function is called on.
897	* @param pvData Opaque data (PVM pointer).
898	*/
899	static DECLCALLBACK(void) hwaccmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
900	{
901	/*
902	* We only care about uninitializing a CPU that is going offline. When a
903	* CPU comes online, the initialization is done lazily in HWACCMR0Enter().
904	*/
905	AssertRelease(idCpu == RTMpCpuId());
906	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
907	switch (enmEvent)
908	{
909	case RTMPEVENT_OFFLINE:
910	{
911	int rc = hwaccmR0DisableCpu(idCpu);
912	AssertRC(rc);
913	break;
914	}
915
916	default:
917	break;
918	}
919	}
920
921
922	/**
923	* Called whenever a system power state change occurs.
924	*
925	* @param enmEvent Power event
926	* @param pvUser User argument
927	*/
928	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
929	{
930	NOREF(pvUser);
931	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
932
933	#ifdef LOG_ENABLED
934	if (enmEvent == RTPOWEREVENT_SUSPEND)
935	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
936	else
937	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_RESUME\n");
938	#endif
939
940	if (enmEvent == RTPOWEREVENT_SUSPEND)
941	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, true);
942
943	if (HWACCMR0Globals.enmHwAccmState == HWACCMSTATE_ENABLED)
944	{
945	int rc;
946	HWACCMR0FIRSTRC FirstRc;
947	hwaccmR0FirstRcInit(&FirstRc);
948
949	if (enmEvent == RTPOWEREVENT_SUSPEND)
950	{
951	if (HWACCMR0Globals.fGlobalInit)
952	{
953	/* Turn off VT-x or AMD-V on all CPUs. */
954	rc = RTMpOnAll(hwaccmR0DisableCpuCallback, NULL, &FirstRc);
955	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
956	}
957	/* else nothing to do here for the local init case */
958	}
959	else
960	{
961	/* Reinit the CPUs from scratch as the suspend state might have messed with the MSRs. (lousy BIOSes as usual) */
962	uintptr_t uFirstArg = HWACCMR0Globals.vmx.fSupported ? X86_CPUID_VENDOR_INTEL_EBX : X86_CPUID_VENDOR_AMD_EBX;
963	rc = RTMpOnAll(hwaccmR0InitCpu, (void *)uFirstArg , &FirstRc);
964	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
965	if (RT_SUCCESS(rc))
966	rc = hwaccmR0FirstRcGetStatus(&FirstRc);
967	#ifdef LOG_ENABLED
968	if (RT_FAILURE(rc))
969	SUPR0Printf("hwaccmR0PowerCallback hwaccmR0InitCpu failed with %Rc\n", rc);
970	#endif
971
972	if (HWACCMR0Globals.fGlobalInit)
973	{
974	/* Turn VT-x or AMD-V back on on all CPUs. */
975	rc = RTMpOnAll(hwaccmR0EnableCpuCallback, NULL, &FirstRc /* output ignored */);
976	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
977	}
978	/* else nothing to do here for the local init case */
979	}
980	}
981	if (enmEvent == RTPOWEREVENT_RESUME)
982	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, false);
983	}
984
985
986	/**
987	* Does Ring-0 per VM HWACCM initialization.
988	*
989	* This is mainly to check that the Host CPU mode is compatible
990	* with VMX.
991	*
992	* @returns VBox status code.
993	* @param pVM The VM to operate on.
994	*/
995	VMMR0DECL(int) HWACCMR0InitVM(PVM pVM)
996	{
997	int rc;
998
999	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1000
1001	#ifdef LOG_ENABLED
1002	SUPR0Printf("HWACCMR0InitVM: %p\n", pVM);
1003	#endif
1004
1005	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
1006	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
1007	return VERR_HWACCM_SUSPEND_PENDING;
1008
1009	pVM->hwaccm.s.vmx.fSupported = HWACCMR0Globals.vmx.fSupported;
1010	pVM->hwaccm.s.svm.fSupported = HWACCMR0Globals.svm.fSupported;
1011
1012	pVM->hwaccm.s.vmx.fUsePreemptTimer = HWACCMR0Globals.vmx.fUsePreemptTimer;
1013	pVM->hwaccm.s.vmx.cPreemptTimerShift = HWACCMR0Globals.vmx.cPreemptTimerShift;
1014	pVM->hwaccm.s.vmx.msr.feature_ctrl = HWACCMR0Globals.vmx.msr.feature_ctrl;
1015	pVM->hwaccm.s.vmx.hostCR4 = HWACCMR0Globals.vmx.hostCR4;
1016	pVM->hwaccm.s.vmx.hostEFER = HWACCMR0Globals.vmx.hostEFER;
1017	pVM->hwaccm.s.vmx.msr.vmx_basic_info = HWACCMR0Globals.vmx.msr.vmx_basic_info;
1018	pVM->hwaccm.s.vmx.msr.vmx_pin_ctls = HWACCMR0Globals.vmx.msr.vmx_pin_ctls;
1019	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls = HWACCMR0Globals.vmx.msr.vmx_proc_ctls;
1020	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2 = HWACCMR0Globals.vmx.msr.vmx_proc_ctls2;
1021	pVM->hwaccm.s.vmx.msr.vmx_exit = HWACCMR0Globals.vmx.msr.vmx_exit;
1022	pVM->hwaccm.s.vmx.msr.vmx_entry = HWACCMR0Globals.vmx.msr.vmx_entry;
1023	pVM->hwaccm.s.vmx.msr.vmx_misc = HWACCMR0Globals.vmx.msr.vmx_misc;
1024	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0;
1025	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1;
1026	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0;
1027	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1;
1028	pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum = HWACCMR0Globals.vmx.msr.vmx_vmcs_enum;
1029	pVM->hwaccm.s.vmx.msr.vmx_eptcaps = HWACCMR0Globals.vmx.msr.vmx_eptcaps;
1030	pVM->hwaccm.s.svm.msrHWCR = HWACCMR0Globals.svm.msrHWCR;
1031	pVM->hwaccm.s.svm.u32Rev = HWACCMR0Globals.svm.u32Rev;
1032	pVM->hwaccm.s.svm.u32Features = HWACCMR0Globals.svm.u32Features;
1033	pVM->hwaccm.s.cpuid.u32AMDFeatureECX = HWACCMR0Globals.cpuid.u32AMDFeatureECX;
1034	pVM->hwaccm.s.cpuid.u32AMDFeatureEDX = HWACCMR0Globals.cpuid.u32AMDFeatureEDX;
1035	pVM->hwaccm.s.lLastError = HWACCMR0Globals.lLastError;
1036
1037	pVM->hwaccm.s.uMaxASID = HWACCMR0Globals.uMaxASID;
1038
1039
1040	if (!pVM->hwaccm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1041	{
1042	pVM->hwaccm.s.cMaxResumeLoops = 1024;
1043	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1044	if (RTThreadPreemptIsPendingTrusty())
1045	pVM->hwaccm.s.cMaxResumeLoops = 8192;
1046	#endif
1047	}
1048
1049	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1050	{
1051	PVMCPU pVCpu = &pVM->aCpus[i];
1052
1053	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1054
1055	/* Invalidate the last cpu we were running on. */
1056	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
1057
1058	/* we'll aways increment this the first time (host uses ASID 0) */
1059	pVCpu->hwaccm.s.uCurrentASID = 0;
1060	}
1061
1062	RTCCUINTREG fFlags = ASMIntDisableFlags();
1063	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1064
1065	/* Note: Not correct as we can be rescheduled to a different cpu, but the fInUse case is mostly for debugging. */
1066	ASMAtomicWriteBool(&pCpu->fInUse, true);
1067	ASMSetFlags(fFlags);
1068
1069	/* Init a VT-x or AMD-V VM. */
1070	rc = HWACCMR0Globals.pfnInitVM(pVM);
1071
1072	ASMAtomicWriteBool(&pCpu->fInUse, false);
1073	return rc;
1074	}
1075
1076
1077	/**
1078	* Does Ring-0 per VM HWACCM termination.
1079	*
1080	* @returns VBox status code.
1081	* @param pVM The VM to operate on.
1082	*/
1083	VMMR0DECL(int) HWACCMR0TermVM(PVM pVM)
1084	{
1085	int rc;
1086
1087	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1088
1089	#ifdef LOG_ENABLED
1090	SUPR0Printf("HWACCMR0TermVM: %p\n", pVM);
1091	#endif
1092
1093	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
1094	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1095
1096	/* @note Not correct as we can be rescheduled to a different cpu, but the fInUse case is mostly for debugging. */
1097	RTCCUINTREG fFlags = ASMIntDisableFlags();
1098	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1099
1100	ASMAtomicWriteBool(&pCpu->fInUse, true);
1101	ASMSetFlags(fFlags);
1102
1103	/* Terminate a VT-x or AMD-V VM. */
1104	rc = HWACCMR0Globals.pfnTermVM(pVM);
1105
1106	ASMAtomicWriteBool(&pCpu->fInUse, false);
1107	return rc;
1108	}
1109
1110
1111	/**
1112	* Sets up a VT-x or AMD-V session
1113	*
1114	* @returns VBox status code.
1115	* @param pVM The VM to operate on.
1116	*/
1117	VMMR0DECL(int) HWACCMR0SetupVM(PVM pVM)
1118	{
1119	int rc;
1120	RTCPUID idCpu = RTMpCpuId();
1121	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1122
1123	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1124
1125	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
1126	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1127
1128	#ifdef LOG_ENABLED
1129	SUPR0Printf("HWACCMR0SetupVM: %p\n", pVM);
1130	#endif
1131
1132	ASMAtomicWriteBool(&pCpu->fInUse, true);
1133
1134	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1135	{
1136	/* On first entry we'll sync everything. */
1137	pVM->aCpus[i].hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1138	}
1139
1140	/* Enable VT-x or AMD-V if local init is required. */
1141	if (!HWACCMR0Globals.fGlobalInit)
1142	{
1143	rc = hwaccmR0EnableCpu(pVM, idCpu);
1144	AssertRCReturn(rc, rc);
1145	}
1146
1147	/* Setup VT-x or AMD-V. */
1148	rc = HWACCMR0Globals.pfnSetupVM(pVM);
1149
1150	/* Disable VT-x or AMD-V if local init was done before. */
1151	if (!HWACCMR0Globals.fGlobalInit)
1152	{
1153	rc = hwaccmR0DisableCpu(idCpu);
1154	AssertRC(rc);
1155	}
1156
1157	ASMAtomicWriteBool(&pCpu->fInUse, false);
1158
1159	return rc;
1160	}
1161
1162
1163	/**
1164	* Enters the VT-x or AMD-V session
1165	*
1166	* @returns VBox status code.
1167	* @param pVM The VM to operate on.
1168	* @param pVCpu VMCPU handle.
1169	*/
1170	VMMR0DECL(int) HWACCMR0Enter(PVM pVM, PVMCPU pVCpu)
1171	{
1172	PCPUMCTX pCtx;
1173	int rc;
1174	RTCPUID idCpu = RTMpCpuId();
1175	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1176
1177	/* Make sure we can't enter a session after we've disabled hwaccm in preparation of a suspend. */
1178	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1179	ASMAtomicWriteBool(&pCpu->fInUse, true);
1180
1181	AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == NIL_RTCPUID, ("%d", (int)pVCpu->hwaccm.s.idEnteredCpu));
1182	pVCpu->hwaccm.s.idEnteredCpu = idCpu;
1183
1184	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1185
1186	/* Always load the guest's FPU/XMM state on-demand. */
1187	CPUMDeactivateGuestFPUState(pVCpu);
1188
1189	/* Always load the guest's debug state on-demand. */
1190	CPUMDeactivateGuestDebugState(pVCpu);
1191
1192	/* Always reload the host context and the guest's CR0 register. (!!!!) */
1193	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0 \| HWACCM_CHANGED_HOST_CONTEXT;
1194
1195	/* Setup the register and mask according to the current execution mode. */
1196	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1197	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFFFFFFFFFF);
1198	else
1199	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFF);
1200
1201	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1202	if ( !pCpu->fConfigured
1203	\|\| !HWACCMR0Globals.fGlobalInit)
1204	{
1205	rc = hwaccmR0EnableCpu(pVM, idCpu);
1206	AssertRCReturn(rc, rc);
1207	}
1208
1209	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1210	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1211	#endif
1212
1213	rc = HWACCMR0Globals.pfnEnterSession(pVM, pVCpu, pCpu);
1214	AssertRC(rc);
1215	/* We must save the host context here (VT-x) as we might be rescheduled on a different cpu after a long jump back to ring 3. */
1216	rc \|= HWACCMR0Globals.pfnSaveHostState(pVM, pVCpu);
1217	AssertRC(rc);
1218	rc \|= HWACCMR0Globals.pfnLoadGuestState(pVM, pVCpu, pCtx);
1219	AssertRC(rc);
1220
1221	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1222	if (fStartedSet)
1223	PGMRZDynMapReleaseAutoSet(pVCpu);
1224	#endif
1225
1226	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1227	if (RT_FAILURE(rc))
1228	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1229	return rc;
1230	}
1231
1232
1233	/**
1234	* Leaves the VT-x or AMD-V session
1235	*
1236	* @returns VBox status code.
1237	* @param pVM The VM to operate on.
1238	* @param pVCpu VMCPU handle.
1239	*/
1240	VMMR0DECL(int) HWACCMR0Leave(PVM pVM, PVMCPU pVCpu)
1241	{
1242	PCPUMCTX pCtx;
1243	int rc;
1244	RTCPUID idCpu = RTMpCpuId();
1245	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1246
1247	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1248
1249	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1250
1251	/* Note: It's rather tricky with longjmps done by e.g. Log statements or the page fault handler.
1252	* We must restore the host FPU here to make absolutely sure we don't leave the guest FPU state active
1253	* or trash somebody else's FPU state.
1254	*/
1255	/* Save the guest FPU and XMM state if necessary. */
1256	if (CPUMIsGuestFPUStateActive(pVCpu))
1257	{
1258	Log2(("CPUMR0SaveGuestFPU\n"));
1259	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
1260
1261	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1262	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1263	}
1264
1265	rc = HWACCMR0Globals.pfnLeaveSession(pVM, pVCpu, pCtx);
1266
1267	/* We don't pass on invlpg information to the recompiler for nested paging guests, so we must make sure the recompiler flushes its TLB
1268	* the next time it executes code.
1269	*/
1270	if ( pVM->hwaccm.s.fNestedPaging
1271	&& CPUMIsGuestInPagedProtectedModeEx(pCtx))
1272	{
1273	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
1274	}
1275
1276	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1277	#ifdef RT_STRICT
1278	if (RT_UNLIKELY( pVCpu->hwaccm.s.idEnteredCpu != idCpu
1279	&& RT_FAILURE(rc)))
1280	{
1281	AssertMsgFailed(("Owner is %d, I'm %d", (int)pVCpu->hwaccm.s.idEnteredCpu, (int)idCpu));
1282	rc = VERR_INTERNAL_ERROR;
1283	}
1284	#endif
1285	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1286
1287	/* Disable VT-x or AMD-V if local init was done before. */
1288	if (!HWACCMR0Globals.fGlobalInit)
1289	{
1290	rc = hwaccmR0DisableCpu(idCpu);
1291	AssertRC(rc);
1292
1293	/* Reset these to force a TLB flush for the next entry. (-> EXPENSIVE) */
1294	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
1295	pVCpu->hwaccm.s.uCurrentASID = 0;
1296	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1297	}
1298
1299	ASMAtomicWriteBool(&pCpu->fInUse, false);
1300	return rc;
1301	}
1302
1303	/**
1304	* Runs guest code in a hardware accelerated VM.
1305	*
1306	* @returns VBox status code.
1307	* @param pVM The VM to operate on.
1308	* @param pVCpu VMCPUD id.
1309	*/
1310	VMMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1311	{
1312	CPUMCTX *pCtx;
1313	int rc;
1314	#ifdef VBOX_STRICT
1315	RTCPUID idCpu = RTMpCpuId(); NOREF(idCpu);
1316	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1317	#endif
1318
1319	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1320	Assert(HWACCMR0Globals.aCpuInfo[idCpu].fConfigured);
1321	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1322	Assert(ASMAtomicReadBool(&pCpu->fInUse) == true);
1323
1324	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1325	PGMRZDynMapStartAutoSet(pVCpu);
1326	#endif
1327
1328	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1329
1330	rc = HWACCMR0Globals.pfnRunGuestCode(pVM, pVCpu, pCtx);
1331
1332	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1333	PGMRZDynMapReleaseAutoSet(pVCpu);
1334	#endif
1335	return rc;
1336	}
1337
1338
1339	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1340	/**
1341	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1342	*
1343	* @returns VBox status code.
1344	* @param pVM VM handle.
1345	* @param pVCpu VMCPU handle.
1346	* @param pCtx CPU context
1347	*/
1348	VMMR0DECL(int) HWACCMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1349	{
1350	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFpu64SwitchBack);
1351	if (pVM->hwaccm.s.vmx.fSupported)
1352	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1353
1354	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1355	}
1356
1357	/**
1358	* Save guest debug state (64 bits guest mode & 32 bits host only)
1359	*
1360	* @returns VBox status code.
1361	* @param pVM VM handle.
1362	* @param pVCpu VMCPU handle.
1363	* @param pCtx CPU context
1364	*/
1365	VMMR0DECL(int) HWACCMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1366	{
1367	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDebug64SwitchBack);
1368	if (pVM->hwaccm.s.vmx.fSupported)
1369	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1370
1371	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1372	}
1373
1374	/**
1375	* Test the 32->64 bits switcher
1376	*
1377	* @returns VBox status code.
1378	* @param pVM VM handle.
1379	*/
1380	VMMR0DECL(int) HWACCMR0TestSwitcher3264(PVM pVM)
1381	{
1382	PVMCPU pVCpu = &pVM->aCpus[0];
1383	CPUMCTX *pCtx;
1384	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1385	int rc;
1386
1387	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1388
1389	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1390	if (pVM->hwaccm.s.vmx.fSupported)
1391	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1392	else
1393	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1394	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1395	return rc;
1396	}
1397
1398	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1399
1400	/**
1401	* Returns suspend status of the host
1402	*
1403	* @returns Suspend pending or not
1404	*/
1405	VMMR0DECL(bool) HWACCMR0SuspendPending()
1406	{
1407	return ASMAtomicReadBool(&HWACCMR0Globals.fSuspended);
1408	}
1409
1410	/**
1411	* Returns the cpu structure for the current cpu.
1412	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1413	*
1414	* @returns cpu structure pointer
1415	*/
1416	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu()
1417	{
1418	RTCPUID idCpu = RTMpCpuId();
1419
1420	return &HWACCMR0Globals.aCpuInfo[idCpu];
1421	}
1422
1423	/**
1424	* Returns the cpu structure for the current cpu.
1425	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1426	*
1427	* @returns cpu structure pointer
1428	* @param idCpu id of the VCPU
1429	*/
1430	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu)
1431	{
1432	return &HWACCMR0Globals.aCpuInfo[idCpu];
1433	}
1434
1435	/**
1436	* Save a pending IO read.
1437	*
1438	* @param pVCpu The VMCPU to operate on.
1439	* @param GCPtrRip Address of IO instruction
1440	* @param GCPtrRipNext Address of the next instruction
1441	* @param uPort Port address
1442	* @param uAndVal And mask for saving the result in eax
1443	* @param cbSize Read size
1444	*/
1445	VMMR0DECL(void) HWACCMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1446	{
1447	pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_PORT_READ;
1448	pVCpu->hwaccm.s.PendingIO.GCPtrRip = GCPtrRip;
1449	pVCpu->hwaccm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1450	pVCpu->hwaccm.s.PendingIO.s.Port.uPort = uPort;
1451	pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal = uAndVal;
1452	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize = cbSize;
1453	return;
1454	}
1455
1456	/**
1457	* Save a pending IO write.
1458	*
1459	* @param pVCpu The VMCPU to operate on.
1460	* @param GCPtrRIP Address of IO instruction
1461	* @param uPort Port address
1462	* @param uAndVal And mask for fetching the result from eax
1463	* @param cbSize Read size
1464	*/
1465	VMMR0DECL(void) HWACCMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1466	{
1467	pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_PORT_WRITE;
1468	pVCpu->hwaccm.s.PendingIO.GCPtrRip = GCPtrRip;
1469	pVCpu->hwaccm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1470	pVCpu->hwaccm.s.PendingIO.s.Port.uPort = uPort;
1471	pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal = uAndVal;
1472	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize = cbSize;
1473	return;
1474	}
1475
1476	/**
1477	* Disable VT-x if it's active and the current switcher turns off paging
1478	*
1479	* @returns VBox status code.
1480	* @param pVM VM handle.
1481	* @param pfVTxDisabled VT-x was disabled or not (out)
1482	*/
1483	VMMR0DECL(int) HWACCMR0EnterSwitcher(PVM pVM, bool *pfVTxDisabled)
1484	{
1485	Assert(!(ASMGetFlags() & X86_EFL_IF) \|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1486
1487	*pfVTxDisabled = false;
1488
1489	if ( HWACCMR0Globals.enmHwAccmState != HWACCMSTATE_ENABLED
1490	\|\| !HWACCMR0Globals.vmx.fSupported /* no such issues with AMD-V */
1491	\|\| !HWACCMR0Globals.fGlobalInit /* Local init implies the CPU is currently not in VMX root mode. */)
1492	return VINF_SUCCESS; /* nothing to do */
1493
1494	switch(VMMGetSwitcher(pVM))
1495	{
1496	case VMMSWITCHER_32_TO_32:
1497	case VMMSWITCHER_PAE_TO_PAE:
1498	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1499
1500	case VMMSWITCHER_32_TO_PAE:
1501	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1502	case VMMSWITCHER_AMD64_TO_32:
1503	case VMMSWITCHER_AMD64_TO_PAE:
1504	break; /* unsafe switchers */
1505
1506	default:
1507	AssertFailed();
1508	return VERR_INTERNAL_ERROR;
1509	}
1510
1511	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1512	void *pvPageCpu;
1513	RTHCPHYS pPageCpuPhys;
1514
1515	AssertReturn(pCpu && pCpu->pMemObj, VERR_INTERNAL_ERROR);
1516	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
1517	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
1518
1519	*pfVTxDisabled = true;
1520	return VMXR0DisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
1521	}
1522
1523	/**
1524	* Enable VT-x if was active and the current switcher turned off paging
1525	*
1526	* @returns VBox status code.
1527	* @param pVM VM handle.
1528	* @param fVTxDisabled VT-x was disabled or not
1529	*/
1530	VMMR0DECL(int) HWACCMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1531	{
1532	Assert(!(ASMGetFlags() & X86_EFL_IF));
1533
1534	if (!fVTxDisabled)
1535	return VINF_SUCCESS; /* nothing to do */
1536
1537	Assert( HWACCMR0Globals.enmHwAccmState == HWACCMSTATE_ENABLED
1538	&& HWACCMR0Globals.vmx.fSupported
1539	&& HWACCMR0Globals.fGlobalInit);
1540
1541	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1542	void *pvPageCpu;
1543	RTHCPHYS pPageCpuPhys;
1544
1545	AssertReturn(pCpu && pCpu->pMemObj, VERR_INTERNAL_ERROR);
1546	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
1547	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
1548
1549	return VMXR0EnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
1550	}
1551
1552	#ifdef VBOX_STRICT
1553	/**
1554	* Dumps a descriptor.
1555	*
1556	* @param pDesc Descriptor to dump.
1557	* @param Sel Selector number.
1558	* @param pszMsg Message to prepend the log entry with.
1559	*/
1560	VMMR0DECL(void) HWACCMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1561	{
1562	/*
1563	* Make variable description string.
1564	*/
1565	static struct
1566	{
1567	unsigned cch;
1568	const char *psz;
1569	} const s_aTypes[32] =
1570	{
1571	# define STRENTRY(str) { sizeof(str) - 1, str }
1572
1573	/* system */
1574	# if HC_ARCH_BITS == 64
1575	STRENTRY("Reserved0 "), /* 0x00 */
1576	STRENTRY("Reserved1 "), /* 0x01 */
1577	STRENTRY("LDT "), /* 0x02 */
1578	STRENTRY("Reserved3 "), /* 0x03 */
1579	STRENTRY("Reserved4 "), /* 0x04 */
1580	STRENTRY("Reserved5 "), /* 0x05 */
1581	STRENTRY("Reserved6 "), /* 0x06 */
1582	STRENTRY("Reserved7 "), /* 0x07 */
1583	STRENTRY("Reserved8 "), /* 0x08 */
1584	STRENTRY("TSS64Avail "), /* 0x09 */
1585	STRENTRY("ReservedA "), /* 0x0a */
1586	STRENTRY("TSS64Busy "), /* 0x0b */
1587	STRENTRY("Call64 "), /* 0x0c */
1588	STRENTRY("ReservedD "), /* 0x0d */
1589	STRENTRY("Int64 "), /* 0x0e */
1590	STRENTRY("Trap64 "), /* 0x0f */
1591	# else
1592	STRENTRY("Reserved0 "), /* 0x00 */
1593	STRENTRY("TSS16Avail "), /* 0x01 */
1594	STRENTRY("LDT "), /* 0x02 */
1595	STRENTRY("TSS16Busy "), /* 0x03 */
1596	STRENTRY("Call16 "), /* 0x04 */
1597	STRENTRY("Task "), /* 0x05 */
1598	STRENTRY("Int16 "), /* 0x06 */
1599	STRENTRY("Trap16 "), /* 0x07 */
1600	STRENTRY("Reserved8 "), /* 0x08 */
1601	STRENTRY("TSS32Avail "), /* 0x09 */
1602	STRENTRY("ReservedA "), /* 0x0a */
1603	STRENTRY("TSS32Busy "), /* 0x0b */
1604	STRENTRY("Call32 "), /* 0x0c */
1605	STRENTRY("ReservedD "), /* 0x0d */
1606	STRENTRY("Int32 "), /* 0x0e */
1607	STRENTRY("Trap32 "), /* 0x0f */
1608	# endif
1609	/* non system */
1610	STRENTRY("DataRO "), /* 0x10 */
1611	STRENTRY("DataRO Accessed "), /* 0x11 */
1612	STRENTRY("DataRW "), /* 0x12 */
1613	STRENTRY("DataRW Accessed "), /* 0x13 */
1614	STRENTRY("DataDownRO "), /* 0x14 */
1615	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1616	STRENTRY("DataDownRW "), /* 0x16 */
1617	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1618	STRENTRY("CodeEO "), /* 0x18 */
1619	STRENTRY("CodeEO Accessed "), /* 0x19 */
1620	STRENTRY("CodeER "), /* 0x1a */
1621	STRENTRY("CodeER Accessed "), /* 0x1b */
1622	STRENTRY("CodeConfEO "), /* 0x1c */
1623	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1624	STRENTRY("CodeConfER "), /* 0x1e */
1625	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1626	# undef SYSENTRY
1627	};
1628	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1629	char szMsg[128];
1630	char *psz = &szMsg[0];
1631	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1632	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1633	psz += s_aTypes[i].cch;
1634
1635	if (pDesc->Gen.u1Present)
1636	ADD_STR(psz, "Present ");
1637	else
1638	ADD_STR(psz, "Not-Present ");
1639	# if HC_ARCH_BITS == 64
1640	if (pDesc->Gen.u1Long)
1641	ADD_STR(psz, "64-bit ");
1642	else
1643	ADD_STR(psz, "Comp ");
1644	# else
1645	if (pDesc->Gen.u1Granularity)
1646	ADD_STR(psz, "Page ");
1647	if (pDesc->Gen.u1DefBig)
1648	ADD_STR(psz, "32-bit ");
1649	else
1650	ADD_STR(psz, "16-bit ");
1651	# endif
1652	# undef ADD_STR
1653	*psz = '\0';
1654
1655	/*
1656	* Limit and Base and format the output.
1657	*/
1658	uint32_t u32Limit = X86DESC_LIMIT(*pDesc);
1659	if (pDesc->Gen.u1Granularity)
1660	u32Limit = u32Limit << PAGE_SHIFT \| PAGE_OFFSET_MASK;
1661
1662	# if HC_ARCH_BITS == 64
1663	uint64_t u32Base = X86DESC64_BASE(*pDesc);
1664
1665	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1666	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1667	# else
1668	uint32_t u32Base = X86DESC_BASE(*pDesc);
1669
1670	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1671	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1672	# endif
1673	}
1674
1675	/**
1676	* Formats a full register dump.
1677	*
1678	* @param pVM The VM to operate on.
1679	* @param pVCpu The VMCPU to operate on.
1680	* @param pCtx The context to format.
1681	*/
1682	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1683	{
1684	/*
1685	* Format the flags.
1686	*/
1687	static struct
1688	{
1689	const char pszSet; const char pszClear; uint32_t fFlag;
1690	} aFlags[] =
1691	{
1692	{ "vip",NULL, X86_EFL_VIP },
1693	{ "vif",NULL, X86_EFL_VIF },
1694	{ "ac", NULL, X86_EFL_AC },
1695	{ "vm", NULL, X86_EFL_VM },
1696	{ "rf", NULL, X86_EFL_RF },
1697	{ "nt", NULL, X86_EFL_NT },
1698	{ "ov", "nv", X86_EFL_OF },
1699	{ "dn", "up", X86_EFL_DF },
1700	{ "ei", "di", X86_EFL_IF },
1701	{ "tf", NULL, X86_EFL_TF },
1702	{ "nt", "pl", X86_EFL_SF },
1703	{ "nz", "zr", X86_EFL_ZF },
1704	{ "ac", "na", X86_EFL_AF },
1705	{ "po", "pe", X86_EFL_PF },
1706	{ "cy", "nc", X86_EFL_CF },
1707	};
1708	char szEFlags[80];
1709	char *psz = szEFlags;
1710	uint32_t efl = pCtx->eflags.u32;
1711	for (unsigned i = 0; i < RT_ELEMENTS(aFlags); i++)
1712	{
1713	const char *pszAdd = aFlags[i].fFlag & efl ? aFlags[i].pszSet : aFlags[i].pszClear;
1714	if (pszAdd)
1715	{
1716	strcpy(psz, pszAdd);
1717	psz += strlen(pszAdd);
1718	*psz++ = ' ';
1719	}
1720	}
1721	psz[-1] = '\0';
1722
1723
1724	/*
1725	* Format the registers.
1726	*/
1727	if (CPUMIsGuestIn64BitCode(pVCpu, CPUMCTX2CORE(pCtx)))
1728	{
1729	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1730	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1731	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1732	"r14=%016RX64 r15=%016RX64\n"
1733	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1734	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1735	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1736	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1737	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1738	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1739	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1740	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1741	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1742	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1743	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1744	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1745	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1746	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1747	,
1748	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1749	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1750	pCtx->r14, pCtx->r15,
1751	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1752	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1753	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1754	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1755	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1756	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1757	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1758	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1759	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1760	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1761	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1762	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1763	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1764	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1765	}
1766	else
1767	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1768	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1769	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1770	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1771	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1772	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1773	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1774	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1775	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1776	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1777	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1778	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1779	,
1780	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1781	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1782	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr[0], pCtx->dr[1],
1783	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr[2], pCtx->dr[3],
1784	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr[4], pCtx->dr[5],
1785	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr[6], pCtx->dr[7],
1786	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0, pCtx->cr2,
1787	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3, pCtx->cr4,
1788	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1789	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1790	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1791	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1792
1793	Log(("FPU:\n"
1794	"FCW=%04x FSW=%04x FTW=%02x\n"
1795	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
1796	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1797	,
1798	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
1799	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsrvd1,
1800	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
1801	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
1802
1803
1804	Log(("MSR:\n"
1805	"EFER =%016RX64\n"
1806	"PAT =%016RX64\n"
1807	"STAR =%016RX64\n"
1808	"CSTAR =%016RX64\n"
1809	"LSTAR =%016RX64\n"
1810	"SFMASK =%016RX64\n"
1811	"KERNELGSBASE =%016RX64\n",
1812	pCtx->msrEFER,
1813	pCtx->msrPAT,
1814	pCtx->msrSTAR,
1815	pCtx->msrCSTAR,
1816	pCtx->msrLSTAR,
1817	pCtx->msrSFMASK,
1818	pCtx->msrKERNELGSBASE));
1819
1820	}
1821	#endif /* VBOX_STRICT */
1822
1823	/* Dummy callback handlers. */
1824	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
1825	{
1826	return VINF_SUCCESS;
1827	}
1828
1829	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1830	{
1831	return VINF_SUCCESS;
1832	}
1833
1834	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1835	{
1836	return VINF_SUCCESS;
1837	}
1838
1839	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1840	{
1841	return VINF_SUCCESS;
1842	}
1843
1844	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM)
1845	{
1846	return VINF_SUCCESS;
1847	}
1848
1849	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM)
1850	{
1851	return VINF_SUCCESS;
1852	}
1853
1854	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM)
1855	{
1856	return VINF_SUCCESS;
1857	}
1858
1859	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1860	{
1861	return VINF_SUCCESS;
1862	}
1863
1864	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
1865	{
1866	return VINF_SUCCESS;
1867	}
1868
1869	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1870	{
1871	return VINF_SUCCESS;
1872	}

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp@ 37250

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