HWACCMR0.cpp@ 10537

Last change on this file since 10537 was 10537, checked in by vboxsync, 16 years ago
Updated HWACCMDumpRegs
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1	/* $Id: HWACCMR0.cpp 10537 2008-07-11 16:23:47Z vboxsync $ */
2	/** @file
3	* HWACCM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_vmx.h>
32	#include <VBox/hwacc_svm.h>
33	#include <VBox/pgm.h>
34	#include <VBox/pdm.h>
35	#include <VBox/err.h>
36	#include <VBox/log.h>
37	#include <VBox/selm.h>
38	#include <VBox/iom.h>
39	#include <iprt/param.h>
40	#include <iprt/assert.h>
41	#include <iprt/asm.h>
42	#include <iprt/string.h>
43	#include <iprt/memobj.h>
44	#include <iprt/cpuset.h>
45	#include "HWVMXR0.h"
46	#include "HWSVMR0.h"
47
48	/*******************************************************************************
49	* Internal Functions *
50	*******************************************************************************/
51	static DECLCALLBACK(void) HWACCMR0EnableCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) HWACCMR0DisableCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static int hwaccmr0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu);
55
56	/*******************************************************************************
57	* Local Variables *
58	*******************************************************************************/
59
60	static struct
61	{
62	HWACCM_CPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
63
64	/** Ring 0 handlers for VT-x and AMD-V. */
65	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PHWACCM_CPUINFO pCpu));
66	DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM));
67	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM));
68	DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, CPUMCTX *pCtx));
69	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, CPUMCTX *pCtx));
70	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
71	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
72	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
73	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
74	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVM pVM));
75
76	struct
77	{
78	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
79	bool fSupported;
80
81	/** Host CR4 value (set by ring-0 VMX init) */
82	uint64_t hostCR4;
83
84	/** VMX MSR values */
85	struct
86	{
87	uint64_t feature_ctrl;
88	uint64_t vmx_basic_info;
89	VMX_CAPABILITY vmx_pin_ctls;
90	VMX_CAPABILITY vmx_proc_ctls;
91	VMX_CAPABILITY vmx_exit;
92	VMX_CAPABILITY vmx_entry;
93	uint64_t vmx_misc;
94	uint64_t vmx_cr0_fixed0;
95	uint64_t vmx_cr0_fixed1;
96	uint64_t vmx_cr4_fixed0;
97	uint64_t vmx_cr4_fixed1;
98	uint64_t vmx_vmcs_enum;
99	} msr;
100	/* Last instruction error */
101	uint32_t ulLastInstrError;
102	} vmx;
103	struct
104	{
105	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
106	bool fSupported;
107
108	/** SVM revision. */
109	uint32_t u32Rev;
110
111	/** Maximum ASID allowed. */
112	uint32_t u32MaxASID;
113
114	/** SVM feature bits from cpuid 0x8000000a */
115	uint32_t u32Features;
116	} svm;
117	/** Saved error from detection */
118	int32_t lLastError;
119
120	struct
121	{
122	uint32_t u32AMDFeatureECX;
123	uint32_t u32AMDFeatureEDX;
124	} cpuid;
125
126	HWACCMSTATE enmHwAccmState;
127	} HWACCMR0Globals;
128
129
130
131	/**
132	* Does global Ring-0 HWACCM initialization.
133	*
134	* @returns VBox status code.
135	*/
136	HWACCMR0DECL(int) HWACCMR0Init()
137	{
138	int rc;
139
140	memset(&HWACCMR0Globals, 0, sizeof(HWACCMR0Globals));
141	HWACCMR0Globals.enmHwAccmState = HWACCMSTATE_UNINITIALIZED;
142
143	/* Fill in all callbacks with placeholders. */
144	HWACCMR0Globals.pfnEnterSession = HWACCMR0DummyEnter;
145	HWACCMR0Globals.pfnLeaveSession = HWACCMR0DummyLeave;
146	HWACCMR0Globals.pfnSaveHostState = HWACCMR0DummySaveHostState;
147	HWACCMR0Globals.pfnLoadGuestState = HWACCMR0DummyLoadGuestState;
148	HWACCMR0Globals.pfnRunGuestCode = HWACCMR0DummyRunGuestCode;
149	HWACCMR0Globals.pfnEnableCpu = HWACCMR0DummyEnableCpu;
150	HWACCMR0Globals.pfnDisableCpu = HWACCMR0DummyDisableCpu;
151	HWACCMR0Globals.pfnInitVM = HWACCMR0DummyInitVM;
152	HWACCMR0Globals.pfnTermVM = HWACCMR0DummyTermVM;
153	HWACCMR0Globals.pfnSetupVM = HWACCMR0DummySetupVM;
154
155	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL /* paranoia */
156
157	/*
158	* Check for VT-x and AMD-V capabilities
159	*/
160	if (ASMHasCpuId())
161	{
162	uint32_t u32FeaturesECX;
163	uint32_t u32Dummy;
164	uint32_t u32FeaturesEDX;
165	uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
166
167	ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
168	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
169	/* Query AMD features. */
170	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy, &HWACCMR0Globals.cpuid.u32AMDFeatureECX, &HWACCMR0Globals.cpuid.u32AMDFeatureEDX);
171
172	if ( u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
173	&& u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
174	&& u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX
175	)
176	{
177	/*
178	* Read all VMX MSRs if VMX is available. (same goes for RDMSR/WRMSR)
179	* We also assume all VMX-enabled CPUs support fxsave/fxrstor.
180	*/
181	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
182	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
183	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
184	)
185	{
186	int aRc[RTCPUSET_MAX_CPUS];
187	RTCPUID idCpu = 0;
188
189	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
190
191	/* We need to check if VT-x has been properly initialized on all CPUs. Some BIOSes do a lousy job. */
192	memset(aRc, 0, sizeof(aRc));
193	HWACCMR0Globals.lLastError = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
194
195	/* Check the return code of all invocations. */
196	if (VBOX_SUCCESS(HWACCMR0Globals.lLastError))
197	HWACCMR0Globals.lLastError = hwaccmr0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
198
199	if (VBOX_SUCCESS(HWACCMR0Globals.lLastError))
200	{
201	/* Reread in case we've changed it. */
202	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
203
204	if ( (HWACCMR0Globals.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
205	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
206	{
207	RTR0MEMOBJ pScatchMemObj;
208	void *pvScatchPage;
209	RTHCPHYS pScatchPagePhys;
210
211	HWACCMR0Globals.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
212	HWACCMR0Globals.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
213	HWACCMR0Globals.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
214	HWACCMR0Globals.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
215	HWACCMR0Globals.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
216	HWACCMR0Globals.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
217	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
218	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
219	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
220	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
221	HWACCMR0Globals.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
222	HWACCMR0Globals.vmx.hostCR4 = ASMGetCR4();
223
224	rc = RTR0MemObjAllocCont(&pScatchMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
225	if (RT_FAILURE(rc))
226	return rc;
227
228	pvScatchPage = RTR0MemObjAddress(pScatchMemObj);
229	pScatchPagePhys = RTR0MemObjGetPagePhysAddr(pScatchMemObj, 0);
230	memset(pvScatchPage, 0, PAGE_SIZE);
231
232	/* Set revision dword at the beginning of the structure. */
233	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(HWACCMR0Globals.vmx.msr.vmx_basic_info);
234
235	/* Make sure we don't get rescheduled to another cpu during this probe. */
236	RTCCUINTREG fFlags = ASMIntDisableFlags();
237
238	/*
239	* Check CR4.VMXE
240	*/
241	if (!(HWACCMR0Globals.vmx.hostCR4 & X86_CR4_VMXE))
242	{
243	/* In theory this bit could be cleared behind our back. Which would cause #UD faults when we
244	* try to execute the VMX instructions...
245	*/
246	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4 \| X86_CR4_VMXE);
247	}
248
249	/* Enter VMX Root Mode */
250	rc = VMXEnable(pScatchPagePhys);
251	if (VBOX_FAILURE(rc))
252	{
253	/* KVM leaves the CPU in VMX root mode. Not only is this not allowed, it will crash the host when we enter raw mode, because
254	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify this bit)
255	* (b) turning off paging causes a #GP (unavoidable when switching from long to 32 bits mode or 32 bits to PAE)
256	*
257	* They should fix their code, but until they do we simply refuse to run.
258	*/
259	HWACCMR0Globals.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
260	}
261	else
262	{
263	HWACCMR0Globals.vmx.fSupported = true;
264	VMXDisable();
265	}
266
267	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it wasn't so before (some software could incorrectly think it's in VMX mode) */
268	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4);
269	ASMSetFlags(fFlags);
270
271	RTR0MemObjFree(pScatchMemObj, false);
272	if (VBOX_FAILURE(HWACCMR0Globals.lLastError))
273	return HWACCMR0Globals.lLastError;
274	}
275	else
276	{
277	AssertFailed(); /* can't hit this case anymore */
278	HWACCMR0Globals.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
279	}
280	}
281	#ifdef LOG_ENABLED
282	else
283	SUPR0Printf("HWACCMR0InitCPU failed with rc=%d\n", HWACCMR0Globals.lLastError);
284	#endif
285	}
286	else
287	HWACCMR0Globals.lLastError = VERR_VMX_NO_VMX;
288	}
289	else
290	if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
291	&& u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
292	&& u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX
293	)
294	{
295	/*
296	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
297	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
298	*/
299	if ( (HWACCMR0Globals.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
300	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
301	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
302	)
303	{
304	int aRc[RTCPUSET_MAX_CPUS];
305	RTCPUID idCpu = 0;
306
307	/* We need to check if AMD-V has been properly initialized on all CPUs. Some BIOSes might do a poor job. */
308	memset(aRc, 0, sizeof(aRc));
309	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
310	AssertRC(rc);
311
312	/* Check the return code of all invocations. */
313	if (VBOX_SUCCESS(rc))
314	rc = hwaccmr0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
315
316	AssertMsg(VBOX_SUCCESS(rc), ("HWACCMR0InitCPU failed for cpu %d with rc=%d\n", idCpu, rc));
317
318	if (VBOX_SUCCESS(rc))
319	{
320	/* Query AMD features. */
321	ASMCpuId(0x8000000A, &HWACCMR0Globals.svm.u32Rev, &HWACCMR0Globals.svm.u32MaxASID, &u32Dummy, &HWACCMR0Globals.svm.u32Features);
322
323	HWACCMR0Globals.svm.fSupported = true;
324	}
325	else
326	HWACCMR0Globals.lLastError = rc;
327	}
328	else
329	HWACCMR0Globals.lLastError = VERR_SVM_NO_SVM;
330	}
331	else
332	HWACCMR0Globals.lLastError = VERR_HWACCM_UNKNOWN_CPU;
333	}
334	else
335	HWACCMR0Globals.lLastError = VERR_HWACCM_NO_CPUID;
336
337	#endif /* !VBOX_WITH_HYBIRD_32BIT_KERNEL */
338
339	if (HWACCMR0Globals.vmx.fSupported)
340	{
341	HWACCMR0Globals.pfnEnterSession = VMXR0Enter;
342	HWACCMR0Globals.pfnLeaveSession = VMXR0Leave;
343	HWACCMR0Globals.pfnSaveHostState = VMXR0SaveHostState;
344	HWACCMR0Globals.pfnLoadGuestState = VMXR0LoadGuestState;
345	HWACCMR0Globals.pfnRunGuestCode = VMXR0RunGuestCode;
346	HWACCMR0Globals.pfnEnableCpu = VMXR0EnableCpu;
347	HWACCMR0Globals.pfnDisableCpu = VMXR0DisableCpu;
348	HWACCMR0Globals.pfnInitVM = VMXR0InitVM;
349	HWACCMR0Globals.pfnTermVM = VMXR0TermVM;
350	HWACCMR0Globals.pfnSetupVM = VMXR0SetupVM;
351	}
352	else
353	if (HWACCMR0Globals.svm.fSupported)
354	{
355	HWACCMR0Globals.pfnEnterSession = SVMR0Enter;
356	HWACCMR0Globals.pfnLeaveSession = SVMR0Leave;
357	HWACCMR0Globals.pfnSaveHostState = SVMR0SaveHostState;
358	HWACCMR0Globals.pfnLoadGuestState = SVMR0LoadGuestState;
359	HWACCMR0Globals.pfnRunGuestCode = SVMR0RunGuestCode;
360	HWACCMR0Globals.pfnEnableCpu = SVMR0EnableCpu;
361	HWACCMR0Globals.pfnDisableCpu = SVMR0DisableCpu;
362	HWACCMR0Globals.pfnInitVM = SVMR0InitVM;
363	HWACCMR0Globals.pfnTermVM = SVMR0TermVM;
364	HWACCMR0Globals.pfnSetupVM = SVMR0SetupVM;
365	}
366
367	return VINF_SUCCESS;
368	}
369
370
371	/**
372	* Checks the error code array filled in for each cpu in the system.
373	*
374	* @returns VBox status code.
375	* @param paRc Error code array
376	* @param cErrorCodes Array size
377	* @param pidCpu Value of the first cpu that set an error (out)
378	*/
379	static int hwaccmr0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu)
380	{
381	int rc = VINF_SUCCESS;
382
383	Assert(cErrorCodes == RTCPUSET_MAX_CPUS);
384
385	for (unsigned i=0;i<cErrorCodes;i++)
386	{
387	if (RTMpIsCpuOnline(i))
388	{
389	if (VBOX_FAILURE(paRc[i]))
390	{
391	rc = paRc[i];
392	*pidCpu = i;
393	break;
394	}
395	}
396	}
397	return rc;
398	}
399
400	/**
401	* Does global Ring-0 HWACCM termination.
402	*
403	* @returns VBox status code.
404	*/
405	HWACCMR0DECL(int) HWACCMR0Term()
406	{
407	int aRc[RTCPUSET_MAX_CPUS];
408
409	memset(aRc, 0, sizeof(aRc));
410	int rc = RTMpOnAll(HWACCMR0DisableCPU, aRc, NULL);
411	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
412
413	/* Free the per-cpu pages used for VT-x and AMD-V */
414	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
415	{
416	AssertMsg(VBOX_SUCCESS(aRc[i]), ("HWACCMR0DisableCPU failed for cpu %d with rc=%d\n", i, aRc[i]));
417	if (HWACCMR0Globals.aCpuInfo[i].pMemObj)
418	{
419	RTR0MemObjFree(HWACCMR0Globals.aCpuInfo[i].pMemObj, false);
420	HWACCMR0Globals.aCpuInfo[i].pMemObj = NULL;
421	}
422	}
423	return rc;
424	}
425
426
427	/**
428	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
429	* is to be called on the target cpus.
430	*
431	* @param idCpu The identifier for the CPU the function is called on.
432	* @param pvUser1 The 1st user argument.
433	* @param pvUser2 The 2nd user argument.
434	*/
435	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
436	{
437	unsigned u32VendorEBX = (uintptr_t)pvUser1;
438	int paRc = (int )pvUser2;
439	uint64_t val;
440
441	#ifdef LOG_ENABLED
442	SUPR0Printf("HWACCMR0InitCPU cpu %d\n", idCpu);
443	#endif
444	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
445
446	if (u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX)
447	{
448	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
449
450	/*
451	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
452	* Once the lock bit is set, this MSR can no longer be modified.
453	*/
454	if (!(val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK)))
455	{
456	/* MSR is not yet locked; we can change it ourselves here */
457	ASMWrMsr(MSR_IA32_FEATURE_CONTROL, HWACCMR0Globals.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
458	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
459	}
460	if ( (val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
461	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
462	paRc[idCpu] = VINF_SUCCESS;
463	else
464	paRc[idCpu] = VERR_VMX_MSR_LOCKED_OR_DISABLED;
465	}
466	else
467	if (u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX)
468	{
469	/* Check if SVM is disabled */
470	val = ASMRdMsr(MSR_K8_VM_CR);
471	if (!(val & MSR_K8_VM_CR_SVM_DISABLE))
472	{
473	/* Turn on SVM in the EFER MSR. */
474	val = ASMRdMsr(MSR_K6_EFER);
475	if (!(val & MSR_K6_EFER_SVME))
476	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
477
478	/* Paranoia. */
479	val = ASMRdMsr(MSR_K6_EFER);
480	if (val & MSR_K6_EFER_SVME)
481	paRc[idCpu] = VINF_SUCCESS;
482	else
483	paRc[idCpu] = VERR_SVM_ILLEGAL_EFER_MSR;
484	}
485	else
486	paRc[idCpu] = HWACCMR0Globals.lLastError = VERR_SVM_DISABLED;
487	}
488	else
489	AssertFailed(); /* can't happen */
490	return;
491	}
492
493
494	/**
495	* Sets up HWACCM on all cpus.
496	*
497	* @returns VBox status code.
498	* @param pVM The VM to operate on.
499	* @param enmNewHwAccmState New hwaccm state
500	*
501	*/
502	HWACCMR0DECL(int) HWACCMR0EnableAllCpus(PVM pVM, HWACCMSTATE enmNewHwAccmState)
503	{
504	Assert(sizeof(HWACCMR0Globals.enmHwAccmState) == sizeof(uint32_t));
505	if (ASMAtomicCmpXchgU32((volatile uint32_t *)&HWACCMR0Globals.enmHwAccmState, enmNewHwAccmState, HWACCMSTATE_UNINITIALIZED))
506	{
507	int aRc[RTCPUSET_MAX_CPUS];
508	RTCPUID idCpu = 0;
509
510	/* Don't setup hwaccm as that might not work (vt-x & 64 bits raw mode) */
511	if (enmNewHwAccmState == HWACCMSTATE_DISABLED)
512	return VINF_SUCCESS;
513
514	memset(aRc, 0, sizeof(aRc));
515
516	/* Allocate one page per cpu for the global vt-x and amd-v pages */
517	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
518	{
519	Assert(!HWACCMR0Globals.aCpuInfo[i].pMemObj);
520
521	/** @todo this is rather dangerous if cpus can be taken offline; we don't care for now */
522	if (RTMpIsCpuOnline(i))
523	{
524	int rc = RTR0MemObjAllocCont(&HWACCMR0Globals.aCpuInfo[i].pMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
525	AssertRC(rc);
526	if (RT_FAILURE(rc))
527	return rc;
528
529	void *pvR0 = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[i].pMemObj);
530	Assert(pvR0);
531	memset(pvR0, 0, PAGE_SIZE);
532
533	#ifdef LOG_ENABLED
534	SUPR0Printf("address %x phys %x\n", pvR0, (uint32_t)RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[i].pMemObj, 0));
535	#endif
536	}
537	}
538	/* First time, so initialize each cpu/core */
539	int rc = RTMpOnAll(HWACCMR0EnableCPU, (void *)pVM, aRc);
540
541	/* Check the return code of all invocations. */
542	if (VBOX_SUCCESS(rc))
543	rc = hwaccmr0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
544
545	AssertMsg(VBOX_SUCCESS(rc), ("HWACCMR0EnableAllCpus failed for cpu %d with rc=%d\n", idCpu, rc));
546	return rc;
547	}
548
549	if (HWACCMR0Globals.enmHwAccmState == enmNewHwAccmState)
550	return VINF_SUCCESS;
551
552	/* Request to change the mode is not allowed */
553	return VERR_ACCESS_DENIED;
554	}
555
556	/**
557	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
558	* is to be called on the target cpus.
559	*
560	* @param idCpu The identifier for the CPU the function is called on.
561	* @param pvUser1 The 1st user argument.
562	* @param pvUser2 The 2nd user argument.
563	*/
564	static DECLCALLBACK(void) HWACCMR0EnableCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
565	{
566	PVM pVM = (PVM)pvUser1;
567	int paRc = (int )pvUser2;
568	void *pvPageCpu;
569	RTHCPHYS pPageCpuPhys;
570	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
571
572	Assert(pVM);
573	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
574	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
575
576	pCpu->idCpu = idCpu;
577
578	/* Make sure we start with a clean TLB. */
579	pCpu->fFlushTLB = true;
580
581	/* Should never happen */
582	if (!HWACCMR0Globals.aCpuInfo[idCpu].pMemObj)
583	{
584	AssertFailed();
585	paRc[idCpu] = VERR_INTERNAL_ERROR;
586	return;
587	}
588
589	pvPageCpu = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[idCpu].pMemObj);
590	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[idCpu].pMemObj, 0);
591
592	paRc[idCpu] = HWACCMR0Globals.pfnEnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
593	AssertRC(paRc[idCpu]);
594	if (VBOX_SUCCESS(paRc[idCpu]))
595	HWACCMR0Globals.aCpuInfo[idCpu].fConfigured = true;
596
597	return;
598	}
599
600	/**
601	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
602	* is to be called on the target cpus.
603	*
604	* @param idCpu The identifier for the CPU the function is called on.
605	* @param pvUser1 The 1st user argument.
606	* @param pvUser2 The 2nd user argument.
607	*/
608	static DECLCALLBACK(void) HWACCMR0DisableCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
609	{
610	void *pvPageCpu;
611	RTHCPHYS pPageCpuPhys;
612	int paRc = (int )pvUser1;
613
614	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
615	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
616
617	if (!HWACCMR0Globals.aCpuInfo[idCpu].pMemObj)
618	return;
619
620	pvPageCpu = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[idCpu].pMemObj);
621	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[idCpu].pMemObj, 0);
622
623	paRc[idCpu] = HWACCMR0Globals.pfnDisableCpu(&HWACCMR0Globals.aCpuInfo[idCpu], pvPageCpu, pPageCpuPhys);
624	AssertRC(paRc[idCpu]);
625	HWACCMR0Globals.aCpuInfo[idCpu].fConfigured = false;
626	return;
627	}
628
629
630	/**
631	* Does Ring-0 per VM HWACCM initialization.
632	*
633	* This is mainly to check that the Host CPU mode is compatible
634	* with VMX.
635	*
636	* @returns VBox status code.
637	* @param pVM The VM to operate on.
638	*/
639	HWACCMR0DECL(int) HWACCMR0InitVM(PVM pVM)
640	{
641	AssertReturn(pVM, VERR_INVALID_PARAMETER);
642
643	#ifdef LOG_ENABLED
644	SUPR0Printf("HWACCMR0InitVM: %p\n", pVM);
645	#endif
646
647	pVM->hwaccm.s.vmx.fSupported = HWACCMR0Globals.vmx.fSupported;
648	pVM->hwaccm.s.svm.fSupported = HWACCMR0Globals.svm.fSupported;
649
650	pVM->hwaccm.s.vmx.msr.feature_ctrl = HWACCMR0Globals.vmx.msr.feature_ctrl;
651	pVM->hwaccm.s.vmx.hostCR4 = HWACCMR0Globals.vmx.hostCR4;
652	pVM->hwaccm.s.vmx.msr.vmx_basic_info = HWACCMR0Globals.vmx.msr.vmx_basic_info;
653	pVM->hwaccm.s.vmx.msr.vmx_pin_ctls = HWACCMR0Globals.vmx.msr.vmx_pin_ctls;
654	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls = HWACCMR0Globals.vmx.msr.vmx_proc_ctls;
655	pVM->hwaccm.s.vmx.msr.vmx_exit = HWACCMR0Globals.vmx.msr.vmx_exit;
656	pVM->hwaccm.s.vmx.msr.vmx_entry = HWACCMR0Globals.vmx.msr.vmx_entry;
657	pVM->hwaccm.s.vmx.msr.vmx_misc = HWACCMR0Globals.vmx.msr.vmx_misc;
658	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0;
659	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1;
660	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0;
661	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1;
662	pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum = HWACCMR0Globals.vmx.msr.vmx_vmcs_enum;
663	pVM->hwaccm.s.svm.u32Rev = HWACCMR0Globals.svm.u32Rev;
664	pVM->hwaccm.s.svm.u32MaxASID = HWACCMR0Globals.svm.u32MaxASID;
665	pVM->hwaccm.s.svm.u32Features = HWACCMR0Globals.svm.u32Features;
666	pVM->hwaccm.s.cpuid.u32AMDFeatureECX = HWACCMR0Globals.cpuid.u32AMDFeatureECX;
667	pVM->hwaccm.s.cpuid.u32AMDFeatureEDX = HWACCMR0Globals.cpuid.u32AMDFeatureEDX;
668	pVM->hwaccm.s.lLastError = HWACCMR0Globals.lLastError;
669
670	/* Init a VT-x or AMD-V VM. */
671	return HWACCMR0Globals.pfnInitVM(pVM);
672	}
673
674
675	/**
676	* Does Ring-0 per VM HWACCM termination.
677	*
678	* @returns VBox status code.
679	* @param pVM The VM to operate on.
680	*/
681	HWACCMR0DECL(int) HWACCMR0TermVM(PVM pVM)
682	{
683	AssertReturn(pVM, VERR_INVALID_PARAMETER);
684
685	#ifdef LOG_ENABLED
686	SUPR0Printf("HWACCMR0TermVM: %p\n", pVM);
687	#endif
688
689	/* Terminate a VT-x or AMD-V VM. */
690	return HWACCMR0Globals.pfnTermVM(pVM);
691	}
692
693
694	/**
695	* Sets up a VT-x or AMD-V session
696	*
697	* @returns VBox status code.
698	* @param pVM The VM to operate on.
699	*/
700	HWACCMR0DECL(int) HWACCMR0SetupVM(PVM pVM)
701	{
702	AssertReturn(pVM, VERR_INVALID_PARAMETER);
703
704	#ifdef LOG_ENABLED
705	SUPR0Printf("HWACCMR0SetupVM: %p\n", pVM);
706	#endif
707
708	/* Setup VT-x or AMD-V. */
709	return HWACCMR0Globals.pfnSetupVM(pVM);
710	}
711
712
713	/**
714	* Enters the VT-x or AMD-V session
715	*
716	* @returns VBox status code.
717	* @param pVM The VM to operate on.
718	*/
719	HWACCMR0DECL(int) HWACCMR0Enter(PVM pVM)
720	{
721	CPUMCTX *pCtx;
722	int rc;
723	RTCPUID idCpu = RTMpCpuId();
724
725	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
726	if (VBOX_FAILURE(rc))
727	return rc;
728
729	/* Always load the guest's FPU/XMM state on-demand. */
730	CPUMDeactivateGuestFPUState(pVM);
731
732	/* Always reload the host context and the guest's CR0 register. (!!!!) */
733	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0 \| HWACCM_CHANGED_HOST_CONTEXT;
734
735	/* Setup the register and mask according to the current execution mode. */
736	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
737	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFFFFFFFFFF);
738	else
739	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFF);
740
741	rc = HWACCMR0Globals.pfnEnterSession(pVM, &HWACCMR0Globals.aCpuInfo[idCpu]);
742	AssertRC(rc);
743	rc \|= HWACCMR0Globals.pfnSaveHostState(pVM);
744	AssertRC(rc);
745	rc \|= HWACCMR0Globals.pfnLoadGuestState(pVM, pCtx);
746	AssertRC(rc);
747	return rc;
748	}
749
750
751	/**
752	* Leaves the VT-x or AMD-V session
753	*
754	* @returns VBox status code.
755	* @param pVM The VM to operate on.
756	*/
757	HWACCMR0DECL(int) HWACCMR0Leave(PVM pVM)
758	{
759	CPUMCTX *pCtx;
760	int rc;
761
762	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
763	if (VBOX_FAILURE(rc))
764	return rc;
765
766	/** @note It's rather tricky with longjmps done by e.g. Log statements or the page fault handler. */
767	/* We must restore the host FPU here to make absolutely sure we don't leave the guest FPU state active
768	* or trash somebody else's FPU state.
769	*/
770
771	/* Restore host FPU and XMM state if necessary. */
772	if (CPUMIsGuestFPUStateActive(pVM))
773	{
774	Log2(("CPUMRestoreHostFPUState\n"));
775	/** @note CPUMRestoreHostFPUState keeps the current CR0 intact. */
776	CPUMRestoreHostFPUState(pVM);
777
778	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
779	}
780
781	return HWACCMR0Globals.pfnLeaveSession(pVM);
782	}
783
784	/**
785	* Runs guest code in a hardware accelerated VM.
786	*
787	* @returns VBox status code.
788	* @param pVM The VM to operate on.
789	*/
790	HWACCMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM)
791	{
792	CPUMCTX *pCtx;
793	int rc;
794	RTCPUID idCpu = RTMpCpuId();
795
796	Assert(!VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL));
797	Assert(HWACCMR0Globals.aCpuInfo[idCpu].fConfigured);
798
799	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
800	if (VBOX_FAILURE(rc))
801	return rc;
802
803	return HWACCMR0Globals.pfnRunGuestCode(pVM, pCtx);
804	}
805
806	/**
807	* Returns the cpu structure for the current cpu.
808	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
809	*
810	* @returns cpu structure pointer
811	* @param pVM The VM to operate on.
812	*/
813	HWACCMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu()
814	{
815	RTCPUID idCpu = RTMpCpuId();
816
817	return &HWACCMR0Globals.aCpuInfo[idCpu];
818	}
819
820	#ifdef VBOX_STRICT
821	#include <iprt/string.h>
822	/**
823	* Dumps a descriptor.
824	*
825	* @param pDesc Descriptor to dump.
826	* @param Sel Selector number.
827	* @param pszMsg Message to prepend the log entry with.
828	*/
829	HWACCMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
830	{
831	/*
832	* Make variable description string.
833	*/
834	static struct
835	{
836	unsigned cch;
837	const char *psz;
838	} const aTypes[32] =
839	{
840	#define STRENTRY(str) { sizeof(str) - 1, str }
841
842	/* system */
843	#if HC_ARCH_BITS == 64
844	STRENTRY("Reserved0 "), /* 0x00 */
845	STRENTRY("Reserved1 "), /* 0x01 */
846	STRENTRY("LDT "), /* 0x02 */
847	STRENTRY("Reserved3 "), /* 0x03 */
848	STRENTRY("Reserved4 "), /* 0x04 */
849	STRENTRY("Reserved5 "), /* 0x05 */
850	STRENTRY("Reserved6 "), /* 0x06 */
851	STRENTRY("Reserved7 "), /* 0x07 */
852	STRENTRY("Reserved8 "), /* 0x08 */
853	STRENTRY("TSS64Avail "), /* 0x09 */
854	STRENTRY("ReservedA "), /* 0x0a */
855	STRENTRY("TSS64Busy "), /* 0x0b */
856	STRENTRY("Call64 "), /* 0x0c */
857	STRENTRY("ReservedD "), /* 0x0d */
858	STRENTRY("Int64 "), /* 0x0e */
859	STRENTRY("Trap64 "), /* 0x0f */
860	#else
861	STRENTRY("Reserved0 "), /* 0x00 */
862	STRENTRY("TSS16Avail "), /* 0x01 */
863	STRENTRY("LDT "), /* 0x02 */
864	STRENTRY("TSS16Busy "), /* 0x03 */
865	STRENTRY("Call16 "), /* 0x04 */
866	STRENTRY("Task "), /* 0x05 */
867	STRENTRY("Int16 "), /* 0x06 */
868	STRENTRY("Trap16 "), /* 0x07 */
869	STRENTRY("Reserved8 "), /* 0x08 */
870	STRENTRY("TSS32Avail "), /* 0x09 */
871	STRENTRY("ReservedA "), /* 0x0a */
872	STRENTRY("TSS32Busy "), /* 0x0b */
873	STRENTRY("Call32 "), /* 0x0c */
874	STRENTRY("ReservedD "), /* 0x0d */
875	STRENTRY("Int32 "), /* 0x0e */
876	STRENTRY("Trap32 "), /* 0x0f */
877	#endif
878	/* non system */
879	STRENTRY("DataRO "), /* 0x10 */
880	STRENTRY("DataRO Accessed "), /* 0x11 */
881	STRENTRY("DataRW "), /* 0x12 */
882	STRENTRY("DataRW Accessed "), /* 0x13 */
883	STRENTRY("DataDownRO "), /* 0x14 */
884	STRENTRY("DataDownRO Accessed "), /* 0x15 */
885	STRENTRY("DataDownRW "), /* 0x16 */
886	STRENTRY("DataDownRW Accessed "), /* 0x17 */
887	STRENTRY("CodeEO "), /* 0x18 */
888	STRENTRY("CodeEO Accessed "), /* 0x19 */
889	STRENTRY("CodeER "), /* 0x1a */
890	STRENTRY("CodeER Accessed "), /* 0x1b */
891	STRENTRY("CodeConfEO "), /* 0x1c */
892	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
893	STRENTRY("CodeConfER "), /* 0x1e */
894	STRENTRY("CodeConfER Accessed ") /* 0x1f */
895	#undef SYSENTRY
896	};
897	#define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
898	char szMsg[128];
899	char *psz = &szMsg[0];
900	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
901	memcpy(psz, aTypes[i].psz, aTypes[i].cch);
902	psz += aTypes[i].cch;
903
904	if (pDesc->Gen.u1Present)
905	ADD_STR(psz, "Present ");
906	else
907	ADD_STR(psz, "Not-Present ");
908	#if HC_ARCH_BITS == 64
909	if (pDesc->Gen.u1Long)
910	ADD_STR(psz, "64-bit ");
911	else
912	ADD_STR(psz, "Comp ");
913	#else
914	if (pDesc->Gen.u1Granularity)
915	ADD_STR(psz, "Page ");
916	if (pDesc->Gen.u1DefBig)
917	ADD_STR(psz, "32-bit ");
918	else
919	ADD_STR(psz, "16-bit ");
920	#endif
921	#undef ADD_STR
922	*psz = '\0';
923
924	/*
925	* Limit and Base and format the output.
926	*/
927	uint32_t u32Limit = X86DESC_LIMIT(*pDesc);
928	if (pDesc->Gen.u1Granularity)
929	u32Limit = u32Limit << PAGE_SHIFT \| PAGE_OFFSET_MASK;
930
931	#if HC_ARCH_BITS == 64
932	uint64_t u32Base = X86DESC64_BASE(*pDesc);
933
934	Log(("%s %04x - %VX64 %VX64 - base=%VX64 limit=%08x dpl=%d %s\n", pszMsg,
935	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
936	#else
937	uint32_t u32Base = X86DESC_BASE(*pDesc);
938
939	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
940	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
941	#endif
942	}
943
944	/**
945	* Formats a full register dump.
946	*
947	* @param pVM The VM to operate on.
948	* @param pCtx The context to format.
949	*/
950	HWACCMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx)
951	{
952	/*
953	* Format the flags.
954	*/
955	static struct
956	{
957	const char pszSet; const char pszClear; uint32_t fFlag;
958	} aFlags[] =
959	{
960	{ "vip",NULL, X86_EFL_VIP },
961	{ "vif",NULL, X86_EFL_VIF },
962	{ "ac", NULL, X86_EFL_AC },
963	{ "vm", NULL, X86_EFL_VM },
964	{ "rf", NULL, X86_EFL_RF },
965	{ "nt", NULL, X86_EFL_NT },
966	{ "ov", "nv", X86_EFL_OF },
967	{ "dn", "up", X86_EFL_DF },
968	{ "ei", "di", X86_EFL_IF },
969	{ "tf", NULL, X86_EFL_TF },
970	{ "nt", "pl", X86_EFL_SF },
971	{ "nz", "zr", X86_EFL_ZF },
972	{ "ac", "na", X86_EFL_AF },
973	{ "po", "pe", X86_EFL_PF },
974	{ "cy", "nc", X86_EFL_CF },
975	};
976	char szEFlags[80];
977	char *psz = szEFlags;
978	uint32_t efl = pCtx->eflags.u32;
979	for (unsigned i = 0; i < ELEMENTS(aFlags); i++)
980	{
981	const char *pszAdd = aFlags[i].fFlag & efl ? aFlags[i].pszSet : aFlags[i].pszClear;
982	if (pszAdd)
983	{
984	strcpy(psz, pszAdd);
985	psz += strlen(pszAdd);
986	*psz++ = ' ';
987	}
988	}
989	psz[-1] = '\0';
990
991
992	/*
993	* Format the registers.
994	*/
995	if (CPUMIsGuestIn64BitCode(pVM, CPUMCTX2CORE(pCtx)))
996	{
997	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
998	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
999	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1000	"r14=%016RX64 r15=%016RX64\n"
1001	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1002	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1003	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1004	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1005	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1006	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1007	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1008	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1009	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1010	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1011	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1012	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1013	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1014	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1015	,
1016	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1017	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1018	pCtx->r14, pCtx->r15,
1019	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1020	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1021	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1022	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1023	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1024	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1025	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1026	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1027	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3,
1028	pCtx->dr4, pCtx->dr5, pCtx->dr6, pCtx->dr7,
1029	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1030	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1031	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1032	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1033	}
1034	else
1035	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1036	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1037	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1038	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1039	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1040	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1041	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1042	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1043	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1044	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1045	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1046	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1047	,
1048	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1049	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1050	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr0, pCtx->dr1,
1051	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr2, pCtx->dr3,
1052	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr4, pCtx->dr5,
1053	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr6, pCtx->dr7,
1054	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0, pCtx->cr2,
1055	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3, pCtx->cr4,
1056	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1057	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1058	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1059	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1060
1061	Log(("FPU:\n"
1062	"FCW=%04x FSW=%04x FTW=%02x\n"
1063	"res1=%02x FOP=%04x FPUIP=%08x CS=%04x Rsvrd1=%04x\n"
1064	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1065	,
1066	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
1067	pCtx->fpu.huh1, pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsvrd1,
1068	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
1069	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
1070
1071
1072	Log(("MSR:\n"
1073	"EFER =%016RX64\n"
1074	"PAT =%016RX64\n"
1075	"STAR =%016RX64\n"
1076	"CSTAR =%016RX64\n"
1077	"LSTAR =%016RX64\n"
1078	"SFMASK =%016RX64\n"
1079	"KERNELGSBASE =%016RX64\n",
1080	pCtx->msrEFER,
1081	pCtx->msrPAT,
1082	pCtx->msrSTAR,
1083	pCtx->msrCSTAR,
1084	pCtx->msrLSTAR,
1085	pCtx->msrSFMASK,
1086	pCtx->msrKERNELGSBASE));
1087
1088	}
1089	#endif
1090
1091	/* Dummy callback handlers. */
1092	HWACCMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PHWACCM_CPUINFO pCpu)
1093	{
1094	return VINF_SUCCESS;
1095	}
1096
1097	HWACCMR0DECL(int) HWACCMR0DummyLeave(PVM pVM)
1098	{
1099	return VINF_SUCCESS;
1100	}
1101
1102	HWACCMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1103	{
1104	return VINF_SUCCESS;
1105	}
1106
1107	HWACCMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1108	{
1109	return VINF_SUCCESS;
1110	}
1111
1112	HWACCMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM)
1113	{
1114	return VINF_SUCCESS;
1115	}
1116
1117	HWACCMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM)
1118	{
1119	return VINF_SUCCESS;
1120	}
1121
1122	HWACCMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM)
1123	{
1124	return VINF_SUCCESS;
1125	}
1126
1127	HWACCMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, CPUMCTX *pCtx)
1128	{
1129	return VINF_SUCCESS;
1130	}
1131
1132	HWACCMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM)
1133	{
1134	return VINF_SUCCESS;
1135	}
1136
1137	HWACCMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, CPUMCTX *pCtx)
1138	{
1139	return VINF_SUCCESS;
1140	}

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp@ 10537

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