HWACCMR0.cpp@ 11938

Last change on this file since 11938 was 11311, checked in by vboxsync, 16 years ago
VMM: ELEMENTS -> RT_ELEMENTS.
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1	/* $Id: HWACCMR0.cpp 11311 2008-08-08 23:31:54Z vboxsync $ */
2	/** @file
3	* HWACCM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_vmx.h>
32	#include <VBox/hwacc_svm.h>
33	#include <VBox/pgm.h>
34	#include <VBox/pdm.h>
35	#include <VBox/err.h>
36	#include <VBox/log.h>
37	#include <VBox/selm.h>
38	#include <VBox/iom.h>
39	#include <iprt/param.h>
40	#include <iprt/assert.h>
41	#include <iprt/asm.h>
42	#include <iprt/string.h>
43	#include <iprt/memobj.h>
44	#include <iprt/cpuset.h>
45	#include "HWVMXR0.h"
46	#include "HWSVMR0.h"
47
48	/*******************************************************************************
49	* Internal Functions *
50	*******************************************************************************/
51	static DECLCALLBACK(void) HWACCMR0EnableCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) HWACCMR0DisableCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static int hwaccmr0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu);
55
56	/*******************************************************************************
57	* Local Variables *
58	*******************************************************************************/
59
60	static struct
61	{
62	HWACCM_CPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
63
64	/** Ring 0 handlers for VT-x and AMD-V. */
65	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PHWACCM_CPUINFO pCpu));
66	DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM));
67	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM));
68	DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, CPUMCTX *pCtx));
69	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, CPUMCTX *pCtx));
70	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
71	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
72	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
73	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
74	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVM pVM));
75
76	struct
77	{
78	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
79	bool fSupported;
80
81	/** Host CR4 value (set by ring-0 VMX init) */
82	uint64_t hostCR4;
83
84	/** VMX MSR values */
85	struct
86	{
87	uint64_t feature_ctrl;
88	uint64_t vmx_basic_info;
89	VMX_CAPABILITY vmx_pin_ctls;
90	VMX_CAPABILITY vmx_proc_ctls;
91	VMX_CAPABILITY vmx_proc_ctls2;
92	VMX_CAPABILITY vmx_exit;
93	VMX_CAPABILITY vmx_entry;
94	uint64_t vmx_misc;
95	uint64_t vmx_cr0_fixed0;
96	uint64_t vmx_cr0_fixed1;
97	uint64_t vmx_cr4_fixed0;
98	uint64_t vmx_cr4_fixed1;
99	uint64_t vmx_vmcs_enum;
100	uint64_t vmx_eptcaps;
101	} msr;
102	/* Last instruction error */
103	uint32_t ulLastInstrError;
104	} vmx;
105	struct
106	{
107	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
108	bool fSupported;
109
110	/** SVM revision. */
111	uint32_t u32Rev;
112
113	/** Maximum ASID allowed. */
114	uint32_t u32MaxASID;
115
116	/** SVM feature bits from cpuid 0x8000000a */
117	uint32_t u32Features;
118	} svm;
119	/** Saved error from detection */
120	int32_t lLastError;
121
122	struct
123	{
124	uint32_t u32AMDFeatureECX;
125	uint32_t u32AMDFeatureEDX;
126	} cpuid;
127
128	HWACCMSTATE enmHwAccmState;
129	} HWACCMR0Globals;
130
131
132
133	/**
134	* Does global Ring-0 HWACCM initialization.
135	*
136	* @returns VBox status code.
137	*/
138	HWACCMR0DECL(int) HWACCMR0Init()
139	{
140	int rc;
141
142	memset(&HWACCMR0Globals, 0, sizeof(HWACCMR0Globals));
143	HWACCMR0Globals.enmHwAccmState = HWACCMSTATE_UNINITIALIZED;
144	for (unsigned i = 0; i < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); i++)
145	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
146
147	/* Fill in all callbacks with placeholders. */
148	HWACCMR0Globals.pfnEnterSession = HWACCMR0DummyEnter;
149	HWACCMR0Globals.pfnLeaveSession = HWACCMR0DummyLeave;
150	HWACCMR0Globals.pfnSaveHostState = HWACCMR0DummySaveHostState;
151	HWACCMR0Globals.pfnLoadGuestState = HWACCMR0DummyLoadGuestState;
152	HWACCMR0Globals.pfnRunGuestCode = HWACCMR0DummyRunGuestCode;
153	HWACCMR0Globals.pfnEnableCpu = HWACCMR0DummyEnableCpu;
154	HWACCMR0Globals.pfnDisableCpu = HWACCMR0DummyDisableCpu;
155	HWACCMR0Globals.pfnInitVM = HWACCMR0DummyInitVM;
156	HWACCMR0Globals.pfnTermVM = HWACCMR0DummyTermVM;
157	HWACCMR0Globals.pfnSetupVM = HWACCMR0DummySetupVM;
158
159	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL /* paranoia */
160
161	/*
162	* Check for VT-x and AMD-V capabilities
163	*/
164	if (ASMHasCpuId())
165	{
166	uint32_t u32FeaturesECX;
167	uint32_t u32Dummy;
168	uint32_t u32FeaturesEDX;
169	uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
170
171	ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
172	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
173	/* Query AMD features. */
174	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy, &HWACCMR0Globals.cpuid.u32AMDFeatureECX, &HWACCMR0Globals.cpuid.u32AMDFeatureEDX);
175
176	if ( u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
177	&& u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
178	&& u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX
179	)
180	{
181	/*
182	* Read all VMX MSRs if VMX is available. (same goes for RDMSR/WRMSR)
183	* We also assume all VMX-enabled CPUs support fxsave/fxrstor.
184	*/
185	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
186	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
187	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
188	)
189	{
190	int aRc[RTCPUSET_MAX_CPUS];
191	RTCPUID idCpu = 0;
192
193	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
194
195	/* We need to check if VT-x has been properly initialized on all CPUs. Some BIOSes do a lousy job. */
196	memset(aRc, 0, sizeof(aRc));
197	HWACCMR0Globals.lLastError = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
198
199	/* Check the return code of all invocations. */
200	if (VBOX_SUCCESS(HWACCMR0Globals.lLastError))
201	HWACCMR0Globals.lLastError = hwaccmr0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
202
203	if (VBOX_SUCCESS(HWACCMR0Globals.lLastError))
204	{
205	/* Reread in case we've changed it. */
206	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
207
208	if ( (HWACCMR0Globals.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
209	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
210	{
211	RTR0MEMOBJ pScatchMemObj;
212	void *pvScatchPage;
213	RTHCPHYS pScatchPagePhys;
214
215	HWACCMR0Globals.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
216	HWACCMR0Globals.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
217	HWACCMR0Globals.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
218	HWACCMR0Globals.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
219	HWACCMR0Globals.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
220	HWACCMR0Globals.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
221	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
222	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
223	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
224	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
225	HWACCMR0Globals.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
226
227	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
228	{
229	HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
230	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT\|VMX_VMCS_CTRL_PROC_EXEC2_VPID))
231	HWACCMR0Globals.vmx.msr.vmx_eptcaps = ASMRdMsr(MSR_IA32_VMX_EPT_CAPS);
232	}
233
234	HWACCMR0Globals.vmx.hostCR4 = ASMGetCR4();
235
236	rc = RTR0MemObjAllocCont(&pScatchMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
237	if (RT_FAILURE(rc))
238	return rc;
239
240	pvScatchPage = RTR0MemObjAddress(pScatchMemObj);
241	pScatchPagePhys = RTR0MemObjGetPagePhysAddr(pScatchMemObj, 0);
242	memset(pvScatchPage, 0, PAGE_SIZE);
243
244	/* Set revision dword at the beginning of the structure. */
245	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(HWACCMR0Globals.vmx.msr.vmx_basic_info);
246
247	/* Make sure we don't get rescheduled to another cpu during this probe. */
248	RTCCUINTREG fFlags = ASMIntDisableFlags();
249
250	/*
251	* Check CR4.VMXE
252	*/
253	if (!(HWACCMR0Globals.vmx.hostCR4 & X86_CR4_VMXE))
254	{
255	/* In theory this bit could be cleared behind our back. Which would cause #UD faults when we
256	* try to execute the VMX instructions...
257	*/
258	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4 \| X86_CR4_VMXE);
259	}
260
261	/* Enter VMX Root Mode */
262	rc = VMXEnable(pScatchPagePhys);
263	if (VBOX_FAILURE(rc))
264	{
265	/* KVM leaves the CPU in VMX root mode. Not only is this not allowed, it will crash the host when we enter raw mode, because
266	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify this bit)
267	* (b) turning off paging causes a #GP (unavoidable when switching from long to 32 bits mode or 32 bits to PAE)
268	*
269	* They should fix their code, but until they do we simply refuse to run.
270	*/
271	HWACCMR0Globals.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
272	}
273	else
274	{
275	HWACCMR0Globals.vmx.fSupported = true;
276	VMXDisable();
277	}
278
279	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it wasn't so before (some software could incorrectly think it's in VMX mode) */
280	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4);
281	ASMSetFlags(fFlags);
282
283	RTR0MemObjFree(pScatchMemObj, false);
284	if (VBOX_FAILURE(HWACCMR0Globals.lLastError))
285	return HWACCMR0Globals.lLastError;
286	}
287	else
288	{
289	AssertFailed(); /* can't hit this case anymore */
290	HWACCMR0Globals.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
291	}
292	}
293	#ifdef LOG_ENABLED
294	else
295	SUPR0Printf("HWACCMR0InitCPU failed with rc=%d\n", HWACCMR0Globals.lLastError);
296	#endif
297	}
298	else
299	HWACCMR0Globals.lLastError = VERR_VMX_NO_VMX;
300	}
301	else
302	if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
303	&& u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
304	&& u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX
305	)
306	{
307	/*
308	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
309	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
310	*/
311	if ( (HWACCMR0Globals.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
312	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
313	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
314	)
315	{
316	int aRc[RTCPUSET_MAX_CPUS];
317	RTCPUID idCpu = 0;
318
319	/* We need to check if AMD-V has been properly initialized on all CPUs. Some BIOSes might do a poor job. */
320	memset(aRc, 0, sizeof(aRc));
321	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
322	AssertRC(rc);
323
324	/* Check the return code of all invocations. */
325	if (VBOX_SUCCESS(rc))
326	rc = hwaccmr0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
327
328	AssertMsg(VBOX_SUCCESS(rc), ("HWACCMR0InitCPU failed for cpu %d with rc=%d\n", idCpu, rc));
329
330	if (VBOX_SUCCESS(rc))
331	{
332	/* Query AMD features. */
333	ASMCpuId(0x8000000A, &HWACCMR0Globals.svm.u32Rev, &HWACCMR0Globals.svm.u32MaxASID, &u32Dummy, &HWACCMR0Globals.svm.u32Features);
334
335	HWACCMR0Globals.svm.fSupported = true;
336	}
337	else
338	HWACCMR0Globals.lLastError = rc;
339	}
340	else
341	HWACCMR0Globals.lLastError = VERR_SVM_NO_SVM;
342	}
343	else
344	HWACCMR0Globals.lLastError = VERR_HWACCM_UNKNOWN_CPU;
345	}
346	else
347	HWACCMR0Globals.lLastError = VERR_HWACCM_NO_CPUID;
348
349	#endif /* !VBOX_WITH_HYBIRD_32BIT_KERNEL */
350
351	if (HWACCMR0Globals.vmx.fSupported)
352	{
353	HWACCMR0Globals.pfnEnterSession = VMXR0Enter;
354	HWACCMR0Globals.pfnLeaveSession = VMXR0Leave;
355	HWACCMR0Globals.pfnSaveHostState = VMXR0SaveHostState;
356	HWACCMR0Globals.pfnLoadGuestState = VMXR0LoadGuestState;
357	HWACCMR0Globals.pfnRunGuestCode = VMXR0RunGuestCode;
358	HWACCMR0Globals.pfnEnableCpu = VMXR0EnableCpu;
359	HWACCMR0Globals.pfnDisableCpu = VMXR0DisableCpu;
360	HWACCMR0Globals.pfnInitVM = VMXR0InitVM;
361	HWACCMR0Globals.pfnTermVM = VMXR0TermVM;
362	HWACCMR0Globals.pfnSetupVM = VMXR0SetupVM;
363	}
364	else
365	if (HWACCMR0Globals.svm.fSupported)
366	{
367	HWACCMR0Globals.pfnEnterSession = SVMR0Enter;
368	HWACCMR0Globals.pfnLeaveSession = SVMR0Leave;
369	HWACCMR0Globals.pfnSaveHostState = SVMR0SaveHostState;
370	HWACCMR0Globals.pfnLoadGuestState = SVMR0LoadGuestState;
371	HWACCMR0Globals.pfnRunGuestCode = SVMR0RunGuestCode;
372	HWACCMR0Globals.pfnEnableCpu = SVMR0EnableCpu;
373	HWACCMR0Globals.pfnDisableCpu = SVMR0DisableCpu;
374	HWACCMR0Globals.pfnInitVM = SVMR0InitVM;
375	HWACCMR0Globals.pfnTermVM = SVMR0TermVM;
376	HWACCMR0Globals.pfnSetupVM = SVMR0SetupVM;
377	}
378
379	return VINF_SUCCESS;
380	}
381
382
383	/**
384	* Checks the error code array filled in for each cpu in the system.
385	*
386	* @returns VBox status code.
387	* @param paRc Error code array
388	* @param cErrorCodes Array size
389	* @param pidCpu Value of the first cpu that set an error (out)
390	*/
391	static int hwaccmr0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu)
392	{
393	int rc = VINF_SUCCESS;
394
395	Assert(cErrorCodes == RTCPUSET_MAX_CPUS);
396
397	for (unsigned i=0;i<cErrorCodes;i++)
398	{
399	if (RTMpIsCpuOnline(i))
400	{
401	if (VBOX_FAILURE(paRc[i]))
402	{
403	rc = paRc[i];
404	*pidCpu = i;
405	break;
406	}
407	}
408	}
409	return rc;
410	}
411
412	/**
413	* Does global Ring-0 HWACCM termination.
414	*
415	* @returns VBox status code.
416	*/
417	HWACCMR0DECL(int) HWACCMR0Term()
418	{
419	int aRc[RTCPUSET_MAX_CPUS];
420
421	memset(aRc, 0, sizeof(aRc));
422	int rc = RTMpOnAll(HWACCMR0DisableCPU, aRc, NULL);
423	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
424
425	/* Free the per-cpu pages used for VT-x and AMD-V */
426	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
427	{
428	AssertMsg(VBOX_SUCCESS(aRc[i]), ("HWACCMR0DisableCPU failed for cpu %d with rc=%d\n", i, aRc[i]));
429	if (HWACCMR0Globals.aCpuInfo[i].pMemObj != NIL_RTR0MEMOBJ)
430	{
431	RTR0MemObjFree(HWACCMR0Globals.aCpuInfo[i].pMemObj, false);
432	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
433	}
434	}
435	return rc;
436	}
437
438
439	/**
440	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
441	* is to be called on the target cpus.
442	*
443	* @param idCpu The identifier for the CPU the function is called on.
444	* @param pvUser1 The 1st user argument.
445	* @param pvUser2 The 2nd user argument.
446	*/
447	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
448	{
449	unsigned u32VendorEBX = (uintptr_t)pvUser1;
450	int paRc = (int )pvUser2;
451	uint64_t val;
452
453	#ifdef LOG_ENABLED
454	SUPR0Printf("HWACCMR0InitCPU cpu %d\n", idCpu);
455	#endif
456	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
457
458	if (u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX)
459	{
460	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
461
462	/*
463	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
464	* Once the lock bit is set, this MSR can no longer be modified.
465	*/
466	if (!(val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK)))
467	{
468	/* MSR is not yet locked; we can change it ourselves here */
469	ASMWrMsr(MSR_IA32_FEATURE_CONTROL, HWACCMR0Globals.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
470	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
471	}
472	if ( (val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
473	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
474	paRc[idCpu] = VINF_SUCCESS;
475	else
476	paRc[idCpu] = VERR_VMX_MSR_LOCKED_OR_DISABLED;
477	}
478	else
479	if (u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX)
480	{
481	/* Check if SVM is disabled */
482	val = ASMRdMsr(MSR_K8_VM_CR);
483	if (!(val & MSR_K8_VM_CR_SVM_DISABLE))
484	{
485	/* Turn on SVM in the EFER MSR. */
486	val = ASMRdMsr(MSR_K6_EFER);
487	if (!(val & MSR_K6_EFER_SVME))
488	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
489
490	/* Paranoia. */
491	val = ASMRdMsr(MSR_K6_EFER);
492	if (val & MSR_K6_EFER_SVME)
493	paRc[idCpu] = VINF_SUCCESS;
494	else
495	paRc[idCpu] = VERR_SVM_ILLEGAL_EFER_MSR;
496	}
497	else
498	paRc[idCpu] = HWACCMR0Globals.lLastError = VERR_SVM_DISABLED;
499	}
500	else
501	AssertFailed(); /* can't happen */
502	return;
503	}
504
505
506	/**
507	* Sets up HWACCM on all cpus.
508	*
509	* @returns VBox status code.
510	* @param pVM The VM to operate on.
511	* @param enmNewHwAccmState New hwaccm state
512	*
513	*/
514	HWACCMR0DECL(int) HWACCMR0EnableAllCpus(PVM pVM, HWACCMSTATE enmNewHwAccmState)
515	{
516	Assert(sizeof(HWACCMR0Globals.enmHwAccmState) == sizeof(uint32_t));
517	if (ASMAtomicCmpXchgU32((volatile uint32_t *)&HWACCMR0Globals.enmHwAccmState, enmNewHwAccmState, HWACCMSTATE_UNINITIALIZED))
518	{
519	int aRc[RTCPUSET_MAX_CPUS];
520	RTCPUID idCpu = 0;
521
522	/* Don't setup hwaccm as that might not work (vt-x & 64 bits raw mode) */
523	if (enmNewHwAccmState == HWACCMSTATE_DISABLED)
524	return VINF_SUCCESS;
525
526	memset(aRc, 0, sizeof(aRc));
527
528	/* Allocate one page per cpu for the global vt-x and amd-v pages */
529	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
530	{
531	Assert(!HWACCMR0Globals.aCpuInfo[i].pMemObj);
532
533	/** @todo this is rather dangerous if cpus can be taken offline; we don't care for now */
534	if (RTMpIsCpuOnline(i))
535	{
536	int rc = RTR0MemObjAllocCont(&HWACCMR0Globals.aCpuInfo[i].pMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
537	AssertRC(rc);
538	if (RT_FAILURE(rc))
539	return rc;
540
541	void *pvR0 = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[i].pMemObj);
542	Assert(pvR0);
543	ASMMemZeroPage(pvR0);
544
545	#ifdef LOG_ENABLED
546	SUPR0Printf("address %x phys %x\n", pvR0, (uint32_t)RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[i].pMemObj, 0));
547	#endif
548	}
549	}
550	/* First time, so initialize each cpu/core */
551	int rc = RTMpOnAll(HWACCMR0EnableCPU, (void *)pVM, aRc);
552
553	/* Check the return code of all invocations. */
554	if (VBOX_SUCCESS(rc))
555	rc = hwaccmr0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
556
557	AssertMsg(VBOX_SUCCESS(rc), ("HWACCMR0EnableAllCpus failed for cpu %d with rc=%d\n", idCpu, rc));
558	return rc;
559	}
560
561	if (HWACCMR0Globals.enmHwAccmState == enmNewHwAccmState)
562	return VINF_SUCCESS;
563
564	/* Request to change the mode is not allowed */
565	return VERR_ACCESS_DENIED;
566	}
567
568	/**
569	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
570	* is to be called on the target cpus.
571	*
572	* @param idCpu The identifier for the CPU the function is called on.
573	* @param pvUser1 The 1st user argument.
574	* @param pvUser2 The 2nd user argument.
575	*/
576	static DECLCALLBACK(void) HWACCMR0EnableCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
577	{
578	PVM pVM = (PVM)pvUser1;
579	int paRc = (int )pvUser2;
580	void *pvPageCpu;
581	RTHCPHYS pPageCpuPhys;
582	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
583
584	Assert(pVM);
585	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
586	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
587
588	pCpu->idCpu = idCpu;
589
590	/* Make sure we start with a clean TLB. */
591	pCpu->fFlushTLB = true;
592
593	/* Should never happen */
594	if (!HWACCMR0Globals.aCpuInfo[idCpu].pMemObj)
595	{
596	AssertFailed();
597	paRc[idCpu] = VERR_INTERNAL_ERROR;
598	return;
599	}
600
601	pvPageCpu = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[idCpu].pMemObj);
602	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[idCpu].pMemObj, 0);
603
604	paRc[idCpu] = HWACCMR0Globals.pfnEnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
605	AssertRC(paRc[idCpu]);
606	if (VBOX_SUCCESS(paRc[idCpu]))
607	HWACCMR0Globals.aCpuInfo[idCpu].fConfigured = true;
608
609	return;
610	}
611
612	/**
613	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
614	* is to be called on the target cpus.
615	*
616	* @param idCpu The identifier for the CPU the function is called on.
617	* @param pvUser1 The 1st user argument.
618	* @param pvUser2 The 2nd user argument.
619	*/
620	static DECLCALLBACK(void) HWACCMR0DisableCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
621	{
622	void *pvPageCpu;
623	RTHCPHYS pPageCpuPhys;
624	int paRc = (int )pvUser1;
625
626	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
627	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
628
629	if (!HWACCMR0Globals.aCpuInfo[idCpu].pMemObj)
630	return;
631
632	pvPageCpu = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[idCpu].pMemObj);
633	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[idCpu].pMemObj, 0);
634
635	paRc[idCpu] = HWACCMR0Globals.pfnDisableCpu(&HWACCMR0Globals.aCpuInfo[idCpu], pvPageCpu, pPageCpuPhys);
636	AssertRC(paRc[idCpu]);
637	HWACCMR0Globals.aCpuInfo[idCpu].fConfigured = false;
638	return;
639	}
640
641
642	/**
643	* Does Ring-0 per VM HWACCM initialization.
644	*
645	* This is mainly to check that the Host CPU mode is compatible
646	* with VMX.
647	*
648	* @returns VBox status code.
649	* @param pVM The VM to operate on.
650	*/
651	HWACCMR0DECL(int) HWACCMR0InitVM(PVM pVM)
652	{
653	AssertReturn(pVM, VERR_INVALID_PARAMETER);
654
655	#ifdef LOG_ENABLED
656	SUPR0Printf("HWACCMR0InitVM: %p\n", pVM);
657	#endif
658
659	pVM->hwaccm.s.vmx.fSupported = HWACCMR0Globals.vmx.fSupported;
660	pVM->hwaccm.s.svm.fSupported = HWACCMR0Globals.svm.fSupported;
661
662	pVM->hwaccm.s.vmx.msr.feature_ctrl = HWACCMR0Globals.vmx.msr.feature_ctrl;
663	pVM->hwaccm.s.vmx.hostCR4 = HWACCMR0Globals.vmx.hostCR4;
664	pVM->hwaccm.s.vmx.msr.vmx_basic_info = HWACCMR0Globals.vmx.msr.vmx_basic_info;
665	pVM->hwaccm.s.vmx.msr.vmx_pin_ctls = HWACCMR0Globals.vmx.msr.vmx_pin_ctls;
666	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls = HWACCMR0Globals.vmx.msr.vmx_proc_ctls;
667	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2 = HWACCMR0Globals.vmx.msr.vmx_proc_ctls2;
668	pVM->hwaccm.s.vmx.msr.vmx_exit = HWACCMR0Globals.vmx.msr.vmx_exit;
669	pVM->hwaccm.s.vmx.msr.vmx_entry = HWACCMR0Globals.vmx.msr.vmx_entry;
670	pVM->hwaccm.s.vmx.msr.vmx_misc = HWACCMR0Globals.vmx.msr.vmx_misc;
671	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0;
672	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1;
673	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0;
674	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1;
675	pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum = HWACCMR0Globals.vmx.msr.vmx_vmcs_enum;
676	pVM->hwaccm.s.vmx.msr.vmx_eptcaps = HWACCMR0Globals.vmx.msr.vmx_eptcaps;
677	pVM->hwaccm.s.svm.u32Rev = HWACCMR0Globals.svm.u32Rev;
678	pVM->hwaccm.s.svm.u32MaxASID = HWACCMR0Globals.svm.u32MaxASID;
679	pVM->hwaccm.s.svm.u32Features = HWACCMR0Globals.svm.u32Features;
680	pVM->hwaccm.s.cpuid.u32AMDFeatureECX = HWACCMR0Globals.cpuid.u32AMDFeatureECX;
681	pVM->hwaccm.s.cpuid.u32AMDFeatureEDX = HWACCMR0Globals.cpuid.u32AMDFeatureEDX;
682	pVM->hwaccm.s.lLastError = HWACCMR0Globals.lLastError;
683
684	/* Init a VT-x or AMD-V VM. */
685	return HWACCMR0Globals.pfnInitVM(pVM);
686	}
687
688
689	/**
690	* Does Ring-0 per VM HWACCM termination.
691	*
692	* @returns VBox status code.
693	* @param pVM The VM to operate on.
694	*/
695	HWACCMR0DECL(int) HWACCMR0TermVM(PVM pVM)
696	{
697	AssertReturn(pVM, VERR_INVALID_PARAMETER);
698
699	#ifdef LOG_ENABLED
700	SUPR0Printf("HWACCMR0TermVM: %p\n", pVM);
701	#endif
702
703	/* Terminate a VT-x or AMD-V VM. */
704	return HWACCMR0Globals.pfnTermVM(pVM);
705	}
706
707
708	/**
709	* Sets up a VT-x or AMD-V session
710	*
711	* @returns VBox status code.
712	* @param pVM The VM to operate on.
713	*/
714	HWACCMR0DECL(int) HWACCMR0SetupVM(PVM pVM)
715	{
716	AssertReturn(pVM, VERR_INVALID_PARAMETER);
717
718	#ifdef LOG_ENABLED
719	SUPR0Printf("HWACCMR0SetupVM: %p\n", pVM);
720	#endif
721
722	/* Setup VT-x or AMD-V. */
723	return HWACCMR0Globals.pfnSetupVM(pVM);
724	}
725
726
727	/**
728	* Enters the VT-x or AMD-V session
729	*
730	* @returns VBox status code.
731	* @param pVM The VM to operate on.
732	*/
733	HWACCMR0DECL(int) HWACCMR0Enter(PVM pVM)
734	{
735	CPUMCTX *pCtx;
736	int rc;
737	RTCPUID idCpu = RTMpCpuId();
738
739	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
740	if (VBOX_FAILURE(rc))
741	return rc;
742
743	/* Always load the guest's FPU/XMM state on-demand. */
744	CPUMDeactivateGuestFPUState(pVM);
745
746	/* Always reload the host context and the guest's CR0 register. (!!!!) */
747	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0 \| HWACCM_CHANGED_HOST_CONTEXT;
748
749	/* Setup the register and mask according to the current execution mode. */
750	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
751	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFFFFFFFFFF);
752	else
753	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFF);
754
755	rc = HWACCMR0Globals.pfnEnterSession(pVM, &HWACCMR0Globals.aCpuInfo[idCpu]);
756	AssertRC(rc);
757	/* We must save the host context here (VT-x) as we might be rescheduled on a different cpu after a long jump back to ring 3. */
758	rc \|= HWACCMR0Globals.pfnSaveHostState(pVM);
759	AssertRC(rc);
760	rc \|= HWACCMR0Globals.pfnLoadGuestState(pVM, pCtx);
761	AssertRC(rc);
762	return rc;
763	}
764
765
766	/**
767	* Leaves the VT-x or AMD-V session
768	*
769	* @returns VBox status code.
770	* @param pVM The VM to operate on.
771	*/
772	HWACCMR0DECL(int) HWACCMR0Leave(PVM pVM)
773	{
774	CPUMCTX *pCtx;
775	int rc;
776
777	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
778	if (VBOX_FAILURE(rc))
779	return rc;
780
781	/** @note It's rather tricky with longjmps done by e.g. Log statements or the page fault handler. */
782	/* We must restore the host FPU here to make absolutely sure we don't leave the guest FPU state active
783	* or trash somebody else's FPU state.
784	*/
785	/* Save the guest FPU and XMM state if necessary. */
786	if (CPUMIsGuestFPUStateActive(pVM))
787	{
788	Log2(("CPUMR0SaveGuestFPU\n"));
789	CPUMR0SaveGuestFPU(pVM, pCtx);
790
791	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
792	}
793
794	return HWACCMR0Globals.pfnLeaveSession(pVM);
795	}
796
797	/**
798	* Runs guest code in a hardware accelerated VM.
799	*
800	* @returns VBox status code.
801	* @param pVM The VM to operate on.
802	*/
803	HWACCMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM)
804	{
805	CPUMCTX *pCtx;
806	int rc;
807	RTCPUID idCpu = RTMpCpuId(); NOREF(idCpu);
808
809	Assert(!VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL));
810	Assert(HWACCMR0Globals.aCpuInfo[idCpu].fConfigured);
811
812	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
813	if (VBOX_FAILURE(rc))
814	return rc;
815
816	return HWACCMR0Globals.pfnRunGuestCode(pVM, pCtx);
817	}
818
819	/**
820	* Returns the cpu structure for the current cpu.
821	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
822	*
823	* @returns cpu structure pointer
824	* @param pVM The VM to operate on.
825	*/
826	HWACCMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu()
827	{
828	RTCPUID idCpu = RTMpCpuId();
829
830	return &HWACCMR0Globals.aCpuInfo[idCpu];
831	}
832
833	#ifdef VBOX_STRICT
834	#include <iprt/string.h>
835	/**
836	* Dumps a descriptor.
837	*
838	* @param pDesc Descriptor to dump.
839	* @param Sel Selector number.
840	* @param pszMsg Message to prepend the log entry with.
841	*/
842	HWACCMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
843	{
844	/*
845	* Make variable description string.
846	*/
847	static struct
848	{
849	unsigned cch;
850	const char *psz;
851	} const aTypes[32] =
852	{
853	#define STRENTRY(str) { sizeof(str) - 1, str }
854
855	/* system */
856	#if HC_ARCH_BITS == 64
857	STRENTRY("Reserved0 "), /* 0x00 */
858	STRENTRY("Reserved1 "), /* 0x01 */
859	STRENTRY("LDT "), /* 0x02 */
860	STRENTRY("Reserved3 "), /* 0x03 */
861	STRENTRY("Reserved4 "), /* 0x04 */
862	STRENTRY("Reserved5 "), /* 0x05 */
863	STRENTRY("Reserved6 "), /* 0x06 */
864	STRENTRY("Reserved7 "), /* 0x07 */
865	STRENTRY("Reserved8 "), /* 0x08 */
866	STRENTRY("TSS64Avail "), /* 0x09 */
867	STRENTRY("ReservedA "), /* 0x0a */
868	STRENTRY("TSS64Busy "), /* 0x0b */
869	STRENTRY("Call64 "), /* 0x0c */
870	STRENTRY("ReservedD "), /* 0x0d */
871	STRENTRY("Int64 "), /* 0x0e */
872	STRENTRY("Trap64 "), /* 0x0f */
873	#else
874	STRENTRY("Reserved0 "), /* 0x00 */
875	STRENTRY("TSS16Avail "), /* 0x01 */
876	STRENTRY("LDT "), /* 0x02 */
877	STRENTRY("TSS16Busy "), /* 0x03 */
878	STRENTRY("Call16 "), /* 0x04 */
879	STRENTRY("Task "), /* 0x05 */
880	STRENTRY("Int16 "), /* 0x06 */
881	STRENTRY("Trap16 "), /* 0x07 */
882	STRENTRY("Reserved8 "), /* 0x08 */
883	STRENTRY("TSS32Avail "), /* 0x09 */
884	STRENTRY("ReservedA "), /* 0x0a */
885	STRENTRY("TSS32Busy "), /* 0x0b */
886	STRENTRY("Call32 "), /* 0x0c */
887	STRENTRY("ReservedD "), /* 0x0d */
888	STRENTRY("Int32 "), /* 0x0e */
889	STRENTRY("Trap32 "), /* 0x0f */
890	#endif
891	/* non system */
892	STRENTRY("DataRO "), /* 0x10 */
893	STRENTRY("DataRO Accessed "), /* 0x11 */
894	STRENTRY("DataRW "), /* 0x12 */
895	STRENTRY("DataRW Accessed "), /* 0x13 */
896	STRENTRY("DataDownRO "), /* 0x14 */
897	STRENTRY("DataDownRO Accessed "), /* 0x15 */
898	STRENTRY("DataDownRW "), /* 0x16 */
899	STRENTRY("DataDownRW Accessed "), /* 0x17 */
900	STRENTRY("CodeEO "), /* 0x18 */
901	STRENTRY("CodeEO Accessed "), /* 0x19 */
902	STRENTRY("CodeER "), /* 0x1a */
903	STRENTRY("CodeER Accessed "), /* 0x1b */
904	STRENTRY("CodeConfEO "), /* 0x1c */
905	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
906	STRENTRY("CodeConfER "), /* 0x1e */
907	STRENTRY("CodeConfER Accessed ") /* 0x1f */
908	#undef SYSENTRY
909	};
910	#define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
911	char szMsg[128];
912	char *psz = &szMsg[0];
913	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
914	memcpy(psz, aTypes[i].psz, aTypes[i].cch);
915	psz += aTypes[i].cch;
916
917	if (pDesc->Gen.u1Present)
918	ADD_STR(psz, "Present ");
919	else
920	ADD_STR(psz, "Not-Present ");
921	#if HC_ARCH_BITS == 64
922	if (pDesc->Gen.u1Long)
923	ADD_STR(psz, "64-bit ");
924	else
925	ADD_STR(psz, "Comp ");
926	#else
927	if (pDesc->Gen.u1Granularity)
928	ADD_STR(psz, "Page ");
929	if (pDesc->Gen.u1DefBig)
930	ADD_STR(psz, "32-bit ");
931	else
932	ADD_STR(psz, "16-bit ");
933	#endif
934	#undef ADD_STR
935	*psz = '\0';
936
937	/*
938	* Limit and Base and format the output.
939	*/
940	uint32_t u32Limit = X86DESC_LIMIT(*pDesc);
941	if (pDesc->Gen.u1Granularity)
942	u32Limit = u32Limit << PAGE_SHIFT \| PAGE_OFFSET_MASK;
943
944	#if HC_ARCH_BITS == 64
945	uint64_t u32Base = X86DESC64_BASE(*pDesc);
946
947	Log(("%s %04x - %VX64 %VX64 - base=%VX64 limit=%08x dpl=%d %s\n", pszMsg,
948	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
949	#else
950	uint32_t u32Base = X86DESC_BASE(*pDesc);
951
952	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
953	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
954	#endif
955	}
956
957	/**
958	* Formats a full register dump.
959	*
960	* @param pVM The VM to operate on.
961	* @param pCtx The context to format.
962	*/
963	HWACCMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx)
964	{
965	/*
966	* Format the flags.
967	*/
968	static struct
969	{
970	const char pszSet; const char pszClear; uint32_t fFlag;
971	} aFlags[] =
972	{
973	{ "vip",NULL, X86_EFL_VIP },
974	{ "vif",NULL, X86_EFL_VIF },
975	{ "ac", NULL, X86_EFL_AC },
976	{ "vm", NULL, X86_EFL_VM },
977	{ "rf", NULL, X86_EFL_RF },
978	{ "nt", NULL, X86_EFL_NT },
979	{ "ov", "nv", X86_EFL_OF },
980	{ "dn", "up", X86_EFL_DF },
981	{ "ei", "di", X86_EFL_IF },
982	{ "tf", NULL, X86_EFL_TF },
983	{ "nt", "pl", X86_EFL_SF },
984	{ "nz", "zr", X86_EFL_ZF },
985	{ "ac", "na", X86_EFL_AF },
986	{ "po", "pe", X86_EFL_PF },
987	{ "cy", "nc", X86_EFL_CF },
988	};
989	char szEFlags[80];
990	char *psz = szEFlags;
991	uint32_t efl = pCtx->eflags.u32;
992	for (unsigned i = 0; i < RT_ELEMENTS(aFlags); i++)
993	{
994	const char *pszAdd = aFlags[i].fFlag & efl ? aFlags[i].pszSet : aFlags[i].pszClear;
995	if (pszAdd)
996	{
997	strcpy(psz, pszAdd);
998	psz += strlen(pszAdd);
999	*psz++ = ' ';
1000	}
1001	}
1002	psz[-1] = '\0';
1003
1004
1005	/*
1006	* Format the registers.
1007	*/
1008	if (CPUMIsGuestIn64BitCode(pVM, CPUMCTX2CORE(pCtx)))
1009	{
1010	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1011	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1012	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1013	"r14=%016RX64 r15=%016RX64\n"
1014	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1015	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1016	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1017	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1018	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1019	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1020	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1021	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1022	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1023	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1024	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1025	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1026	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1027	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1028	,
1029	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1030	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1031	pCtx->r14, pCtx->r15,
1032	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1033	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1034	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1035	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1036	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1037	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1038	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1039	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1040	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3,
1041	pCtx->dr4, pCtx->dr5, pCtx->dr6, pCtx->dr7,
1042	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1043	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1044	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1045	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1046	}
1047	else
1048	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1049	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1050	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1051	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1052	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1053	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1054	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1055	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1056	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1057	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1058	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1059	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1060	,
1061	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1062	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1063	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr0, pCtx->dr1,
1064	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr2, pCtx->dr3,
1065	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr4, pCtx->dr5,
1066	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr6, pCtx->dr7,
1067	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0, pCtx->cr2,
1068	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3, pCtx->cr4,
1069	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1070	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1071	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1072	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1073
1074	Log(("FPU:\n"
1075	"FCW=%04x FSW=%04x FTW=%02x\n"
1076	"res1=%02x FOP=%04x FPUIP=%08x CS=%04x Rsvrd1=%04x\n"
1077	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1078	,
1079	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
1080	pCtx->fpu.huh1, pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsvrd1,
1081	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
1082	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
1083
1084
1085	Log(("MSR:\n"
1086	"EFER =%016RX64\n"
1087	"PAT =%016RX64\n"
1088	"STAR =%016RX64\n"
1089	"CSTAR =%016RX64\n"
1090	"LSTAR =%016RX64\n"
1091	"SFMASK =%016RX64\n"
1092	"KERNELGSBASE =%016RX64\n",
1093	pCtx->msrEFER,
1094	pCtx->msrPAT,
1095	pCtx->msrSTAR,
1096	pCtx->msrCSTAR,
1097	pCtx->msrLSTAR,
1098	pCtx->msrSFMASK,
1099	pCtx->msrKERNELGSBASE));
1100
1101	}
1102	#endif
1103
1104	/* Dummy callback handlers. */
1105	HWACCMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PHWACCM_CPUINFO pCpu)
1106	{
1107	return VINF_SUCCESS;
1108	}
1109
1110	HWACCMR0DECL(int) HWACCMR0DummyLeave(PVM pVM)
1111	{
1112	return VINF_SUCCESS;
1113	}
1114
1115	HWACCMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1116	{
1117	return VINF_SUCCESS;
1118	}
1119
1120	HWACCMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1121	{
1122	return VINF_SUCCESS;
1123	}
1124
1125	HWACCMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM)
1126	{
1127	return VINF_SUCCESS;
1128	}
1129
1130	HWACCMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM)
1131	{
1132	return VINF_SUCCESS;
1133	}
1134
1135	HWACCMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM)
1136	{
1137	return VINF_SUCCESS;
1138	}
1139
1140	HWACCMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, CPUMCTX *pCtx)
1141	{
1142	return VINF_SUCCESS;
1143	}
1144
1145	HWACCMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM)
1146	{
1147	return VINF_SUCCESS;
1148	}
1149
1150	HWACCMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, CPUMCTX *pCtx)
1151	{
1152	return VINF_SUCCESS;
1153	}

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp@ 11938

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