HWACCMR0.cpp@ 14660

Last change on this file since 14660 was 14658, checked in by vboxsync, 16 years ago
HWACCMR0: Added PGMDynMap*AutoSet calls upon entry and exit (darwin only).
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1	/* $Id: HWACCMR0.cpp 14658 2008-11-26 18:09:32Z vboxsync $ */
2	/** @file
3	* HWACCM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_vmx.h>
32	#include <VBox/hwacc_svm.h>
33	#include <VBox/pgm.h>
34	#include <VBox/pdm.h>
35	#include <VBox/err.h>
36	#include <VBox/log.h>
37	#include <VBox/selm.h>
38	#include <VBox/iom.h>
39	#include <iprt/param.h>
40	#include <iprt/assert.h>
41	#include <iprt/asm.h>
42	#include <iprt/string.h>
43	#include <iprt/memobj.h>
44	#include <iprt/cpuset.h>
45	#include <iprt/power.h>
46	#include "HWVMXR0.h"
47	#include "HWSVMR0.h"
48
49	/*******************************************************************************
50	* Internal Functions *
51	*******************************************************************************/
52	static DECLCALLBACK(void) HWACCMR0EnableCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) HWACCMR0DisableCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
55	static int hwaccmR0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu);
56	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
57
58	/*******************************************************************************
59	* Global Variables *
60	*******************************************************************************/
61
62	static struct
63	{
64	HWACCM_CPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
65
66	/** Ring 0 handlers for VT-x and AMD-V. */
67	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu));
68	DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
69	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
70	DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
71	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
72	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
73	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
74	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
75	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
76	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVM pVM));
77
78	/** Maximum ASID allowed. */
79	uint32_t uMaxASID;
80
81	struct
82	{
83	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
84	bool fSupported;
85
86	/** Host CR4 value (set by ring-0 VMX init) */
87	uint64_t hostCR4;
88
89	/** VMX MSR values */
90	struct
91	{
92	uint64_t feature_ctrl;
93	uint64_t vmx_basic_info;
94	VMX_CAPABILITY vmx_pin_ctls;
95	VMX_CAPABILITY vmx_proc_ctls;
96	VMX_CAPABILITY vmx_proc_ctls2;
97	VMX_CAPABILITY vmx_exit;
98	VMX_CAPABILITY vmx_entry;
99	uint64_t vmx_misc;
100	uint64_t vmx_cr0_fixed0;
101	uint64_t vmx_cr0_fixed1;
102	uint64_t vmx_cr4_fixed0;
103	uint64_t vmx_cr4_fixed1;
104	uint64_t vmx_vmcs_enum;
105	uint64_t vmx_eptcaps;
106	} msr;
107	/* Last instruction error */
108	uint32_t ulLastInstrError;
109	} vmx;
110	struct
111	{
112	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
113	bool fSupported;
114
115	/** SVM revision. */
116	uint32_t u32Rev;
117
118	/** SVM feature bits from cpuid 0x8000000a */
119	uint32_t u32Features;
120	} svm;
121	/** Saved error from detection */
122	int32_t lLastError;
123
124	struct
125	{
126	uint32_t u32AMDFeatureECX;
127	uint32_t u32AMDFeatureEDX;
128	} cpuid;
129
130	HWACCMSTATE enmHwAccmState;
131
132	volatile bool fSuspended;
133	} HWACCMR0Globals;
134
135
136
137	/**
138	* Does global Ring-0 HWACCM initialization.
139	*
140	* @returns VBox status code.
141	*/
142	VMMR0DECL(int) HWACCMR0Init(void)
143	{
144	int rc;
145
146	memset(&HWACCMR0Globals, 0, sizeof(HWACCMR0Globals));
147	HWACCMR0Globals.enmHwAccmState = HWACCMSTATE_UNINITIALIZED;
148	for (unsigned i = 0; i < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); i++)
149	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
150
151	/* Fill in all callbacks with placeholders. */
152	HWACCMR0Globals.pfnEnterSession = HWACCMR0DummyEnter;
153	HWACCMR0Globals.pfnLeaveSession = HWACCMR0DummyLeave;
154	HWACCMR0Globals.pfnSaveHostState = HWACCMR0DummySaveHostState;
155	HWACCMR0Globals.pfnLoadGuestState = HWACCMR0DummyLoadGuestState;
156	HWACCMR0Globals.pfnRunGuestCode = HWACCMR0DummyRunGuestCode;
157	HWACCMR0Globals.pfnEnableCpu = HWACCMR0DummyEnableCpu;
158	HWACCMR0Globals.pfnDisableCpu = HWACCMR0DummyDisableCpu;
159	HWACCMR0Globals.pfnInitVM = HWACCMR0DummyInitVM;
160	HWACCMR0Globals.pfnTermVM = HWACCMR0DummyTermVM;
161	HWACCMR0Globals.pfnSetupVM = HWACCMR0DummySetupVM;
162
163	/*
164	* Check for VT-x and AMD-V capabilities
165	*/
166	#ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
167	if ( ASMHasCpuId()
168	&& SUPR0GetPagingMode() < SUPPAGINGMODE_AMD64) /* VMON -> #UD in compatability mode; temporary hack. */
169	#else
170	if (ASMHasCpuId())
171	#endif
172	{
173	uint32_t u32FeaturesECX;
174	uint32_t u32Dummy;
175	uint32_t u32FeaturesEDX;
176	uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
177
178	ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
179	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
180	/* Query AMD features. */
181	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy, &HWACCMR0Globals.cpuid.u32AMDFeatureECX, &HWACCMR0Globals.cpuid.u32AMDFeatureEDX);
182
183	if ( u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
184	&& u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
185	&& u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX
186	)
187	{
188	/*
189	* Read all VMX MSRs if VMX is available. (same goes for RDMSR/WRMSR)
190	* We also assume all VMX-enabled CPUs support fxsave/fxrstor.
191	*/
192	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
193	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
194	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
195	)
196	{
197	int aRc[RTCPUSET_MAX_CPUS];
198	RTCPUID idCpu = 0;
199
200	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
201
202	/* We need to check if VT-x has been properly initialized on all CPUs. Some BIOSes do a lousy job. */
203	memset(aRc, 0, sizeof(aRc));
204	HWACCMR0Globals.lLastError = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
205
206	/* Check the return code of all invocations. */
207	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
208	HWACCMR0Globals.lLastError = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
209
210	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
211	{
212	/* Reread in case we've changed it. */
213	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
214
215	if ( (HWACCMR0Globals.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
216	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
217	{
218	RTR0MEMOBJ pScatchMemObj;
219	void *pvScatchPage;
220	RTHCPHYS pScatchPagePhys;
221
222	HWACCMR0Globals.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
223	HWACCMR0Globals.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
224	HWACCMR0Globals.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
225	HWACCMR0Globals.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
226	HWACCMR0Globals.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
227	HWACCMR0Globals.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
228	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
229	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
230	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
231	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
232	HWACCMR0Globals.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
233	/* VPID 16 bits ASID. */
234	HWACCMR0Globals.uMaxASID = 0x10000; /* exclusive */
235
236	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
237	{
238	HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
239	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT\|VMX_VMCS_CTRL_PROC_EXEC2_VPID))
240	HWACCMR0Globals.vmx.msr.vmx_eptcaps = ASMRdMsr(MSR_IA32_VMX_EPT_CAPS);
241	}
242
243	HWACCMR0Globals.vmx.hostCR4 = ASMGetCR4();
244
245	rc = RTR0MemObjAllocCont(&pScatchMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
246	if (RT_FAILURE(rc))
247	return rc;
248
249	pvScatchPage = RTR0MemObjAddress(pScatchMemObj);
250	pScatchPagePhys = RTR0MemObjGetPagePhysAddr(pScatchMemObj, 0);
251	memset(pvScatchPage, 0, PAGE_SIZE);
252
253	/* Set revision dword at the beginning of the structure. */
254	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(HWACCMR0Globals.vmx.msr.vmx_basic_info);
255
256	/* Make sure we don't get rescheduled to another cpu during this probe. */
257	RTCCUINTREG fFlags = ASMIntDisableFlags();
258
259	/*
260	* Check CR4.VMXE
261	*/
262	if (!(HWACCMR0Globals.vmx.hostCR4 & X86_CR4_VMXE))
263	{
264	/* In theory this bit could be cleared behind our back. Which would cause #UD faults when we
265	* try to execute the VMX instructions...
266	*/
267	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4 \| X86_CR4_VMXE);
268	}
269
270	/* Enter VMX Root Mode */
271	rc = VMXEnable(pScatchPagePhys);
272	if (RT_FAILURE(rc))
273	{
274	/* KVM leaves the CPU in VMX root mode. Not only is this not allowed, it will crash the host when we enter raw mode, because
275	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify this bit)
276	* (b) turning off paging causes a #GP (unavoidable when switching from long to 32 bits mode or 32 bits to PAE)
277	*
278	* They should fix their code, but until they do we simply refuse to run.
279	*/
280	HWACCMR0Globals.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
281	}
282	else
283	{
284	HWACCMR0Globals.vmx.fSupported = true;
285	VMXDisable();
286	}
287
288	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it wasn't so before (some software could incorrectly think it's in VMX mode) */
289	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4);
290	ASMSetFlags(fFlags);
291
292	RTR0MemObjFree(pScatchMemObj, false);
293	if (RT_FAILURE(HWACCMR0Globals.lLastError))
294	return HWACCMR0Globals.lLastError;
295	}
296	else
297	{
298	AssertFailed(); /* can't hit this case anymore */
299	HWACCMR0Globals.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
300	}
301	}
302	#ifdef LOG_ENABLED
303	else
304	SUPR0Printf("HWACCMR0InitCPU failed with rc=%d\n", HWACCMR0Globals.lLastError);
305	#endif
306	}
307	else
308	HWACCMR0Globals.lLastError = VERR_VMX_NO_VMX;
309	}
310	else
311	if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
312	&& u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
313	&& u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX
314	)
315	{
316	/*
317	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
318	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
319	*/
320	if ( (HWACCMR0Globals.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
321	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
322	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
323	)
324	{
325	int aRc[RTCPUSET_MAX_CPUS];
326	RTCPUID idCpu = 0;
327
328	/* We need to check if AMD-V has been properly initialized on all CPUs. Some BIOSes might do a poor job. */
329	memset(aRc, 0, sizeof(aRc));
330	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
331	AssertRC(rc);
332
333	/* Check the return code of all invocations. */
334	if (RT_SUCCESS(rc))
335	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
336
337	AssertMsgRC(rc, ("HWACCMR0InitCPU failed for cpu %d with rc=%d\n", idCpu, rc));
338
339	if (RT_SUCCESS(rc))
340	{
341	/* Query AMD features. */
342	ASMCpuId(0x8000000A, &HWACCMR0Globals.svm.u32Rev, &HWACCMR0Globals.uMaxASID, &u32Dummy, &HWACCMR0Globals.svm.u32Features);
343
344	HWACCMR0Globals.svm.fSupported = true;
345	}
346	else
347	HWACCMR0Globals.lLastError = rc;
348	}
349	else
350	HWACCMR0Globals.lLastError = VERR_SVM_NO_SVM;
351	}
352	else
353	HWACCMR0Globals.lLastError = VERR_HWACCM_UNKNOWN_CPU;
354	}
355	else
356	HWACCMR0Globals.lLastError = VERR_HWACCM_NO_CPUID;
357
358	if (HWACCMR0Globals.vmx.fSupported)
359	{
360	HWACCMR0Globals.pfnEnterSession = VMXR0Enter;
361	HWACCMR0Globals.pfnLeaveSession = VMXR0Leave;
362	HWACCMR0Globals.pfnSaveHostState = VMXR0SaveHostState;
363	HWACCMR0Globals.pfnLoadGuestState = VMXR0LoadGuestState;
364	HWACCMR0Globals.pfnRunGuestCode = VMXR0RunGuestCode;
365	HWACCMR0Globals.pfnEnableCpu = VMXR0EnableCpu;
366	HWACCMR0Globals.pfnDisableCpu = VMXR0DisableCpu;
367	HWACCMR0Globals.pfnInitVM = VMXR0InitVM;
368	HWACCMR0Globals.pfnTermVM = VMXR0TermVM;
369	HWACCMR0Globals.pfnSetupVM = VMXR0SetupVM;
370	}
371	else
372	if (HWACCMR0Globals.svm.fSupported)
373	{
374	HWACCMR0Globals.pfnEnterSession = SVMR0Enter;
375	HWACCMR0Globals.pfnLeaveSession = SVMR0Leave;
376	HWACCMR0Globals.pfnSaveHostState = SVMR0SaveHostState;
377	HWACCMR0Globals.pfnLoadGuestState = SVMR0LoadGuestState;
378	HWACCMR0Globals.pfnRunGuestCode = SVMR0RunGuestCode;
379	HWACCMR0Globals.pfnEnableCpu = SVMR0EnableCpu;
380	HWACCMR0Globals.pfnDisableCpu = SVMR0DisableCpu;
381	HWACCMR0Globals.pfnInitVM = SVMR0InitVM;
382	HWACCMR0Globals.pfnTermVM = SVMR0TermVM;
383	HWACCMR0Globals.pfnSetupVM = SVMR0SetupVM;
384	}
385
386	rc = RTPowerNotificationRegister(hwaccmR0PowerCallback, 0);
387	Assert(RT_SUCCESS(rc));
388
389	return VINF_SUCCESS;
390	}
391
392
393	/**
394	* Checks the error code array filled in for each cpu in the system.
395	*
396	* @returns VBox status code.
397	* @param paRc Error code array
398	* @param cErrorCodes Array size
399	* @param pidCpu Value of the first cpu that set an error (out)
400	*/
401	static int hwaccmR0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu)
402	{
403	int rc = VINF_SUCCESS;
404
405	Assert(cErrorCodes == RTCPUSET_MAX_CPUS);
406
407	for (unsigned i=0;i<cErrorCodes;i++)
408	{
409	if (RTMpIsCpuOnline(i))
410	{
411	if (RT_FAILURE(paRc[i]))
412	{
413	rc = paRc[i];
414	*pidCpu = i;
415	break;
416	}
417	}
418	}
419	return rc;
420	}
421
422	/**
423	* Does global Ring-0 HWACCM termination.
424	*
425	* @returns VBox status code.
426	*/
427	VMMR0DECL(int) HWACCMR0Term(void)
428	{
429	int aRc[RTCPUSET_MAX_CPUS];
430	int rc;
431
432	rc = RTPowerNotificationDeregister(hwaccmR0PowerCallback, 0);
433	Assert(RT_SUCCESS(rc));
434
435	memset(aRc, 0, sizeof(aRc));
436	rc = RTMpOnAll(HWACCMR0DisableCPU, aRc, NULL);
437	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
438
439	/* Free the per-cpu pages used for VT-x and AMD-V */
440	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
441	{
442	AssertMsgRC(aRc[i], ("HWACCMR0DisableCPU failed for cpu %d with rc=%d\n", i, aRc[i]));
443	if (HWACCMR0Globals.aCpuInfo[i].pMemObj != NIL_RTR0MEMOBJ)
444	{
445	RTR0MemObjFree(HWACCMR0Globals.aCpuInfo[i].pMemObj, false);
446	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
447	}
448	}
449	return rc;
450	}
451
452
453	/**
454	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
455	* is to be called on the target cpus.
456	*
457	* @param idCpu The identifier for the CPU the function is called on.
458	* @param pvUser1 The 1st user argument.
459	* @param pvUser2 The 2nd user argument.
460	*/
461	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
462	{
463	unsigned u32VendorEBX = (uintptr_t)pvUser1;
464	int paRc = (int )pvUser2;
465	uint64_t val;
466
467	#ifdef LOG_ENABLED
468	SUPR0Printf("HWACCMR0InitCPU cpu %d\n", idCpu);
469	#endif
470	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
471
472	if (u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX)
473	{
474	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
475
476	/*
477	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
478	* Once the lock bit is set, this MSR can no longer be modified.
479	*/
480	if (!(val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK)))
481	{
482	/* MSR is not yet locked; we can change it ourselves here */
483	ASMWrMsr(MSR_IA32_FEATURE_CONTROL, HWACCMR0Globals.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
484	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
485	}
486	if ( (val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
487	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
488	paRc[idCpu] = VINF_SUCCESS;
489	else
490	paRc[idCpu] = VERR_VMX_MSR_LOCKED_OR_DISABLED;
491	}
492	else
493	if (u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX)
494	{
495	/* Check if SVM is disabled */
496	val = ASMRdMsr(MSR_K8_VM_CR);
497	if (!(val & MSR_K8_VM_CR_SVM_DISABLE))
498	{
499	/* Turn on SVM in the EFER MSR. */
500	val = ASMRdMsr(MSR_K6_EFER);
501	if (!(val & MSR_K6_EFER_SVME))
502	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
503
504	/* Paranoia. */
505	val = ASMRdMsr(MSR_K6_EFER);
506	if (val & MSR_K6_EFER_SVME)
507	paRc[idCpu] = VINF_SUCCESS;
508	else
509	paRc[idCpu] = VERR_SVM_ILLEGAL_EFER_MSR;
510	}
511	else
512	paRc[idCpu] = HWACCMR0Globals.lLastError = VERR_SVM_DISABLED;
513	}
514	else
515	AssertFailed(); /* can't happen */
516	return;
517	}
518
519
520	/**
521	* Sets up HWACCM on all cpus.
522	*
523	* @returns VBox status code.
524	* @param pVM The VM to operate on.
525	* @param enmNewHwAccmState New hwaccm state
526	*
527	*/
528	VMMR0DECL(int) HWACCMR0EnableAllCpus(PVM pVM, HWACCMSTATE enmNewHwAccmState)
529	{
530	Assert(sizeof(HWACCMR0Globals.enmHwAccmState) == sizeof(uint32_t));
531
532	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
533	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
534	return VERR_HWACCM_SUSPEND_PENDING;
535
536	if (ASMAtomicCmpXchgU32((volatile uint32_t *)&HWACCMR0Globals.enmHwAccmState, enmNewHwAccmState, HWACCMSTATE_UNINITIALIZED))
537	{
538	int aRc[RTCPUSET_MAX_CPUS];
539	RTCPUID idCpu = 0;
540
541	/* Don't setup hwaccm as that might not work (vt-x & 64 bits raw mode) */
542	if (enmNewHwAccmState == HWACCMSTATE_DISABLED)
543	return VINF_SUCCESS;
544
545	memset(aRc, 0, sizeof(aRc));
546
547	/* Allocate one page per cpu for the global vt-x and amd-v pages */
548	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
549	{
550	Assert(!HWACCMR0Globals.aCpuInfo[i].pMemObj);
551
552	/** @todo this is rather dangerous if cpus can be taken offline; we don't care for now */
553	if (RTMpIsCpuOnline(i))
554	{
555	int rc = RTR0MemObjAllocCont(&HWACCMR0Globals.aCpuInfo[i].pMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
556	AssertRC(rc);
557	if (RT_FAILURE(rc))
558	return rc;
559
560	void *pvR0 = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[i].pMemObj);
561	Assert(pvR0);
562	ASMMemZeroPage(pvR0);
563
564	#ifdef LOG_ENABLED
565	SUPR0Printf("address %x phys %x\n", pvR0, (uint32_t)RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[i].pMemObj, 0));
566	#endif
567	}
568	}
569	/* First time, so initialize each cpu/core */
570	int rc = RTMpOnAll(HWACCMR0EnableCPU, (void *)pVM, aRc);
571
572	/* Check the return code of all invocations. */
573	if (RT_SUCCESS(rc))
574	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
575
576	AssertMsgRC(rc, ("HWACCMR0EnableAllCpus failed for cpu %d with rc=%d\n", idCpu, rc));
577	return rc;
578	}
579
580	if (HWACCMR0Globals.enmHwAccmState == enmNewHwAccmState)
581	return VINF_SUCCESS;
582
583	/* Request to change the mode is not allowed */
584	return VERR_ACCESS_DENIED;
585	}
586
587	/**
588	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
589	* is to be called on the target cpus.
590	*
591	* @param idCpu The identifier for the CPU the function is called on.
592	* @param pvUser1 The 1st user argument.
593	* @param pvUser2 The 2nd user argument.
594	*/
595	static DECLCALLBACK(void) HWACCMR0EnableCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
596	{
597	PVM pVM = (PVM)pvUser1; /* can be NULL! */
598	int paRc = (int )pvUser2;
599	void *pvPageCpu;
600	RTHCPHYS pPageCpuPhys;
601	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
602
603	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
604	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
605	Assert(!pCpu->fConfigured);
606	Assert(ASMAtomicReadBool(&pCpu->fInUse) == false);
607
608	pCpu->idCpu = idCpu;
609
610	/* Make sure we start with a clean TLB. */
611	pCpu->fFlushTLB = true;
612
613	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
614	pCpu->cTLBFlushes = 0;
615
616	/* Should never happen */
617	if (!pCpu->pMemObj)
618	{
619	AssertFailed();
620	paRc[idCpu] = VERR_INTERNAL_ERROR;
621	return;
622	}
623
624	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
625	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
626
627	paRc[idCpu] = HWACCMR0Globals.pfnEnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
628	AssertRC(paRc[idCpu]);
629	if (RT_SUCCESS(paRc[idCpu]))
630	pCpu->fConfigured = true;
631
632	return;
633	}
634
635	/**
636	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
637	* is to be called on the target cpus.
638	*
639	* @param idCpu The identifier for the CPU the function is called on.
640	* @param pvUser1 The 1st user argument.
641	* @param pvUser2 The 2nd user argument.
642	*/
643	static DECLCALLBACK(void) HWACCMR0DisableCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
644	{
645	void *pvPageCpu;
646	RTHCPHYS pPageCpuPhys;
647	int paRc = (int )pvUser1;
648	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
649
650	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
651	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
652	Assert(ASMAtomicReadBool(&pCpu->fInUse) == false);
653
654	if (!pCpu->pMemObj)
655	return;
656
657	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
658	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
659
660	if (pCpu->fConfigured)
661	{
662	paRc[idCpu] = HWACCMR0Globals.pfnDisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
663	AssertRC(paRc[idCpu]);
664	pCpu->fConfigured = false;
665	}
666	else
667	paRc[idCpu] = VINF_SUCCESS; /* nothing to do */
668
669	pCpu->uCurrentASID = 0;
670	return;
671	}
672
673	/**
674	* Called whenever a system power state change occurs.
675	*
676	* @param enmEvent Power event
677	* @param pvUser User argument
678	*/
679	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
680	{
681	NOREF(pvUser);
682
683	#ifdef LOG_ENABLED
684	if (enmEvent == RTPOWEREVENT_SUSPEND)
685	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
686	else
687	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_RESUME\n");
688	#endif
689
690	if (enmEvent == RTPOWEREVENT_SUSPEND)
691	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, true);
692
693	if (HWACCMR0Globals.enmHwAccmState == HWACCMSTATE_ENABLED)
694	{
695	int aRc[RTCPUSET_MAX_CPUS];
696	int rc;
697	RTCPUID idCpu;
698
699	memset(aRc, 0, sizeof(aRc));
700	if (enmEvent == RTPOWEREVENT_SUSPEND)
701	{
702	/* Turn off VT-x or AMD-V on all CPUs. */
703	rc = RTMpOnAll(HWACCMR0DisableCPU, aRc, NULL);
704	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
705	}
706	else
707	{
708	/* Reinit the CPUs from scratch as the suspend state has messed with the MSRs. */
709	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)((HWACCMR0Globals.vmx.fSupported) ? X86_CPUID_VENDOR_INTEL_EBX : X86_CPUID_VENDOR_AMD_EBX), aRc);
710	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
711
712	if (RT_SUCCESS(rc))
713	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
714	#ifdef LOG_ENABLED
715	if (RT_FAILURE(rc))
716	SUPR0Printf("hwaccmR0PowerCallback HWACCMR0InitCPU failed with %d\n", rc);
717	#endif
718
719	/* Turn VT-x or AMD-V back on on all CPUs. */
720	rc = RTMpOnAll(HWACCMR0EnableCPU, NULL, aRc);
721	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
722	}
723	}
724	if (enmEvent == RTPOWEREVENT_RESUME)
725	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, false);
726	}
727
728
729	/**
730	* Does Ring-0 per VM HWACCM initialization.
731	*
732	* This is mainly to check that the Host CPU mode is compatible
733	* with VMX.
734	*
735	* @returns VBox status code.
736	* @param pVM The VM to operate on.
737	*/
738	VMMR0DECL(int) HWACCMR0InitVM(PVM pVM)
739	{
740	int rc;
741	RTCPUID idCpu = RTMpCpuId();
742	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
743
744	AssertReturn(pVM, VERR_INVALID_PARAMETER);
745
746	#ifdef LOG_ENABLED
747	SUPR0Printf("HWACCMR0InitVM: %p\n", pVM);
748	#endif
749
750	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
751	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
752	return VERR_HWACCM_SUSPEND_PENDING;
753
754	pVM->hwaccm.s.vmx.fSupported = HWACCMR0Globals.vmx.fSupported;
755	pVM->hwaccm.s.svm.fSupported = HWACCMR0Globals.svm.fSupported;
756
757	pVM->hwaccm.s.vmx.msr.feature_ctrl = HWACCMR0Globals.vmx.msr.feature_ctrl;
758	pVM->hwaccm.s.vmx.hostCR4 = HWACCMR0Globals.vmx.hostCR4;
759	pVM->hwaccm.s.vmx.msr.vmx_basic_info = HWACCMR0Globals.vmx.msr.vmx_basic_info;
760	pVM->hwaccm.s.vmx.msr.vmx_pin_ctls = HWACCMR0Globals.vmx.msr.vmx_pin_ctls;
761	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls = HWACCMR0Globals.vmx.msr.vmx_proc_ctls;
762	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2 = HWACCMR0Globals.vmx.msr.vmx_proc_ctls2;
763	pVM->hwaccm.s.vmx.msr.vmx_exit = HWACCMR0Globals.vmx.msr.vmx_exit;
764	pVM->hwaccm.s.vmx.msr.vmx_entry = HWACCMR0Globals.vmx.msr.vmx_entry;
765	pVM->hwaccm.s.vmx.msr.vmx_misc = HWACCMR0Globals.vmx.msr.vmx_misc;
766	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0;
767	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1;
768	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0;
769	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1;
770	pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum = HWACCMR0Globals.vmx.msr.vmx_vmcs_enum;
771	pVM->hwaccm.s.vmx.msr.vmx_eptcaps = HWACCMR0Globals.vmx.msr.vmx_eptcaps;
772	pVM->hwaccm.s.svm.u32Rev = HWACCMR0Globals.svm.u32Rev;
773	pVM->hwaccm.s.svm.u32Features = HWACCMR0Globals.svm.u32Features;
774	pVM->hwaccm.s.cpuid.u32AMDFeatureECX = HWACCMR0Globals.cpuid.u32AMDFeatureECX;
775	pVM->hwaccm.s.cpuid.u32AMDFeatureEDX = HWACCMR0Globals.cpuid.u32AMDFeatureEDX;
776	pVM->hwaccm.s.lLastError = HWACCMR0Globals.lLastError;
777
778	pVM->hwaccm.s.uMaxASID = HWACCMR0Globals.uMaxASID;
779
780	for (unsigned i=0;i<pVM->cCPUs;i++)
781	{
782	PVMCPU pVCpu = &pVM->aCpus[i];
783
784	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
785
786	/* Invalidate the last cpu we were running on. */
787	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
788
789	/* we'll aways increment this the first time (host uses ASID 0) */
790	pVCpu->hwaccm.s.uCurrentASID = 0;
791	}
792
793	ASMAtomicWriteBool(&pCpu->fInUse, true);
794
795	/* Init a VT-x or AMD-V VM. */
796	rc = HWACCMR0Globals.pfnInitVM(pVM);
797
798	ASMAtomicWriteBool(&pCpu->fInUse, false);
799
800	return rc;
801	}
802
803
804	/**
805	* Does Ring-0 per VM HWACCM termination.
806	*
807	* @returns VBox status code.
808	* @param pVM The VM to operate on.
809	*/
810	VMMR0DECL(int) HWACCMR0TermVM(PVM pVM)
811	{
812	int rc;
813	RTCPUID idCpu = RTMpCpuId();
814	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
815
816	AssertReturn(pVM, VERR_INVALID_PARAMETER);
817
818	#ifdef LOG_ENABLED
819	SUPR0Printf("HWACCMR0TermVM: %p\n", pVM);
820	#endif
821
822	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
823	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
824
825	ASMAtomicWriteBool(&pCpu->fInUse, true);
826
827	/* Terminate a VT-x or AMD-V VM. */
828	rc = HWACCMR0Globals.pfnTermVM(pVM);
829
830	ASMAtomicWriteBool(&pCpu->fInUse, false);
831	return rc;
832	}
833
834
835	/**
836	* Sets up a VT-x or AMD-V session
837	*
838	* @returns VBox status code.
839	* @param pVM The VM to operate on.
840	*/
841	VMMR0DECL(int) HWACCMR0SetupVM(PVM pVM)
842	{
843	int rc;
844	RTCPUID idCpu = RTMpCpuId();
845	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
846
847	AssertReturn(pVM, VERR_INVALID_PARAMETER);
848
849	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
850	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
851
852	#ifdef LOG_ENABLED
853	SUPR0Printf("HWACCMR0SetupVM: %p\n", pVM);
854	#endif
855
856	ASMAtomicWriteBool(&pCpu->fInUse, true);
857
858	for (unsigned i=0;i<pVM->cCPUs;i++)
859	{
860	/* On first entry we'll sync everything. */
861	pVM->aCpus[i].hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
862	}
863
864	/* Setup VT-x or AMD-V. */
865	rc = HWACCMR0Globals.pfnSetupVM(pVM);
866
867	ASMAtomicWriteBool(&pCpu->fInUse, false);
868
869	return rc;
870	}
871
872
873	/**
874	* Enters the VT-x or AMD-V session
875	*
876	* @returns VBox status code.
877	* @param pVM The VM to operate on.
878	* @param pVCpu VMCPUD id.
879	*/
880	VMMR0DECL(int) HWACCMR0Enter(PVM pVM, PVMCPU pVCpu)
881	{
882	PCPUMCTX pCtx;
883	int rc;
884	RTCPUID idCpu = RTMpCpuId();
885	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
886
887	/* Make sure we can't enter a session after we've disabled hwaccm in preparation of a suspend. */
888	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
889	ASMAtomicWriteBool(&pCpu->fInUse, true);
890
891	pCtx = CPUMQueryGuestCtxPtrEx(pVM, pVCpu);
892
893	/* Always load the guest's FPU/XMM state on-demand. */
894	CPUMDeactivateGuestFPUState(pVM);
895
896	/* Always load the guest's debug state on-demand. */
897	CPUMDeactivateGuestDebugState(pVM);
898
899	/* Always reload the host context and the guest's CR0 register. (!!!!) */
900	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0 \| HWACCM_CHANGED_HOST_CONTEXT;
901
902	/* Setup the register and mask according to the current execution mode. */
903	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
904	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFFFFFFFFFF);
905	else
906	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFF);
907
908	rc = HWACCMR0Globals.pfnEnterSession(pVM, pVCpu, pCpu);
909	AssertRC(rc);
910	/* We must save the host context here (VT-x) as we might be rescheduled on a different cpu after a long jump back to ring 3. */
911	rc \|= HWACCMR0Globals.pfnSaveHostState(pVM, pVCpu);
912	AssertRC(rc);
913	rc \|= HWACCMR0Globals.pfnLoadGuestState(pVM, pVCpu, pCtx);
914	AssertRC(rc);
915
916	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
917	if (RT_SUCCESS(rc))
918	{
919	AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == NIL_RTCPUID, ("%d", (int)pVCpu->hwaccm.s.idEnteredCpu));
920	pVCpu->hwaccm.s.idEnteredCpu = idCpu;
921
922	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
923	PGMDynMapMigrateAutoSet(pVCpu);
924	#endif
925	}
926	return rc;
927	}
928
929
930	/**
931	* Leaves the VT-x or AMD-V session
932	*
933	* @returns VBox status code.
934	* @param pVM The VM to operate on.
935	* @param pVCpu VMCPUD id.
936	*/
937	VMMR0DECL(int) HWACCMR0Leave(PVM pVM, PVMCPU pVCpu)
938	{
939	PCPUMCTX pCtx;
940	int rc;
941	RTCPUID idCpu = RTMpCpuId();
942	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
943
944	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
945
946	pCtx = CPUMQueryGuestCtxPtrEx(pVM, pVCpu);
947
948	/* Note: It's rather tricky with longjmps done by e.g. Log statements or the page fault handler.
949	* We must restore the host FPU here to make absolutely sure we don't leave the guest FPU state active
950	* or trash somebody else's FPU state.
951	*/
952	/* Save the guest FPU and XMM state if necessary. */
953	if (CPUMIsGuestFPUStateActive(pVCpu))
954	{
955	Log2(("CPUMR0SaveGuestFPU\n"));
956	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
957
958	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
959	}
960
961	rc = HWACCMR0Globals.pfnLeaveSession(pVM, pVCpu, pCtx);
962
963	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
964	AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == idCpu, ("owner is %d, I'm %d", (int)pVCpu->hwaccm.s.idEnteredCpu, (int)idCpu));
965	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
966
967	ASMAtomicWriteBool(&pCpu->fInUse, false);
968	return rc;
969	}
970
971	/**
972	* Runs guest code in a hardware accelerated VM.
973	*
974	* @returns VBox status code.
975	* @param pVM The VM to operate on.
976	* @param pVCpu VMCPUD id.
977	*/
978	VMMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
979	{
980	CPUMCTX *pCtx;
981	RTCPUID idCpu = RTMpCpuId(); NOREF(idCpu);
982	int rc;
983	#ifdef VBOX_STRICT
984	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
985	#endif
986
987	Assert(!VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL));
988	Assert(HWACCMR0Globals.aCpuInfo[idCpu].fConfigured);
989	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
990	Assert(ASMAtomicReadBool(&pCpu->fInUse) == true);
991
992	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
993	PGMDynMapStartAutoSet(pVCpu);
994	#endif
995
996	pCtx = CPUMQueryGuestCtxPtrEx(pVM, pVCpu);
997
998	rc = HWACCMR0Globals.pfnRunGuestCode(pVM, pVCpu, pCtx);
999
1000	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1001	PGMDynMapReleaseAutoSet(pVCpu);
1002	#endif
1003	return rc;
1004	}
1005
1006	/**
1007	* Returns suspend status of the host
1008	*
1009	* @returns Suspend pending or not
1010	*/
1011	VMMR0DECL(bool) HWACCMR0SuspendPending()
1012	{
1013	return ASMAtomicReadBool(&HWACCMR0Globals.fSuspended);
1014	}
1015
1016	/**
1017	* Returns the cpu structure for the current cpu.
1018	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1019	*
1020	* @returns cpu structure pointer
1021	* @param pVM The VM to operate on.
1022	*/
1023	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu()
1024	{
1025	RTCPUID idCpu = RTMpCpuId();
1026
1027	return &HWACCMR0Globals.aCpuInfo[idCpu];
1028	}
1029
1030	#ifdef VBOX_STRICT
1031	# include <iprt/string.h>
1032	/**
1033	* Dumps a descriptor.
1034	*
1035	* @param pDesc Descriptor to dump.
1036	* @param Sel Selector number.
1037	* @param pszMsg Message to prepend the log entry with.
1038	*/
1039	VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1040	{
1041	/*
1042	* Make variable description string.
1043	*/
1044	static struct
1045	{
1046	unsigned cch;
1047	const char *psz;
1048	} const aTypes[32] =
1049	{
1050	# define STRENTRY(str) { sizeof(str) - 1, str }
1051
1052	/* system */
1053	# if HC_ARCH_BITS == 64
1054	STRENTRY("Reserved0 "), /* 0x00 */
1055	STRENTRY("Reserved1 "), /* 0x01 */
1056	STRENTRY("LDT "), /* 0x02 */
1057	STRENTRY("Reserved3 "), /* 0x03 */
1058	STRENTRY("Reserved4 "), /* 0x04 */
1059	STRENTRY("Reserved5 "), /* 0x05 */
1060	STRENTRY("Reserved6 "), /* 0x06 */
1061	STRENTRY("Reserved7 "), /* 0x07 */
1062	STRENTRY("Reserved8 "), /* 0x08 */
1063	STRENTRY("TSS64Avail "), /* 0x09 */
1064	STRENTRY("ReservedA "), /* 0x0a */
1065	STRENTRY("TSS64Busy "), /* 0x0b */
1066	STRENTRY("Call64 "), /* 0x0c */
1067	STRENTRY("ReservedD "), /* 0x0d */
1068	STRENTRY("Int64 "), /* 0x0e */
1069	STRENTRY("Trap64 "), /* 0x0f */
1070	# else
1071	STRENTRY("Reserved0 "), /* 0x00 */
1072	STRENTRY("TSS16Avail "), /* 0x01 */
1073	STRENTRY("LDT "), /* 0x02 */
1074	STRENTRY("TSS16Busy "), /* 0x03 */
1075	STRENTRY("Call16 "), /* 0x04 */
1076	STRENTRY("Task "), /* 0x05 */
1077	STRENTRY("Int16 "), /* 0x06 */
1078	STRENTRY("Trap16 "), /* 0x07 */
1079	STRENTRY("Reserved8 "), /* 0x08 */
1080	STRENTRY("TSS32Avail "), /* 0x09 */
1081	STRENTRY("ReservedA "), /* 0x0a */
1082	STRENTRY("TSS32Busy "), /* 0x0b */
1083	STRENTRY("Call32 "), /* 0x0c */
1084	STRENTRY("ReservedD "), /* 0x0d */
1085	STRENTRY("Int32 "), /* 0x0e */
1086	STRENTRY("Trap32 "), /* 0x0f */
1087	# endif
1088	/* non system */
1089	STRENTRY("DataRO "), /* 0x10 */
1090	STRENTRY("DataRO Accessed "), /* 0x11 */
1091	STRENTRY("DataRW "), /* 0x12 */
1092	STRENTRY("DataRW Accessed "), /* 0x13 */
1093	STRENTRY("DataDownRO "), /* 0x14 */
1094	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1095	STRENTRY("DataDownRW "), /* 0x16 */
1096	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1097	STRENTRY("CodeEO "), /* 0x18 */
1098	STRENTRY("CodeEO Accessed "), /* 0x19 */
1099	STRENTRY("CodeER "), /* 0x1a */
1100	STRENTRY("CodeER Accessed "), /* 0x1b */
1101	STRENTRY("CodeConfEO "), /* 0x1c */
1102	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1103	STRENTRY("CodeConfER "), /* 0x1e */
1104	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1105	# undef SYSENTRY
1106	};
1107	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1108	char szMsg[128];
1109	char *psz = &szMsg[0];
1110	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1111	memcpy(psz, aTypes[i].psz, aTypes[i].cch);
1112	psz += aTypes[i].cch;
1113
1114	if (pDesc->Gen.u1Present)
1115	ADD_STR(psz, "Present ");
1116	else
1117	ADD_STR(psz, "Not-Present ");
1118	# if HC_ARCH_BITS == 64
1119	if (pDesc->Gen.u1Long)
1120	ADD_STR(psz, "64-bit ");
1121	else
1122	ADD_STR(psz, "Comp ");
1123	# else
1124	if (pDesc->Gen.u1Granularity)
1125	ADD_STR(psz, "Page ");
1126	if (pDesc->Gen.u1DefBig)
1127	ADD_STR(psz, "32-bit ");
1128	else
1129	ADD_STR(psz, "16-bit ");
1130	# endif
1131	# undef ADD_STR
1132	*psz = '\0';
1133
1134	/*
1135	* Limit and Base and format the output.
1136	*/
1137	uint32_t u32Limit = X86DESC_LIMIT(*pDesc);
1138	if (pDesc->Gen.u1Granularity)
1139	u32Limit = u32Limit << PAGE_SHIFT \| PAGE_OFFSET_MASK;
1140
1141	# if HC_ARCH_BITS == 64
1142	uint64_t u32Base = X86DESC64_BASE(*pDesc);
1143
1144	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1145	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1146	# else
1147	uint32_t u32Base = X86DESC_BASE(*pDesc);
1148
1149	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1150	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1151	# endif
1152	}
1153
1154	/**
1155	* Formats a full register dump.
1156	*
1157	* @param pVM The VM to operate on.
1158	* @param pCtx The context to format.
1159	*/
1160	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx)
1161	{
1162	/*
1163	* Format the flags.
1164	*/
1165	static struct
1166	{
1167	const char pszSet; const char pszClear; uint32_t fFlag;
1168	} aFlags[] =
1169	{
1170	{ "vip",NULL, X86_EFL_VIP },
1171	{ "vif",NULL, X86_EFL_VIF },
1172	{ "ac", NULL, X86_EFL_AC },
1173	{ "vm", NULL, X86_EFL_VM },
1174	{ "rf", NULL, X86_EFL_RF },
1175	{ "nt", NULL, X86_EFL_NT },
1176	{ "ov", "nv", X86_EFL_OF },
1177	{ "dn", "up", X86_EFL_DF },
1178	{ "ei", "di", X86_EFL_IF },
1179	{ "tf", NULL, X86_EFL_TF },
1180	{ "nt", "pl", X86_EFL_SF },
1181	{ "nz", "zr", X86_EFL_ZF },
1182	{ "ac", "na", X86_EFL_AF },
1183	{ "po", "pe", X86_EFL_PF },
1184	{ "cy", "nc", X86_EFL_CF },
1185	};
1186	char szEFlags[80];
1187	char *psz = szEFlags;
1188	uint32_t efl = pCtx->eflags.u32;
1189	for (unsigned i = 0; i < RT_ELEMENTS(aFlags); i++)
1190	{
1191	const char *pszAdd = aFlags[i].fFlag & efl ? aFlags[i].pszSet : aFlags[i].pszClear;
1192	if (pszAdd)
1193	{
1194	strcpy(psz, pszAdd);
1195	psz += strlen(pszAdd);
1196	*psz++ = ' ';
1197	}
1198	}
1199	psz[-1] = '\0';
1200
1201
1202	/*
1203	* Format the registers.
1204	*/
1205	if (CPUMIsGuestIn64BitCode(pVM, CPUMCTX2CORE(pCtx)))
1206	{
1207	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1208	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1209	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1210	"r14=%016RX64 r15=%016RX64\n"
1211	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1212	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1213	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1214	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1215	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1216	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1217	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1218	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1219	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1220	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1221	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1222	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1223	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1224	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1225	,
1226	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1227	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1228	pCtx->r14, pCtx->r15,
1229	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1230	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1231	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1232	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1233	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1234	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1235	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1236	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1237	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1238	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1239	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1240	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1241	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1242	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1243	}
1244	else
1245	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1246	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1247	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1248	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1249	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1250	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1251	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1252	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1253	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1254	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1255	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1256	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1257	,
1258	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1259	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1260	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr[0], pCtx->dr[1],
1261	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr[2], pCtx->dr[3],
1262	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr[4], pCtx->dr[5],
1263	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr[6], pCtx->dr[7],
1264	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0, pCtx->cr2,
1265	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3, pCtx->cr4,
1266	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1267	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1268	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1269	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1270
1271	Log(("FPU:\n"
1272	"FCW=%04x FSW=%04x FTW=%02x\n"
1273	"res1=%02x FOP=%04x FPUIP=%08x CS=%04x Rsvrd1=%04x\n"
1274	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1275	,
1276	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
1277	pCtx->fpu.huh1, pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsvrd1,
1278	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
1279	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
1280
1281
1282	Log(("MSR:\n"
1283	"EFER =%016RX64\n"
1284	"PAT =%016RX64\n"
1285	"STAR =%016RX64\n"
1286	"CSTAR =%016RX64\n"
1287	"LSTAR =%016RX64\n"
1288	"SFMASK =%016RX64\n"
1289	"KERNELGSBASE =%016RX64\n",
1290	pCtx->msrEFER,
1291	pCtx->msrPAT,
1292	pCtx->msrSTAR,
1293	pCtx->msrCSTAR,
1294	pCtx->msrLSTAR,
1295	pCtx->msrSFMASK,
1296	pCtx->msrKERNELGSBASE));
1297
1298	}
1299	#endif /* VBOX_STRICT */
1300
1301	/* Dummy callback handlers. */
1302	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
1303	{
1304	return VINF_SUCCESS;
1305	}
1306
1307	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1308	{
1309	return VINF_SUCCESS;
1310	}
1311
1312	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1313	{
1314	return VINF_SUCCESS;
1315	}
1316
1317	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1318	{
1319	return VINF_SUCCESS;
1320	}
1321
1322	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM)
1323	{
1324	return VINF_SUCCESS;
1325	}
1326
1327	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM)
1328	{
1329	return VINF_SUCCESS;
1330	}
1331
1332	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM)
1333	{
1334	return VINF_SUCCESS;
1335	}
1336
1337	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1338	{
1339	return VINF_SUCCESS;
1340	}
1341
1342	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
1343	{
1344	return VINF_SUCCESS;
1345	}
1346
1347	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1348	{
1349	return VINF_SUCCESS;
1350	}

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp@ 14660

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