HWACCMR0.cpp@ 14875

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1	/* $Id: HWACCMR0.cpp 14875 2008-12-01 16:24:22Z vboxsync $ */
2	/** @file
3	* HWACCM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_vmx.h>
32	#include <VBox/hwacc_svm.h>
33	#include <VBox/pgm.h>
34	#include <VBox/pdm.h>
35	#include <VBox/err.h>
36	#include <VBox/log.h>
37	#include <VBox/selm.h>
38	#include <VBox/iom.h>
39	#include <iprt/param.h>
40	#include <iprt/assert.h>
41	#include <iprt/asm.h>
42	#include <iprt/string.h>
43	#include <iprt/memobj.h>
44	#include <iprt/cpuset.h>
45	#include <iprt/power.h>
46	#include "HWVMXR0.h"
47	#include "HWSVMR0.h"
48
49	/*******************************************************************************
50	* Internal Functions *
51	*******************************************************************************/
52	static DECLCALLBACK(void) HWACCMR0EnableCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) HWACCMR0DisableCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
55	static int hwaccmR0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu);
56	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
57
58	/*******************************************************************************
59	* Global Variables *
60	*******************************************************************************/
61
62	static struct
63	{
64	HWACCM_CPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
65
66	/** Ring 0 handlers for VT-x and AMD-V. */
67	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu));
68	DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
69	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
70	DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
71	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
72	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
73	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
74	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
75	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
76	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVM pVM));
77
78	/** Maximum ASID allowed. */
79	uint32_t uMaxASID;
80
81	struct
82	{
83	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
84	bool fSupported;
85
86	/** Host CR4 value (set by ring-0 VMX init) */
87	uint64_t hostCR4;
88
89	/** VMX MSR values */
90	struct
91	{
92	uint64_t feature_ctrl;
93	uint64_t vmx_basic_info;
94	VMX_CAPABILITY vmx_pin_ctls;
95	VMX_CAPABILITY vmx_proc_ctls;
96	VMX_CAPABILITY vmx_proc_ctls2;
97	VMX_CAPABILITY vmx_exit;
98	VMX_CAPABILITY vmx_entry;
99	uint64_t vmx_misc;
100	uint64_t vmx_cr0_fixed0;
101	uint64_t vmx_cr0_fixed1;
102	uint64_t vmx_cr4_fixed0;
103	uint64_t vmx_cr4_fixed1;
104	uint64_t vmx_vmcs_enum;
105	uint64_t vmx_eptcaps;
106	} msr;
107	/* Last instruction error */
108	uint32_t ulLastInstrError;
109	} vmx;
110	struct
111	{
112	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
113	bool fSupported;
114
115	/** SVM revision. */
116	uint32_t u32Rev;
117
118	/** SVM feature bits from cpuid 0x8000000a */
119	uint32_t u32Features;
120	} svm;
121	/** Saved error from detection */
122	int32_t lLastError;
123
124	struct
125	{
126	uint32_t u32AMDFeatureECX;
127	uint32_t u32AMDFeatureEDX;
128	} cpuid;
129
130	HWACCMSTATE enmHwAccmState;
131
132	volatile bool fSuspended;
133	} HWACCMR0Globals;
134
135
136
137	/**
138	* Does global Ring-0 HWACCM initialization.
139	*
140	* @returns VBox status code.
141	*/
142	VMMR0DECL(int) HWACCMR0Init(void)
143	{
144	int rc;
145
146	memset(&HWACCMR0Globals, 0, sizeof(HWACCMR0Globals));
147	HWACCMR0Globals.enmHwAccmState = HWACCMSTATE_UNINITIALIZED;
148	for (unsigned i = 0; i < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); i++)
149	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
150
151	/* Fill in all callbacks with placeholders. */
152	HWACCMR0Globals.pfnEnterSession = HWACCMR0DummyEnter;
153	HWACCMR0Globals.pfnLeaveSession = HWACCMR0DummyLeave;
154	HWACCMR0Globals.pfnSaveHostState = HWACCMR0DummySaveHostState;
155	HWACCMR0Globals.pfnLoadGuestState = HWACCMR0DummyLoadGuestState;
156	HWACCMR0Globals.pfnRunGuestCode = HWACCMR0DummyRunGuestCode;
157	HWACCMR0Globals.pfnEnableCpu = HWACCMR0DummyEnableCpu;
158	HWACCMR0Globals.pfnDisableCpu = HWACCMR0DummyDisableCpu;
159	HWACCMR0Globals.pfnInitVM = HWACCMR0DummyInitVM;
160	HWACCMR0Globals.pfnTermVM = HWACCMR0DummyTermVM;
161	HWACCMR0Globals.pfnSetupVM = HWACCMR0DummySetupVM;
162
163	/*
164	* Check for VT-x and AMD-V capabilities
165	*/
166	if (ASMHasCpuId())
167	{
168	uint32_t u32FeaturesECX;
169	uint32_t u32Dummy;
170	uint32_t u32FeaturesEDX;
171	uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
172
173	ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
174	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
175	/* Query AMD features. */
176	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy, &HWACCMR0Globals.cpuid.u32AMDFeatureECX, &HWACCMR0Globals.cpuid.u32AMDFeatureEDX);
177
178	if ( u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
179	&& u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
180	&& u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX
181	)
182	{
183	/*
184	* Read all VMX MSRs if VMX is available. (same goes for RDMSR/WRMSR)
185	* We also assume all VMX-enabled CPUs support fxsave/fxrstor.
186	*/
187	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
188	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
189	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
190	)
191	{
192	int aRc[RTCPUSET_MAX_CPUS];
193	RTCPUID idCpu = 0;
194
195	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
196
197	/* We need to check if VT-x has been properly initialized on all CPUs. Some BIOSes do a lousy job. */
198	memset(aRc, 0, sizeof(aRc));
199	HWACCMR0Globals.lLastError = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
200
201	/* Check the return code of all invocations. */
202	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
203	HWACCMR0Globals.lLastError = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
204
205	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
206	{
207	/* Reread in case we've changed it. */
208	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
209
210	if ( (HWACCMR0Globals.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
211	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
212	{
213	RTR0MEMOBJ pScatchMemObj;
214	void *pvScatchPage;
215	RTHCPHYS pScatchPagePhys;
216
217	HWACCMR0Globals.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
218	HWACCMR0Globals.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
219	HWACCMR0Globals.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
220	HWACCMR0Globals.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
221	HWACCMR0Globals.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
222	HWACCMR0Globals.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
223	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
224	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
225	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
226	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
227	HWACCMR0Globals.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
228	/* VPID 16 bits ASID. */
229	HWACCMR0Globals.uMaxASID = 0x10000; /* exclusive */
230
231	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
232	{
233	HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
234	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT\|VMX_VMCS_CTRL_PROC_EXEC2_VPID))
235	HWACCMR0Globals.vmx.msr.vmx_eptcaps = ASMRdMsr(MSR_IA32_VMX_EPT_CAPS);
236	}
237
238	HWACCMR0Globals.vmx.hostCR4 = ASMGetCR4();
239
240	rc = RTR0MemObjAllocCont(&pScatchMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
241	if (RT_FAILURE(rc))
242	return rc;
243
244	pvScatchPage = RTR0MemObjAddress(pScatchMemObj);
245	pScatchPagePhys = RTR0MemObjGetPagePhysAddr(pScatchMemObj, 0);
246	memset(pvScatchPage, 0, PAGE_SIZE);
247
248	/* Set revision dword at the beginning of the structure. */
249	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(HWACCMR0Globals.vmx.msr.vmx_basic_info);
250
251	/* Make sure we don't get rescheduled to another cpu during this probe. */
252	RTCCUINTREG fFlags = ASMIntDisableFlags();
253
254	/*
255	* Check CR4.VMXE
256	*/
257	if (!(HWACCMR0Globals.vmx.hostCR4 & X86_CR4_VMXE))
258	{
259	/* In theory this bit could be cleared behind our back. Which would cause #UD faults when we
260	* try to execute the VMX instructions...
261	*/
262	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4 \| X86_CR4_VMXE);
263	}
264
265	/* Enter VMX Root Mode */
266	rc = VMXEnable(pScatchPagePhys);
267	if (RT_FAILURE(rc))
268	{
269	/* KVM leaves the CPU in VMX root mode. Not only is this not allowed, it will crash the host when we enter raw mode, because
270	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify this bit)
271	* (b) turning off paging causes a #GP (unavoidable when switching from long to 32 bits mode or 32 bits to PAE)
272	*
273	* They should fix their code, but until they do we simply refuse to run.
274	*/
275	HWACCMR0Globals.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
276	}
277	else
278	{
279	HWACCMR0Globals.vmx.fSupported = true;
280	VMXDisable();
281	}
282
283	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it wasn't so before (some software could incorrectly think it's in VMX mode) */
284	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4);
285	ASMSetFlags(fFlags);
286
287	RTR0MemObjFree(pScatchMemObj, false);
288	if (RT_FAILURE(HWACCMR0Globals.lLastError))
289	return HWACCMR0Globals.lLastError;
290	}
291	else
292	{
293	AssertFailed(); /* can't hit this case anymore */
294	HWACCMR0Globals.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
295	}
296	}
297	#ifdef LOG_ENABLED
298	else
299	SUPR0Printf("HWACCMR0InitCPU failed with rc=%d\n", HWACCMR0Globals.lLastError);
300	#endif
301	}
302	else
303	HWACCMR0Globals.lLastError = VERR_VMX_NO_VMX;
304	}
305	else
306	if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
307	&& u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
308	&& u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX
309	)
310	{
311	/*
312	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
313	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
314	*/
315	if ( (HWACCMR0Globals.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
316	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
317	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
318	)
319	{
320	int aRc[RTCPUSET_MAX_CPUS];
321	RTCPUID idCpu = 0;
322
323	/* We need to check if AMD-V has been properly initialized on all CPUs. Some BIOSes might do a poor job. */
324	memset(aRc, 0, sizeof(aRc));
325	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
326	AssertRC(rc);
327
328	/* Check the return code of all invocations. */
329	if (RT_SUCCESS(rc))
330	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
331
332	AssertMsgRC(rc, ("HWACCMR0InitCPU failed for cpu %d with rc=%d\n", idCpu, rc));
333
334	if (RT_SUCCESS(rc))
335	{
336	/* Query AMD features. */
337	ASMCpuId(0x8000000A, &HWACCMR0Globals.svm.u32Rev, &HWACCMR0Globals.uMaxASID, &u32Dummy, &HWACCMR0Globals.svm.u32Features);
338
339	HWACCMR0Globals.svm.fSupported = true;
340	}
341	else
342	HWACCMR0Globals.lLastError = rc;
343	}
344	else
345	HWACCMR0Globals.lLastError = VERR_SVM_NO_SVM;
346	}
347	else
348	HWACCMR0Globals.lLastError = VERR_HWACCM_UNKNOWN_CPU;
349	}
350	else
351	HWACCMR0Globals.lLastError = VERR_HWACCM_NO_CPUID;
352
353	if (HWACCMR0Globals.vmx.fSupported)
354	{
355	HWACCMR0Globals.pfnEnterSession = VMXR0Enter;
356	HWACCMR0Globals.pfnLeaveSession = VMXR0Leave;
357	HWACCMR0Globals.pfnSaveHostState = VMXR0SaveHostState;
358	HWACCMR0Globals.pfnLoadGuestState = VMXR0LoadGuestState;
359	HWACCMR0Globals.pfnRunGuestCode = VMXR0RunGuestCode;
360	HWACCMR0Globals.pfnEnableCpu = VMXR0EnableCpu;
361	HWACCMR0Globals.pfnDisableCpu = VMXR0DisableCpu;
362	HWACCMR0Globals.pfnInitVM = VMXR0InitVM;
363	HWACCMR0Globals.pfnTermVM = VMXR0TermVM;
364	HWACCMR0Globals.pfnSetupVM = VMXR0SetupVM;
365	}
366	else
367	if (HWACCMR0Globals.svm.fSupported)
368	{
369	HWACCMR0Globals.pfnEnterSession = SVMR0Enter;
370	HWACCMR0Globals.pfnLeaveSession = SVMR0Leave;
371	HWACCMR0Globals.pfnSaveHostState = SVMR0SaveHostState;
372	HWACCMR0Globals.pfnLoadGuestState = SVMR0LoadGuestState;
373	HWACCMR0Globals.pfnRunGuestCode = SVMR0RunGuestCode;
374	HWACCMR0Globals.pfnEnableCpu = SVMR0EnableCpu;
375	HWACCMR0Globals.pfnDisableCpu = SVMR0DisableCpu;
376	HWACCMR0Globals.pfnInitVM = SVMR0InitVM;
377	HWACCMR0Globals.pfnTermVM = SVMR0TermVM;
378	HWACCMR0Globals.pfnSetupVM = SVMR0SetupVM;
379	}
380
381	rc = RTPowerNotificationRegister(hwaccmR0PowerCallback, 0);
382	Assert(RT_SUCCESS(rc));
383
384	return VINF_SUCCESS;
385	}
386
387
388	/**
389	* Checks the error code array filled in for each cpu in the system.
390	*
391	* @returns VBox status code.
392	* @param paRc Error code array
393	* @param cErrorCodes Array size
394	* @param pidCpu Value of the first cpu that set an error (out)
395	*/
396	static int hwaccmR0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu)
397	{
398	int rc = VINF_SUCCESS;
399
400	Assert(cErrorCodes == RTCPUSET_MAX_CPUS);
401
402	for (unsigned i=0;i<cErrorCodes;i++)
403	{
404	if (RTMpIsCpuOnline(i))
405	{
406	if (RT_FAILURE(paRc[i]))
407	{
408	rc = paRc[i];
409	*pidCpu = i;
410	break;
411	}
412	}
413	}
414	return rc;
415	}
416
417	/**
418	* Does global Ring-0 HWACCM termination.
419	*
420	* @returns VBox status code.
421	*/
422	VMMR0DECL(int) HWACCMR0Term(void)
423	{
424	int aRc[RTCPUSET_MAX_CPUS];
425	int rc;
426
427	rc = RTPowerNotificationDeregister(hwaccmR0PowerCallback, 0);
428	Assert(RT_SUCCESS(rc));
429
430	memset(aRc, 0, sizeof(aRc));
431	rc = RTMpOnAll(HWACCMR0DisableCPU, aRc, NULL);
432	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
433
434	/* Free the per-cpu pages used for VT-x and AMD-V */
435	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
436	{
437	AssertMsgRC(aRc[i], ("HWACCMR0DisableCPU failed for cpu %d with rc=%d\n", i, aRc[i]));
438	if (HWACCMR0Globals.aCpuInfo[i].pMemObj != NIL_RTR0MEMOBJ)
439	{
440	RTR0MemObjFree(HWACCMR0Globals.aCpuInfo[i].pMemObj, false);
441	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
442	}
443	}
444	return rc;
445	}
446
447
448	/**
449	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
450	* is to be called on the target cpus.
451	*
452	* @param idCpu The identifier for the CPU the function is called on.
453	* @param pvUser1 The 1st user argument.
454	* @param pvUser2 The 2nd user argument.
455	*/
456	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
457	{
458	unsigned u32VendorEBX = (uintptr_t)pvUser1;
459	int paRc = (int )pvUser2;
460	uint64_t val;
461
462	#ifdef LOG_ENABLED
463	SUPR0Printf("HWACCMR0InitCPU cpu %d\n", idCpu);
464	#endif
465	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
466
467	if (u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX)
468	{
469	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
470
471	/*
472	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
473	* Once the lock bit is set, this MSR can no longer be modified.
474	*/
475	if (!(val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK)))
476	{
477	/* MSR is not yet locked; we can change it ourselves here */
478	ASMWrMsr(MSR_IA32_FEATURE_CONTROL, HWACCMR0Globals.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
479	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
480	}
481	if ( (val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
482	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
483	paRc[idCpu] = VINF_SUCCESS;
484	else
485	paRc[idCpu] = VERR_VMX_MSR_LOCKED_OR_DISABLED;
486	}
487	else
488	if (u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX)
489	{
490	/* Check if SVM is disabled */
491	val = ASMRdMsr(MSR_K8_VM_CR);
492	if (!(val & MSR_K8_VM_CR_SVM_DISABLE))
493	{
494	/* Turn on SVM in the EFER MSR. */
495	val = ASMRdMsr(MSR_K6_EFER);
496	if (!(val & MSR_K6_EFER_SVME))
497	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
498
499	/* Paranoia. */
500	val = ASMRdMsr(MSR_K6_EFER);
501	if (val & MSR_K6_EFER_SVME)
502	paRc[idCpu] = VINF_SUCCESS;
503	else
504	paRc[idCpu] = VERR_SVM_ILLEGAL_EFER_MSR;
505	}
506	else
507	paRc[idCpu] = HWACCMR0Globals.lLastError = VERR_SVM_DISABLED;
508	}
509	else
510	AssertFailed(); /* can't happen */
511	return;
512	}
513
514
515	/**
516	* Sets up HWACCM on all cpus.
517	*
518	* @returns VBox status code.
519	* @param pVM The VM to operate on.
520	* @param enmNewHwAccmState New hwaccm state
521	*
522	*/
523	VMMR0DECL(int) HWACCMR0EnableAllCpus(PVM pVM, HWACCMSTATE enmNewHwAccmState)
524	{
525	Assert(sizeof(HWACCMR0Globals.enmHwAccmState) == sizeof(uint32_t));
526
527	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
528	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
529	return VERR_HWACCM_SUSPEND_PENDING;
530
531	if (ASMAtomicCmpXchgU32((volatile uint32_t *)&HWACCMR0Globals.enmHwAccmState, enmNewHwAccmState, HWACCMSTATE_UNINITIALIZED))
532	{
533	int aRc[RTCPUSET_MAX_CPUS];
534	RTCPUID idCpu = 0;
535
536	/* Don't setup hwaccm as that might not work (vt-x & 64 bits raw mode) */
537	if (enmNewHwAccmState == HWACCMSTATE_DISABLED)
538	return VINF_SUCCESS;
539
540	memset(aRc, 0, sizeof(aRc));
541
542	/* Allocate one page per cpu for the global vt-x and amd-v pages */
543	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
544	{
545	Assert(!HWACCMR0Globals.aCpuInfo[i].pMemObj);
546
547	/** @todo this is rather dangerous if cpus can be taken offline; we don't care for now */
548	if (RTMpIsCpuOnline(i))
549	{
550	int rc = RTR0MemObjAllocCont(&HWACCMR0Globals.aCpuInfo[i].pMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
551	AssertRC(rc);
552	if (RT_FAILURE(rc))
553	return rc;
554
555	void *pvR0 = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[i].pMemObj);
556	Assert(pvR0);
557	ASMMemZeroPage(pvR0);
558
559	#ifdef LOG_ENABLED
560	SUPR0Printf("address %x phys %x\n", pvR0, (uint32_t)RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[i].pMemObj, 0));
561	#endif
562	}
563	}
564	/* First time, so initialize each cpu/core */
565	int rc = RTMpOnAll(HWACCMR0EnableCPU, (void *)pVM, aRc);
566
567	/* Check the return code of all invocations. */
568	if (RT_SUCCESS(rc))
569	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
570
571	AssertMsgRC(rc, ("HWACCMR0EnableAllCpus failed for cpu %d with rc=%d\n", idCpu, rc));
572	return rc;
573	}
574
575	if (HWACCMR0Globals.enmHwAccmState == enmNewHwAccmState)
576	return VINF_SUCCESS;
577
578	/* Request to change the mode is not allowed */
579	return VERR_ACCESS_DENIED;
580	}
581
582	/**
583	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
584	* is to be called on the target cpus.
585	*
586	* @param idCpu The identifier for the CPU the function is called on.
587	* @param pvUser1 The 1st user argument.
588	* @param pvUser2 The 2nd user argument.
589	*/
590	static DECLCALLBACK(void) HWACCMR0EnableCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
591	{
592	PVM pVM = (PVM)pvUser1; /* can be NULL! */
593	int paRc = (int )pvUser2;
594	void *pvPageCpu;
595	RTHCPHYS pPageCpuPhys;
596	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
597
598	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
599	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
600	Assert(!pCpu->fConfigured);
601	Assert(ASMAtomicReadBool(&pCpu->fInUse) == false);
602
603	pCpu->idCpu = idCpu;
604
605	/* Make sure we start with a clean TLB. */
606	pCpu->fFlushTLB = true;
607
608	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
609	pCpu->cTLBFlushes = 0;
610
611	/* Should never happen */
612	if (!pCpu->pMemObj)
613	{
614	AssertFailed();
615	paRc[idCpu] = VERR_INTERNAL_ERROR;
616	return;
617	}
618
619	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
620	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
621
622	paRc[idCpu] = HWACCMR0Globals.pfnEnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
623	AssertRC(paRc[idCpu]);
624	if (RT_SUCCESS(paRc[idCpu]))
625	pCpu->fConfigured = true;
626
627	return;
628	}
629
630	/**
631	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
632	* is to be called on the target cpus.
633	*
634	* @param idCpu The identifier for the CPU the function is called on.
635	* @param pvUser1 The 1st user argument.
636	* @param pvUser2 The 2nd user argument.
637	*/
638	static DECLCALLBACK(void) HWACCMR0DisableCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
639	{
640	void *pvPageCpu;
641	RTHCPHYS pPageCpuPhys;
642	int paRc = (int )pvUser1;
643	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
644
645	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
646	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
647	Assert(ASMAtomicReadBool(&pCpu->fInUse) == false);
648
649	if (!pCpu->pMemObj)
650	return;
651
652	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
653	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
654
655	if (pCpu->fConfigured)
656	{
657	paRc[idCpu] = HWACCMR0Globals.pfnDisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
658	AssertRC(paRc[idCpu]);
659	pCpu->fConfigured = false;
660	}
661	else
662	paRc[idCpu] = VINF_SUCCESS; /* nothing to do */
663
664	pCpu->uCurrentASID = 0;
665	return;
666	}
667
668	/**
669	* Called whenever a system power state change occurs.
670	*
671	* @param enmEvent Power event
672	* @param pvUser User argument
673	*/
674	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
675	{
676	NOREF(pvUser);
677
678	#ifdef LOG_ENABLED
679	if (enmEvent == RTPOWEREVENT_SUSPEND)
680	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
681	else
682	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_RESUME\n");
683	#endif
684
685	if (enmEvent == RTPOWEREVENT_SUSPEND)
686	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, true);
687
688	if (HWACCMR0Globals.enmHwAccmState == HWACCMSTATE_ENABLED)
689	{
690	int aRc[RTCPUSET_MAX_CPUS];
691	int rc;
692	RTCPUID idCpu;
693
694	memset(aRc, 0, sizeof(aRc));
695	if (enmEvent == RTPOWEREVENT_SUSPEND)
696	{
697	/* Turn off VT-x or AMD-V on all CPUs. */
698	rc = RTMpOnAll(HWACCMR0DisableCPU, aRc, NULL);
699	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
700	}
701	else
702	{
703	/* Reinit the CPUs from scratch as the suspend state has messed with the MSRs. */
704	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)((HWACCMR0Globals.vmx.fSupported) ? X86_CPUID_VENDOR_INTEL_EBX : X86_CPUID_VENDOR_AMD_EBX), aRc);
705	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
706
707	if (RT_SUCCESS(rc))
708	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
709	#ifdef LOG_ENABLED
710	if (RT_FAILURE(rc))
711	SUPR0Printf("hwaccmR0PowerCallback HWACCMR0InitCPU failed with %d\n", rc);
712	#endif
713
714	/* Turn VT-x or AMD-V back on on all CPUs. */
715	rc = RTMpOnAll(HWACCMR0EnableCPU, NULL, aRc);
716	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
717	}
718	}
719	if (enmEvent == RTPOWEREVENT_RESUME)
720	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, false);
721	}
722
723
724	/**
725	* Does Ring-0 per VM HWACCM initialization.
726	*
727	* This is mainly to check that the Host CPU mode is compatible
728	* with VMX.
729	*
730	* @returns VBox status code.
731	* @param pVM The VM to operate on.
732	*/
733	VMMR0DECL(int) HWACCMR0InitVM(PVM pVM)
734	{
735	int rc;
736	RTCPUID idCpu = RTMpCpuId();
737	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
738
739	AssertReturn(pVM, VERR_INVALID_PARAMETER);
740
741	#ifdef LOG_ENABLED
742	SUPR0Printf("HWACCMR0InitVM: %p\n", pVM);
743	#endif
744
745	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
746	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
747	return VERR_HWACCM_SUSPEND_PENDING;
748
749	pVM->hwaccm.s.vmx.fSupported = HWACCMR0Globals.vmx.fSupported;
750	pVM->hwaccm.s.svm.fSupported = HWACCMR0Globals.svm.fSupported;
751
752	pVM->hwaccm.s.vmx.msr.feature_ctrl = HWACCMR0Globals.vmx.msr.feature_ctrl;
753	pVM->hwaccm.s.vmx.hostCR4 = HWACCMR0Globals.vmx.hostCR4;
754	pVM->hwaccm.s.vmx.msr.vmx_basic_info = HWACCMR0Globals.vmx.msr.vmx_basic_info;
755	pVM->hwaccm.s.vmx.msr.vmx_pin_ctls = HWACCMR0Globals.vmx.msr.vmx_pin_ctls;
756	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls = HWACCMR0Globals.vmx.msr.vmx_proc_ctls;
757	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2 = HWACCMR0Globals.vmx.msr.vmx_proc_ctls2;
758	pVM->hwaccm.s.vmx.msr.vmx_exit = HWACCMR0Globals.vmx.msr.vmx_exit;
759	pVM->hwaccm.s.vmx.msr.vmx_entry = HWACCMR0Globals.vmx.msr.vmx_entry;
760	pVM->hwaccm.s.vmx.msr.vmx_misc = HWACCMR0Globals.vmx.msr.vmx_misc;
761	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0;
762	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1;
763	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0;
764	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1;
765	pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum = HWACCMR0Globals.vmx.msr.vmx_vmcs_enum;
766	pVM->hwaccm.s.vmx.msr.vmx_eptcaps = HWACCMR0Globals.vmx.msr.vmx_eptcaps;
767	pVM->hwaccm.s.svm.u32Rev = HWACCMR0Globals.svm.u32Rev;
768	pVM->hwaccm.s.svm.u32Features = HWACCMR0Globals.svm.u32Features;
769	pVM->hwaccm.s.cpuid.u32AMDFeatureECX = HWACCMR0Globals.cpuid.u32AMDFeatureECX;
770	pVM->hwaccm.s.cpuid.u32AMDFeatureEDX = HWACCMR0Globals.cpuid.u32AMDFeatureEDX;
771	pVM->hwaccm.s.lLastError = HWACCMR0Globals.lLastError;
772
773	pVM->hwaccm.s.uMaxASID = HWACCMR0Globals.uMaxASID;
774
775	for (unsigned i=0;i<pVM->cCPUs;i++)
776	{
777	PVMCPU pVCpu = &pVM->aCpus[i];
778
779	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
780
781	/* Invalidate the last cpu we were running on. */
782	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
783
784	/* we'll aways increment this the first time (host uses ASID 0) */
785	pVCpu->hwaccm.s.uCurrentASID = 0;
786	}
787
788	ASMAtomicWriteBool(&pCpu->fInUse, true);
789
790	/* Init a VT-x or AMD-V VM. */
791	rc = HWACCMR0Globals.pfnInitVM(pVM);
792
793	ASMAtomicWriteBool(&pCpu->fInUse, false);
794
795	return rc;
796	}
797
798
799	/**
800	* Does Ring-0 per VM HWACCM termination.
801	*
802	* @returns VBox status code.
803	* @param pVM The VM to operate on.
804	*/
805	VMMR0DECL(int) HWACCMR0TermVM(PVM pVM)
806	{
807	int rc;
808	RTCPUID idCpu = RTMpCpuId();
809	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
810
811	AssertReturn(pVM, VERR_INVALID_PARAMETER);
812
813	#ifdef LOG_ENABLED
814	SUPR0Printf("HWACCMR0TermVM: %p\n", pVM);
815	#endif
816
817	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
818	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
819
820	ASMAtomicWriteBool(&pCpu->fInUse, true);
821
822	/* Terminate a VT-x or AMD-V VM. */
823	rc = HWACCMR0Globals.pfnTermVM(pVM);
824
825	ASMAtomicWriteBool(&pCpu->fInUse, false);
826	return rc;
827	}
828
829
830	/**
831	* Sets up a VT-x or AMD-V session
832	*
833	* @returns VBox status code.
834	* @param pVM The VM to operate on.
835	*/
836	VMMR0DECL(int) HWACCMR0SetupVM(PVM pVM)
837	{
838	int rc;
839	RTCPUID idCpu = RTMpCpuId();
840	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
841
842	AssertReturn(pVM, VERR_INVALID_PARAMETER);
843
844	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
845	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
846
847	#ifdef LOG_ENABLED
848	SUPR0Printf("HWACCMR0SetupVM: %p\n", pVM);
849	#endif
850
851	ASMAtomicWriteBool(&pCpu->fInUse, true);
852
853	for (unsigned i=0;i<pVM->cCPUs;i++)
854	{
855	/* On first entry we'll sync everything. */
856	pVM->aCpus[i].hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
857	}
858
859	/* Setup VT-x or AMD-V. */
860	rc = HWACCMR0Globals.pfnSetupVM(pVM);
861
862	ASMAtomicWriteBool(&pCpu->fInUse, false);
863
864	return rc;
865	}
866
867
868	/**
869	* Enters the VT-x or AMD-V session
870	*
871	* @returns VBox status code.
872	* @param pVM The VM to operate on.
873	* @param pVCpu VMCPUD id.
874	*/
875	VMMR0DECL(int) HWACCMR0Enter(PVM pVM, PVMCPU pVCpu)
876	{
877	PCPUMCTX pCtx;
878	int rc;
879	RTCPUID idCpu = RTMpCpuId();
880	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
881
882	/* Make sure we can't enter a session after we've disabled hwaccm in preparation of a suspend. */
883	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
884	ASMAtomicWriteBool(&pCpu->fInUse, true);
885
886	pCtx = CPUMQueryGuestCtxPtrEx(pVM, pVCpu);
887
888	/* Always load the guest's FPU/XMM state on-demand. */
889	CPUMDeactivateGuestFPUState(pVM);
890
891	/* Always load the guest's debug state on-demand. */
892	CPUMDeactivateGuestDebugState(pVM);
893
894	/* Always reload the host context and the guest's CR0 register. (!!!!) */
895	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0 \| HWACCM_CHANGED_HOST_CONTEXT;
896
897	/* Setup the register and mask according to the current execution mode. */
898	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
899	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFFFFFFFFFF);
900	else
901	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFF);
902
903	rc = HWACCMR0Globals.pfnEnterSession(pVM, pVCpu, pCpu);
904	AssertRC(rc);
905	/* We must save the host context here (VT-x) as we might be rescheduled on a different cpu after a long jump back to ring 3. */
906	rc \|= HWACCMR0Globals.pfnSaveHostState(pVM, pVCpu);
907	AssertRC(rc);
908	rc \|= HWACCMR0Globals.pfnLoadGuestState(pVM, pVCpu, pCtx);
909	AssertRC(rc);
910
911	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
912	if (RT_SUCCESS(rc))
913	{
914	AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == NIL_RTCPUID, ("%d", (int)pVCpu->hwaccm.s.idEnteredCpu));
915	pVCpu->hwaccm.s.idEnteredCpu = idCpu;
916
917	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
918	PGMDynMapMigrateAutoSet(pVCpu);
919	#endif
920	}
921	return rc;
922	}
923
924
925	/**
926	* Leaves the VT-x or AMD-V session
927	*
928	* @returns VBox status code.
929	* @param pVM The VM to operate on.
930	* @param pVCpu VMCPUD id.
931	*/
932	VMMR0DECL(int) HWACCMR0Leave(PVM pVM, PVMCPU pVCpu)
933	{
934	PCPUMCTX pCtx;
935	int rc;
936	RTCPUID idCpu = RTMpCpuId();
937	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
938
939	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
940
941	pCtx = CPUMQueryGuestCtxPtrEx(pVM, pVCpu);
942
943	/* Note: It's rather tricky with longjmps done by e.g. Log statements or the page fault handler.
944	* We must restore the host FPU here to make absolutely sure we don't leave the guest FPU state active
945	* or trash somebody else's FPU state.
946	*/
947	/* Save the guest FPU and XMM state if necessary. */
948	if (CPUMIsGuestFPUStateActive(pVCpu))
949	{
950	Log2(("CPUMR0SaveGuestFPU\n"));
951	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
952
953	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
954	}
955
956	rc = HWACCMR0Globals.pfnLeaveSession(pVM, pVCpu, pCtx);
957
958	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
959	AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == idCpu, ("owner is %d, I'm %d", (int)pVCpu->hwaccm.s.idEnteredCpu, (int)idCpu));
960	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
961
962	ASMAtomicWriteBool(&pCpu->fInUse, false);
963	return rc;
964	}
965
966	/**
967	* Runs guest code in a hardware accelerated VM.
968	*
969	* @returns VBox status code.
970	* @param pVM The VM to operate on.
971	* @param pVCpu VMCPUD id.
972	*/
973	VMMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
974	{
975	CPUMCTX *pCtx;
976	RTCPUID idCpu = RTMpCpuId(); NOREF(idCpu);
977	int rc;
978	#ifdef VBOX_STRICT
979	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
980	#endif
981
982	Assert(!VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL));
983	Assert(HWACCMR0Globals.aCpuInfo[idCpu].fConfigured);
984	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
985	Assert(ASMAtomicReadBool(&pCpu->fInUse) == true);
986
987	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
988	PGMDynMapStartAutoSet(pVCpu);
989	#endif
990
991	pCtx = CPUMQueryGuestCtxPtrEx(pVM, pVCpu);
992
993	rc = HWACCMR0Globals.pfnRunGuestCode(pVM, pVCpu, pCtx);
994
995	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
996	PGMDynMapReleaseAutoSet(pVCpu);
997	#endif
998	return rc;
999	}
1000
1001
1002	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1003	/**
1004	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1005	*
1006	* @returns VBox status code.
1007	* @param pVM VM handle.
1008	* @param pVCpu VMCPU handle.
1009	* @param pCtx CPU context
1010	*/
1011	VMMR0DECL(int) HWACCMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1012	{
1013	if (pVM->hwaccm.s.vmx.fSupported)
1014	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64);
1015
1016	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64);
1017	}
1018
1019	/**
1020	* Save guest debug state (64 bits guest mode & 32 bits host only)
1021	*
1022	* @returns VBox status code.
1023	* @param pVM VM handle.
1024	* @param pVCpu VMCPU handle.
1025	* @param pCtx CPU context
1026	*/
1027	VMMR0DECL(int) HWACCMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1028	{
1029	if (pVM->hwaccm.s.vmx.fSupported)
1030	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64);
1031
1032	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64);
1033	}
1034
1035	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) */
1036
1037	/**
1038	* Returns suspend status of the host
1039	*
1040	* @returns Suspend pending or not
1041	*/
1042	VMMR0DECL(bool) HWACCMR0SuspendPending()
1043	{
1044	return ASMAtomicReadBool(&HWACCMR0Globals.fSuspended);
1045	}
1046
1047	/**
1048	* Returns the cpu structure for the current cpu.
1049	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1050	*
1051	* @returns cpu structure pointer
1052	*/
1053	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu()
1054	{
1055	RTCPUID idCpu = RTMpCpuId();
1056
1057	return &HWACCMR0Globals.aCpuInfo[idCpu];
1058	}
1059
1060	/**
1061	* Returns the cpu structure for the current cpu.
1062	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1063	*
1064	* @returns cpu structure pointer
1065	* @param idCpu id of the VCPU
1066	*/
1067	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu)
1068	{
1069	return &HWACCMR0Globals.aCpuInfo[idCpu];
1070	}
1071
1072	#ifdef VBOX_STRICT
1073	# include <iprt/string.h>
1074	/**
1075	* Dumps a descriptor.
1076	*
1077	* @param pDesc Descriptor to dump.
1078	* @param Sel Selector number.
1079	* @param pszMsg Message to prepend the log entry with.
1080	*/
1081	VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1082	{
1083	/*
1084	* Make variable description string.
1085	*/
1086	static struct
1087	{
1088	unsigned cch;
1089	const char *psz;
1090	} const aTypes[32] =
1091	{
1092	# define STRENTRY(str) { sizeof(str) - 1, str }
1093
1094	/* system */
1095	# if HC_ARCH_BITS == 64
1096	STRENTRY("Reserved0 "), /* 0x00 */
1097	STRENTRY("Reserved1 "), /* 0x01 */
1098	STRENTRY("LDT "), /* 0x02 */
1099	STRENTRY("Reserved3 "), /* 0x03 */
1100	STRENTRY("Reserved4 "), /* 0x04 */
1101	STRENTRY("Reserved5 "), /* 0x05 */
1102	STRENTRY("Reserved6 "), /* 0x06 */
1103	STRENTRY("Reserved7 "), /* 0x07 */
1104	STRENTRY("Reserved8 "), /* 0x08 */
1105	STRENTRY("TSS64Avail "), /* 0x09 */
1106	STRENTRY("ReservedA "), /* 0x0a */
1107	STRENTRY("TSS64Busy "), /* 0x0b */
1108	STRENTRY("Call64 "), /* 0x0c */
1109	STRENTRY("ReservedD "), /* 0x0d */
1110	STRENTRY("Int64 "), /* 0x0e */
1111	STRENTRY("Trap64 "), /* 0x0f */
1112	# else
1113	STRENTRY("Reserved0 "), /* 0x00 */
1114	STRENTRY("TSS16Avail "), /* 0x01 */
1115	STRENTRY("LDT "), /* 0x02 */
1116	STRENTRY("TSS16Busy "), /* 0x03 */
1117	STRENTRY("Call16 "), /* 0x04 */
1118	STRENTRY("Task "), /* 0x05 */
1119	STRENTRY("Int16 "), /* 0x06 */
1120	STRENTRY("Trap16 "), /* 0x07 */
1121	STRENTRY("Reserved8 "), /* 0x08 */
1122	STRENTRY("TSS32Avail "), /* 0x09 */
1123	STRENTRY("ReservedA "), /* 0x0a */
1124	STRENTRY("TSS32Busy "), /* 0x0b */
1125	STRENTRY("Call32 "), /* 0x0c */
1126	STRENTRY("ReservedD "), /* 0x0d */
1127	STRENTRY("Int32 "), /* 0x0e */
1128	STRENTRY("Trap32 "), /* 0x0f */
1129	# endif
1130	/* non system */
1131	STRENTRY("DataRO "), /* 0x10 */
1132	STRENTRY("DataRO Accessed "), /* 0x11 */
1133	STRENTRY("DataRW "), /* 0x12 */
1134	STRENTRY("DataRW Accessed "), /* 0x13 */
1135	STRENTRY("DataDownRO "), /* 0x14 */
1136	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1137	STRENTRY("DataDownRW "), /* 0x16 */
1138	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1139	STRENTRY("CodeEO "), /* 0x18 */
1140	STRENTRY("CodeEO Accessed "), /* 0x19 */
1141	STRENTRY("CodeER "), /* 0x1a */
1142	STRENTRY("CodeER Accessed "), /* 0x1b */
1143	STRENTRY("CodeConfEO "), /* 0x1c */
1144	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1145	STRENTRY("CodeConfER "), /* 0x1e */
1146	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1147	# undef SYSENTRY
1148	};
1149	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1150	char szMsg[128];
1151	char *psz = &szMsg[0];
1152	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1153	memcpy(psz, aTypes[i].psz, aTypes[i].cch);
1154	psz += aTypes[i].cch;
1155
1156	if (pDesc->Gen.u1Present)
1157	ADD_STR(psz, "Present ");
1158	else
1159	ADD_STR(psz, "Not-Present ");
1160	# if HC_ARCH_BITS == 64
1161	if (pDesc->Gen.u1Long)
1162	ADD_STR(psz, "64-bit ");
1163	else
1164	ADD_STR(psz, "Comp ");
1165	# else
1166	if (pDesc->Gen.u1Granularity)
1167	ADD_STR(psz, "Page ");
1168	if (pDesc->Gen.u1DefBig)
1169	ADD_STR(psz, "32-bit ");
1170	else
1171	ADD_STR(psz, "16-bit ");
1172	# endif
1173	# undef ADD_STR
1174	*psz = '\0';
1175
1176	/*
1177	* Limit and Base and format the output.
1178	*/
1179	uint32_t u32Limit = X86DESC_LIMIT(*pDesc);
1180	if (pDesc->Gen.u1Granularity)
1181	u32Limit = u32Limit << PAGE_SHIFT \| PAGE_OFFSET_MASK;
1182
1183	# if HC_ARCH_BITS == 64
1184	uint64_t u32Base = X86DESC64_BASE(*pDesc);
1185
1186	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1187	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1188	# else
1189	uint32_t u32Base = X86DESC_BASE(*pDesc);
1190
1191	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1192	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1193	# endif
1194	}
1195
1196	/**
1197	* Formats a full register dump.
1198	*
1199	* @param pVM The VM to operate on.
1200	* @param pCtx The context to format.
1201	*/
1202	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx)
1203	{
1204	/*
1205	* Format the flags.
1206	*/
1207	static struct
1208	{
1209	const char pszSet; const char pszClear; uint32_t fFlag;
1210	} aFlags[] =
1211	{
1212	{ "vip",NULL, X86_EFL_VIP },
1213	{ "vif",NULL, X86_EFL_VIF },
1214	{ "ac", NULL, X86_EFL_AC },
1215	{ "vm", NULL, X86_EFL_VM },
1216	{ "rf", NULL, X86_EFL_RF },
1217	{ "nt", NULL, X86_EFL_NT },
1218	{ "ov", "nv", X86_EFL_OF },
1219	{ "dn", "up", X86_EFL_DF },
1220	{ "ei", "di", X86_EFL_IF },
1221	{ "tf", NULL, X86_EFL_TF },
1222	{ "nt", "pl", X86_EFL_SF },
1223	{ "nz", "zr", X86_EFL_ZF },
1224	{ "ac", "na", X86_EFL_AF },
1225	{ "po", "pe", X86_EFL_PF },
1226	{ "cy", "nc", X86_EFL_CF },
1227	};
1228	char szEFlags[80];
1229	char *psz = szEFlags;
1230	uint32_t efl = pCtx->eflags.u32;
1231	for (unsigned i = 0; i < RT_ELEMENTS(aFlags); i++)
1232	{
1233	const char *pszAdd = aFlags[i].fFlag & efl ? aFlags[i].pszSet : aFlags[i].pszClear;
1234	if (pszAdd)
1235	{
1236	strcpy(psz, pszAdd);
1237	psz += strlen(pszAdd);
1238	*psz++ = ' ';
1239	}
1240	}
1241	psz[-1] = '\0';
1242
1243
1244	/*
1245	* Format the registers.
1246	*/
1247	if (CPUMIsGuestIn64BitCode(pVM, CPUMCTX2CORE(pCtx)))
1248	{
1249	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1250	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1251	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1252	"r14=%016RX64 r15=%016RX64\n"
1253	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1254	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1255	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1256	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1257	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1258	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1259	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1260	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1261	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1262	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1263	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1264	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1265	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1266	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1267	,
1268	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1269	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1270	pCtx->r14, pCtx->r15,
1271	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1272	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1273	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1274	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1275	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1276	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1277	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1278	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1279	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1280	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1281	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1282	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1283	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1284	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1285	}
1286	else
1287	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1288	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1289	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1290	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1291	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1292	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1293	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1294	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1295	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1296	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1297	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1298	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1299	,
1300	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1301	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1302	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr[0], pCtx->dr[1],
1303	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr[2], pCtx->dr[3],
1304	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr[4], pCtx->dr[5],
1305	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr[6], pCtx->dr[7],
1306	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0, pCtx->cr2,
1307	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3, pCtx->cr4,
1308	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1309	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1310	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1311	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1312
1313	Log(("FPU:\n"
1314	"FCW=%04x FSW=%04x FTW=%02x\n"
1315	"res1=%02x FOP=%04x FPUIP=%08x CS=%04x Rsvrd1=%04x\n"
1316	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1317	,
1318	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
1319	pCtx->fpu.huh1, pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsvrd1,
1320	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
1321	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
1322
1323
1324	Log(("MSR:\n"
1325	"EFER =%016RX64\n"
1326	"PAT =%016RX64\n"
1327	"STAR =%016RX64\n"
1328	"CSTAR =%016RX64\n"
1329	"LSTAR =%016RX64\n"
1330	"SFMASK =%016RX64\n"
1331	"KERNELGSBASE =%016RX64\n",
1332	pCtx->msrEFER,
1333	pCtx->msrPAT,
1334	pCtx->msrSTAR,
1335	pCtx->msrCSTAR,
1336	pCtx->msrLSTAR,
1337	pCtx->msrSFMASK,
1338	pCtx->msrKERNELGSBASE));
1339
1340	}
1341	#endif /* VBOX_STRICT */
1342
1343	/* Dummy callback handlers. */
1344	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
1345	{
1346	return VINF_SUCCESS;
1347	}
1348
1349	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1350	{
1351	return VINF_SUCCESS;
1352	}
1353
1354	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1355	{
1356	return VINF_SUCCESS;
1357	}
1358
1359	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1360	{
1361	return VINF_SUCCESS;
1362	}
1363
1364	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM)
1365	{
1366	return VINF_SUCCESS;
1367	}
1368
1369	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM)
1370	{
1371	return VINF_SUCCESS;
1372	}
1373
1374	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM)
1375	{
1376	return VINF_SUCCESS;
1377	}
1378
1379	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1380	{
1381	return VINF_SUCCESS;
1382	}
1383
1384	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
1385	{
1386	return VINF_SUCCESS;
1387	}
1388
1389	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1390	{
1391	return VINF_SUCCESS;
1392	}

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp@ 14875

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