HWACCMR0.cpp@ 17212

Last change on this file since 17212 was 16119, checked in by vboxsync, 16 years ago
Clear CPUM_SYNC_FPU_STATE in CPUMR0SaveGuestFPU.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 56.3 KB

Line
1	/* $Id: HWACCMR0.cpp 16119 2009-01-21 10:19:34Z vboxsync $ */
2	/** @file
3	* HWACCM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_vmx.h>
32	#include <VBox/hwacc_svm.h>
33	#include <VBox/pgm.h>
34	#include <VBox/pdm.h>
35	#include <VBox/err.h>
36	#include <VBox/log.h>
37	#include <VBox/selm.h>
38	#include <VBox/iom.h>
39	#include <iprt/param.h>
40	#include <iprt/assert.h>
41	#include <iprt/asm.h>
42	#include <iprt/string.h>
43	#include <iprt/memobj.h>
44	#include <iprt/cpuset.h>
45	#include <iprt/power.h>
46	#include "HWVMXR0.h"
47	#include "HWSVMR0.h"
48
49	/*******************************************************************************
50	* Internal Functions *
51	*******************************************************************************/
52	static DECLCALLBACK(void) hwaccmR0EnableCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hwaccmR0DisableCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
55	static int hwaccmR0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu);
56	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
57
58	/*******************************************************************************
59	* Global Variables *
60	*******************************************************************************/
61
62	static struct
63	{
64	HWACCM_CPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
65
66	/** Ring 0 handlers for VT-x and AMD-V. */
67	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu));
68	DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
69	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
70	DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
71	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
72	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
73	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
74	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
75	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
76	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVM pVM));
77
78	/** Maximum ASID allowed. */
79	uint32_t uMaxASID;
80
81	struct
82	{
83	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
84	bool fSupported;
85	/** Whether we're using SUPR0EnableVTx or not. */
86	bool fUsingSUPR0EnableVTx;
87
88	/** Host CR4 value (set by ring-0 VMX init) */
89	uint64_t hostCR4;
90
91	/** VMX MSR values */
92	struct
93	{
94	uint64_t feature_ctrl;
95	uint64_t vmx_basic_info;
96	VMX_CAPABILITY vmx_pin_ctls;
97	VMX_CAPABILITY vmx_proc_ctls;
98	VMX_CAPABILITY vmx_proc_ctls2;
99	VMX_CAPABILITY vmx_exit;
100	VMX_CAPABILITY vmx_entry;
101	uint64_t vmx_misc;
102	uint64_t vmx_cr0_fixed0;
103	uint64_t vmx_cr0_fixed1;
104	uint64_t vmx_cr4_fixed0;
105	uint64_t vmx_cr4_fixed1;
106	uint64_t vmx_vmcs_enum;
107	uint64_t vmx_eptcaps;
108	} msr;
109	/* Last instruction error */
110	uint32_t ulLastInstrError;
111	} vmx;
112	struct
113	{
114	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
115	bool fSupported;
116
117	/** SVM revision. */
118	uint32_t u32Rev;
119
120	/** SVM feature bits from cpuid 0x8000000a */
121	uint32_t u32Features;
122	} svm;
123	/** Saved error from detection */
124	int32_t lLastError;
125
126	struct
127	{
128	uint32_t u32AMDFeatureECX;
129	uint32_t u32AMDFeatureEDX;
130	} cpuid;
131
132	HWACCMSTATE enmHwAccmState;
133
134	volatile bool fSuspended;
135	} HWACCMR0Globals;
136
137
138
139	/**
140	* Does global Ring-0 HWACCM initialization.
141	*
142	* @returns VBox status code.
143	*/
144	VMMR0DECL(int) HWACCMR0Init(void)
145	{
146	int rc;
147
148	memset(&HWACCMR0Globals, 0, sizeof(HWACCMR0Globals));
149	HWACCMR0Globals.enmHwAccmState = HWACCMSTATE_UNINITIALIZED;
150	for (unsigned i = 0; i < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); i++)
151	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
152
153	/* Fill in all callbacks with placeholders. */
154	HWACCMR0Globals.pfnEnterSession = HWACCMR0DummyEnter;
155	HWACCMR0Globals.pfnLeaveSession = HWACCMR0DummyLeave;
156	HWACCMR0Globals.pfnSaveHostState = HWACCMR0DummySaveHostState;
157	HWACCMR0Globals.pfnLoadGuestState = HWACCMR0DummyLoadGuestState;
158	HWACCMR0Globals.pfnRunGuestCode = HWACCMR0DummyRunGuestCode;
159	HWACCMR0Globals.pfnEnableCpu = HWACCMR0DummyEnableCpu;
160	HWACCMR0Globals.pfnDisableCpu = HWACCMR0DummyDisableCpu;
161	HWACCMR0Globals.pfnInitVM = HWACCMR0DummyInitVM;
162	HWACCMR0Globals.pfnTermVM = HWACCMR0DummyTermVM;
163	HWACCMR0Globals.pfnSetupVM = HWACCMR0DummySetupVM;
164
165	/*
166	* Check for VT-x and AMD-V capabilities
167	*/
168	if (ASMHasCpuId())
169	{
170	uint32_t u32FeaturesECX;
171	uint32_t u32Dummy;
172	uint32_t u32FeaturesEDX;
173	uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
174
175	ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
176	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
177	/* Query AMD features. */
178	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy, &HWACCMR0Globals.cpuid.u32AMDFeatureECX, &HWACCMR0Globals.cpuid.u32AMDFeatureEDX);
179
180	if ( u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
181	&& u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
182	&& u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX
183	)
184	{
185	/*
186	* Read all VMX MSRs if VMX is available. (same goes for RDMSR/WRMSR)
187	* We also assume all VMX-enabled CPUs support fxsave/fxrstor.
188	*/
189	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
190	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
191	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
192	)
193	{
194	int aRc[RTCPUSET_MAX_CPUS];
195	RTCPUID idCpu = 0;
196
197	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
198
199	/*
200	* First try use native kernel API for controlling VT-x.
201	* (This is only supported by some Mac OS X kernels atm.)
202	*/
203	HWACCMR0Globals.lLastError = rc = SUPR0EnableVTx(true /* fEnable */);
204	if (rc != VERR_NOT_SUPPORTED)
205	{
206	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
207	HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx = true;
208	if (RT_SUCCESS(rc))
209	{
210	HWACCMR0Globals.vmx.fSupported = true;
211	rc = SUPR0EnableVTx(false /* fEnable */);
212	AssertRC(rc);
213	}
214	}
215	else
216	{
217	HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx = false;
218
219	/* We need to check if VT-x has been properly initialized on all CPUs. Some BIOSes do a lousy job. */
220	memset(aRc, 0, sizeof(aRc));
221	HWACCMR0Globals.lLastError = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
222
223	/* Check the return code of all invocations. */
224	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
225	HWACCMR0Globals.lLastError = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
226	}
227	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
228	{
229	/* Reread in case we've changed it. */
230	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
231
232	if ( (HWACCMR0Globals.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
233	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
234	{
235	RTR0MEMOBJ pScatchMemObj;
236	void *pvScatchPage;
237	RTHCPHYS pScatchPagePhys;
238
239	HWACCMR0Globals.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
240	HWACCMR0Globals.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
241	HWACCMR0Globals.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
242	HWACCMR0Globals.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
243	HWACCMR0Globals.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
244	HWACCMR0Globals.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
245	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
246	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
247	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
248	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
249	HWACCMR0Globals.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
250	/* VPID 16 bits ASID. */
251	HWACCMR0Globals.uMaxASID = 0x10000; /* exclusive */
252
253	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
254	{
255	HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
256	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT\|VMX_VMCS_CTRL_PROC_EXEC2_VPID))
257	HWACCMR0Globals.vmx.msr.vmx_eptcaps = ASMRdMsr(MSR_IA32_VMX_EPT_CAPS);
258	}
259
260	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
261	{
262	HWACCMR0Globals.vmx.hostCR4 = ASMGetCR4();
263
264	rc = RTR0MemObjAllocCont(&pScatchMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
265	if (RT_FAILURE(rc))
266	return rc;
267
268	pvScatchPage = RTR0MemObjAddress(pScatchMemObj);
269	pScatchPagePhys = RTR0MemObjGetPagePhysAddr(pScatchMemObj, 0);
270	memset(pvScatchPage, 0, PAGE_SIZE);
271
272	/* Set revision dword at the beginning of the structure. */
273	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(HWACCMR0Globals.vmx.msr.vmx_basic_info);
274
275	/* Make sure we don't get rescheduled to another cpu during this probe. */
276	RTCCUINTREG fFlags = ASMIntDisableFlags();
277
278	/*
279	* Check CR4.VMXE
280	*/
281	if (!(HWACCMR0Globals.vmx.hostCR4 & X86_CR4_VMXE))
282	{
283	/* In theory this bit could be cleared behind our back. Which would cause #UD faults when we
284	* try to execute the VMX instructions...
285	*/
286	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4 \| X86_CR4_VMXE);
287	}
288
289	/* Enter VMX Root Mode */
290	rc = VMXEnable(pScatchPagePhys);
291	if (RT_FAILURE(rc))
292	{
293	/* KVM leaves the CPU in VMX root mode. Not only is this not allowed, it will crash the host when we enter raw mode, because
294	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify this bit)
295	* (b) turning off paging causes a #GP (unavoidable when switching from long to 32 bits mode or 32 bits to PAE)
296	*
297	* They should fix their code, but until they do we simply refuse to run.
298	*/
299	HWACCMR0Globals.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
300	}
301	else
302	{
303	HWACCMR0Globals.vmx.fSupported = true;
304	VMXDisable();
305	}
306
307	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it wasn't so before (some software could incorrectly think it's in VMX mode) */
308	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4);
309	ASMSetFlags(fFlags);
310
311	RTR0MemObjFree(pScatchMemObj, false);
312	if (RT_FAILURE(HWACCMR0Globals.lLastError))
313	return HWACCMR0Globals.lLastError;
314	}
315	}
316	else
317	{
318	AssertFailed(); /* can't hit this case anymore */
319	HWACCMR0Globals.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
320	}
321	}
322	#ifdef LOG_ENABLED
323	else
324	SUPR0Printf("HWACCMR0InitCPU failed with rc=%d\n", HWACCMR0Globals.lLastError);
325	#endif
326	}
327	else
328	HWACCMR0Globals.lLastError = VERR_VMX_NO_VMX;
329	}
330	else
331	if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
332	&& u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
333	&& u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX
334	)
335	{
336	/*
337	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
338	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
339	*/
340	if ( (HWACCMR0Globals.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
341	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
342	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
343	)
344	{
345	int aRc[RTCPUSET_MAX_CPUS];
346	RTCPUID idCpu = 0;
347
348	/* We need to check if AMD-V has been properly initialized on all CPUs. Some BIOSes might do a poor job. */
349	memset(aRc, 0, sizeof(aRc));
350	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
351	AssertRC(rc);
352
353	/* Check the return code of all invocations. */
354	if (RT_SUCCESS(rc))
355	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
356
357	AssertMsgRC(rc, ("HWACCMR0InitCPU failed for cpu %d with rc=%d\n", idCpu, rc));
358
359	if (RT_SUCCESS(rc))
360	{
361	/* Query AMD features. */
362	ASMCpuId(0x8000000A, &HWACCMR0Globals.svm.u32Rev, &HWACCMR0Globals.uMaxASID, &u32Dummy, &HWACCMR0Globals.svm.u32Features);
363
364	HWACCMR0Globals.svm.fSupported = true;
365	}
366	else
367	HWACCMR0Globals.lLastError = rc;
368	}
369	else
370	HWACCMR0Globals.lLastError = VERR_SVM_NO_SVM;
371	}
372	else
373	HWACCMR0Globals.lLastError = VERR_HWACCM_UNKNOWN_CPU;
374	}
375	else
376	HWACCMR0Globals.lLastError = VERR_HWACCM_NO_CPUID;
377
378	if (HWACCMR0Globals.vmx.fSupported)
379	{
380	HWACCMR0Globals.pfnEnterSession = VMXR0Enter;
381	HWACCMR0Globals.pfnLeaveSession = VMXR0Leave;
382	HWACCMR0Globals.pfnSaveHostState = VMXR0SaveHostState;
383	HWACCMR0Globals.pfnLoadGuestState = VMXR0LoadGuestState;
384	HWACCMR0Globals.pfnRunGuestCode = VMXR0RunGuestCode;
385	HWACCMR0Globals.pfnEnableCpu = VMXR0EnableCpu;
386	HWACCMR0Globals.pfnDisableCpu = VMXR0DisableCpu;
387	HWACCMR0Globals.pfnInitVM = VMXR0InitVM;
388	HWACCMR0Globals.pfnTermVM = VMXR0TermVM;
389	HWACCMR0Globals.pfnSetupVM = VMXR0SetupVM;
390	}
391	else
392	if (HWACCMR0Globals.svm.fSupported)
393	{
394	HWACCMR0Globals.pfnEnterSession = SVMR0Enter;
395	HWACCMR0Globals.pfnLeaveSession = SVMR0Leave;
396	HWACCMR0Globals.pfnSaveHostState = SVMR0SaveHostState;
397	HWACCMR0Globals.pfnLoadGuestState = SVMR0LoadGuestState;
398	HWACCMR0Globals.pfnRunGuestCode = SVMR0RunGuestCode;
399	HWACCMR0Globals.pfnEnableCpu = SVMR0EnableCpu;
400	HWACCMR0Globals.pfnDisableCpu = SVMR0DisableCpu;
401	HWACCMR0Globals.pfnInitVM = SVMR0InitVM;
402	HWACCMR0Globals.pfnTermVM = SVMR0TermVM;
403	HWACCMR0Globals.pfnSetupVM = SVMR0SetupVM;
404	}
405
406	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
407	{
408	rc = RTPowerNotificationRegister(hwaccmR0PowerCallback, 0);
409	AssertRC(rc);
410	}
411
412	return VINF_SUCCESS;
413	}
414
415
416	/**
417	* Checks the error code array filled in for each cpu in the system.
418	*
419	* @returns VBox status code.
420	* @param paRc Error code array
421	* @param cErrorCodes Array size
422	* @param pidCpu Value of the first cpu that set an error (out)
423	*/
424	static int hwaccmR0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu)
425	{
426	int rc = VINF_SUCCESS;
427
428	Assert(cErrorCodes == RTCPUSET_MAX_CPUS);
429
430	for (unsigned i=0;i<cErrorCodes;i++)
431	{
432	if (RTMpIsCpuOnline(i))
433	{
434	if (RT_FAILURE(paRc[i]))
435	{
436	rc = paRc[i];
437	*pidCpu = i;
438	break;
439	}
440	}
441	}
442	return rc;
443	}
444
445	/**
446	* Does global Ring-0 HWACCM termination.
447	*
448	* @returns VBox status code.
449	*/
450	VMMR0DECL(int) HWACCMR0Term(void)
451	{
452	int rc;
453	if ( HWACCMR0Globals.vmx.fSupported
454	&& HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
455	{
456	rc = SUPR0EnableVTx(false /* fEnable */);
457	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); iCpu++)
458	{
459	HWACCMR0Globals.aCpuInfo[iCpu].fConfigured = false;
460	Assert(HWACCMR0Globals.aCpuInfo[iCpu].pMemObj == NIL_RTR0MEMOBJ);
461	}
462	}
463	else
464	{
465	int aRc[RTCPUSET_MAX_CPUS];
466
467	rc = RTPowerNotificationDeregister(hwaccmR0PowerCallback, 0);
468	Assert(RT_SUCCESS(rc));
469
470	memset(aRc, 0, sizeof(aRc));
471	rc = RTMpOnAll(hwaccmR0DisableCPU, aRc, NULL);
472	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
473
474	/* Free the per-cpu pages used for VT-x and AMD-V */
475	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
476	{
477	AssertMsgRC(aRc[i], ("hwaccmR0DisableCPU failed for cpu %d with rc=%d\n", i, aRc[i]));
478	if (HWACCMR0Globals.aCpuInfo[i].pMemObj != NIL_RTR0MEMOBJ)
479	{
480	RTR0MemObjFree(HWACCMR0Globals.aCpuInfo[i].pMemObj, false);
481	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
482	}
483	}
484	}
485	return rc;
486	}
487
488
489	/**
490	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
491	* is to be called on the target cpus.
492	*
493	* @param idCpu The identifier for the CPU the function is called on.
494	* @param pvUser1 The 1st user argument.
495	* @param pvUser2 The 2nd user argument.
496	*/
497	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
498	{
499	unsigned u32VendorEBX = (uintptr_t)pvUser1;
500	int paRc = (int )pvUser2;
501	uint64_t val;
502
503	#ifdef LOG_ENABLED
504	SUPR0Printf("HWACCMR0InitCPU cpu %d\n", idCpu);
505	#endif
506	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
507
508	if (u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX)
509	{
510	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
511
512	/*
513	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
514	* Once the lock bit is set, this MSR can no longer be modified.
515	*/
516	if (!(val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK)))
517	{
518	/* MSR is not yet locked; we can change it ourselves here */
519	ASMWrMsr(MSR_IA32_FEATURE_CONTROL, HWACCMR0Globals.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
520	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
521	}
522	if ( (val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
523	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
524	paRc[idCpu] = VINF_SUCCESS;
525	else
526	paRc[idCpu] = VERR_VMX_MSR_LOCKED_OR_DISABLED;
527	}
528	else
529	if (u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX)
530	{
531	/* Check if SVM is disabled */
532	val = ASMRdMsr(MSR_K8_VM_CR);
533	if (!(val & MSR_K8_VM_CR_SVM_DISABLE))
534	{
535	/* Turn on SVM in the EFER MSR. */
536	val = ASMRdMsr(MSR_K6_EFER);
537	if (!(val & MSR_K6_EFER_SVME))
538	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
539
540	/* Paranoia. */
541	val = ASMRdMsr(MSR_K6_EFER);
542	if (val & MSR_K6_EFER_SVME)
543	{
544	/* Restore previous value. */
545	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
546	paRc[idCpu] = VINF_SUCCESS;
547	}
548	else
549	paRc[idCpu] = VERR_SVM_ILLEGAL_EFER_MSR;
550	}
551	else
552	paRc[idCpu] = HWACCMR0Globals.lLastError = VERR_SVM_DISABLED;
553	}
554	else
555	AssertFailed(); /* can't happen */
556	return;
557	}
558
559
560	/**
561	* Sets up HWACCM on all cpus.
562	*
563	* @returns VBox status code.
564	* @param pVM The VM to operate on.
565	* @param enmNewHwAccmState New hwaccm state
566	*
567	*/
568	VMMR0DECL(int) HWACCMR0EnableAllCpus(PVM pVM, HWACCMSTATE enmNewHwAccmState)
569	{
570	Assert(sizeof(HWACCMR0Globals.enmHwAccmState) == sizeof(uint32_t));
571
572	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
573	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
574	return VERR_HWACCM_SUSPEND_PENDING;
575
576	if (ASMAtomicCmpXchgU32((volatile uint32_t *)&HWACCMR0Globals.enmHwAccmState, enmNewHwAccmState, HWACCMSTATE_UNINITIALIZED))
577	{
578	int rc;
579
580	/* Don't setup hwaccm as that might not work (vt-x & 64 bits raw mode) */
581	if (enmNewHwAccmState == HWACCMSTATE_DISABLED)
582	return VINF_SUCCESS;
583
584	if ( HWACCMR0Globals.vmx.fSupported
585	&& HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
586	{
587	rc = SUPR0EnableVTx(true /* fEnable */);
588	if (RT_SUCCESS(rc))
589	{
590	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); iCpu++)
591	{
592	HWACCMR0Globals.aCpuInfo[iCpu].fConfigured = true;
593	Assert(HWACCMR0Globals.aCpuInfo[iCpu].pMemObj == NIL_RTR0MEMOBJ);
594	}
595	}
596	else
597	AssertMsgFailed(("HWACCMR0EnableAllCpus/SUPR0EnableVTx: rc=%Rrc\n", rc));
598	}
599	else
600	{
601	int aRc[RTCPUSET_MAX_CPUS];
602	RTCPUID idCpu = 0;
603
604	memset(aRc, 0, sizeof(aRc));
605
606	/* Allocate one page per cpu for the global vt-x and amd-v pages */
607	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
608	{
609	Assert(!HWACCMR0Globals.aCpuInfo[i].pMemObj);
610
611	/** @todo this is rather dangerous if cpus can be taken offline; we don't care for now */
612	if (RTMpIsCpuOnline(i))
613	{
614	rc = RTR0MemObjAllocCont(&HWACCMR0Globals.aCpuInfo[i].pMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
615	AssertRC(rc);
616	if (RT_FAILURE(rc))
617	return rc;
618
619	void *pvR0 = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[i].pMemObj);
620	Assert(pvR0);
621	ASMMemZeroPage(pvR0);
622
623	#ifdef LOG_ENABLED
624	SUPR0Printf("address %x phys %x\n", pvR0, (uint32_t)RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[i].pMemObj, 0));
625	#endif
626	}
627	}
628	/* First time, so initialize each cpu/core */
629	rc = RTMpOnAll(hwaccmR0EnableCPU, (void *)pVM, aRc);
630
631	/* Check the return code of all invocations. */
632	if (RT_SUCCESS(rc))
633	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
634	AssertMsgRC(rc, ("HWACCMR0EnableAllCpus failed for cpu %d with rc=%d\n", idCpu, rc));
635	}
636
637	return rc;
638	}
639
640	if (HWACCMR0Globals.enmHwAccmState == enmNewHwAccmState)
641	return VINF_SUCCESS;
642
643	/* Request to change the mode is not allowed */
644	return VERR_ACCESS_DENIED;
645	}
646
647	/**
648	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
649	* is to be called on the target cpus.
650	*
651	* @param idCpu The identifier for the CPU the function is called on.
652	* @param pvUser1 The 1st user argument.
653	* @param pvUser2 The 2nd user argument.
654	*/
655	static DECLCALLBACK(void) hwaccmR0EnableCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
656	{
657	PVM pVM = (PVM)pvUser1; /* can be NULL! */
658	int paRc = (int )pvUser2;
659	void *pvPageCpu;
660	RTHCPHYS pPageCpuPhys;
661	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
662
663	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
664	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
665	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
666	Assert(!pCpu->fConfigured);
667	Assert(ASMAtomicReadBool(&pCpu->fInUse) == false);
668
669	pCpu->idCpu = idCpu;
670
671	/* Make sure we start with a clean TLB. */
672	pCpu->fFlushTLB = true;
673
674	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
675	pCpu->cTLBFlushes = 0;
676
677	/* Should never happen */
678	if (!pCpu->pMemObj)
679	{
680	AssertFailed();
681	paRc[idCpu] = VERR_INTERNAL_ERROR;
682	return;
683	}
684
685	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
686	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
687
688	paRc[idCpu] = HWACCMR0Globals.pfnEnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
689	AssertRC(paRc[idCpu]);
690	if (RT_SUCCESS(paRc[idCpu]))
691	pCpu->fConfigured = true;
692
693	return;
694	}
695
696	/**
697	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
698	* is to be called on the target cpus.
699	*
700	* @param idCpu The identifier for the CPU the function is called on.
701	* @param pvUser1 The 1st user argument.
702	* @param pvUser2 The 2nd user argument.
703	*/
704	static DECLCALLBACK(void) hwaccmR0DisableCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
705	{
706	void *pvPageCpu;
707	RTHCPHYS pPageCpuPhys;
708	int paRc = (int )pvUser1;
709	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
710
711	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
712	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
713	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
714	Assert(ASMAtomicReadBool(&pCpu->fInUse) == false);
715
716	if (!pCpu->pMemObj)
717	return;
718
719	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
720	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
721
722	if (pCpu->fConfigured)
723	{
724	paRc[idCpu] = HWACCMR0Globals.pfnDisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
725	AssertRC(paRc[idCpu]);
726	pCpu->fConfigured = false;
727	}
728	else
729	paRc[idCpu] = VINF_SUCCESS; /* nothing to do */
730
731	pCpu->uCurrentASID = 0;
732	return;
733	}
734
735	/**
736	* Called whenever a system power state change occurs.
737	*
738	* @param enmEvent Power event
739	* @param pvUser User argument
740	*/
741	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
742	{
743	NOREF(pvUser);
744	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
745
746	#ifdef LOG_ENABLED
747	if (enmEvent == RTPOWEREVENT_SUSPEND)
748	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
749	else
750	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_RESUME\n");
751	#endif
752
753	if (enmEvent == RTPOWEREVENT_SUSPEND)
754	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, true);
755
756	if (HWACCMR0Globals.enmHwAccmState == HWACCMSTATE_ENABLED)
757	{
758	int aRc[RTCPUSET_MAX_CPUS];
759	int rc;
760	RTCPUID idCpu;
761
762	memset(aRc, 0, sizeof(aRc));
763	if (enmEvent == RTPOWEREVENT_SUSPEND)
764	{
765	/* Turn off VT-x or AMD-V on all CPUs. */
766	rc = RTMpOnAll(hwaccmR0DisableCPU, aRc, NULL);
767	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
768	}
769	else
770	{
771	/* Reinit the CPUs from scratch as the suspend state has messed with the MSRs. */
772	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)((HWACCMR0Globals.vmx.fSupported) ? X86_CPUID_VENDOR_INTEL_EBX : X86_CPUID_VENDOR_AMD_EBX), aRc);
773	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
774
775	if (RT_SUCCESS(rc))
776	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
777	#ifdef LOG_ENABLED
778	if (RT_FAILURE(rc))
779	SUPR0Printf("hwaccmR0PowerCallback HWACCMR0InitCPU failed with %d\n", rc);
780	#endif
781
782	/* Turn VT-x or AMD-V back on on all CPUs. */
783	rc = RTMpOnAll(hwaccmR0EnableCPU, NULL, aRc);
784	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
785	}
786	}
787	if (enmEvent == RTPOWEREVENT_RESUME)
788	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, false);
789	}
790
791
792	/**
793	* Does Ring-0 per VM HWACCM initialization.
794	*
795	* This is mainly to check that the Host CPU mode is compatible
796	* with VMX.
797	*
798	* @returns VBox status code.
799	* @param pVM The VM to operate on.
800	*/
801	VMMR0DECL(int) HWACCMR0InitVM(PVM pVM)
802	{
803	int rc;
804
805	AssertReturn(pVM, VERR_INVALID_PARAMETER);
806
807	#ifdef LOG_ENABLED
808	SUPR0Printf("HWACCMR0InitVM: %p\n", pVM);
809	#endif
810
811	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
812	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
813	return VERR_HWACCM_SUSPEND_PENDING;
814
815	pVM->hwaccm.s.vmx.fSupported = HWACCMR0Globals.vmx.fSupported;
816	pVM->hwaccm.s.svm.fSupported = HWACCMR0Globals.svm.fSupported;
817
818	pVM->hwaccm.s.vmx.msr.feature_ctrl = HWACCMR0Globals.vmx.msr.feature_ctrl;
819	pVM->hwaccm.s.vmx.hostCR4 = HWACCMR0Globals.vmx.hostCR4;
820	pVM->hwaccm.s.vmx.msr.vmx_basic_info = HWACCMR0Globals.vmx.msr.vmx_basic_info;
821	pVM->hwaccm.s.vmx.msr.vmx_pin_ctls = HWACCMR0Globals.vmx.msr.vmx_pin_ctls;
822	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls = HWACCMR0Globals.vmx.msr.vmx_proc_ctls;
823	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2 = HWACCMR0Globals.vmx.msr.vmx_proc_ctls2;
824	pVM->hwaccm.s.vmx.msr.vmx_exit = HWACCMR0Globals.vmx.msr.vmx_exit;
825	pVM->hwaccm.s.vmx.msr.vmx_entry = HWACCMR0Globals.vmx.msr.vmx_entry;
826	pVM->hwaccm.s.vmx.msr.vmx_misc = HWACCMR0Globals.vmx.msr.vmx_misc;
827	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0;
828	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1;
829	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0;
830	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1;
831	pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum = HWACCMR0Globals.vmx.msr.vmx_vmcs_enum;
832	pVM->hwaccm.s.vmx.msr.vmx_eptcaps = HWACCMR0Globals.vmx.msr.vmx_eptcaps;
833	pVM->hwaccm.s.svm.u32Rev = HWACCMR0Globals.svm.u32Rev;
834	pVM->hwaccm.s.svm.u32Features = HWACCMR0Globals.svm.u32Features;
835	pVM->hwaccm.s.cpuid.u32AMDFeatureECX = HWACCMR0Globals.cpuid.u32AMDFeatureECX;
836	pVM->hwaccm.s.cpuid.u32AMDFeatureEDX = HWACCMR0Globals.cpuid.u32AMDFeatureEDX;
837	pVM->hwaccm.s.lLastError = HWACCMR0Globals.lLastError;
838
839	pVM->hwaccm.s.uMaxASID = HWACCMR0Globals.uMaxASID;
840
841	for (unsigned i=0;i<pVM->cCPUs;i++)
842	{
843	PVMCPU pVCpu = &pVM->aCpus[i];
844
845	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
846
847	/* Invalidate the last cpu we were running on. */
848	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
849
850	/* we'll aways increment this the first time (host uses ASID 0) */
851	pVCpu->hwaccm.s.uCurrentASID = 0;
852	}
853
854	RTCCUINTREG fFlags = ASMIntDisableFlags();
855	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
856
857	/* @note Not correct as we can be rescheduled to a different cpu, but the fInUse case is mostly for debugging. */
858	ASMAtomicWriteBool(&pCpu->fInUse, true);
859	ASMSetFlags(fFlags);
860
861	/* Init a VT-x or AMD-V VM. */
862	rc = HWACCMR0Globals.pfnInitVM(pVM);
863
864	ASMAtomicWriteBool(&pCpu->fInUse, false);
865	return rc;
866	}
867
868
869	/**
870	* Does Ring-0 per VM HWACCM termination.
871	*
872	* @returns VBox status code.
873	* @param pVM The VM to operate on.
874	*/
875	VMMR0DECL(int) HWACCMR0TermVM(PVM pVM)
876	{
877	int rc;
878
879	AssertReturn(pVM, VERR_INVALID_PARAMETER);
880
881	#ifdef LOG_ENABLED
882	SUPR0Printf("HWACCMR0TermVM: %p\n", pVM);
883	#endif
884
885	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
886	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
887
888	/* @note Not correct as we can be rescheduled to a different cpu, but the fInUse case is mostly for debugging. */
889	RTCCUINTREG fFlags = ASMIntDisableFlags();
890	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
891
892	ASMAtomicWriteBool(&pCpu->fInUse, true);
893	ASMSetFlags(fFlags);
894
895	/* Terminate a VT-x or AMD-V VM. */
896	rc = HWACCMR0Globals.pfnTermVM(pVM);
897
898	ASMAtomicWriteBool(&pCpu->fInUse, false);
899	return rc;
900	}
901
902
903	/**
904	* Sets up a VT-x or AMD-V session
905	*
906	* @returns VBox status code.
907	* @param pVM The VM to operate on.
908	*/
909	VMMR0DECL(int) HWACCMR0SetupVM(PVM pVM)
910	{
911	int rc;
912	RTCPUID idCpu = RTMpCpuId();
913	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
914
915	AssertReturn(pVM, VERR_INVALID_PARAMETER);
916
917	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
918	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
919
920	#ifdef LOG_ENABLED
921	SUPR0Printf("HWACCMR0SetupVM: %p\n", pVM);
922	#endif
923
924	ASMAtomicWriteBool(&pCpu->fInUse, true);
925
926	for (unsigned i=0;i<pVM->cCPUs;i++)
927	{
928	/* On first entry we'll sync everything. */
929	pVM->aCpus[i].hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
930	}
931
932	/* Setup VT-x or AMD-V. */
933	rc = HWACCMR0Globals.pfnSetupVM(pVM);
934
935	ASMAtomicWriteBool(&pCpu->fInUse, false);
936
937	return rc;
938	}
939
940
941	/**
942	* Enters the VT-x or AMD-V session
943	*
944	* @returns VBox status code.
945	* @param pVM The VM to operate on.
946	* @param pVCpu VMCPUD id.
947	*/
948	VMMR0DECL(int) HWACCMR0Enter(PVM pVM, PVMCPU pVCpu)
949	{
950	PCPUMCTX pCtx;
951	int rc;
952	RTCPUID idCpu = RTMpCpuId();
953	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
954
955	/* Make sure we can't enter a session after we've disabled hwaccm in preparation of a suspend. */
956	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
957	ASMAtomicWriteBool(&pCpu->fInUse, true);
958
959	pCtx = CPUMQueryGuestCtxPtrEx(pVM, pVCpu);
960
961	/* Always load the guest's FPU/XMM state on-demand. */
962	CPUMDeactivateGuestFPUState(pVM);
963
964	/* Always load the guest's debug state on-demand. */
965	CPUMDeactivateGuestDebugState(pVM);
966
967	/* Always reload the host context and the guest's CR0 register. (!!!!) */
968	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0 \| HWACCM_CHANGED_HOST_CONTEXT;
969
970	/* Setup the register and mask according to the current execution mode. */
971	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
972	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFFFFFFFFFF);
973	else
974	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFF);
975
976	rc = HWACCMR0Globals.pfnEnterSession(pVM, pVCpu, pCpu);
977	AssertRC(rc);
978	/* We must save the host context here (VT-x) as we might be rescheduled on a different cpu after a long jump back to ring 3. */
979	rc \|= HWACCMR0Globals.pfnSaveHostState(pVM, pVCpu);
980	AssertRC(rc);
981	rc \|= HWACCMR0Globals.pfnLoadGuestState(pVM, pVCpu, pCtx);
982	AssertRC(rc);
983
984	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
985	if (RT_SUCCESS(rc))
986	{
987	AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == NIL_RTCPUID, ("%d", (int)pVCpu->hwaccm.s.idEnteredCpu));
988	pVCpu->hwaccm.s.idEnteredCpu = idCpu;
989
990	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
991	PGMDynMapMigrateAutoSet(pVCpu);
992	#endif
993	}
994	return rc;
995	}
996
997
998	/**
999	* Leaves the VT-x or AMD-V session
1000	*
1001	* @returns VBox status code.
1002	* @param pVM The VM to operate on.
1003	* @param pVCpu VMCPUD id.
1004	*/
1005	VMMR0DECL(int) HWACCMR0Leave(PVM pVM, PVMCPU pVCpu)
1006	{
1007	PCPUMCTX pCtx;
1008	int rc;
1009	RTCPUID idCpu = RTMpCpuId();
1010	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1011
1012	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1013
1014	pCtx = CPUMQueryGuestCtxPtrEx(pVM, pVCpu);
1015
1016	/* Note: It's rather tricky with longjmps done by e.g. Log statements or the page fault handler.
1017	* We must restore the host FPU here to make absolutely sure we don't leave the guest FPU state active
1018	* or trash somebody else's FPU state.
1019	*/
1020	/* Save the guest FPU and XMM state if necessary. */
1021	if (CPUMIsGuestFPUStateActive(pVCpu))
1022	{
1023	Log2(("CPUMR0SaveGuestFPU\n"));
1024	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
1025
1026	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1027	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1028	}
1029
1030	rc = HWACCMR0Globals.pfnLeaveSession(pVM, pVCpu, pCtx);
1031
1032	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1033	#ifdef RT_STRICT
1034	if (RT_UNLIKELY( pVCpu->hwaccm.s.idEnteredCpu != idCpu
1035	&& RT_FAILURE(rc)))
1036	{
1037	AssertMsgFailed(("Owner is %d, I'm %d", (int)pVCpu->hwaccm.s.idEnteredCpu, (int)idCpu));
1038	rc = VERR_INTERNAL_ERROR;
1039	}
1040	#endif
1041	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1042
1043	ASMAtomicWriteBool(&pCpu->fInUse, false);
1044	return rc;
1045	}
1046
1047	/**
1048	* Runs guest code in a hardware accelerated VM.
1049	*
1050	* @returns VBox status code.
1051	* @param pVM The VM to operate on.
1052	* @param pVCpu VMCPUD id.
1053	*/
1054	VMMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1055	{
1056	CPUMCTX *pCtx;
1057	RTCPUID idCpu = RTMpCpuId(); NOREF(idCpu);
1058	int rc;
1059	#ifdef VBOX_STRICT
1060	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1061	#endif
1062
1063	Assert(!VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL));
1064	Assert(HWACCMR0Globals.aCpuInfo[idCpu].fConfigured);
1065	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1066	Assert(ASMAtomicReadBool(&pCpu->fInUse) == true);
1067
1068	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1069	PGMDynMapStartAutoSet(pVCpu);
1070	#endif
1071
1072	pCtx = CPUMQueryGuestCtxPtrEx(pVM, pVCpu);
1073
1074	rc = HWACCMR0Globals.pfnRunGuestCode(pVM, pVCpu, pCtx);
1075
1076	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1077	PGMDynMapReleaseAutoSet(pVCpu);
1078	#endif
1079	return rc;
1080	}
1081
1082
1083	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1084	/**
1085	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1086	*
1087	* @returns VBox status code.
1088	* @param pVM VM handle.
1089	* @param pVCpu VMCPU handle.
1090	* @param pCtx CPU context
1091	*/
1092	VMMR0DECL(int) HWACCMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1093	{
1094	if (pVM->hwaccm.s.vmx.fSupported)
1095	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1096
1097	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1098	}
1099
1100	/**
1101	* Save guest debug state (64 bits guest mode & 32 bits host only)
1102	*
1103	* @returns VBox status code.
1104	* @param pVM VM handle.
1105	* @param pVCpu VMCPU handle.
1106	* @param pCtx CPU context
1107	*/
1108	VMMR0DECL(int) HWACCMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1109	{
1110	if (pVM->hwaccm.s.vmx.fSupported)
1111	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1112
1113	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1114	}
1115
1116	/**
1117	* Test the 32->64 bits switcher
1118	*
1119	* @returns VBox status code.
1120	* @param pVM VM handle.
1121	*/
1122	VMMR0DECL(int) HWACCMR0TestSwitcher3264(PVM pVM)
1123	{
1124	PVMCPU pVCpu = &pVM->aCpus[0];
1125	CPUMCTX *pCtx;
1126	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1127	int rc;
1128
1129	pCtx = CPUMQueryGuestCtxPtrEx(pVM, pVCpu);
1130
1131	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1132	if (pVM->hwaccm.s.vmx.fSupported)
1133	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1134	else
1135	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1136	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1137	return rc;
1138	}
1139
1140	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1141
1142	/**
1143	* Returns suspend status of the host
1144	*
1145	* @returns Suspend pending or not
1146	*/
1147	VMMR0DECL(bool) HWACCMR0SuspendPending()
1148	{
1149	return ASMAtomicReadBool(&HWACCMR0Globals.fSuspended);
1150	}
1151
1152	/**
1153	* Returns the cpu structure for the current cpu.
1154	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1155	*
1156	* @returns cpu structure pointer
1157	*/
1158	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu()
1159	{
1160	RTCPUID idCpu = RTMpCpuId();
1161
1162	return &HWACCMR0Globals.aCpuInfo[idCpu];
1163	}
1164
1165	/**
1166	* Returns the cpu structure for the current cpu.
1167	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1168	*
1169	* @returns cpu structure pointer
1170	* @param idCpu id of the VCPU
1171	*/
1172	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu)
1173	{
1174	return &HWACCMR0Globals.aCpuInfo[idCpu];
1175	}
1176
1177	#ifdef VBOX_STRICT
1178	# include <iprt/string.h>
1179	/**
1180	* Dumps a descriptor.
1181	*
1182	* @param pDesc Descriptor to dump.
1183	* @param Sel Selector number.
1184	* @param pszMsg Message to prepend the log entry with.
1185	*/
1186	VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1187	{
1188	/*
1189	* Make variable description string.
1190	*/
1191	static struct
1192	{
1193	unsigned cch;
1194	const char *psz;
1195	} const aTypes[32] =
1196	{
1197	# define STRENTRY(str) { sizeof(str) - 1, str }
1198
1199	/* system */
1200	# if HC_ARCH_BITS == 64
1201	STRENTRY("Reserved0 "), /* 0x00 */
1202	STRENTRY("Reserved1 "), /* 0x01 */
1203	STRENTRY("LDT "), /* 0x02 */
1204	STRENTRY("Reserved3 "), /* 0x03 */
1205	STRENTRY("Reserved4 "), /* 0x04 */
1206	STRENTRY("Reserved5 "), /* 0x05 */
1207	STRENTRY("Reserved6 "), /* 0x06 */
1208	STRENTRY("Reserved7 "), /* 0x07 */
1209	STRENTRY("Reserved8 "), /* 0x08 */
1210	STRENTRY("TSS64Avail "), /* 0x09 */
1211	STRENTRY("ReservedA "), /* 0x0a */
1212	STRENTRY("TSS64Busy "), /* 0x0b */
1213	STRENTRY("Call64 "), /* 0x0c */
1214	STRENTRY("ReservedD "), /* 0x0d */
1215	STRENTRY("Int64 "), /* 0x0e */
1216	STRENTRY("Trap64 "), /* 0x0f */
1217	# else
1218	STRENTRY("Reserved0 "), /* 0x00 */
1219	STRENTRY("TSS16Avail "), /* 0x01 */
1220	STRENTRY("LDT "), /* 0x02 */
1221	STRENTRY("TSS16Busy "), /* 0x03 */
1222	STRENTRY("Call16 "), /* 0x04 */
1223	STRENTRY("Task "), /* 0x05 */
1224	STRENTRY("Int16 "), /* 0x06 */
1225	STRENTRY("Trap16 "), /* 0x07 */
1226	STRENTRY("Reserved8 "), /* 0x08 */
1227	STRENTRY("TSS32Avail "), /* 0x09 */
1228	STRENTRY("ReservedA "), /* 0x0a */
1229	STRENTRY("TSS32Busy "), /* 0x0b */
1230	STRENTRY("Call32 "), /* 0x0c */
1231	STRENTRY("ReservedD "), /* 0x0d */
1232	STRENTRY("Int32 "), /* 0x0e */
1233	STRENTRY("Trap32 "), /* 0x0f */
1234	# endif
1235	/* non system */
1236	STRENTRY("DataRO "), /* 0x10 */
1237	STRENTRY("DataRO Accessed "), /* 0x11 */
1238	STRENTRY("DataRW "), /* 0x12 */
1239	STRENTRY("DataRW Accessed "), /* 0x13 */
1240	STRENTRY("DataDownRO "), /* 0x14 */
1241	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1242	STRENTRY("DataDownRW "), /* 0x16 */
1243	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1244	STRENTRY("CodeEO "), /* 0x18 */
1245	STRENTRY("CodeEO Accessed "), /* 0x19 */
1246	STRENTRY("CodeER "), /* 0x1a */
1247	STRENTRY("CodeER Accessed "), /* 0x1b */
1248	STRENTRY("CodeConfEO "), /* 0x1c */
1249	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1250	STRENTRY("CodeConfER "), /* 0x1e */
1251	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1252	# undef SYSENTRY
1253	};
1254	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1255	char szMsg[128];
1256	char *psz = &szMsg[0];
1257	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1258	memcpy(psz, aTypes[i].psz, aTypes[i].cch);
1259	psz += aTypes[i].cch;
1260
1261	if (pDesc->Gen.u1Present)
1262	ADD_STR(psz, "Present ");
1263	else
1264	ADD_STR(psz, "Not-Present ");
1265	# if HC_ARCH_BITS == 64
1266	if (pDesc->Gen.u1Long)
1267	ADD_STR(psz, "64-bit ");
1268	else
1269	ADD_STR(psz, "Comp ");
1270	# else
1271	if (pDesc->Gen.u1Granularity)
1272	ADD_STR(psz, "Page ");
1273	if (pDesc->Gen.u1DefBig)
1274	ADD_STR(psz, "32-bit ");
1275	else
1276	ADD_STR(psz, "16-bit ");
1277	# endif
1278	# undef ADD_STR
1279	*psz = '\0';
1280
1281	/*
1282	* Limit and Base and format the output.
1283	*/
1284	uint32_t u32Limit = X86DESC_LIMIT(*pDesc);
1285	if (pDesc->Gen.u1Granularity)
1286	u32Limit = u32Limit << PAGE_SHIFT \| PAGE_OFFSET_MASK;
1287
1288	# if HC_ARCH_BITS == 64
1289	uint64_t u32Base = X86DESC64_BASE(*pDesc);
1290
1291	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1292	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1293	# else
1294	uint32_t u32Base = X86DESC_BASE(*pDesc);
1295
1296	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1297	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1298	# endif
1299	}
1300
1301	/**
1302	* Formats a full register dump.
1303	*
1304	* @param pVM The VM to operate on.
1305	* @param pCtx The context to format.
1306	*/
1307	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx)
1308	{
1309	/*
1310	* Format the flags.
1311	*/
1312	static struct
1313	{
1314	const char pszSet; const char pszClear; uint32_t fFlag;
1315	} aFlags[] =
1316	{
1317	{ "vip",NULL, X86_EFL_VIP },
1318	{ "vif",NULL, X86_EFL_VIF },
1319	{ "ac", NULL, X86_EFL_AC },
1320	{ "vm", NULL, X86_EFL_VM },
1321	{ "rf", NULL, X86_EFL_RF },
1322	{ "nt", NULL, X86_EFL_NT },
1323	{ "ov", "nv", X86_EFL_OF },
1324	{ "dn", "up", X86_EFL_DF },
1325	{ "ei", "di", X86_EFL_IF },
1326	{ "tf", NULL, X86_EFL_TF },
1327	{ "nt", "pl", X86_EFL_SF },
1328	{ "nz", "zr", X86_EFL_ZF },
1329	{ "ac", "na", X86_EFL_AF },
1330	{ "po", "pe", X86_EFL_PF },
1331	{ "cy", "nc", X86_EFL_CF },
1332	};
1333	char szEFlags[80];
1334	char *psz = szEFlags;
1335	uint32_t efl = pCtx->eflags.u32;
1336	for (unsigned i = 0; i < RT_ELEMENTS(aFlags); i++)
1337	{
1338	const char *pszAdd = aFlags[i].fFlag & efl ? aFlags[i].pszSet : aFlags[i].pszClear;
1339	if (pszAdd)
1340	{
1341	strcpy(psz, pszAdd);
1342	psz += strlen(pszAdd);
1343	*psz++ = ' ';
1344	}
1345	}
1346	psz[-1] = '\0';
1347
1348
1349	/*
1350	* Format the registers.
1351	*/
1352	if (CPUMIsGuestIn64BitCode(pVM, CPUMCTX2CORE(pCtx)))
1353	{
1354	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1355	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1356	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1357	"r14=%016RX64 r15=%016RX64\n"
1358	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1359	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1360	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1361	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1362	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1363	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1364	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1365	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1366	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1367	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1368	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1369	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1370	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1371	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1372	,
1373	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1374	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1375	pCtx->r14, pCtx->r15,
1376	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1377	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1378	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1379	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1380	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1381	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1382	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1383	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1384	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1385	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1386	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1387	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1388	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1389	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1390	}
1391	else
1392	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1393	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1394	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1395	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1396	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1397	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1398	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1399	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1400	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1401	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1402	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1403	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1404	,
1405	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1406	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1407	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr[0], pCtx->dr[1],
1408	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr[2], pCtx->dr[3],
1409	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr[4], pCtx->dr[5],
1410	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr[6], pCtx->dr[7],
1411	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0, pCtx->cr2,
1412	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3, pCtx->cr4,
1413	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1414	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1415	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1416	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1417
1418	Log(("FPU:\n"
1419	"FCW=%04x FSW=%04x FTW=%02x\n"
1420	"res1=%02x FOP=%04x FPUIP=%08x CS=%04x Rsvrd1=%04x\n"
1421	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1422	,
1423	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
1424	pCtx->fpu.huh1, pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsvrd1,
1425	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
1426	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
1427
1428
1429	Log(("MSR:\n"
1430	"EFER =%016RX64\n"
1431	"PAT =%016RX64\n"
1432	"STAR =%016RX64\n"
1433	"CSTAR =%016RX64\n"
1434	"LSTAR =%016RX64\n"
1435	"SFMASK =%016RX64\n"
1436	"KERNELGSBASE =%016RX64\n",
1437	pCtx->msrEFER,
1438	pCtx->msrPAT,
1439	pCtx->msrSTAR,
1440	pCtx->msrCSTAR,
1441	pCtx->msrLSTAR,
1442	pCtx->msrSFMASK,
1443	pCtx->msrKERNELGSBASE));
1444
1445	}
1446	#endif /* VBOX_STRICT */
1447
1448	/* Dummy callback handlers. */
1449	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
1450	{
1451	return VINF_SUCCESS;
1452	}
1453
1454	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1455	{
1456	return VINF_SUCCESS;
1457	}
1458
1459	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1460	{
1461	return VINF_SUCCESS;
1462	}
1463
1464	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1465	{
1466	return VINF_SUCCESS;
1467	}
1468
1469	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM)
1470	{
1471	return VINF_SUCCESS;
1472	}
1473
1474	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM)
1475	{
1476	return VINF_SUCCESS;
1477	}
1478
1479	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM)
1480	{
1481	return VINF_SUCCESS;
1482	}
1483
1484	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1485	{
1486	return VINF_SUCCESS;
1487	}
1488
1489	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
1490	{
1491	return VINF_SUCCESS;
1492	}
1493
1494	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1495	{
1496	return VINF_SUCCESS;
1497	}

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp@ 17212

Download in other formats: