HWACCMR0.cpp@ 17327

Last change on this file since 17327 was 17246, checked in by vboxsync, 16 years ago
Allow mixing of VT-x and software virtualization. (untested so far)
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 58.2 KB

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1	/* $Id: HWACCMR0.cpp 17246 2009-03-02 12:31:50Z vboxsync $ */
2	/** @file
3	* HWACCM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_vmx.h>
32	#include <VBox/hwacc_svm.h>
33	#include <VBox/pgm.h>
34	#include <VBox/pdm.h>
35	#include <VBox/err.h>
36	#include <VBox/log.h>
37	#include <VBox/selm.h>
38	#include <VBox/iom.h>
39	#include <iprt/param.h>
40	#include <iprt/assert.h>
41	#include <iprt/asm.h>
42	#include <iprt/string.h>
43	#include <iprt/memobj.h>
44	#include <iprt/cpuset.h>
45	#include <iprt/power.h>
46	#include "HWVMXR0.h"
47	#include "HWSVMR0.h"
48
49	/*******************************************************************************
50	* Internal Functions *
51	*******************************************************************************/
52	static DECLCALLBACK(void) hwaccmR0EnableCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hwaccmR0DisableCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
55	static int hwaccmR0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu);
56	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
57
58	/*******************************************************************************
59	* Global Variables *
60	*******************************************************************************/
61
62	static struct
63	{
64	HWACCM_CPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
65
66	/** Ring 0 handlers for VT-x and AMD-V. */
67	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu));
68	DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
69	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
70	DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
71	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
72	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
73	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
74	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
75	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
76	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVM pVM));
77
78	/** Maximum ASID allowed. */
79	uint32_t uMaxASID;
80
81	struct
82	{
83	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
84	bool fSupported;
85	/** Whether we're using SUPR0EnableVTx or not. */
86	bool fUsingSUPR0EnableVTx;
87
88	/** Host CR4 value (set by ring-0 VMX init) */
89	uint64_t hostCR4;
90
91	/** VMX MSR values */
92	struct
93	{
94	uint64_t feature_ctrl;
95	uint64_t vmx_basic_info;
96	VMX_CAPABILITY vmx_pin_ctls;
97	VMX_CAPABILITY vmx_proc_ctls;
98	VMX_CAPABILITY vmx_proc_ctls2;
99	VMX_CAPABILITY vmx_exit;
100	VMX_CAPABILITY vmx_entry;
101	uint64_t vmx_misc;
102	uint64_t vmx_cr0_fixed0;
103	uint64_t vmx_cr0_fixed1;
104	uint64_t vmx_cr4_fixed0;
105	uint64_t vmx_cr4_fixed1;
106	uint64_t vmx_vmcs_enum;
107	uint64_t vmx_eptcaps;
108	} msr;
109	/* Last instruction error */
110	uint32_t ulLastInstrError;
111	} vmx;
112	struct
113	{
114	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
115	bool fSupported;
116
117	/** SVM revision. */
118	uint32_t u32Rev;
119
120	/** SVM feature bits from cpuid 0x8000000a */
121	uint32_t u32Features;
122	} svm;
123	/** Saved error from detection */
124	int32_t lLastError;
125
126	struct
127	{
128	uint32_t u32AMDFeatureECX;
129	uint32_t u32AMDFeatureEDX;
130	} cpuid;
131
132	HWACCMSTATE enmHwAccmState;
133
134	volatile bool fSuspended;
135	} HWACCMR0Globals;
136
137
138
139	/**
140	* Does global Ring-0 HWACCM initialization.
141	*
142	* @returns VBox status code.
143	*/
144	VMMR0DECL(int) HWACCMR0Init(void)
145	{
146	int rc;
147
148	memset(&HWACCMR0Globals, 0, sizeof(HWACCMR0Globals));
149	HWACCMR0Globals.enmHwAccmState = HWACCMSTATE_UNINITIALIZED;
150	for (unsigned i = 0; i < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); i++)
151	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
152
153	/* Fill in all callbacks with placeholders. */
154	HWACCMR0Globals.pfnEnterSession = HWACCMR0DummyEnter;
155	HWACCMR0Globals.pfnLeaveSession = HWACCMR0DummyLeave;
156	HWACCMR0Globals.pfnSaveHostState = HWACCMR0DummySaveHostState;
157	HWACCMR0Globals.pfnLoadGuestState = HWACCMR0DummyLoadGuestState;
158	HWACCMR0Globals.pfnRunGuestCode = HWACCMR0DummyRunGuestCode;
159	HWACCMR0Globals.pfnEnableCpu = HWACCMR0DummyEnableCpu;
160	HWACCMR0Globals.pfnDisableCpu = HWACCMR0DummyDisableCpu;
161	HWACCMR0Globals.pfnInitVM = HWACCMR0DummyInitVM;
162	HWACCMR0Globals.pfnTermVM = HWACCMR0DummyTermVM;
163	HWACCMR0Globals.pfnSetupVM = HWACCMR0DummySetupVM;
164
165	/*
166	* Check for VT-x and AMD-V capabilities
167	*/
168	if (ASMHasCpuId())
169	{
170	uint32_t u32FeaturesECX;
171	uint32_t u32Dummy;
172	uint32_t u32FeaturesEDX;
173	uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
174
175	ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
176	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
177	/* Query AMD features. */
178	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy, &HWACCMR0Globals.cpuid.u32AMDFeatureECX, &HWACCMR0Globals.cpuid.u32AMDFeatureEDX);
179
180	if ( u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
181	&& u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
182	&& u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX
183	)
184	{
185	/*
186	* Read all VMX MSRs if VMX is available. (same goes for RDMSR/WRMSR)
187	* We also assume all VMX-enabled CPUs support fxsave/fxrstor.
188	*/
189	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
190	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
191	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
192	)
193	{
194	int aRc[RTCPUSET_MAX_CPUS];
195	RTCPUID idCpu = 0;
196
197	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
198
199	/*
200	* First try use native kernel API for controlling VT-x.
201	* (This is only supported by some Mac OS X kernels atm.)
202	*/
203	HWACCMR0Globals.lLastError = rc = SUPR0EnableVTx(true /* fEnable */);
204	if (rc != VERR_NOT_SUPPORTED)
205	{
206	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
207	HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx = true;
208	if (RT_SUCCESS(rc))
209	{
210	HWACCMR0Globals.vmx.fSupported = true;
211	rc = SUPR0EnableVTx(false /* fEnable */);
212	AssertRC(rc);
213	}
214	}
215	else
216	{
217	HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx = false;
218
219	/* We need to check if VT-x has been properly initialized on all CPUs. Some BIOSes do a lousy job. */
220	memset(aRc, 0, sizeof(aRc));
221	HWACCMR0Globals.lLastError = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
222
223	/* Check the return code of all invocations. */
224	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
225	HWACCMR0Globals.lLastError = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
226	}
227	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
228	{
229	/* Reread in case we've changed it. */
230	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
231
232	if ( (HWACCMR0Globals.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
233	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
234	{
235	RTR0MEMOBJ pScatchMemObj;
236	void *pvScatchPage;
237	RTHCPHYS pScatchPagePhys;
238
239	HWACCMR0Globals.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
240	HWACCMR0Globals.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
241	HWACCMR0Globals.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
242	HWACCMR0Globals.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
243	HWACCMR0Globals.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
244	HWACCMR0Globals.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
245	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
246	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
247	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
248	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
249	HWACCMR0Globals.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
250	/* VPID 16 bits ASID. */
251	HWACCMR0Globals.uMaxASID = 0x10000; /* exclusive */
252
253	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
254	{
255	HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
256	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT\|VMX_VMCS_CTRL_PROC_EXEC2_VPID))
257	HWACCMR0Globals.vmx.msr.vmx_eptcaps = ASMRdMsr(MSR_IA32_VMX_EPT_CAPS);
258	}
259
260	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
261	{
262	HWACCMR0Globals.vmx.hostCR4 = ASMGetCR4();
263
264	rc = RTR0MemObjAllocCont(&pScatchMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
265	if (RT_FAILURE(rc))
266	return rc;
267
268	pvScatchPage = RTR0MemObjAddress(pScatchMemObj);
269	pScatchPagePhys = RTR0MemObjGetPagePhysAddr(pScatchMemObj, 0);
270	memset(pvScatchPage, 0, PAGE_SIZE);
271
272	/* Set revision dword at the beginning of the structure. */
273	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(HWACCMR0Globals.vmx.msr.vmx_basic_info);
274
275	/* Make sure we don't get rescheduled to another cpu during this probe. */
276	RTCCUINTREG fFlags = ASMIntDisableFlags();
277
278	/*
279	* Check CR4.VMXE
280	*/
281	if (!(HWACCMR0Globals.vmx.hostCR4 & X86_CR4_VMXE))
282	{
283	/* In theory this bit could be cleared behind our back. Which would cause #UD faults when we
284	* try to execute the VMX instructions...
285	*/
286	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4 \| X86_CR4_VMXE);
287	}
288
289	/* Enter VMX Root Mode */
290	rc = VMXEnable(pScatchPagePhys);
291	if (RT_FAILURE(rc))
292	{
293	/* KVM leaves the CPU in VMX root mode. Not only is this not allowed, it will crash the host when we enter raw mode, because
294	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify this bit)
295	* (b) turning off paging causes a #GP (unavoidable when switching from long to 32 bits mode or 32 bits to PAE)
296	*
297	* They should fix their code, but until they do we simply refuse to run.
298	*/
299	HWACCMR0Globals.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
300	}
301	else
302	{
303	HWACCMR0Globals.vmx.fSupported = true;
304	VMXDisable();
305	}
306
307	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it wasn't so before (some software could incorrectly think it's in VMX mode) */
308	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4);
309	ASMSetFlags(fFlags);
310
311	RTR0MemObjFree(pScatchMemObj, false);
312	if (RT_FAILURE(HWACCMR0Globals.lLastError))
313	return HWACCMR0Globals.lLastError;
314	}
315	}
316	else
317	{
318	AssertFailed(); /* can't hit this case anymore */
319	HWACCMR0Globals.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
320	}
321	}
322	#ifdef LOG_ENABLED
323	else
324	SUPR0Printf("HWACCMR0InitCPU failed with rc=%d\n", HWACCMR0Globals.lLastError);
325	#endif
326	}
327	else
328	HWACCMR0Globals.lLastError = VERR_VMX_NO_VMX;
329	}
330	else
331	if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
332	&& u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
333	&& u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX
334	)
335	{
336	/*
337	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
338	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
339	*/
340	if ( (HWACCMR0Globals.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
341	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
342	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
343	)
344	{
345	int aRc[RTCPUSET_MAX_CPUS];
346	RTCPUID idCpu = 0;
347
348	/* We need to check if AMD-V has been properly initialized on all CPUs. Some BIOSes might do a poor job. */
349	memset(aRc, 0, sizeof(aRc));
350	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
351	AssertRC(rc);
352
353	/* Check the return code of all invocations. */
354	if (RT_SUCCESS(rc))
355	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
356
357	AssertMsgRC(rc, ("HWACCMR0InitCPU failed for cpu %d with rc=%d\n", idCpu, rc));
358
359	if (RT_SUCCESS(rc))
360	{
361	/* Query AMD features. */
362	ASMCpuId(0x8000000A, &HWACCMR0Globals.svm.u32Rev, &HWACCMR0Globals.uMaxASID, &u32Dummy, &HWACCMR0Globals.svm.u32Features);
363
364	HWACCMR0Globals.svm.fSupported = true;
365	}
366	else
367	HWACCMR0Globals.lLastError = rc;
368	}
369	else
370	HWACCMR0Globals.lLastError = VERR_SVM_NO_SVM;
371	}
372	else
373	HWACCMR0Globals.lLastError = VERR_HWACCM_UNKNOWN_CPU;
374	}
375	else
376	HWACCMR0Globals.lLastError = VERR_HWACCM_NO_CPUID;
377
378	if (HWACCMR0Globals.vmx.fSupported)
379	{
380	HWACCMR0Globals.pfnEnterSession = VMXR0Enter;
381	HWACCMR0Globals.pfnLeaveSession = VMXR0Leave;
382	HWACCMR0Globals.pfnSaveHostState = VMXR0SaveHostState;
383	HWACCMR0Globals.pfnLoadGuestState = VMXR0LoadGuestState;
384	HWACCMR0Globals.pfnRunGuestCode = VMXR0RunGuestCode;
385	HWACCMR0Globals.pfnEnableCpu = VMXR0EnableCpu;
386	HWACCMR0Globals.pfnDisableCpu = VMXR0DisableCpu;
387	HWACCMR0Globals.pfnInitVM = VMXR0InitVM;
388	HWACCMR0Globals.pfnTermVM = VMXR0TermVM;
389	HWACCMR0Globals.pfnSetupVM = VMXR0SetupVM;
390	}
391	else
392	if (HWACCMR0Globals.svm.fSupported)
393	{
394	HWACCMR0Globals.pfnEnterSession = SVMR0Enter;
395	HWACCMR0Globals.pfnLeaveSession = SVMR0Leave;
396	HWACCMR0Globals.pfnSaveHostState = SVMR0SaveHostState;
397	HWACCMR0Globals.pfnLoadGuestState = SVMR0LoadGuestState;
398	HWACCMR0Globals.pfnRunGuestCode = SVMR0RunGuestCode;
399	HWACCMR0Globals.pfnEnableCpu = SVMR0EnableCpu;
400	HWACCMR0Globals.pfnDisableCpu = SVMR0DisableCpu;
401	HWACCMR0Globals.pfnInitVM = SVMR0InitVM;
402	HWACCMR0Globals.pfnTermVM = SVMR0TermVM;
403	HWACCMR0Globals.pfnSetupVM = SVMR0SetupVM;
404	}
405
406	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
407	{
408	rc = RTPowerNotificationRegister(hwaccmR0PowerCallback, 0);
409	AssertRC(rc);
410	}
411
412	return VINF_SUCCESS;
413	}
414
415
416	/**
417	* Checks the error code array filled in for each cpu in the system.
418	*
419	* @returns VBox status code.
420	* @param paRc Error code array
421	* @param cErrorCodes Array size
422	* @param pidCpu Value of the first cpu that set an error (out)
423	*/
424	static int hwaccmR0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu)
425	{
426	int rc = VINF_SUCCESS;
427
428	Assert(cErrorCodes == RTCPUSET_MAX_CPUS);
429
430	for (unsigned i=0;i<cErrorCodes;i++)
431	{
432	if (RTMpIsCpuOnline(i))
433	{
434	if (RT_FAILURE(paRc[i]))
435	{
436	rc = paRc[i];
437	*pidCpu = i;
438	break;
439	}
440	}
441	}
442	return rc;
443	}
444
445	/**
446	* Does global Ring-0 HWACCM termination.
447	*
448	* @returns VBox status code.
449	*/
450	VMMR0DECL(int) HWACCMR0Term(void)
451	{
452	int rc;
453	if ( HWACCMR0Globals.vmx.fSupported
454	&& HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
455	{
456	rc = SUPR0EnableVTx(false /* fEnable */);
457	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); iCpu++)
458	{
459	HWACCMR0Globals.aCpuInfo[iCpu].fConfigured = false;
460	Assert(HWACCMR0Globals.aCpuInfo[iCpu].pMemObj == NIL_RTR0MEMOBJ);
461	}
462	}
463	else
464	{
465	int aRc[RTCPUSET_MAX_CPUS];
466
467	rc = RTPowerNotificationDeregister(hwaccmR0PowerCallback, 0);
468	Assert(RT_SUCCESS(rc));
469
470	memset(aRc, 0, sizeof(aRc));
471	rc = RTMpOnAll(hwaccmR0DisableCPU, aRc, NULL);
472	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
473
474	/* Free the per-cpu pages used for VT-x and AMD-V */
475	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
476	{
477	AssertMsgRC(aRc[i], ("hwaccmR0DisableCPU failed for cpu %d with rc=%d\n", i, aRc[i]));
478	if (HWACCMR0Globals.aCpuInfo[i].pMemObj != NIL_RTR0MEMOBJ)
479	{
480	RTR0MemObjFree(HWACCMR0Globals.aCpuInfo[i].pMemObj, false);
481	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
482	}
483	}
484	}
485	return rc;
486	}
487
488
489	/**
490	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
491	* is to be called on the target cpus.
492	*
493	* @param idCpu The identifier for the CPU the function is called on.
494	* @param pvUser1 The 1st user argument.
495	* @param pvUser2 The 2nd user argument.
496	*/
497	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
498	{
499	unsigned u32VendorEBX = (uintptr_t)pvUser1;
500	int paRc = (int )pvUser2;
501	uint64_t val;
502
503	#ifdef LOG_ENABLED
504	SUPR0Printf("HWACCMR0InitCPU cpu %d\n", idCpu);
505	#endif
506	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
507
508	if (u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX)
509	{
510	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
511
512	/*
513	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
514	* Once the lock bit is set, this MSR can no longer be modified.
515	*/
516	if (!(val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK)))
517	{
518	/* MSR is not yet locked; we can change it ourselves here */
519	ASMWrMsr(MSR_IA32_FEATURE_CONTROL, HWACCMR0Globals.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
520	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
521	}
522	if ( (val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
523	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
524	paRc[idCpu] = VINF_SUCCESS;
525	else
526	paRc[idCpu] = VERR_VMX_MSR_LOCKED_OR_DISABLED;
527	}
528	else
529	if (u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX)
530	{
531	/* Check if SVM is disabled */
532	val = ASMRdMsr(MSR_K8_VM_CR);
533	if (!(val & MSR_K8_VM_CR_SVM_DISABLE))
534	{
535	/* Turn on SVM in the EFER MSR. */
536	val = ASMRdMsr(MSR_K6_EFER);
537	if (!(val & MSR_K6_EFER_SVME))
538	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
539
540	/* Paranoia. */
541	val = ASMRdMsr(MSR_K6_EFER);
542	if (val & MSR_K6_EFER_SVME)
543	{
544	/* Restore previous value. */
545	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
546	paRc[idCpu] = VINF_SUCCESS;
547	}
548	else
549	paRc[idCpu] = VERR_SVM_ILLEGAL_EFER_MSR;
550	}
551	else
552	paRc[idCpu] = HWACCMR0Globals.lLastError = VERR_SVM_DISABLED;
553	}
554	else
555	AssertFailed(); /* can't happen */
556	return;
557	}
558
559
560	/**
561	* Sets up HWACCM on all cpus.
562	*
563	* @returns VBox status code.
564	* @param pVM The VM to operate on.
565	*
566	*/
567	VMMR0DECL(int) HWACCMR0EnableAllCpus(PVM pVM)
568	{
569	AssertCompile(sizeof(HWACCMR0Globals.enmHwAccmState) == sizeof(uint32_t));
570
571	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
572	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
573	return VERR_HWACCM_SUSPEND_PENDING;
574
575	if (ASMAtomicCmpXchgU32((volatile uint32_t *)&HWACCMR0Globals.enmHwAccmState, HWACCMSTATE_ENABLED, HWACCMSTATE_UNINITIALIZED))
576	{
577	int rc;
578
579	if ( HWACCMR0Globals.vmx.fSupported
580	&& HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
581	{
582	rc = SUPR0EnableVTx(true /* fEnable */);
583	if (RT_SUCCESS(rc))
584	{
585	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); iCpu++)
586	{
587	HWACCMR0Globals.aCpuInfo[iCpu].fConfigured = true;
588	Assert(HWACCMR0Globals.aCpuInfo[iCpu].pMemObj == NIL_RTR0MEMOBJ);
589	}
590	}
591	else
592	AssertMsgFailed(("HWACCMR0EnableAllCpus/SUPR0EnableVTx: rc=%Rrc\n", rc));
593	}
594	else
595	{
596	int aRc[RTCPUSET_MAX_CPUS];
597	RTCPUID idCpu = 0;
598
599	memset(aRc, 0, sizeof(aRc));
600
601	/* Allocate one page per cpu for the global vt-x and amd-v pages */
602	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
603	{
604	Assert(!HWACCMR0Globals.aCpuInfo[i].pMemObj);
605
606	/** @todo this is rather dangerous if cpus can be taken offline; we don't care for now */
607	if (RTMpIsCpuOnline(i))
608	{
609	rc = RTR0MemObjAllocCont(&HWACCMR0Globals.aCpuInfo[i].pMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
610	AssertRC(rc);
611	if (RT_FAILURE(rc))
612	return rc;
613
614	void *pvR0 = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[i].pMemObj);
615	Assert(pvR0);
616	ASMMemZeroPage(pvR0);
617
618	#ifdef LOG_ENABLED
619	SUPR0Printf("address %x phys %x\n", pvR0, (uint32_t)RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[i].pMemObj, 0));
620	#endif
621	}
622	}
623	/* First time, so initialize each cpu/core */
624	rc = RTMpOnAll(hwaccmR0EnableCPU, (void *)pVM, aRc);
625
626	/* Check the return code of all invocations. */
627	if (RT_SUCCESS(rc))
628	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
629	AssertMsgRC(rc, ("HWACCMR0EnableAllCpus failed for cpu %d with rc=%d\n", idCpu, rc));
630	}
631
632	return rc;
633	}
634	return VINF_SUCCESS;
635	}
636
637	/**
638	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
639	* is to be called on the target cpus.
640	*
641	* @param idCpu The identifier for the CPU the function is called on.
642	* @param pvUser1 The 1st user argument.
643	* @param pvUser2 The 2nd user argument.
644	*/
645	static DECLCALLBACK(void) hwaccmR0EnableCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
646	{
647	PVM pVM = (PVM)pvUser1; /* can be NULL! */
648	int paRc = (int )pvUser2;
649	void *pvPageCpu;
650	RTHCPHYS pPageCpuPhys;
651	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
652
653	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
654	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
655	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
656	Assert(!pCpu->fConfigured);
657	Assert(ASMAtomicReadBool(&pCpu->fInUse) == false);
658
659	pCpu->idCpu = idCpu;
660
661	/* Make sure we start with a clean TLB. */
662	pCpu->fFlushTLB = true;
663
664	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
665	pCpu->cTLBFlushes = 0;
666
667	/* Should never happen */
668	if (!pCpu->pMemObj)
669	{
670	AssertFailed();
671	paRc[idCpu] = VERR_INTERNAL_ERROR;
672	return;
673	}
674
675	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
676	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
677
678	paRc[idCpu] = HWACCMR0Globals.pfnEnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
679	AssertRC(paRc[idCpu]);
680	if (RT_SUCCESS(paRc[idCpu]))
681	pCpu->fConfigured = true;
682
683	return;
684	}
685
686	/**
687	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
688	* is to be called on the target cpus.
689	*
690	* @param idCpu The identifier for the CPU the function is called on.
691	* @param pvUser1 The 1st user argument.
692	* @param pvUser2 The 2nd user argument.
693	*/
694	static DECLCALLBACK(void) hwaccmR0DisableCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
695	{
696	void *pvPageCpu;
697	RTHCPHYS pPageCpuPhys;
698	int paRc = (int )pvUser1;
699	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
700
701	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
702	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
703	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
704	Assert(ASMAtomicReadBool(&pCpu->fInUse) == false);
705
706	if (!pCpu->pMemObj)
707	return;
708
709	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
710	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
711
712	if (pCpu->fConfigured)
713	{
714	paRc[idCpu] = HWACCMR0Globals.pfnDisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
715	AssertRC(paRc[idCpu]);
716	pCpu->fConfigured = false;
717	}
718	else
719	paRc[idCpu] = VINF_SUCCESS; /* nothing to do */
720
721	pCpu->uCurrentASID = 0;
722	return;
723	}
724
725	/**
726	* Called whenever a system power state change occurs.
727	*
728	* @param enmEvent Power event
729	* @param pvUser User argument
730	*/
731	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
732	{
733	NOREF(pvUser);
734	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
735
736	#ifdef LOG_ENABLED
737	if (enmEvent == RTPOWEREVENT_SUSPEND)
738	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
739	else
740	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_RESUME\n");
741	#endif
742
743	if (enmEvent == RTPOWEREVENT_SUSPEND)
744	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, true);
745
746	if (HWACCMR0Globals.enmHwAccmState == HWACCMSTATE_ENABLED)
747	{
748	int aRc[RTCPUSET_MAX_CPUS];
749	int rc;
750	RTCPUID idCpu;
751
752	memset(aRc, 0, sizeof(aRc));
753	if (enmEvent == RTPOWEREVENT_SUSPEND)
754	{
755	/* Turn off VT-x or AMD-V on all CPUs. */
756	rc = RTMpOnAll(hwaccmR0DisableCPU, aRc, NULL);
757	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
758	}
759	else
760	{
761	/* Reinit the CPUs from scratch as the suspend state has messed with the MSRs. */
762	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)((HWACCMR0Globals.vmx.fSupported) ? X86_CPUID_VENDOR_INTEL_EBX : X86_CPUID_VENDOR_AMD_EBX), aRc);
763	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
764
765	if (RT_SUCCESS(rc))
766	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
767	#ifdef LOG_ENABLED
768	if (RT_FAILURE(rc))
769	SUPR0Printf("hwaccmR0PowerCallback HWACCMR0InitCPU failed with %d\n", rc);
770	#endif
771
772	/* Turn VT-x or AMD-V back on on all CPUs. */
773	rc = RTMpOnAll(hwaccmR0EnableCPU, NULL, aRc);
774	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
775	}
776	}
777	if (enmEvent == RTPOWEREVENT_RESUME)
778	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, false);
779	}
780
781
782	/**
783	* Does Ring-0 per VM HWACCM initialization.
784	*
785	* This is mainly to check that the Host CPU mode is compatible
786	* with VMX.
787	*
788	* @returns VBox status code.
789	* @param pVM The VM to operate on.
790	*/
791	VMMR0DECL(int) HWACCMR0InitVM(PVM pVM)
792	{
793	int rc;
794
795	AssertReturn(pVM, VERR_INVALID_PARAMETER);
796
797	#ifdef LOG_ENABLED
798	SUPR0Printf("HWACCMR0InitVM: %p\n", pVM);
799	#endif
800
801	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
802	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
803	return VERR_HWACCM_SUSPEND_PENDING;
804
805	pVM->hwaccm.s.vmx.fSupported = HWACCMR0Globals.vmx.fSupported;
806	pVM->hwaccm.s.svm.fSupported = HWACCMR0Globals.svm.fSupported;
807
808	pVM->hwaccm.s.vmx.msr.feature_ctrl = HWACCMR0Globals.vmx.msr.feature_ctrl;
809	pVM->hwaccm.s.vmx.hostCR4 = HWACCMR0Globals.vmx.hostCR4;
810	pVM->hwaccm.s.vmx.msr.vmx_basic_info = HWACCMR0Globals.vmx.msr.vmx_basic_info;
811	pVM->hwaccm.s.vmx.msr.vmx_pin_ctls = HWACCMR0Globals.vmx.msr.vmx_pin_ctls;
812	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls = HWACCMR0Globals.vmx.msr.vmx_proc_ctls;
813	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2 = HWACCMR0Globals.vmx.msr.vmx_proc_ctls2;
814	pVM->hwaccm.s.vmx.msr.vmx_exit = HWACCMR0Globals.vmx.msr.vmx_exit;
815	pVM->hwaccm.s.vmx.msr.vmx_entry = HWACCMR0Globals.vmx.msr.vmx_entry;
816	pVM->hwaccm.s.vmx.msr.vmx_misc = HWACCMR0Globals.vmx.msr.vmx_misc;
817	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0;
818	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1;
819	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0;
820	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1;
821	pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum = HWACCMR0Globals.vmx.msr.vmx_vmcs_enum;
822	pVM->hwaccm.s.vmx.msr.vmx_eptcaps = HWACCMR0Globals.vmx.msr.vmx_eptcaps;
823	pVM->hwaccm.s.svm.u32Rev = HWACCMR0Globals.svm.u32Rev;
824	pVM->hwaccm.s.svm.u32Features = HWACCMR0Globals.svm.u32Features;
825	pVM->hwaccm.s.cpuid.u32AMDFeatureECX = HWACCMR0Globals.cpuid.u32AMDFeatureECX;
826	pVM->hwaccm.s.cpuid.u32AMDFeatureEDX = HWACCMR0Globals.cpuid.u32AMDFeatureEDX;
827	pVM->hwaccm.s.lLastError = HWACCMR0Globals.lLastError;
828
829	pVM->hwaccm.s.uMaxASID = HWACCMR0Globals.uMaxASID;
830
831	for (unsigned i=0;i<pVM->cCPUs;i++)
832	{
833	PVMCPU pVCpu = &pVM->aCpus[i];
834
835	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
836
837	/* Invalidate the last cpu we were running on. */
838	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
839
840	/* we'll aways increment this the first time (host uses ASID 0) */
841	pVCpu->hwaccm.s.uCurrentASID = 0;
842	}
843
844	RTCCUINTREG fFlags = ASMIntDisableFlags();
845	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
846
847	/* @note Not correct as we can be rescheduled to a different cpu, but the fInUse case is mostly for debugging. */
848	ASMAtomicWriteBool(&pCpu->fInUse, true);
849	ASMSetFlags(fFlags);
850
851	/* Init a VT-x or AMD-V VM. */
852	rc = HWACCMR0Globals.pfnInitVM(pVM);
853
854	ASMAtomicWriteBool(&pCpu->fInUse, false);
855	return rc;
856	}
857
858
859	/**
860	* Does Ring-0 per VM HWACCM termination.
861	*
862	* @returns VBox status code.
863	* @param pVM The VM to operate on.
864	*/
865	VMMR0DECL(int) HWACCMR0TermVM(PVM pVM)
866	{
867	int rc;
868
869	AssertReturn(pVM, VERR_INVALID_PARAMETER);
870
871	#ifdef LOG_ENABLED
872	SUPR0Printf("HWACCMR0TermVM: %p\n", pVM);
873	#endif
874
875	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
876	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
877
878	/* @note Not correct as we can be rescheduled to a different cpu, but the fInUse case is mostly for debugging. */
879	RTCCUINTREG fFlags = ASMIntDisableFlags();
880	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
881
882	ASMAtomicWriteBool(&pCpu->fInUse, true);
883	ASMSetFlags(fFlags);
884
885	/* Terminate a VT-x or AMD-V VM. */
886	rc = HWACCMR0Globals.pfnTermVM(pVM);
887
888	ASMAtomicWriteBool(&pCpu->fInUse, false);
889	return rc;
890	}
891
892
893	/**
894	* Sets up a VT-x or AMD-V session
895	*
896	* @returns VBox status code.
897	* @param pVM The VM to operate on.
898	*/
899	VMMR0DECL(int) HWACCMR0SetupVM(PVM pVM)
900	{
901	int rc;
902	RTCPUID idCpu = RTMpCpuId();
903	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
904
905	AssertReturn(pVM, VERR_INVALID_PARAMETER);
906
907	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
908	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
909
910	#ifdef LOG_ENABLED
911	SUPR0Printf("HWACCMR0SetupVM: %p\n", pVM);
912	#endif
913
914	ASMAtomicWriteBool(&pCpu->fInUse, true);
915
916	for (unsigned i=0;i<pVM->cCPUs;i++)
917	{
918	/* On first entry we'll sync everything. */
919	pVM->aCpus[i].hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
920	}
921
922	/* Setup VT-x or AMD-V. */
923	rc = HWACCMR0Globals.pfnSetupVM(pVM);
924
925	ASMAtomicWriteBool(&pCpu->fInUse, false);
926
927	return rc;
928	}
929
930
931	/**
932	* Enters the VT-x or AMD-V session
933	*
934	* @returns VBox status code.
935	* @param pVM The VM to operate on.
936	* @param pVCpu VMCPUD id.
937	*/
938	VMMR0DECL(int) HWACCMR0Enter(PVM pVM, PVMCPU pVCpu)
939	{
940	PCPUMCTX pCtx;
941	int rc;
942	RTCPUID idCpu = RTMpCpuId();
943	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
944
945	/* Make sure we can't enter a session after we've disabled hwaccm in preparation of a suspend. */
946	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
947	ASMAtomicWriteBool(&pCpu->fInUse, true);
948
949	pCtx = CPUMQueryGuestCtxPtrEx(pVM, pVCpu);
950
951	/* Always load the guest's FPU/XMM state on-demand. */
952	CPUMDeactivateGuestFPUState(pVM);
953
954	/* Always load the guest's debug state on-demand. */
955	CPUMDeactivateGuestDebugState(pVM);
956
957	/* Always reload the host context and the guest's CR0 register. (!!!!) */
958	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0 \| HWACCM_CHANGED_HOST_CONTEXT;
959
960	/* Setup the register and mask according to the current execution mode. */
961	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
962	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFFFFFFFFFF);
963	else
964	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFF);
965
966	rc = HWACCMR0Globals.pfnEnterSession(pVM, pVCpu, pCpu);
967	AssertRC(rc);
968	/* We must save the host context here (VT-x) as we might be rescheduled on a different cpu after a long jump back to ring 3. */
969	rc \|= HWACCMR0Globals.pfnSaveHostState(pVM, pVCpu);
970	AssertRC(rc);
971	rc \|= HWACCMR0Globals.pfnLoadGuestState(pVM, pVCpu, pCtx);
972	AssertRC(rc);
973
974	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
975	if (RT_SUCCESS(rc))
976	{
977	AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == NIL_RTCPUID, ("%d", (int)pVCpu->hwaccm.s.idEnteredCpu));
978	pVCpu->hwaccm.s.idEnteredCpu = idCpu;
979
980	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
981	PGMDynMapMigrateAutoSet(pVCpu);
982	#endif
983	}
984	return rc;
985	}
986
987
988	/**
989	* Leaves the VT-x or AMD-V session
990	*
991	* @returns VBox status code.
992	* @param pVM The VM to operate on.
993	* @param pVCpu VMCPUD id.
994	*/
995	VMMR0DECL(int) HWACCMR0Leave(PVM pVM, PVMCPU pVCpu)
996	{
997	PCPUMCTX pCtx;
998	int rc;
999	RTCPUID idCpu = RTMpCpuId();
1000	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1001
1002	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1003
1004	pCtx = CPUMQueryGuestCtxPtrEx(pVM, pVCpu);
1005
1006	/* Note: It's rather tricky with longjmps done by e.g. Log statements or the page fault handler.
1007	* We must restore the host FPU here to make absolutely sure we don't leave the guest FPU state active
1008	* or trash somebody else's FPU state.
1009	*/
1010	/* Save the guest FPU and XMM state if necessary. */
1011	if (CPUMIsGuestFPUStateActive(pVCpu))
1012	{
1013	Log2(("CPUMR0SaveGuestFPU\n"));
1014	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
1015
1016	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1017	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1018	}
1019
1020	rc = HWACCMR0Globals.pfnLeaveSession(pVM, pVCpu, pCtx);
1021
1022	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1023	#ifdef RT_STRICT
1024	if (RT_UNLIKELY( pVCpu->hwaccm.s.idEnteredCpu != idCpu
1025	&& RT_FAILURE(rc)))
1026	{
1027	AssertMsgFailed(("Owner is %d, I'm %d", (int)pVCpu->hwaccm.s.idEnteredCpu, (int)idCpu));
1028	rc = VERR_INTERNAL_ERROR;
1029	}
1030	#endif
1031	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1032
1033	ASMAtomicWriteBool(&pCpu->fInUse, false);
1034	return rc;
1035	}
1036
1037	/**
1038	* Runs guest code in a hardware accelerated VM.
1039	*
1040	* @returns VBox status code.
1041	* @param pVM The VM to operate on.
1042	* @param pVCpu VMCPUD id.
1043	*/
1044	VMMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1045	{
1046	CPUMCTX *pCtx;
1047	RTCPUID idCpu = RTMpCpuId(); NOREF(idCpu);
1048	int rc;
1049	#ifdef VBOX_STRICT
1050	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1051	#endif
1052
1053	Assert(!VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL));
1054	Assert(HWACCMR0Globals.aCpuInfo[idCpu].fConfigured);
1055	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1056	Assert(ASMAtomicReadBool(&pCpu->fInUse) == true);
1057
1058	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1059	PGMDynMapStartAutoSet(pVCpu);
1060	#endif
1061
1062	pCtx = CPUMQueryGuestCtxPtrEx(pVM, pVCpu);
1063
1064	rc = HWACCMR0Globals.pfnRunGuestCode(pVM, pVCpu, pCtx);
1065
1066	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1067	PGMDynMapReleaseAutoSet(pVCpu);
1068	#endif
1069	return rc;
1070	}
1071
1072
1073	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1074	/**
1075	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1076	*
1077	* @returns VBox status code.
1078	* @param pVM VM handle.
1079	* @param pVCpu VMCPU handle.
1080	* @param pCtx CPU context
1081	*/
1082	VMMR0DECL(int) HWACCMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1083	{
1084	if (pVM->hwaccm.s.vmx.fSupported)
1085	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1086
1087	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1088	}
1089
1090	/**
1091	* Save guest debug state (64 bits guest mode & 32 bits host only)
1092	*
1093	* @returns VBox status code.
1094	* @param pVM VM handle.
1095	* @param pVCpu VMCPU handle.
1096	* @param pCtx CPU context
1097	*/
1098	VMMR0DECL(int) HWACCMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1099	{
1100	if (pVM->hwaccm.s.vmx.fSupported)
1101	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1102
1103	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1104	}
1105
1106	/**
1107	* Test the 32->64 bits switcher
1108	*
1109	* @returns VBox status code.
1110	* @param pVM VM handle.
1111	*/
1112	VMMR0DECL(int) HWACCMR0TestSwitcher3264(PVM pVM)
1113	{
1114	PVMCPU pVCpu = &pVM->aCpus[0];
1115	CPUMCTX *pCtx;
1116	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1117	int rc;
1118
1119	pCtx = CPUMQueryGuestCtxPtrEx(pVM, pVCpu);
1120
1121	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1122	if (pVM->hwaccm.s.vmx.fSupported)
1123	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1124	else
1125	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1126	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1127	return rc;
1128	}
1129
1130	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1131
1132	/**
1133	* Returns suspend status of the host
1134	*
1135	* @returns Suspend pending or not
1136	*/
1137	VMMR0DECL(bool) HWACCMR0SuspendPending()
1138	{
1139	return ASMAtomicReadBool(&HWACCMR0Globals.fSuspended);
1140	}
1141
1142	/**
1143	* Returns the cpu structure for the current cpu.
1144	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1145	*
1146	* @returns cpu structure pointer
1147	*/
1148	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu()
1149	{
1150	RTCPUID idCpu = RTMpCpuId();
1151
1152	return &HWACCMR0Globals.aCpuInfo[idCpu];
1153	}
1154
1155	/**
1156	* Returns the cpu structure for the current cpu.
1157	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1158	*
1159	* @returns cpu structure pointer
1160	* @param idCpu id of the VCPU
1161	*/
1162	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu)
1163	{
1164	return &HWACCMR0Globals.aCpuInfo[idCpu];
1165	}
1166
1167	/**
1168	* Disable VT-x if it's active and the current switcher turns off paging
1169	*
1170	* @returns VBox status code.
1171	* @param pVM VM handle.
1172	* @param pfVTxDisabled VT-x was disabled or not (out)
1173	*/
1174	VMMR0DECL(int) HWACCMR0EnterSwitcher(PVM pVM, bool *pfVTxDisabled)
1175	{
1176	Assert(!(ASMGetFlags() & X86_EFL_IF));
1177
1178	*pfVTxDisabled = false;
1179
1180	if ( HWACCMR0Globals.enmHwAccmState != HWACCMSTATE_ENABLED
1181	\|\| !HWACCMR0Globals.vmx.fSupported /* no such issues with AMD-V */)
1182	return VINF_SUCCESS; /* nothing to do */
1183
1184	switch(VMMGetSwitcher(pVM))
1185	{
1186	case VMMSWITCHER_32_TO_32:
1187	case VMMSWITCHER_PAE_TO_PAE:
1188	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1189
1190	case VMMSWITCHER_32_TO_PAE:
1191	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1192	case VMMSWITCHER_AMD64_TO_32:
1193	case VMMSWITCHER_AMD64_TO_PAE:
1194	break; /* unsafe switchers */
1195
1196	default:
1197	AssertFailed();
1198	return VERR_INTERNAL_ERROR;
1199	}
1200
1201	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1202	void *pvPageCpu;
1203	RTHCPHYS pPageCpuPhys;
1204
1205	AssertReturn(pCpu && pCpu->pMemObj, VERR_INTERNAL_ERROR);
1206	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
1207	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
1208
1209	*pfVTxDisabled = true;
1210	return VMXR0DisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
1211	}
1212
1213	/**
1214	* Reeable VT-x if was active and the current switcher turned off paging
1215	*
1216	* @returns VBox status code.
1217	* @param pVM VM handle.
1218	* @param fVTxDisabled VT-x was disabled or not
1219	*/
1220	VMMR0DECL(int) HWACCMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1221	{
1222	Assert(!(ASMGetFlags() & X86_EFL_IF));
1223
1224	if (!fVTxDisabled)
1225	return VINF_SUCCESS; /* nothing to do */
1226
1227	Assert( HWACCMR0Globals.enmHwAccmState == HWACCMSTATE_ENABLED
1228	&& HWACCMR0Globals.vmx.fSupported);
1229
1230	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1231	void *pvPageCpu;
1232	RTHCPHYS pPageCpuPhys;
1233
1234	AssertReturn(pCpu && pCpu->pMemObj, VERR_INTERNAL_ERROR);
1235	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
1236	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
1237
1238	return VMXR0EnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
1239	}
1240
1241	#ifdef VBOX_STRICT
1242	# include <iprt/string.h>
1243	/**
1244	* Dumps a descriptor.
1245	*
1246	* @param pDesc Descriptor to dump.
1247	* @param Sel Selector number.
1248	* @param pszMsg Message to prepend the log entry with.
1249	*/
1250	VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1251	{
1252	/*
1253	* Make variable description string.
1254	*/
1255	static struct
1256	{
1257	unsigned cch;
1258	const char *psz;
1259	} const aTypes[32] =
1260	{
1261	# define STRENTRY(str) { sizeof(str) - 1, str }
1262
1263	/* system */
1264	# if HC_ARCH_BITS == 64
1265	STRENTRY("Reserved0 "), /* 0x00 */
1266	STRENTRY("Reserved1 "), /* 0x01 */
1267	STRENTRY("LDT "), /* 0x02 */
1268	STRENTRY("Reserved3 "), /* 0x03 */
1269	STRENTRY("Reserved4 "), /* 0x04 */
1270	STRENTRY("Reserved5 "), /* 0x05 */
1271	STRENTRY("Reserved6 "), /* 0x06 */
1272	STRENTRY("Reserved7 "), /* 0x07 */
1273	STRENTRY("Reserved8 "), /* 0x08 */
1274	STRENTRY("TSS64Avail "), /* 0x09 */
1275	STRENTRY("ReservedA "), /* 0x0a */
1276	STRENTRY("TSS64Busy "), /* 0x0b */
1277	STRENTRY("Call64 "), /* 0x0c */
1278	STRENTRY("ReservedD "), /* 0x0d */
1279	STRENTRY("Int64 "), /* 0x0e */
1280	STRENTRY("Trap64 "), /* 0x0f */
1281	# else
1282	STRENTRY("Reserved0 "), /* 0x00 */
1283	STRENTRY("TSS16Avail "), /* 0x01 */
1284	STRENTRY("LDT "), /* 0x02 */
1285	STRENTRY("TSS16Busy "), /* 0x03 */
1286	STRENTRY("Call16 "), /* 0x04 */
1287	STRENTRY("Task "), /* 0x05 */
1288	STRENTRY("Int16 "), /* 0x06 */
1289	STRENTRY("Trap16 "), /* 0x07 */
1290	STRENTRY("Reserved8 "), /* 0x08 */
1291	STRENTRY("TSS32Avail "), /* 0x09 */
1292	STRENTRY("ReservedA "), /* 0x0a */
1293	STRENTRY("TSS32Busy "), /* 0x0b */
1294	STRENTRY("Call32 "), /* 0x0c */
1295	STRENTRY("ReservedD "), /* 0x0d */
1296	STRENTRY("Int32 "), /* 0x0e */
1297	STRENTRY("Trap32 "), /* 0x0f */
1298	# endif
1299	/* non system */
1300	STRENTRY("DataRO "), /* 0x10 */
1301	STRENTRY("DataRO Accessed "), /* 0x11 */
1302	STRENTRY("DataRW "), /* 0x12 */
1303	STRENTRY("DataRW Accessed "), /* 0x13 */
1304	STRENTRY("DataDownRO "), /* 0x14 */
1305	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1306	STRENTRY("DataDownRW "), /* 0x16 */
1307	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1308	STRENTRY("CodeEO "), /* 0x18 */
1309	STRENTRY("CodeEO Accessed "), /* 0x19 */
1310	STRENTRY("CodeER "), /* 0x1a */
1311	STRENTRY("CodeER Accessed "), /* 0x1b */
1312	STRENTRY("CodeConfEO "), /* 0x1c */
1313	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1314	STRENTRY("CodeConfER "), /* 0x1e */
1315	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1316	# undef SYSENTRY
1317	};
1318	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1319	char szMsg[128];
1320	char *psz = &szMsg[0];
1321	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1322	memcpy(psz, aTypes[i].psz, aTypes[i].cch);
1323	psz += aTypes[i].cch;
1324
1325	if (pDesc->Gen.u1Present)
1326	ADD_STR(psz, "Present ");
1327	else
1328	ADD_STR(psz, "Not-Present ");
1329	# if HC_ARCH_BITS == 64
1330	if (pDesc->Gen.u1Long)
1331	ADD_STR(psz, "64-bit ");
1332	else
1333	ADD_STR(psz, "Comp ");
1334	# else
1335	if (pDesc->Gen.u1Granularity)
1336	ADD_STR(psz, "Page ");
1337	if (pDesc->Gen.u1DefBig)
1338	ADD_STR(psz, "32-bit ");
1339	else
1340	ADD_STR(psz, "16-bit ");
1341	# endif
1342	# undef ADD_STR
1343	*psz = '\0';
1344
1345	/*
1346	* Limit and Base and format the output.
1347	*/
1348	uint32_t u32Limit = X86DESC_LIMIT(*pDesc);
1349	if (pDesc->Gen.u1Granularity)
1350	u32Limit = u32Limit << PAGE_SHIFT \| PAGE_OFFSET_MASK;
1351
1352	# if HC_ARCH_BITS == 64
1353	uint64_t u32Base = X86DESC64_BASE(*pDesc);
1354
1355	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1356	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1357	# else
1358	uint32_t u32Base = X86DESC_BASE(*pDesc);
1359
1360	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1361	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1362	# endif
1363	}
1364
1365	/**
1366	* Formats a full register dump.
1367	*
1368	* @param pVM The VM to operate on.
1369	* @param pCtx The context to format.
1370	*/
1371	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx)
1372	{
1373	/*
1374	* Format the flags.
1375	*/
1376	static struct
1377	{
1378	const char pszSet; const char pszClear; uint32_t fFlag;
1379	} aFlags[] =
1380	{
1381	{ "vip",NULL, X86_EFL_VIP },
1382	{ "vif",NULL, X86_EFL_VIF },
1383	{ "ac", NULL, X86_EFL_AC },
1384	{ "vm", NULL, X86_EFL_VM },
1385	{ "rf", NULL, X86_EFL_RF },
1386	{ "nt", NULL, X86_EFL_NT },
1387	{ "ov", "nv", X86_EFL_OF },
1388	{ "dn", "up", X86_EFL_DF },
1389	{ "ei", "di", X86_EFL_IF },
1390	{ "tf", NULL, X86_EFL_TF },
1391	{ "nt", "pl", X86_EFL_SF },
1392	{ "nz", "zr", X86_EFL_ZF },
1393	{ "ac", "na", X86_EFL_AF },
1394	{ "po", "pe", X86_EFL_PF },
1395	{ "cy", "nc", X86_EFL_CF },
1396	};
1397	char szEFlags[80];
1398	char *psz = szEFlags;
1399	uint32_t efl = pCtx->eflags.u32;
1400	for (unsigned i = 0; i < RT_ELEMENTS(aFlags); i++)
1401	{
1402	const char *pszAdd = aFlags[i].fFlag & efl ? aFlags[i].pszSet : aFlags[i].pszClear;
1403	if (pszAdd)
1404	{
1405	strcpy(psz, pszAdd);
1406	psz += strlen(pszAdd);
1407	*psz++ = ' ';
1408	}
1409	}
1410	psz[-1] = '\0';
1411
1412
1413	/*
1414	* Format the registers.
1415	*/
1416	if (CPUMIsGuestIn64BitCode(pVM, CPUMCTX2CORE(pCtx)))
1417	{
1418	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1419	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1420	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1421	"r14=%016RX64 r15=%016RX64\n"
1422	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1423	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1424	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1425	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1426	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1427	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1428	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1429	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1430	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1431	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1432	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1433	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1434	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1435	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1436	,
1437	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1438	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1439	pCtx->r14, pCtx->r15,
1440	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1441	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1442	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1443	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1444	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1445	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1446	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1447	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1448	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1449	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1450	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1451	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1452	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1453	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1454	}
1455	else
1456	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1457	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1458	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1459	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1460	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1461	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1462	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1463	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1464	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1465	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1466	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1467	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1468	,
1469	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1470	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1471	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr[0], pCtx->dr[1],
1472	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr[2], pCtx->dr[3],
1473	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr[4], pCtx->dr[5],
1474	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr[6], pCtx->dr[7],
1475	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0, pCtx->cr2,
1476	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3, pCtx->cr4,
1477	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1478	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1479	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1480	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1481
1482	Log(("FPU:\n"
1483	"FCW=%04x FSW=%04x FTW=%02x\n"
1484	"res1=%02x FOP=%04x FPUIP=%08x CS=%04x Rsvrd1=%04x\n"
1485	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1486	,
1487	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
1488	pCtx->fpu.huh1, pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsvrd1,
1489	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
1490	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
1491
1492
1493	Log(("MSR:\n"
1494	"EFER =%016RX64\n"
1495	"PAT =%016RX64\n"
1496	"STAR =%016RX64\n"
1497	"CSTAR =%016RX64\n"
1498	"LSTAR =%016RX64\n"
1499	"SFMASK =%016RX64\n"
1500	"KERNELGSBASE =%016RX64\n",
1501	pCtx->msrEFER,
1502	pCtx->msrPAT,
1503	pCtx->msrSTAR,
1504	pCtx->msrCSTAR,
1505	pCtx->msrLSTAR,
1506	pCtx->msrSFMASK,
1507	pCtx->msrKERNELGSBASE));
1508
1509	}
1510	#endif /* VBOX_STRICT */
1511
1512	/* Dummy callback handlers. */
1513	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
1514	{
1515	return VINF_SUCCESS;
1516	}
1517
1518	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1519	{
1520	return VINF_SUCCESS;
1521	}
1522
1523	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1524	{
1525	return VINF_SUCCESS;
1526	}
1527
1528	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1529	{
1530	return VINF_SUCCESS;
1531	}
1532
1533	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM)
1534	{
1535	return VINF_SUCCESS;
1536	}
1537
1538	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM)
1539	{
1540	return VINF_SUCCESS;
1541	}
1542
1543	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM)
1544	{
1545	return VINF_SUCCESS;
1546	}
1547
1548	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1549	{
1550	return VINF_SUCCESS;
1551	}
1552
1553	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
1554	{
1555	return VINF_SUCCESS;
1556	}
1557
1558	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1559	{
1560	return VINF_SUCCESS;
1561	}

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp@ 17327

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