HWACCMR0.cpp@ 24760

Last change on this file since 24760 was 24507, checked in by vboxsync, 15 years ago
HWACCMR0.cpp: privately disabled the assertion.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 64.9 KB

Line
1	/* $Id: HWACCMR0.cpp 24507 2009-11-09 14:43:42Z vboxsync $ */
2	/** @file
3	* HWACCM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_vmx.h>
32	#include <VBox/hwacc_svm.h>
33	#include <VBox/pgm.h>
34	#include <VBox/pdm.h>
35	#include <VBox/err.h>
36	#include <VBox/log.h>
37	#include <VBox/selm.h>
38	#include <VBox/iom.h>
39	#include <iprt/assert.h>
40	#include <iprt/asm.h>
41	#include <iprt/cpuset.h>
42	#include <iprt/memobj.h>
43	#include <iprt/param.h>
44	#include <iprt/power.h>
45	#include <iprt/string.h>
46	#include <iprt/thread.h>
47	#include "HWVMXR0.h"
48	#include "HWSVMR0.h"
49
50	/*******************************************************************************
51	* Internal Functions *
52	*******************************************************************************/
53	static DECLCALLBACK(void) hwaccmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hwaccmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
55	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
56	static int hwaccmR0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu);
57	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
58
59	/*******************************************************************************
60	* Global Variables *
61	*******************************************************************************/
62
63	static struct
64	{
65	HWACCM_CPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
66
67	/** Ring 0 handlers for VT-x and AMD-V. */
68	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu));
69	DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
70	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
71	DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
72	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
73	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
74	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
75	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
76	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
77	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVM pVM));
78
79	/** Maximum ASID allowed. */
80	uint32_t uMaxASID;
81
82	struct
83	{
84	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
85	bool fSupported;
86	/** Whether we're using SUPR0EnableVTx or not. */
87	bool fUsingSUPR0EnableVTx;
88
89	/** Host CR4 value (set by ring-0 VMX init) */
90	uint64_t hostCR4;
91
92	/** VMX MSR values */
93	struct
94	{
95	uint64_t feature_ctrl;
96	uint64_t vmx_basic_info;
97	VMX_CAPABILITY vmx_pin_ctls;
98	VMX_CAPABILITY vmx_proc_ctls;
99	VMX_CAPABILITY vmx_proc_ctls2;
100	VMX_CAPABILITY vmx_exit;
101	VMX_CAPABILITY vmx_entry;
102	uint64_t vmx_misc;
103	uint64_t vmx_cr0_fixed0;
104	uint64_t vmx_cr0_fixed1;
105	uint64_t vmx_cr4_fixed0;
106	uint64_t vmx_cr4_fixed1;
107	uint64_t vmx_vmcs_enum;
108	uint64_t vmx_eptcaps;
109	} msr;
110	/* Last instruction error */
111	uint32_t ulLastInstrError;
112	} vmx;
113	struct
114	{
115	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
116	bool fSupported;
117
118	/** SVM revision. */
119	uint32_t u32Rev;
120
121	/** SVM feature bits from cpuid 0x8000000a */
122	uint32_t u32Features;
123	} svm;
124	/** Saved error from detection */
125	int32_t lLastError;
126
127	struct
128	{
129	uint32_t u32AMDFeatureECX;
130	uint32_t u32AMDFeatureEDX;
131	} cpuid;
132
133	HWACCMSTATE enmHwAccmState;
134
135	bool fGlobalInit;
136	volatile bool fSuspended;
137	} HWACCMR0Globals;
138
139
140
141	/**
142	* Does global Ring-0 HWACCM initialization.
143	*
144	* @returns VBox status code.
145	*/
146	VMMR0DECL(int) HWACCMR0Init(void)
147	{
148	int rc;
149
150	memset(&HWACCMR0Globals, 0, sizeof(HWACCMR0Globals));
151	HWACCMR0Globals.enmHwAccmState = HWACCMSTATE_UNINITIALIZED;
152	for (unsigned i = 0; i < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); i++)
153	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
154
155	/* Fill in all callbacks with placeholders. */
156	HWACCMR0Globals.pfnEnterSession = HWACCMR0DummyEnter;
157	HWACCMR0Globals.pfnLeaveSession = HWACCMR0DummyLeave;
158	HWACCMR0Globals.pfnSaveHostState = HWACCMR0DummySaveHostState;
159	HWACCMR0Globals.pfnLoadGuestState = HWACCMR0DummyLoadGuestState;
160	HWACCMR0Globals.pfnRunGuestCode = HWACCMR0DummyRunGuestCode;
161	HWACCMR0Globals.pfnEnableCpu = HWACCMR0DummyEnableCpu;
162	HWACCMR0Globals.pfnDisableCpu = HWACCMR0DummyDisableCpu;
163	HWACCMR0Globals.pfnInitVM = HWACCMR0DummyInitVM;
164	HWACCMR0Globals.pfnTermVM = HWACCMR0DummyTermVM;
165	HWACCMR0Globals.pfnSetupVM = HWACCMR0DummySetupVM;
166
167	/* Default is global VT-x/AMD-V init */
168	HWACCMR0Globals.fGlobalInit = true;
169
170	/*
171	* Check for VT-x and AMD-V capabilities
172	*/
173	if (ASMHasCpuId())
174	{
175	uint32_t u32FeaturesECX;
176	uint32_t u32Dummy;
177	uint32_t u32FeaturesEDX;
178	uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
179
180	ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
181	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
182	/* Query AMD features. */
183	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy, &HWACCMR0Globals.cpuid.u32AMDFeatureECX, &HWACCMR0Globals.cpuid.u32AMDFeatureEDX);
184
185	if ( u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
186	&& u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
187	&& u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX
188	)
189	{
190	/*
191	* Read all VMX MSRs if VMX is available. (same goes for RDMSR/WRMSR)
192	* We also assume all VMX-enabled CPUs support fxsave/fxrstor.
193	*/
194	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
195	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
196	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
197	)
198	{
199	int aRc[RTCPUSET_MAX_CPUS];
200	RTCPUID idCpu = 0;
201
202	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
203
204	/*
205	* First try use native kernel API for controlling VT-x.
206	* (This is only supported by some Mac OS X kernels atm.)
207	*/
208	HWACCMR0Globals.lLastError = rc = SUPR0EnableVTx(true /* fEnable */);
209	if (rc != VERR_NOT_SUPPORTED)
210	{
211	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
212	HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx = true;
213	if (RT_SUCCESS(rc))
214	{
215	HWACCMR0Globals.vmx.fSupported = true;
216	rc = SUPR0EnableVTx(false /* fEnable */);
217	AssertRC(rc);
218	}
219	}
220	else
221	{
222	HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx = false;
223
224	/* We need to check if VT-x has been properly initialized on all CPUs. Some BIOSes do a lousy job. */
225	memset(aRc, 0, sizeof(aRc));
226	HWACCMR0Globals.lLastError = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
227
228	/* Check the return code of all invocations. */
229	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
230	HWACCMR0Globals.lLastError = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
231	}
232	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
233	{
234	/* Reread in case we've changed it. */
235	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
236
237	if ( (HWACCMR0Globals.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
238	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
239	{
240	RTR0MEMOBJ pScatchMemObj;
241	void *pvScatchPage;
242	RTHCPHYS pScatchPagePhys;
243
244	HWACCMR0Globals.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
245	HWACCMR0Globals.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
246	HWACCMR0Globals.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
247	HWACCMR0Globals.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
248	HWACCMR0Globals.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
249	HWACCMR0Globals.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
250	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
251	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
252	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
253	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
254	HWACCMR0Globals.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
255	/* VPID 16 bits ASID. */
256	HWACCMR0Globals.uMaxASID = 0x10000; /* exclusive */
257
258	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
259	{
260	HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
261	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT\|VMX_VMCS_CTRL_PROC_EXEC2_VPID))
262	HWACCMR0Globals.vmx.msr.vmx_eptcaps = ASMRdMsr(MSR_IA32_VMX_EPT_CAPS);
263	}
264
265	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
266	{
267	HWACCMR0Globals.vmx.hostCR4 = ASMGetCR4();
268
269	rc = RTR0MemObjAllocCont(&pScatchMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
270	if (RT_FAILURE(rc))
271	return rc;
272
273	pvScatchPage = RTR0MemObjAddress(pScatchMemObj);
274	pScatchPagePhys = RTR0MemObjGetPagePhysAddr(pScatchMemObj, 0);
275	memset(pvScatchPage, 0, PAGE_SIZE);
276
277	/* Set revision dword at the beginning of the structure. */
278	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(HWACCMR0Globals.vmx.msr.vmx_basic_info);
279
280	/* Make sure we don't get rescheduled to another cpu during this probe. */
281	RTCCUINTREG fFlags = ASMIntDisableFlags();
282
283	/*
284	* Check CR4.VMXE
285	*/
286	if (!(HWACCMR0Globals.vmx.hostCR4 & X86_CR4_VMXE))
287	{
288	/* In theory this bit could be cleared behind our back. Which would cause #UD faults when we
289	* try to execute the VMX instructions...
290	*/
291	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4 \| X86_CR4_VMXE);
292	}
293
294	/* Enter VMX Root Mode */
295	rc = VMXEnable(pScatchPagePhys);
296	if (RT_FAILURE(rc))
297	{
298	/* KVM leaves the CPU in VMX root mode. Not only is this not allowed, it will crash the host when we enter raw mode, because
299	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify this bit)
300	* (b) turning off paging causes a #GP (unavoidable when switching from long to 32 bits mode or 32 bits to PAE)
301	*
302	* They should fix their code, but until they do we simply refuse to run.
303	*/
304	HWACCMR0Globals.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
305	}
306	else
307	{
308	HWACCMR0Globals.vmx.fSupported = true;
309	VMXDisable();
310	}
311
312	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it wasn't so before (some software could incorrectly think it's in VMX mode) */
313	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4);
314	ASMSetFlags(fFlags);
315
316	RTR0MemObjFree(pScatchMemObj, false);
317	if (RT_FAILURE(HWACCMR0Globals.lLastError))
318	return HWACCMR0Globals.lLastError;
319	}
320	}
321	else
322	{
323	AssertFailed(); /* can't hit this case anymore */
324	HWACCMR0Globals.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
325	}
326	}
327	#ifdef LOG_ENABLED
328	else
329	SUPR0Printf("HWACCMR0InitCPU failed with rc=%d\n", HWACCMR0Globals.lLastError);
330	#endif
331	}
332	else
333	HWACCMR0Globals.lLastError = VERR_VMX_NO_VMX;
334	}
335	else
336	if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
337	&& u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
338	&& u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX
339	)
340	{
341	/*
342	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
343	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
344	*/
345	if ( (HWACCMR0Globals.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
346	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
347	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
348	)
349	{
350	int aRc[RTCPUSET_MAX_CPUS];
351	RTCPUID idCpu = 0;
352
353	/* We need to check if AMD-V has been properly initialized on all CPUs. Some BIOSes might do a poor job. */
354	memset(aRc, 0, sizeof(aRc));
355	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
356	AssertRC(rc);
357
358	/* Check the return code of all invocations. */
359	if (RT_SUCCESS(rc))
360	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
361
362	#ifndef DEBUG_bird
363	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE, ("HWACCMR0InitCPU failed for cpu %d with rc=%d\n", idCpu, rc));
364	#endif
365	if (RT_SUCCESS(rc))
366	{
367	/* Query AMD features. */
368	ASMCpuId(0x8000000A, &HWACCMR0Globals.svm.u32Rev, &HWACCMR0Globals.uMaxASID, &u32Dummy, &HWACCMR0Globals.svm.u32Features);
369
370	HWACCMR0Globals.svm.fSupported = true;
371	}
372	else
373	HWACCMR0Globals.lLastError = rc;
374	}
375	else
376	HWACCMR0Globals.lLastError = VERR_SVM_NO_SVM;
377	}
378	else
379	HWACCMR0Globals.lLastError = VERR_HWACCM_UNKNOWN_CPU;
380	}
381	else
382	HWACCMR0Globals.lLastError = VERR_HWACCM_NO_CPUID;
383
384	if (HWACCMR0Globals.vmx.fSupported)
385	{
386	HWACCMR0Globals.pfnEnterSession = VMXR0Enter;
387	HWACCMR0Globals.pfnLeaveSession = VMXR0Leave;
388	HWACCMR0Globals.pfnSaveHostState = VMXR0SaveHostState;
389	HWACCMR0Globals.pfnLoadGuestState = VMXR0LoadGuestState;
390	HWACCMR0Globals.pfnRunGuestCode = VMXR0RunGuestCode;
391	HWACCMR0Globals.pfnEnableCpu = VMXR0EnableCpu;
392	HWACCMR0Globals.pfnDisableCpu = VMXR0DisableCpu;
393	HWACCMR0Globals.pfnInitVM = VMXR0InitVM;
394	HWACCMR0Globals.pfnTermVM = VMXR0TermVM;
395	HWACCMR0Globals.pfnSetupVM = VMXR0SetupVM;
396	}
397	else
398	if (HWACCMR0Globals.svm.fSupported)
399	{
400	HWACCMR0Globals.pfnEnterSession = SVMR0Enter;
401	HWACCMR0Globals.pfnLeaveSession = SVMR0Leave;
402	HWACCMR0Globals.pfnSaveHostState = SVMR0SaveHostState;
403	HWACCMR0Globals.pfnLoadGuestState = SVMR0LoadGuestState;
404	HWACCMR0Globals.pfnRunGuestCode = SVMR0RunGuestCode;
405	HWACCMR0Globals.pfnEnableCpu = SVMR0EnableCpu;
406	HWACCMR0Globals.pfnDisableCpu = SVMR0DisableCpu;
407	HWACCMR0Globals.pfnInitVM = SVMR0InitVM;
408	HWACCMR0Globals.pfnTermVM = SVMR0TermVM;
409	HWACCMR0Globals.pfnSetupVM = SVMR0SetupVM;
410	}
411
412	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
413	{
414	rc = RTPowerNotificationRegister(hwaccmR0PowerCallback, 0);
415	AssertRC(rc);
416	}
417
418	return VINF_SUCCESS;
419	}
420
421
422	/**
423	* Checks the error code array filled in for each cpu in the system.
424	*
425	* @returns VBox status code.
426	* @param paRc Error code array
427	* @param cErrorCodes Array size
428	* @param pidCpu Value of the first cpu that set an error (out)
429	*/
430	static int hwaccmR0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu)
431	{
432	int rc = VINF_SUCCESS;
433
434	Assert(cErrorCodes == RTCPUSET_MAX_CPUS);
435
436	for (unsigned i=0;i<cErrorCodes;i++)
437	{
438	if (RTMpIsCpuOnline(i))
439	{
440	if (RT_FAILURE(paRc[i]))
441	{
442	rc = paRc[i];
443	*pidCpu = i;
444	break;
445	}
446	}
447	}
448	return rc;
449	}
450
451	/**
452	* Does global Ring-0 HWACCM termination.
453	*
454	* @returns VBox status code.
455	*/
456	VMMR0DECL(int) HWACCMR0Term(void)
457	{
458	int rc;
459	if ( HWACCMR0Globals.vmx.fSupported
460	&& HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
461	{
462	Assert(HWACCMR0Globals.fGlobalInit);
463	rc = SUPR0EnableVTx(false /* fEnable */);
464	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); iCpu++)
465	{
466	HWACCMR0Globals.aCpuInfo[iCpu].fConfigured = false;
467	Assert(HWACCMR0Globals.aCpuInfo[iCpu].pMemObj == NIL_RTR0MEMOBJ);
468	}
469	}
470	else
471	{
472	Assert(!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
473	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
474	{
475	rc = RTPowerNotificationDeregister(hwaccmR0PowerCallback, 0);
476	Assert(RT_SUCCESS(rc));
477	}
478	else
479	rc = VINF_SUCCESS;
480
481	/* Only disable VT-x/AMD-V on all CPUs if we enabled it before. */
482	if (HWACCMR0Globals.fGlobalInit)
483	{
484	int aRc[RTCPUSET_MAX_CPUS];
485
486	memset(aRc, 0, sizeof(aRc));
487	rc = RTMpOnAll(hwaccmR0DisableCpuCallback, aRc, NULL);
488	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
489	#ifdef VBOX_STRICT
490	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
491	AssertMsgRC(aRc[i], ("hwaccmR0DisableCpuCallback failed for cpu %d with rc=%d\n", i, aRc[i]));
492	#endif
493	}
494
495	/* Free the per-cpu pages used for VT-x and AMD-V */
496	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
497	{
498	if (HWACCMR0Globals.aCpuInfo[i].pMemObj != NIL_RTR0MEMOBJ)
499	{
500	RTR0MemObjFree(HWACCMR0Globals.aCpuInfo[i].pMemObj, false);
501	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
502	}
503	}
504	}
505	return rc;
506	}
507
508
509	/**
510	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
511	* is to be called on the target cpus.
512	*
513	* @param idCpu The identifier for the CPU the function is called on.
514	* @param pvUser1 The 1st user argument.
515	* @param pvUser2 The 2nd user argument.
516	*/
517	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
518	{
519	unsigned u32VendorEBX = (uintptr_t)pvUser1;
520	int paRc = (int )pvUser2;
521	uint64_t val;
522
523	#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
524	SUPR0Printf("HWACCMR0InitCPU cpu %d\n", idCpu);
525	#endif
526	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
527
528	if (u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX)
529	{
530	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
531
532	/*
533	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
534	* Once the lock bit is set, this MSR can no longer be modified.
535	*/
536	if ( !(val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
537	\|\| ((val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK)) == MSR_IA32_FEATURE_CONTROL_VMXON) /* Some BIOSes forget to set the locked bit. */
538	)
539	{
540	/* MSR is not yet locked; we can change it ourselves here */
541	ASMWrMsr(MSR_IA32_FEATURE_CONTROL, HWACCMR0Globals.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
542	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
543	}
544	if ( (val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
545	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
546	paRc[idCpu] = VINF_SUCCESS;
547	else
548	paRc[idCpu] = VERR_VMX_MSR_LOCKED_OR_DISABLED;
549	}
550	else
551	if (u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX)
552	{
553	/* Check if SVM is disabled */
554	val = ASMRdMsr(MSR_K8_VM_CR);
555	if (!(val & MSR_K8_VM_CR_SVM_DISABLE))
556	{
557	/* Turn on SVM in the EFER MSR. */
558	val = ASMRdMsr(MSR_K6_EFER);
559	if (val & MSR_K6_EFER_SVME)
560	{
561	paRc[idCpu] = VERR_SVM_IN_USE;
562	}
563	else
564	{
565	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
566
567	/* Paranoia. */
568	val = ASMRdMsr(MSR_K6_EFER);
569	if (val & MSR_K6_EFER_SVME)
570	{
571	/* Restore previous value. */
572	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
573	paRc[idCpu] = VINF_SUCCESS;
574	}
575	else
576	paRc[idCpu] = VERR_SVM_ILLEGAL_EFER_MSR;
577	}
578	}
579	else
580	paRc[idCpu] = VERR_SVM_DISABLED;
581	}
582	else
583	AssertFailed(); /* can't happen */
584	return;
585	}
586
587
588	/**
589	* Sets up HWACCM on all cpus.
590	*
591	* @returns VBox status code.
592	* @param pVM The VM to operate on.
593	*
594	*/
595	VMMR0DECL(int) HWACCMR0EnableAllCpus(PVM pVM)
596	{
597	AssertCompile(sizeof(HWACCMR0Globals.enmHwAccmState) == sizeof(uint32_t));
598
599	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
600	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
601	return VERR_HWACCM_SUSPEND_PENDING;
602
603	if (ASMAtomicCmpXchgU32((volatile uint32_t *)&HWACCMR0Globals.enmHwAccmState, HWACCMSTATE_ENABLED, HWACCMSTATE_UNINITIALIZED))
604	{
605	int rc;
606
607	HWACCMR0Globals.fGlobalInit = pVM->hwaccm.s.fGlobalInit;
608
609	if ( HWACCMR0Globals.vmx.fSupported
610	&& HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
611	{
612	rc = SUPR0EnableVTx(true /* fEnable */);
613	if (RT_SUCCESS(rc))
614	{
615	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); iCpu++)
616	{
617	HWACCMR0Globals.aCpuInfo[iCpu].fConfigured = true;
618	Assert(HWACCMR0Globals.aCpuInfo[iCpu].pMemObj == NIL_RTR0MEMOBJ);
619	}
620	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
621	HWACCMR0Globals.fGlobalInit = pVM->hwaccm.s.fGlobalInit = true;
622	}
623	else
624	AssertMsgFailed(("HWACCMR0EnableAllCpus/SUPR0EnableVTx: rc=%Rrc\n", rc));
625	}
626	else
627	{
628	int aRc[RTCPUSET_MAX_CPUS];
629	RTCPUID idCpu = 0;
630
631	memset(aRc, 0, sizeof(aRc));
632
633	/* Allocate one page per cpu for the global vt-x and amd-v pages */
634	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
635	{
636	Assert(!HWACCMR0Globals.aCpuInfo[i].pMemObj);
637
638	/** @todo this is rather dangerous if cpus can be taken offline; we don't care for now */
639	if (RTMpIsCpuOnline(i))
640	{
641	rc = RTR0MemObjAllocCont(&HWACCMR0Globals.aCpuInfo[i].pMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
642	AssertRC(rc);
643	if (RT_FAILURE(rc))
644	return rc;
645
646	void *pvR0 = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[i].pMemObj);
647	Assert(pvR0);
648	ASMMemZeroPage(pvR0);
649
650	#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
651	SUPR0Printf("address %x phys %x\n", pvR0, (uint32_t)RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[i].pMemObj, 0));
652	#endif
653	}
654	}
655	if (HWACCMR0Globals.fGlobalInit)
656	{
657	/* First time, so initialize each cpu/core */
658	rc = RTMpOnAll(hwaccmR0EnableCpuCallback, (void *)pVM, aRc);
659
660	/* Check the return code of all invocations. */
661	if (RT_SUCCESS(rc))
662	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
663	AssertMsgRC(rc, ("HWACCMR0EnableAllCpus failed for cpu %d with rc=%d\n", idCpu, rc));
664	}
665	else
666	rc = VINF_SUCCESS;
667	}
668
669	return rc;
670	}
671	return VINF_SUCCESS;
672	}
673
674	/**
675	* Disable VT-x or AMD-V on the current CPU
676	*
677	* @returns VBox status code.
678	* @param pVM VM handle (can be 0!)
679	* @param idCpu The identifier for the CPU the function is called on.
680	*/
681	static int hwaccmR0EnableCpu(PVM pVM, RTCPUID idCpu)
682	{
683	void *pvPageCpu;
684	RTHCPHYS pPageCpuPhys;
685	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
686
687	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
688	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
689	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
690	Assert(!pCpu->fConfigured);
691	Assert(!HWACCMR0Globals.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
692
693	pCpu->idCpu = idCpu;
694
695	/* Make sure we start with a clean TLB. */
696	pCpu->fFlushTLB = true;
697
698	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
699	pCpu->cTLBFlushes = 0;
700
701	/* Should never happen */
702	if (!pCpu->pMemObj)
703	{
704	AssertFailed();
705	return VERR_INTERNAL_ERROR;
706	}
707
708	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
709	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
710
711	int rc = HWACCMR0Globals.pfnEnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
712	AssertRC(rc);
713	if (RT_SUCCESS(rc))
714	pCpu->fConfigured = true;
715
716	return rc;
717	}
718
719
720	/**
721	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
722	* is to be called on the target cpus.
723	*
724	* @param idCpu The identifier for the CPU the function is called on.
725	* @param pvUser1 The 1st user argument.
726	* @param pvUser2 The 2nd user argument.
727	*/
728	static DECLCALLBACK(void) hwaccmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
729	{
730	PVM pVM = (PVM)pvUser1; /* can be NULL! */
731	int paRc = (int )pvUser2;
732
733	if (!HWACCMR0Globals.fGlobalInit)
734	{
735	paRc[idCpu] = VINF_SUCCESS;
736	AssertFailed();
737	return;
738	}
739
740	paRc[idCpu] = hwaccmR0EnableCpu(pVM, idCpu);
741	}
742
743
744	/**
745	* Disable VT-x or AMD-V on the current CPU
746	*
747	* @returns VBox status code.
748	* @param idCpu The identifier for the CPU the function is called on.
749	*/
750	static int hwaccmR0DisableCpu(RTCPUID idCpu)
751	{
752	void *pvPageCpu;
753	RTHCPHYS pPageCpuPhys;
754	int rc;
755	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
756
757	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
758	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
759	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
760	Assert(!HWACCMR0Globals.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
761	Assert(!pCpu->fConfigured \|\| pCpu->pMemObj);
762
763	if (!pCpu->pMemObj)
764	return (pCpu->fConfigured) ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
765
766	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
767	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
768
769	if (pCpu->fConfigured)
770	{
771	rc = HWACCMR0Globals.pfnDisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
772	AssertRC(rc);
773	pCpu->fConfigured = false;
774	}
775	else
776	rc = VINF_SUCCESS; /* nothing to do */
777
778	pCpu->uCurrentASID = 0;
779	return rc;
780	}
781
782	/**
783	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
784	* is to be called on the target cpus.
785	*
786	* @param idCpu The identifier for the CPU the function is called on.
787	* @param pvUser1 The 1st user argument.
788	* @param pvUser2 The 2nd user argument.
789	*/
790	static DECLCALLBACK(void) hwaccmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
791	{
792	int paRc = (int )pvUser1;
793
794	if (!HWACCMR0Globals.fGlobalInit)
795	{
796	paRc[idCpu] = VINF_SUCCESS;
797	AssertFailed();
798	return;
799	}
800
801	paRc[idCpu] = hwaccmR0DisableCpu(idCpu);
802	}
803
804	/**
805	* Called whenever a system power state change occurs.
806	*
807	* @param enmEvent Power event
808	* @param pvUser User argument
809	*/
810	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
811	{
812	NOREF(pvUser);
813	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
814
815	#ifdef LOG_ENABLED
816	if (enmEvent == RTPOWEREVENT_SUSPEND)
817	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
818	else
819	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_RESUME\n");
820	#endif
821
822	if (enmEvent == RTPOWEREVENT_SUSPEND)
823	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, true);
824
825	if (HWACCMR0Globals.enmHwAccmState == HWACCMSTATE_ENABLED)
826	{
827	int aRc[RTCPUSET_MAX_CPUS];
828	int rc;
829	RTCPUID idCpu;
830
831	memset(aRc, 0, sizeof(aRc));
832	if (enmEvent == RTPOWEREVENT_SUSPEND)
833	{
834	if (HWACCMR0Globals.fGlobalInit)
835	{
836	/* Turn off VT-x or AMD-V on all CPUs. */
837	rc = RTMpOnAll(hwaccmR0DisableCpuCallback, aRc, NULL);
838	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
839	}
840	/* else nothing to do here for the local init case */
841	}
842	else
843	{
844	/* Reinit the CPUs from scratch as the suspend state might have messed with the MSRs. (lousy BIOSes as usual) */
845	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)((HWACCMR0Globals.vmx.fSupported) ? X86_CPUID_VENDOR_INTEL_EBX : X86_CPUID_VENDOR_AMD_EBX), aRc);
846	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
847
848	if (RT_SUCCESS(rc))
849	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
850	#ifdef LOG_ENABLED
851	if (RT_FAILURE(rc))
852	SUPR0Printf("hwaccmR0PowerCallback HWACCMR0InitCPU failed with %d\n", rc);
853	#endif
854
855	if (HWACCMR0Globals.fGlobalInit)
856	{
857	/* Turn VT-x or AMD-V back on on all CPUs. */
858	rc = RTMpOnAll(hwaccmR0EnableCpuCallback, NULL, aRc);
859	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
860	}
861	/* else nothing to do here for the local init case */
862	}
863	}
864	if (enmEvent == RTPOWEREVENT_RESUME)
865	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, false);
866	}
867
868
869	/**
870	* Does Ring-0 per VM HWACCM initialization.
871	*
872	* This is mainly to check that the Host CPU mode is compatible
873	* with VMX.
874	*
875	* @returns VBox status code.
876	* @param pVM The VM to operate on.
877	*/
878	VMMR0DECL(int) HWACCMR0InitVM(PVM pVM)
879	{
880	int rc;
881
882	AssertReturn(pVM, VERR_INVALID_PARAMETER);
883
884	#ifdef LOG_ENABLED
885	SUPR0Printf("HWACCMR0InitVM: %p\n", pVM);
886	#endif
887
888	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
889	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
890	return VERR_HWACCM_SUSPEND_PENDING;
891
892	pVM->hwaccm.s.vmx.fSupported = HWACCMR0Globals.vmx.fSupported;
893	pVM->hwaccm.s.svm.fSupported = HWACCMR0Globals.svm.fSupported;
894
895	pVM->hwaccm.s.vmx.msr.feature_ctrl = HWACCMR0Globals.vmx.msr.feature_ctrl;
896	pVM->hwaccm.s.vmx.hostCR4 = HWACCMR0Globals.vmx.hostCR4;
897	pVM->hwaccm.s.vmx.msr.vmx_basic_info = HWACCMR0Globals.vmx.msr.vmx_basic_info;
898	pVM->hwaccm.s.vmx.msr.vmx_pin_ctls = HWACCMR0Globals.vmx.msr.vmx_pin_ctls;
899	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls = HWACCMR0Globals.vmx.msr.vmx_proc_ctls;
900	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2 = HWACCMR0Globals.vmx.msr.vmx_proc_ctls2;
901	pVM->hwaccm.s.vmx.msr.vmx_exit = HWACCMR0Globals.vmx.msr.vmx_exit;
902	pVM->hwaccm.s.vmx.msr.vmx_entry = HWACCMR0Globals.vmx.msr.vmx_entry;
903	pVM->hwaccm.s.vmx.msr.vmx_misc = HWACCMR0Globals.vmx.msr.vmx_misc;
904	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0;
905	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1;
906	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0;
907	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1;
908	pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum = HWACCMR0Globals.vmx.msr.vmx_vmcs_enum;
909	pVM->hwaccm.s.vmx.msr.vmx_eptcaps = HWACCMR0Globals.vmx.msr.vmx_eptcaps;
910	pVM->hwaccm.s.svm.u32Rev = HWACCMR0Globals.svm.u32Rev;
911	pVM->hwaccm.s.svm.u32Features = HWACCMR0Globals.svm.u32Features;
912	pVM->hwaccm.s.cpuid.u32AMDFeatureECX = HWACCMR0Globals.cpuid.u32AMDFeatureECX;
913	pVM->hwaccm.s.cpuid.u32AMDFeatureEDX = HWACCMR0Globals.cpuid.u32AMDFeatureEDX;
914	pVM->hwaccm.s.lLastError = HWACCMR0Globals.lLastError;
915
916	pVM->hwaccm.s.uMaxASID = HWACCMR0Globals.uMaxASID;
917
918
919	if (!pVM->hwaccm.s.cMaxResumeLoops) /* allow ring-3 overrides */
920	{
921	pVM->hwaccm.s.cMaxResumeLoops = 1024;
922	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
923	if (RTThreadPreemptIsPendingTrusty())
924	pVM->hwaccm.s.cMaxResumeLoops = 8192;
925	#endif
926	}
927
928	for (VMCPUID i = 0; i < pVM->cCpus; i++)
929	{
930	PVMCPU pVCpu = &pVM->aCpus[i];
931
932	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
933
934	/* Invalidate the last cpu we were running on. */
935	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
936
937	/* we'll aways increment this the first time (host uses ASID 0) */
938	pVCpu->hwaccm.s.uCurrentASID = 0;
939	}
940
941	RTCCUINTREG fFlags = ASMIntDisableFlags();
942	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
943
944	/* Note: Not correct as we can be rescheduled to a different cpu, but the fInUse case is mostly for debugging. */
945	ASMAtomicWriteBool(&pCpu->fInUse, true);
946	ASMSetFlags(fFlags);
947
948	/* Init a VT-x or AMD-V VM. */
949	rc = HWACCMR0Globals.pfnInitVM(pVM);
950
951	ASMAtomicWriteBool(&pCpu->fInUse, false);
952	return rc;
953	}
954
955
956	/**
957	* Does Ring-0 per VM HWACCM termination.
958	*
959	* @returns VBox status code.
960	* @param pVM The VM to operate on.
961	*/
962	VMMR0DECL(int) HWACCMR0TermVM(PVM pVM)
963	{
964	int rc;
965
966	AssertReturn(pVM, VERR_INVALID_PARAMETER);
967
968	#ifdef LOG_ENABLED
969	SUPR0Printf("HWACCMR0TermVM: %p\n", pVM);
970	#endif
971
972	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
973	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
974
975	/* @note Not correct as we can be rescheduled to a different cpu, but the fInUse case is mostly for debugging. */
976	RTCCUINTREG fFlags = ASMIntDisableFlags();
977	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
978
979	ASMAtomicWriteBool(&pCpu->fInUse, true);
980	ASMSetFlags(fFlags);
981
982	/* Terminate a VT-x or AMD-V VM. */
983	rc = HWACCMR0Globals.pfnTermVM(pVM);
984
985	ASMAtomicWriteBool(&pCpu->fInUse, false);
986	return rc;
987	}
988
989
990	/**
991	* Sets up a VT-x or AMD-V session
992	*
993	* @returns VBox status code.
994	* @param pVM The VM to operate on.
995	*/
996	VMMR0DECL(int) HWACCMR0SetupVM(PVM pVM)
997	{
998	int rc;
999	RTCPUID idCpu = RTMpCpuId();
1000	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1001
1002	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1003
1004	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
1005	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1006
1007	#ifdef LOG_ENABLED
1008	SUPR0Printf("HWACCMR0SetupVM: %p\n", pVM);
1009	#endif
1010
1011	ASMAtomicWriteBool(&pCpu->fInUse, true);
1012
1013	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1014	{
1015	/* On first entry we'll sync everything. */
1016	pVM->aCpus[i].hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1017	}
1018
1019	/* Enable VT-x or AMD-V if local init is required. */
1020	if (!HWACCMR0Globals.fGlobalInit)
1021	{
1022	rc = hwaccmR0EnableCpu(pVM, idCpu);
1023	AssertRCReturn(rc, rc);
1024	}
1025
1026	/* Setup VT-x or AMD-V. */
1027	rc = HWACCMR0Globals.pfnSetupVM(pVM);
1028
1029	/* Disable VT-x or AMD-V if local init was done before. */
1030	if (!HWACCMR0Globals.fGlobalInit)
1031	{
1032	rc = hwaccmR0DisableCpu(idCpu);
1033	AssertRC(rc);
1034	}
1035
1036	ASMAtomicWriteBool(&pCpu->fInUse, false);
1037
1038	return rc;
1039	}
1040
1041
1042	/**
1043	* Enters the VT-x or AMD-V session
1044	*
1045	* @returns VBox status code.
1046	* @param pVM The VM to operate on.
1047	* @param pVCpu VMCPUD id.
1048	*/
1049	VMMR0DECL(int) HWACCMR0Enter(PVM pVM, PVMCPU pVCpu)
1050	{
1051	PCPUMCTX pCtx;
1052	int rc;
1053	RTCPUID idCpu = RTMpCpuId();
1054	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1055
1056	/* Make sure we can't enter a session after we've disabled hwaccm in preparation of a suspend. */
1057	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1058	ASMAtomicWriteBool(&pCpu->fInUse, true);
1059
1060	AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == NIL_RTCPUID, ("%d", (int)pVCpu->hwaccm.s.idEnteredCpu));
1061	pVCpu->hwaccm.s.idEnteredCpu = idCpu;
1062
1063	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1064
1065	/* Always load the guest's FPU/XMM state on-demand. */
1066	CPUMDeactivateGuestFPUState(pVCpu);
1067
1068	/* Always load the guest's debug state on-demand. */
1069	CPUMDeactivateGuestDebugState(pVCpu);
1070
1071	/* Always reload the host context and the guest's CR0 register. (!!!!) */
1072	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0 \| HWACCM_CHANGED_HOST_CONTEXT;
1073
1074	/* Setup the register and mask according to the current execution mode. */
1075	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1076	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFFFFFFFFFF);
1077	else
1078	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFF);
1079
1080	/* Enable VT-x or AMD-V if local init is required. */
1081	if (!HWACCMR0Globals.fGlobalInit)
1082	{
1083	rc = hwaccmR0EnableCpu(pVM, idCpu);
1084	AssertRCReturn(rc, rc);
1085	}
1086
1087	rc = HWACCMR0Globals.pfnEnterSession(pVM, pVCpu, pCpu);
1088	AssertRC(rc);
1089	/* We must save the host context here (VT-x) as we might be rescheduled on a different cpu after a long jump back to ring 3. */
1090	rc \|= HWACCMR0Globals.pfnSaveHostState(pVM, pVCpu);
1091	AssertRC(rc);
1092	rc \|= HWACCMR0Globals.pfnLoadGuestState(pVM, pVCpu, pCtx);
1093	AssertRC(rc);
1094
1095	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1096	if (RT_SUCCESS(rc))
1097	{
1098	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1099	PGMDynMapMigrateAutoSet(pVCpu);
1100	#endif
1101	}
1102	else
1103	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1104	return rc;
1105	}
1106
1107
1108	/**
1109	* Leaves the VT-x or AMD-V session
1110	*
1111	* @returns VBox status code.
1112	* @param pVM The VM to operate on.
1113	* @param pVCpu VMCPUD id.
1114	*/
1115	VMMR0DECL(int) HWACCMR0Leave(PVM pVM, PVMCPU pVCpu)
1116	{
1117	PCPUMCTX pCtx;
1118	int rc;
1119	RTCPUID idCpu = RTMpCpuId();
1120	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1121
1122	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1123
1124	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1125
1126	/* Note: It's rather tricky with longjmps done by e.g. Log statements or the page fault handler.
1127	* We must restore the host FPU here to make absolutely sure we don't leave the guest FPU state active
1128	* or trash somebody else's FPU state.
1129	*/
1130	/* Save the guest FPU and XMM state if necessary. */
1131	if (CPUMIsGuestFPUStateActive(pVCpu))
1132	{
1133	Log2(("CPUMR0SaveGuestFPU\n"));
1134	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
1135
1136	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1137	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1138	}
1139
1140	rc = HWACCMR0Globals.pfnLeaveSession(pVM, pVCpu, pCtx);
1141
1142	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1143	#ifdef RT_STRICT
1144	if (RT_UNLIKELY( pVCpu->hwaccm.s.idEnteredCpu != idCpu
1145	&& RT_FAILURE(rc)))
1146	{
1147	AssertMsgFailed(("Owner is %d, I'm %d", (int)pVCpu->hwaccm.s.idEnteredCpu, (int)idCpu));
1148	rc = VERR_INTERNAL_ERROR;
1149	}
1150	#endif
1151	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1152
1153	/* Disable VT-x or AMD-V if local init was done before. */
1154	if (!HWACCMR0Globals.fGlobalInit)
1155	{
1156	rc = hwaccmR0DisableCpu(idCpu);
1157	AssertRC(rc);
1158
1159	/* Reset these to force a TLB flush for the next entry. (-> EXPENSIVE) */
1160	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
1161	pVCpu->hwaccm.s.uCurrentASID = 0;
1162	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1163	}
1164
1165	ASMAtomicWriteBool(&pCpu->fInUse, false);
1166	return rc;
1167	}
1168
1169	/**
1170	* Runs guest code in a hardware accelerated VM.
1171	*
1172	* @returns VBox status code.
1173	* @param pVM The VM to operate on.
1174	* @param pVCpu VMCPUD id.
1175	*/
1176	VMMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1177	{
1178	CPUMCTX *pCtx;
1179	int rc;
1180	#ifdef VBOX_STRICT
1181	RTCPUID idCpu = RTMpCpuId(); NOREF(idCpu);
1182	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1183	#endif
1184
1185	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1186	Assert(HWACCMR0Globals.aCpuInfo[idCpu].fConfigured);
1187	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1188	Assert(ASMAtomicReadBool(&pCpu->fInUse) == true);
1189
1190	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1191	PGMDynMapStartAutoSet(pVCpu);
1192	#endif
1193
1194	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1195
1196	rc = HWACCMR0Globals.pfnRunGuestCode(pVM, pVCpu, pCtx);
1197
1198	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1199	PGMDynMapReleaseAutoSet(pVCpu);
1200	#endif
1201	return rc;
1202	}
1203
1204
1205	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1206	/**
1207	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1208	*
1209	* @returns VBox status code.
1210	* @param pVM VM handle.
1211	* @param pVCpu VMCPU handle.
1212	* @param pCtx CPU context
1213	*/
1214	VMMR0DECL(int) HWACCMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1215	{
1216	if (pVM->hwaccm.s.vmx.fSupported)
1217	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1218
1219	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1220	}
1221
1222	/**
1223	* Save guest debug state (64 bits guest mode & 32 bits host only)
1224	*
1225	* @returns VBox status code.
1226	* @param pVM VM handle.
1227	* @param pVCpu VMCPU handle.
1228	* @param pCtx CPU context
1229	*/
1230	VMMR0DECL(int) HWACCMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1231	{
1232	if (pVM->hwaccm.s.vmx.fSupported)
1233	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1234
1235	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1236	}
1237
1238	/**
1239	* Test the 32->64 bits switcher
1240	*
1241	* @returns VBox status code.
1242	* @param pVM VM handle.
1243	*/
1244	VMMR0DECL(int) HWACCMR0TestSwitcher3264(PVM pVM)
1245	{
1246	PVMCPU pVCpu = &pVM->aCpus[0];
1247	CPUMCTX *pCtx;
1248	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1249	int rc;
1250
1251	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1252
1253	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1254	if (pVM->hwaccm.s.vmx.fSupported)
1255	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1256	else
1257	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1258	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1259	return rc;
1260	}
1261
1262	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1263
1264	/**
1265	* Returns suspend status of the host
1266	*
1267	* @returns Suspend pending or not
1268	*/
1269	VMMR0DECL(bool) HWACCMR0SuspendPending()
1270	{
1271	return ASMAtomicReadBool(&HWACCMR0Globals.fSuspended);
1272	}
1273
1274	/**
1275	* Returns the cpu structure for the current cpu.
1276	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1277	*
1278	* @returns cpu structure pointer
1279	*/
1280	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu()
1281	{
1282	RTCPUID idCpu = RTMpCpuId();
1283
1284	return &HWACCMR0Globals.aCpuInfo[idCpu];
1285	}
1286
1287	/**
1288	* Returns the cpu structure for the current cpu.
1289	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1290	*
1291	* @returns cpu structure pointer
1292	* @param idCpu id of the VCPU
1293	*/
1294	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu)
1295	{
1296	return &HWACCMR0Globals.aCpuInfo[idCpu];
1297	}
1298
1299	/**
1300	* Returns the VMCPU of the current EMT thread.
1301	*
1302	* @param pVM The VM to operate on.
1303	*/
1304	VMMR0DECL(PVMCPU) HWACCMR0GetVMCPU(PVM pVM)
1305	{
1306	/* RTMpCpuId had better be cheap. */
1307	RTCPUID idHostCpu = RTMpCpuId();
1308
1309	/** @todo optimize for large number of VCPUs when that becomes more common. */
1310	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1311	{
1312	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1313
1314	if (pVCpu->hwaccm.s.idEnteredCpu == idHostCpu)
1315	return pVCpu;
1316	}
1317	return NULL;
1318	}
1319
1320	/**
1321	* Returns the VMCPU id of the current EMT thread.
1322	*
1323	* @param pVM The VM to operate on.
1324	*/
1325	VMMR0DECL(VMCPUID) HWACCMR0GetVMCPUId(PVM pVM)
1326	{
1327	PVMCPU pVCpu = HWACCMR0GetVMCPU(pVM);
1328	if (pVCpu)
1329	return pVCpu->idCpu;
1330
1331	return 0;
1332	}
1333
1334	/**
1335	* Save a pending IO read.
1336	*
1337	* @param pVCpu The VMCPU to operate on.
1338	* @param GCPtrRip Address of IO instruction
1339	* @param GCPtrRipNext Address of the next instruction
1340	* @param uPort Port address
1341	* @param uAndVal And mask for saving the result in eax
1342	* @param cbSize Read size
1343	*/
1344	VMMR0DECL(void) HWACCMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1345	{
1346	pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_PORT_READ;
1347	pVCpu->hwaccm.s.PendingIO.GCPtrRip = GCPtrRip;
1348	pVCpu->hwaccm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1349	pVCpu->hwaccm.s.PendingIO.s.Port.uPort = uPort;
1350	pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal = uAndVal;
1351	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize = cbSize;
1352	return;
1353	}
1354
1355	/**
1356	* Save a pending IO write.
1357	*
1358	* @param pVCpu The VMCPU to operate on.
1359	* @param GCPtrRIP Address of IO instruction
1360	* @param uPort Port address
1361	* @param uAndVal And mask for fetching the result from eax
1362	* @param cbSize Read size
1363	*/
1364	VMMR0DECL(void) HWACCMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1365	{
1366	pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_PORT_WRITE;
1367	pVCpu->hwaccm.s.PendingIO.GCPtrRip = GCPtrRip;
1368	pVCpu->hwaccm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1369	pVCpu->hwaccm.s.PendingIO.s.Port.uPort = uPort;
1370	pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal = uAndVal;
1371	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize = cbSize;
1372	return;
1373	}
1374
1375	/**
1376	* Disable VT-x if it's active and the current switcher turns off paging
1377	*
1378	* @returns VBox status code.
1379	* @param pVM VM handle.
1380	* @param pfVTxDisabled VT-x was disabled or not (out)
1381	*/
1382	VMMR0DECL(int) HWACCMR0EnterSwitcher(PVM pVM, bool *pfVTxDisabled)
1383	{
1384	Assert(!(ASMGetFlags() & X86_EFL_IF));
1385
1386	*pfVTxDisabled = false;
1387
1388	if ( HWACCMR0Globals.enmHwAccmState != HWACCMSTATE_ENABLED
1389	\|\| !HWACCMR0Globals.vmx.fSupported /* no such issues with AMD-V */
1390	\|\| !pVM->hwaccm.s.fGlobalInit /* Local init implies the CPU is currently not in VMX root mode. */)
1391	return VINF_SUCCESS; /* nothing to do */
1392
1393	switch(VMMGetSwitcher(pVM))
1394	{
1395	case VMMSWITCHER_32_TO_32:
1396	case VMMSWITCHER_PAE_TO_PAE:
1397	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1398
1399	case VMMSWITCHER_32_TO_PAE:
1400	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1401	case VMMSWITCHER_AMD64_TO_32:
1402	case VMMSWITCHER_AMD64_TO_PAE:
1403	break; /* unsafe switchers */
1404
1405	default:
1406	AssertFailed();
1407	return VERR_INTERNAL_ERROR;
1408	}
1409
1410	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1411	void *pvPageCpu;
1412	RTHCPHYS pPageCpuPhys;
1413
1414	AssertReturn(pCpu && pCpu->pMemObj, VERR_INTERNAL_ERROR);
1415	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
1416	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
1417
1418	*pfVTxDisabled = true;
1419	return VMXR0DisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
1420	}
1421
1422	/**
1423	* Reeable VT-x if was active and the current switcher turned off paging
1424	*
1425	* @returns VBox status code.
1426	* @param pVM VM handle.
1427	* @param fVTxDisabled VT-x was disabled or not
1428	*/
1429	VMMR0DECL(int) HWACCMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1430	{
1431	Assert(!(ASMGetFlags() & X86_EFL_IF));
1432
1433	if (!fVTxDisabled)
1434	return VINF_SUCCESS; /* nothing to do */
1435
1436	Assert( HWACCMR0Globals.enmHwAccmState == HWACCMSTATE_ENABLED
1437	&& HWACCMR0Globals.vmx.fSupported
1438	&& pVM->hwaccm.s.fGlobalInit);
1439
1440	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1441	void *pvPageCpu;
1442	RTHCPHYS pPageCpuPhys;
1443
1444	AssertReturn(pCpu && pCpu->pMemObj, VERR_INTERNAL_ERROR);
1445	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
1446	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
1447
1448	return VMXR0EnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
1449	}
1450
1451	#ifdef VBOX_STRICT
1452	/**
1453	* Dumps a descriptor.
1454	*
1455	* @param pDesc Descriptor to dump.
1456	* @param Sel Selector number.
1457	* @param pszMsg Message to prepend the log entry with.
1458	*/
1459	VMMR0DECL(void) HWACCMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1460	{
1461	/*
1462	* Make variable description string.
1463	*/
1464	static struct
1465	{
1466	unsigned cch;
1467	const char *psz;
1468	} const s_aTypes[32] =
1469	{
1470	# define STRENTRY(str) { sizeof(str) - 1, str }
1471
1472	/* system */
1473	# if HC_ARCH_BITS == 64
1474	STRENTRY("Reserved0 "), /* 0x00 */
1475	STRENTRY("Reserved1 "), /* 0x01 */
1476	STRENTRY("LDT "), /* 0x02 */
1477	STRENTRY("Reserved3 "), /* 0x03 */
1478	STRENTRY("Reserved4 "), /* 0x04 */
1479	STRENTRY("Reserved5 "), /* 0x05 */
1480	STRENTRY("Reserved6 "), /* 0x06 */
1481	STRENTRY("Reserved7 "), /* 0x07 */
1482	STRENTRY("Reserved8 "), /* 0x08 */
1483	STRENTRY("TSS64Avail "), /* 0x09 */
1484	STRENTRY("ReservedA "), /* 0x0a */
1485	STRENTRY("TSS64Busy "), /* 0x0b */
1486	STRENTRY("Call64 "), /* 0x0c */
1487	STRENTRY("ReservedD "), /* 0x0d */
1488	STRENTRY("Int64 "), /* 0x0e */
1489	STRENTRY("Trap64 "), /* 0x0f */
1490	# else
1491	STRENTRY("Reserved0 "), /* 0x00 */
1492	STRENTRY("TSS16Avail "), /* 0x01 */
1493	STRENTRY("LDT "), /* 0x02 */
1494	STRENTRY("TSS16Busy "), /* 0x03 */
1495	STRENTRY("Call16 "), /* 0x04 */
1496	STRENTRY("Task "), /* 0x05 */
1497	STRENTRY("Int16 "), /* 0x06 */
1498	STRENTRY("Trap16 "), /* 0x07 */
1499	STRENTRY("Reserved8 "), /* 0x08 */
1500	STRENTRY("TSS32Avail "), /* 0x09 */
1501	STRENTRY("ReservedA "), /* 0x0a */
1502	STRENTRY("TSS32Busy "), /* 0x0b */
1503	STRENTRY("Call32 "), /* 0x0c */
1504	STRENTRY("ReservedD "), /* 0x0d */
1505	STRENTRY("Int32 "), /* 0x0e */
1506	STRENTRY("Trap32 "), /* 0x0f */
1507	# endif
1508	/* non system */
1509	STRENTRY("DataRO "), /* 0x10 */
1510	STRENTRY("DataRO Accessed "), /* 0x11 */
1511	STRENTRY("DataRW "), /* 0x12 */
1512	STRENTRY("DataRW Accessed "), /* 0x13 */
1513	STRENTRY("DataDownRO "), /* 0x14 */
1514	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1515	STRENTRY("DataDownRW "), /* 0x16 */
1516	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1517	STRENTRY("CodeEO "), /* 0x18 */
1518	STRENTRY("CodeEO Accessed "), /* 0x19 */
1519	STRENTRY("CodeER "), /* 0x1a */
1520	STRENTRY("CodeER Accessed "), /* 0x1b */
1521	STRENTRY("CodeConfEO "), /* 0x1c */
1522	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1523	STRENTRY("CodeConfER "), /* 0x1e */
1524	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1525	# undef SYSENTRY
1526	};
1527	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1528	char szMsg[128];
1529	char *psz = &szMsg[0];
1530	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1531	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1532	psz += s_aTypes[i].cch;
1533
1534	if (pDesc->Gen.u1Present)
1535	ADD_STR(psz, "Present ");
1536	else
1537	ADD_STR(psz, "Not-Present ");
1538	# if HC_ARCH_BITS == 64
1539	if (pDesc->Gen.u1Long)
1540	ADD_STR(psz, "64-bit ");
1541	else
1542	ADD_STR(psz, "Comp ");
1543	# else
1544	if (pDesc->Gen.u1Granularity)
1545	ADD_STR(psz, "Page ");
1546	if (pDesc->Gen.u1DefBig)
1547	ADD_STR(psz, "32-bit ");
1548	else
1549	ADD_STR(psz, "16-bit ");
1550	# endif
1551	# undef ADD_STR
1552	*psz = '\0';
1553
1554	/*
1555	* Limit and Base and format the output.
1556	*/
1557	uint32_t u32Limit = X86DESC_LIMIT(*pDesc);
1558	if (pDesc->Gen.u1Granularity)
1559	u32Limit = u32Limit << PAGE_SHIFT \| PAGE_OFFSET_MASK;
1560
1561	# if HC_ARCH_BITS == 64
1562	uint64_t u32Base = X86DESC64_BASE(*pDesc);
1563
1564	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1565	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1566	# else
1567	uint32_t u32Base = X86DESC_BASE(*pDesc);
1568
1569	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1570	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1571	# endif
1572	}
1573
1574	/**
1575	* Formats a full register dump.
1576	*
1577	* @param pVM The VM to operate on.
1578	* @param pVCpu The VMCPU to operate on.
1579	* @param pCtx The context to format.
1580	*/
1581	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1582	{
1583	/*
1584	* Format the flags.
1585	*/
1586	static struct
1587	{
1588	const char pszSet; const char pszClear; uint32_t fFlag;
1589	} aFlags[] =
1590	{
1591	{ "vip",NULL, X86_EFL_VIP },
1592	{ "vif",NULL, X86_EFL_VIF },
1593	{ "ac", NULL, X86_EFL_AC },
1594	{ "vm", NULL, X86_EFL_VM },
1595	{ "rf", NULL, X86_EFL_RF },
1596	{ "nt", NULL, X86_EFL_NT },
1597	{ "ov", "nv", X86_EFL_OF },
1598	{ "dn", "up", X86_EFL_DF },
1599	{ "ei", "di", X86_EFL_IF },
1600	{ "tf", NULL, X86_EFL_TF },
1601	{ "nt", "pl", X86_EFL_SF },
1602	{ "nz", "zr", X86_EFL_ZF },
1603	{ "ac", "na", X86_EFL_AF },
1604	{ "po", "pe", X86_EFL_PF },
1605	{ "cy", "nc", X86_EFL_CF },
1606	};
1607	char szEFlags[80];
1608	char *psz = szEFlags;
1609	uint32_t efl = pCtx->eflags.u32;
1610	for (unsigned i = 0; i < RT_ELEMENTS(aFlags); i++)
1611	{
1612	const char *pszAdd = aFlags[i].fFlag & efl ? aFlags[i].pszSet : aFlags[i].pszClear;
1613	if (pszAdd)
1614	{
1615	strcpy(psz, pszAdd);
1616	psz += strlen(pszAdd);
1617	*psz++ = ' ';
1618	}
1619	}
1620	psz[-1] = '\0';
1621
1622
1623	/*
1624	* Format the registers.
1625	*/
1626	if (CPUMIsGuestIn64BitCode(pVCpu, CPUMCTX2CORE(pCtx)))
1627	{
1628	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1629	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1630	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1631	"r14=%016RX64 r15=%016RX64\n"
1632	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1633	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1634	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1635	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1636	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1637	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1638	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1639	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1640	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1641	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1642	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1643	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1644	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1645	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1646	,
1647	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1648	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1649	pCtx->r14, pCtx->r15,
1650	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1651	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1652	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1653	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1654	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1655	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1656	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1657	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1658	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1659	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1660	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1661	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1662	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1663	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1664	}
1665	else
1666	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1667	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1668	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1669	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1670	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1671	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1672	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1673	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1674	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1675	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1676	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1677	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1678	,
1679	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1680	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1681	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr[0], pCtx->dr[1],
1682	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr[2], pCtx->dr[3],
1683	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr[4], pCtx->dr[5],
1684	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr[6], pCtx->dr[7],
1685	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0, pCtx->cr2,
1686	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3, pCtx->cr4,
1687	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1688	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1689	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1690	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1691
1692	Log(("FPU:\n"
1693	"FCW=%04x FSW=%04x FTW=%02x\n"
1694	"res1=%02x FOP=%04x FPUIP=%08x CS=%04x Rsvrd1=%04x\n"
1695	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1696	,
1697	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
1698	pCtx->fpu.huh1, pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsvrd1,
1699	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
1700	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
1701
1702
1703	Log(("MSR:\n"
1704	"EFER =%016RX64\n"
1705	"PAT =%016RX64\n"
1706	"STAR =%016RX64\n"
1707	"CSTAR =%016RX64\n"
1708	"LSTAR =%016RX64\n"
1709	"SFMASK =%016RX64\n"
1710	"KERNELGSBASE =%016RX64\n",
1711	pCtx->msrEFER,
1712	pCtx->msrPAT,
1713	pCtx->msrSTAR,
1714	pCtx->msrCSTAR,
1715	pCtx->msrLSTAR,
1716	pCtx->msrSFMASK,
1717	pCtx->msrKERNELGSBASE));
1718
1719	}
1720	#endif /* VBOX_STRICT */
1721
1722	/* Dummy callback handlers. */
1723	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
1724	{
1725	return VINF_SUCCESS;
1726	}
1727
1728	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1729	{
1730	return VINF_SUCCESS;
1731	}
1732
1733	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1734	{
1735	return VINF_SUCCESS;
1736	}
1737
1738	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1739	{
1740	return VINF_SUCCESS;
1741	}
1742
1743	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM)
1744	{
1745	return VINF_SUCCESS;
1746	}
1747
1748	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM)
1749	{
1750	return VINF_SUCCESS;
1751	}
1752
1753	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM)
1754	{
1755	return VINF_SUCCESS;
1756	}
1757
1758	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1759	{
1760	return VINF_SUCCESS;
1761	}
1762
1763	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
1764	{
1765	return VINF_SUCCESS;
1766	}
1767
1768	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1769	{
1770	return VINF_SUCCESS;
1771	}

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp@ 24760

Download in other formats: