HWACCMR0.cpp@ 28137

Last change on this file since 28137 was 27630, checked in by vboxsync, 15 years ago
PGM,HWACCM: Fix for panic on 32-bit mac os x when using nested paging. The dynamic mapping set was used without being started during HWACCMR0Enter by VMXR0LoadGuestState/vmxR0PrefetchPAEPdptrs. The fix is to start + stop it in HWACCMR0Enter. (defect 4741)
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File size: 65.5 KB

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1	/* $Id: HWACCMR0.cpp 27630 2010-03-23 13:48:50Z vboxsync $ */
2	/** @file
3	* HWACCM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include <VBox/pgm.h>
29	#include "HWACCMInternal.h"
30	#include <VBox/vm.h>
31	#include <VBox/x86.h>
32	#include <VBox/hwacc_vmx.h>
33	#include <VBox/hwacc_svm.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <iprt/assert.h>
37	#include <iprt/asm.h>
38	#include <iprt/cpuset.h>
39	#include <iprt/memobj.h>
40	#include <iprt/param.h>
41	#include <iprt/power.h>
42	#include <iprt/string.h>
43	#include <iprt/thread.h>
44	#include "HWVMXR0.h"
45	#include "HWSVMR0.h"
46
47	/*******************************************************************************
48	* Internal Functions *
49	*******************************************************************************/
50	static DECLCALLBACK(void) hwaccmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static DECLCALLBACK(void) hwaccmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static int hwaccmR0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu);
54	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
55
56	/*******************************************************************************
57	* Global Variables *
58	*******************************************************************************/
59
60	static struct
61	{
62	HWACCM_CPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
63
64	/** Ring 0 handlers for VT-x and AMD-V. */
65	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu));
66	DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
67	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
68	DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
69	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
70	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
71	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
72	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
73	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
74	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVM pVM));
75
76	/** Maximum ASID allowed. */
77	uint32_t uMaxASID;
78
79	struct
80	{
81	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
82	bool fSupported;
83	/** Whether we're using SUPR0EnableVTx or not. */
84	bool fUsingSUPR0EnableVTx;
85
86	/** Host CR4 value (set by ring-0 VMX init) */
87	uint64_t hostCR4;
88
89	/** Host EFER value (set by ring-0 VMX init) */
90	uint64_t hostEFER;
91
92	/** VMX MSR values */
93	struct
94	{
95	uint64_t feature_ctrl;
96	uint64_t vmx_basic_info;
97	VMX_CAPABILITY vmx_pin_ctls;
98	VMX_CAPABILITY vmx_proc_ctls;
99	VMX_CAPABILITY vmx_proc_ctls2;
100	VMX_CAPABILITY vmx_exit;
101	VMX_CAPABILITY vmx_entry;
102	uint64_t vmx_misc;
103	uint64_t vmx_cr0_fixed0;
104	uint64_t vmx_cr0_fixed1;
105	uint64_t vmx_cr4_fixed0;
106	uint64_t vmx_cr4_fixed1;
107	uint64_t vmx_vmcs_enum;
108	uint64_t vmx_eptcaps;
109	} msr;
110	/* Last instruction error */
111	uint32_t ulLastInstrError;
112	} vmx;
113	struct
114	{
115	/* HWCR msr (for diagnostics) */
116	uint64_t msrHWCR;
117
118	/** SVM revision. */
119	uint32_t u32Rev;
120
121	/** SVM feature bits from cpuid 0x8000000a */
122	uint32_t u32Features;
123
124	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
125	bool fSupported;
126	} svm;
127	/** Saved error from detection */
128	int32_t lLastError;
129
130	struct
131	{
132	uint32_t u32AMDFeatureECX;
133	uint32_t u32AMDFeatureEDX;
134	} cpuid;
135
136	HWACCMSTATE enmHwAccmState;
137
138	bool fGlobalInit;
139	volatile bool fSuspended;
140	} HWACCMR0Globals;
141
142
143
144	/**
145	* Does global Ring-0 HWACCM initialization.
146	*
147	* @returns VBox status code.
148	*/
149	VMMR0DECL(int) HWACCMR0Init(void)
150	{
151	int rc;
152	bool fAMDVPresent = false;
153
154	memset(&HWACCMR0Globals, 0, sizeof(HWACCMR0Globals));
155	HWACCMR0Globals.enmHwAccmState = HWACCMSTATE_UNINITIALIZED;
156	for (unsigned i = 0; i < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); i++)
157	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
158
159	/* Fill in all callbacks with placeholders. */
160	HWACCMR0Globals.pfnEnterSession = HWACCMR0DummyEnter;
161	HWACCMR0Globals.pfnLeaveSession = HWACCMR0DummyLeave;
162	HWACCMR0Globals.pfnSaveHostState = HWACCMR0DummySaveHostState;
163	HWACCMR0Globals.pfnLoadGuestState = HWACCMR0DummyLoadGuestState;
164	HWACCMR0Globals.pfnRunGuestCode = HWACCMR0DummyRunGuestCode;
165	HWACCMR0Globals.pfnEnableCpu = HWACCMR0DummyEnableCpu;
166	HWACCMR0Globals.pfnDisableCpu = HWACCMR0DummyDisableCpu;
167	HWACCMR0Globals.pfnInitVM = HWACCMR0DummyInitVM;
168	HWACCMR0Globals.pfnTermVM = HWACCMR0DummyTermVM;
169	HWACCMR0Globals.pfnSetupVM = HWACCMR0DummySetupVM;
170
171	/* Default is global VT-x/AMD-V init */
172	HWACCMR0Globals.fGlobalInit = true;
173
174	/*
175	* Check for VT-x and AMD-V capabilities
176	*/
177	if (ASMHasCpuId())
178	{
179	uint32_t u32FeaturesECX;
180	uint32_t u32Dummy;
181	uint32_t u32FeaturesEDX;
182	uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
183
184	ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
185	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
186	/* Query AMD features. */
187	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy, &HWACCMR0Globals.cpuid.u32AMDFeatureECX, &HWACCMR0Globals.cpuid.u32AMDFeatureEDX);
188
189	if ( u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
190	&& u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
191	&& u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX
192	)
193	{
194	/*
195	* Read all VMX MSRs if VMX is available. (same goes for RDMSR/WRMSR)
196	* We also assume all VMX-enabled CPUs support fxsave/fxrstor.
197	*/
198	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
199	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
200	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
201	)
202	{
203	int aRc[RTCPUSET_MAX_CPUS];
204	RTCPUID idCpu = 0;
205
206	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
207
208	/*
209	* First try use native kernel API for controlling VT-x.
210	* (This is only supported by some Mac OS X kernels atm.)
211	*/
212	HWACCMR0Globals.lLastError = rc = SUPR0EnableVTx(true /* fEnable */);
213	if (rc != VERR_NOT_SUPPORTED)
214	{
215	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
216	HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx = true;
217	if (RT_SUCCESS(rc))
218	{
219	HWACCMR0Globals.vmx.fSupported = true;
220	rc = SUPR0EnableVTx(false /* fEnable */);
221	AssertRC(rc);
222	}
223	}
224	else
225	{
226	HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx = false;
227
228	/* We need to check if VT-x has been properly initialized on all CPUs. Some BIOSes do a lousy job. */
229	memset(aRc, 0, sizeof(aRc));
230	HWACCMR0Globals.lLastError = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
231
232	/* Check the return code of all invocations. */
233	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
234	HWACCMR0Globals.lLastError = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
235	}
236	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
237	{
238	/* Reread in case we've changed it. */
239	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
240
241	if ( (HWACCMR0Globals.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
242	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
243	{
244	RTR0MEMOBJ pScatchMemObj;
245	void *pvScatchPage;
246	RTHCPHYS pScatchPagePhys;
247
248	HWACCMR0Globals.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
249	HWACCMR0Globals.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
250	HWACCMR0Globals.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
251	HWACCMR0Globals.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
252	HWACCMR0Globals.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
253	HWACCMR0Globals.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
254	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
255	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
256	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
257	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
258	HWACCMR0Globals.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
259	/* VPID 16 bits ASID. */
260	HWACCMR0Globals.uMaxASID = 0x10000; /* exclusive */
261
262	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
263	{
264	HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
265	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT\|VMX_VMCS_CTRL_PROC_EXEC2_VPID))
266	HWACCMR0Globals.vmx.msr.vmx_eptcaps = ASMRdMsr(MSR_IA32_VMX_EPT_CAPS);
267	}
268
269	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
270	{
271	HWACCMR0Globals.vmx.hostCR4 = ASMGetCR4();
272	HWACCMR0Globals.vmx.hostEFER = ASMRdMsr(MSR_K6_EFER);
273
274	rc = RTR0MemObjAllocCont(&pScatchMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
275	if (RT_FAILURE(rc))
276	return rc;
277
278	pvScatchPage = RTR0MemObjAddress(pScatchMemObj);
279	pScatchPagePhys = RTR0MemObjGetPagePhysAddr(pScatchMemObj, 0);
280	memset(pvScatchPage, 0, PAGE_SIZE);
281
282	/* Set revision dword at the beginning of the structure. */
283	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(HWACCMR0Globals.vmx.msr.vmx_basic_info);
284
285	/* Make sure we don't get rescheduled to another cpu during this probe. */
286	RTCCUINTREG fFlags = ASMIntDisableFlags();
287
288	/*
289	* Check CR4.VMXE
290	*/
291	if (!(HWACCMR0Globals.vmx.hostCR4 & X86_CR4_VMXE))
292	{
293	/* In theory this bit could be cleared behind our back. Which would cause #UD faults when we
294	* try to execute the VMX instructions...
295	*/
296	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4 \| X86_CR4_VMXE);
297	}
298
299	/* Enter VMX Root Mode */
300	rc = VMXEnable(pScatchPagePhys);
301	if (RT_FAILURE(rc))
302	{
303	/* KVM leaves the CPU in VMX root mode. Not only is this not allowed, it will crash the host when we enter raw mode, because
304	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify this bit)
305	* (b) turning off paging causes a #GP (unavoidable when switching from long to 32 bits mode or 32 bits to PAE)
306	*
307	* They should fix their code, but until they do we simply refuse to run.
308	*/
309	HWACCMR0Globals.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
310	}
311	else
312	{
313	HWACCMR0Globals.vmx.fSupported = true;
314	VMXDisable();
315	}
316
317	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it wasn't so before (some software could incorrectly think it's in VMX mode) */
318	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4);
319	ASMSetFlags(fFlags);
320
321	RTR0MemObjFree(pScatchMemObj, false);
322	if (RT_FAILURE(HWACCMR0Globals.lLastError))
323	return HWACCMR0Globals.lLastError;
324	}
325	}
326	else
327	{
328	AssertFailed(); /* can't hit this case anymore */
329	HWACCMR0Globals.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
330	}
331	}
332	#ifdef LOG_ENABLED
333	else
334	SUPR0Printf("HWACCMR0InitCPU failed with rc=%d\n", HWACCMR0Globals.lLastError);
335	#endif
336	}
337	else
338	HWACCMR0Globals.lLastError = VERR_VMX_NO_VMX;
339	}
340	else
341	if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
342	&& u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
343	&& u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX
344	)
345	{
346	/*
347	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
348	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
349	*/
350	if ( (HWACCMR0Globals.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
351	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
352	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
353	)
354	{
355	int aRc[RTCPUSET_MAX_CPUS];
356	RTCPUID idCpu = 0;
357
358	fAMDVPresent = true;
359
360	/* Query AMD features. */
361	ASMCpuId(0x8000000A, &HWACCMR0Globals.svm.u32Rev, &HWACCMR0Globals.uMaxASID, &u32Dummy, &HWACCMR0Globals.svm.u32Features);
362
363	/* We need to check if AMD-V has been properly initialized on all CPUs. Some BIOSes might do a poor job. */
364	memset(aRc, 0, sizeof(aRc));
365	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
366	AssertRC(rc);
367
368	/* Check the return code of all invocations. */
369	if (RT_SUCCESS(rc))
370	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
371
372	#ifndef DEBUG_bird
373	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE, ("HWACCMR0InitCPU failed for cpu %d with rc=%d\n", idCpu, rc));
374	#endif
375	if (RT_SUCCESS(rc))
376	{
377	/* Read the HWCR msr for diagnostics. */
378	HWACCMR0Globals.svm.msrHWCR = ASMRdMsr(MSR_K8_HWCR);
379	HWACCMR0Globals.svm.fSupported = true;
380	}
381	else
382	HWACCMR0Globals.lLastError = rc;
383	}
384	else
385	HWACCMR0Globals.lLastError = VERR_SVM_NO_SVM;
386	}
387	else
388	HWACCMR0Globals.lLastError = VERR_HWACCM_UNKNOWN_CPU;
389	}
390	else
391	HWACCMR0Globals.lLastError = VERR_HWACCM_NO_CPUID;
392
393	if (HWACCMR0Globals.vmx.fSupported)
394	{
395	HWACCMR0Globals.pfnEnterSession = VMXR0Enter;
396	HWACCMR0Globals.pfnLeaveSession = VMXR0Leave;
397	HWACCMR0Globals.pfnSaveHostState = VMXR0SaveHostState;
398	HWACCMR0Globals.pfnLoadGuestState = VMXR0LoadGuestState;
399	HWACCMR0Globals.pfnRunGuestCode = VMXR0RunGuestCode;
400	HWACCMR0Globals.pfnEnableCpu = VMXR0EnableCpu;
401	HWACCMR0Globals.pfnDisableCpu = VMXR0DisableCpu;
402	HWACCMR0Globals.pfnInitVM = VMXR0InitVM;
403	HWACCMR0Globals.pfnTermVM = VMXR0TermVM;
404	HWACCMR0Globals.pfnSetupVM = VMXR0SetupVM;
405	}
406	else
407	if (fAMDVPresent)
408	{
409	HWACCMR0Globals.pfnEnterSession = SVMR0Enter;
410	HWACCMR0Globals.pfnLeaveSession = SVMR0Leave;
411	HWACCMR0Globals.pfnSaveHostState = SVMR0SaveHostState;
412	HWACCMR0Globals.pfnLoadGuestState = SVMR0LoadGuestState;
413	HWACCMR0Globals.pfnRunGuestCode = SVMR0RunGuestCode;
414	HWACCMR0Globals.pfnEnableCpu = SVMR0EnableCpu;
415	HWACCMR0Globals.pfnDisableCpu = SVMR0DisableCpu;
416	HWACCMR0Globals.pfnInitVM = SVMR0InitVM;
417	HWACCMR0Globals.pfnTermVM = SVMR0TermVM;
418	HWACCMR0Globals.pfnSetupVM = SVMR0SetupVM;
419	}
420
421	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
422	{
423	rc = RTPowerNotificationRegister(hwaccmR0PowerCallback, 0);
424	AssertRC(rc);
425	}
426
427	return VINF_SUCCESS;
428	}
429
430
431	/**
432	* Checks the error code array filled in for each cpu in the system.
433	*
434	* @returns VBox status code.
435	* @param paRc Error code array
436	* @param cErrorCodes Array size
437	* @param pidCpu Value of the first cpu that set an error (out)
438	*/
439	static int hwaccmR0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu)
440	{
441	int rc = VINF_SUCCESS;
442
443	Assert(cErrorCodes == RTCPUSET_MAX_CPUS);
444
445	for (unsigned i=0;i<cErrorCodes;i++)
446	{
447	if (RTMpIsCpuOnline(i))
448	{
449	if (RT_FAILURE(paRc[i]))
450	{
451	rc = paRc[i];
452	*pidCpu = i;
453	break;
454	}
455	}
456	}
457	return rc;
458	}
459
460	/**
461	* Does global Ring-0 HWACCM termination.
462	*
463	* @returns VBox status code.
464	*/
465	VMMR0DECL(int) HWACCMR0Term(void)
466	{
467	int rc;
468	if ( HWACCMR0Globals.vmx.fSupported
469	&& HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
470	{
471	Assert(HWACCMR0Globals.fGlobalInit);
472	rc = SUPR0EnableVTx(false /* fEnable */);
473	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); iCpu++)
474	{
475	HWACCMR0Globals.aCpuInfo[iCpu].fConfigured = false;
476	Assert(HWACCMR0Globals.aCpuInfo[iCpu].pMemObj == NIL_RTR0MEMOBJ);
477	}
478	}
479	else
480	{
481	Assert(!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
482	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
483	{
484	rc = RTPowerNotificationDeregister(hwaccmR0PowerCallback, 0);
485	AssertRC(rc);
486	}
487	else
488	rc = VINF_SUCCESS;
489
490	/* Only disable VT-x/AMD-V on all CPUs if we enabled it before. */
491	if (HWACCMR0Globals.fGlobalInit)
492	{
493	int aRc[RTCPUSET_MAX_CPUS];
494
495	memset(aRc, 0, sizeof(aRc));
496	rc = RTMpOnAll(hwaccmR0DisableCpuCallback, aRc, NULL);
497	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
498	#ifdef VBOX_STRICT
499	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
500	AssertMsgRC(aRc[i], ("hwaccmR0DisableCpuCallback failed for cpu %d with rc=%d\n", i, aRc[i]));
501	#endif
502	}
503
504	/* Free the per-cpu pages used for VT-x and AMD-V */
505	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
506	{
507	if (HWACCMR0Globals.aCpuInfo[i].pMemObj != NIL_RTR0MEMOBJ)
508	{
509	RTR0MemObjFree(HWACCMR0Globals.aCpuInfo[i].pMemObj, false);
510	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
511	}
512	}
513	}
514	return rc;
515	}
516
517
518	/**
519	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
520	* is to be called on the target cpus.
521	*
522	* @param idCpu The identifier for the CPU the function is called on.
523	* @param pvUser1 The 1st user argument.
524	* @param pvUser2 The 2nd user argument.
525	*/
526	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
527	{
528	unsigned u32VendorEBX = (uintptr_t)pvUser1;
529	int paRc = (int )pvUser2;
530	uint64_t val;
531
532	#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
533	SUPR0Printf("HWACCMR0InitCPU cpu %d\n", idCpu);
534	#endif
535	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
536
537	if (u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX)
538	{
539	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
540
541	/*
542	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
543	* Once the lock bit is set, this MSR can no longer be modified.
544	*/
545	if ( !(val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
546	\|\| ((val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK)) == MSR_IA32_FEATURE_CONTROL_VMXON) /* Some BIOSes forget to set the locked bit. */
547	)
548	{
549	/* MSR is not yet locked; we can change it ourselves here */
550	ASMWrMsr(MSR_IA32_FEATURE_CONTROL, HWACCMR0Globals.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
551	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
552	}
553	if ( (val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
554	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
555	paRc[idCpu] = VINF_SUCCESS;
556	else
557	paRc[idCpu] = VERR_VMX_MSR_LOCKED_OR_DISABLED;
558	}
559	else
560	if (u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX)
561	{
562	/* Check if SVM is disabled */
563	val = ASMRdMsr(MSR_K8_VM_CR);
564	if (!(val & MSR_K8_VM_CR_SVM_DISABLE))
565	{
566	/* Turn on SVM in the EFER MSR. */
567	val = ASMRdMsr(MSR_K6_EFER);
568	if (val & MSR_K6_EFER_SVME)
569	{
570	paRc[idCpu] = VERR_SVM_IN_USE;
571	}
572	else
573	{
574	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
575
576	/* Paranoia. */
577	val = ASMRdMsr(MSR_K6_EFER);
578	if (val & MSR_K6_EFER_SVME)
579	{
580	/* Restore previous value. */
581	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
582	paRc[idCpu] = VINF_SUCCESS;
583	}
584	else
585	paRc[idCpu] = VERR_SVM_ILLEGAL_EFER_MSR;
586	}
587	}
588	else
589	paRc[idCpu] = VERR_SVM_DISABLED;
590	}
591	else
592	AssertFailed(); /* can't happen */
593	return;
594	}
595
596
597	/**
598	* Sets up HWACCM on all cpus.
599	*
600	* @returns VBox status code.
601	* @param pVM The VM to operate on.
602	*
603	*/
604	VMMR0DECL(int) HWACCMR0EnableAllCpus(PVM pVM)
605	{
606	AssertCompile(sizeof(HWACCMR0Globals.enmHwAccmState) == sizeof(uint32_t));
607
608	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
609	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
610	return VERR_HWACCM_SUSPEND_PENDING;
611
612	if (ASMAtomicCmpXchgU32((volatile uint32_t *)&HWACCMR0Globals.enmHwAccmState, HWACCMSTATE_ENABLED, HWACCMSTATE_UNINITIALIZED))
613	{
614	int rc;
615
616	HWACCMR0Globals.fGlobalInit = pVM->hwaccm.s.fGlobalInit;
617
618	if ( HWACCMR0Globals.vmx.fSupported
619	&& HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
620	{
621	rc = SUPR0EnableVTx(true /* fEnable */);
622	if (RT_SUCCESS(rc))
623	{
624	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); iCpu++)
625	{
626	HWACCMR0Globals.aCpuInfo[iCpu].fConfigured = true;
627	Assert(HWACCMR0Globals.aCpuInfo[iCpu].pMemObj == NIL_RTR0MEMOBJ);
628	}
629	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
630	HWACCMR0Globals.fGlobalInit = pVM->hwaccm.s.fGlobalInit = true;
631	}
632	else
633	AssertMsgFailed(("HWACCMR0EnableAllCpus/SUPR0EnableVTx: rc=%Rrc\n", rc));
634	}
635	else
636	{
637	int aRc[RTCPUSET_MAX_CPUS];
638	RTCPUID idCpu = 0;
639
640	memset(aRc, 0, sizeof(aRc));
641
642	/* Allocate one page per cpu for the global vt-x and amd-v pages */
643	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
644	{
645	Assert(!HWACCMR0Globals.aCpuInfo[i].pMemObj);
646
647	/** @todo this is rather dangerous if cpus can be taken offline; we don't care for now */
648	if (RTMpIsCpuOnline(i))
649	{
650	rc = RTR0MemObjAllocCont(&HWACCMR0Globals.aCpuInfo[i].pMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
651	AssertRC(rc);
652	if (RT_FAILURE(rc))
653	return rc;
654
655	void *pvR0 = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[i].pMemObj);
656	Assert(pvR0);
657	ASMMemZeroPage(pvR0);
658
659	#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
660	SUPR0Printf("address %x phys %x\n", pvR0, (uint32_t)RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[i].pMemObj, 0));
661	#endif
662	}
663	}
664	if (HWACCMR0Globals.fGlobalInit)
665	{
666	/* First time, so initialize each cpu/core */
667	rc = RTMpOnAll(hwaccmR0EnableCpuCallback, (void *)pVM, aRc);
668
669	/* Check the return code of all invocations. */
670	if (RT_SUCCESS(rc))
671	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
672	AssertMsgRC(rc, ("HWACCMR0EnableAllCpus failed for cpu %d with rc=%d\n", idCpu, rc));
673	}
674	else
675	rc = VINF_SUCCESS;
676	}
677
678	return rc;
679	}
680	return VINF_SUCCESS;
681	}
682
683	/**
684	* Disable VT-x or AMD-V on the current CPU
685	*
686	* @returns VBox status code.
687	* @param pVM VM handle (can be 0!)
688	* @param idCpu The identifier for the CPU the function is called on.
689	*/
690	static int hwaccmR0EnableCpu(PVM pVM, RTCPUID idCpu)
691	{
692	void *pvPageCpu;
693	RTHCPHYS pPageCpuPhys;
694	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
695
696	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
697	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
698	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
699	Assert(!pCpu->fConfigured);
700	Assert(!HWACCMR0Globals.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
701
702	pCpu->idCpu = idCpu;
703
704	/* Make sure we start with a clean TLB. */
705	pCpu->fFlushTLB = true;
706
707	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
708	pCpu->cTLBFlushes = 0;
709
710	/* Should never happen */
711	if (!pCpu->pMemObj)
712	{
713	AssertFailed();
714	return VERR_INTERNAL_ERROR;
715	}
716
717	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
718	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
719
720	int rc = HWACCMR0Globals.pfnEnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
721	AssertRC(rc);
722	if (RT_SUCCESS(rc))
723	pCpu->fConfigured = true;
724
725	return rc;
726	}
727
728
729	/**
730	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
731	* is to be called on the target cpus.
732	*
733	* @param idCpu The identifier for the CPU the function is called on.
734	* @param pvUser1 The 1st user argument.
735	* @param pvUser2 The 2nd user argument.
736	*/
737	static DECLCALLBACK(void) hwaccmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
738	{
739	PVM pVM = (PVM)pvUser1; /* can be NULL! */
740	int paRc = (int )pvUser2;
741
742	if (!HWACCMR0Globals.fGlobalInit)
743	{
744	paRc[idCpu] = VINF_SUCCESS;
745	AssertFailed();
746	return;
747	}
748
749	paRc[idCpu] = hwaccmR0EnableCpu(pVM, idCpu);
750	}
751
752
753	/**
754	* Disable VT-x or AMD-V on the current CPU
755	*
756	* @returns VBox status code.
757	* @param idCpu The identifier for the CPU the function is called on.
758	*/
759	static int hwaccmR0DisableCpu(RTCPUID idCpu)
760	{
761	void *pvPageCpu;
762	RTHCPHYS pPageCpuPhys;
763	int rc;
764	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
765
766	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
767	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
768	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
769	Assert(!HWACCMR0Globals.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
770	Assert(!pCpu->fConfigured \|\| pCpu->pMemObj);
771
772	if (!pCpu->pMemObj)
773	return (pCpu->fConfigured) ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
774
775	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
776	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
777
778	if (pCpu->fConfigured)
779	{
780	rc = HWACCMR0Globals.pfnDisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
781	AssertRC(rc);
782	pCpu->fConfigured = false;
783	}
784	else
785	rc = VINF_SUCCESS; /* nothing to do */
786
787	pCpu->uCurrentASID = 0;
788	return rc;
789	}
790
791	/**
792	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
793	* is to be called on the target cpus.
794	*
795	* @param idCpu The identifier for the CPU the function is called on.
796	* @param pvUser1 The 1st user argument.
797	* @param pvUser2 The 2nd user argument.
798	*/
799	static DECLCALLBACK(void) hwaccmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
800	{
801	int paRc = (int )pvUser1;
802
803	if (!HWACCMR0Globals.fGlobalInit)
804	{
805	paRc[idCpu] = VINF_SUCCESS;
806	AssertFailed();
807	return;
808	}
809
810	paRc[idCpu] = hwaccmR0DisableCpu(idCpu);
811	}
812
813	/**
814	* Called whenever a system power state change occurs.
815	*
816	* @param enmEvent Power event
817	* @param pvUser User argument
818	*/
819	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
820	{
821	NOREF(pvUser);
822	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
823
824	#ifdef LOG_ENABLED
825	if (enmEvent == RTPOWEREVENT_SUSPEND)
826	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
827	else
828	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_RESUME\n");
829	#endif
830
831	if (enmEvent == RTPOWEREVENT_SUSPEND)
832	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, true);
833
834	if (HWACCMR0Globals.enmHwAccmState == HWACCMSTATE_ENABLED)
835	{
836	int aRc[RTCPUSET_MAX_CPUS];
837	int rc;
838	RTCPUID idCpu;
839
840	memset(aRc, 0, sizeof(aRc));
841	if (enmEvent == RTPOWEREVENT_SUSPEND)
842	{
843	if (HWACCMR0Globals.fGlobalInit)
844	{
845	/* Turn off VT-x or AMD-V on all CPUs. */
846	rc = RTMpOnAll(hwaccmR0DisableCpuCallback, aRc, NULL);
847	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
848	}
849	/* else nothing to do here for the local init case */
850	}
851	else
852	{
853	/* Reinit the CPUs from scratch as the suspend state might have messed with the MSRs. (lousy BIOSes as usual) */
854	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)((HWACCMR0Globals.vmx.fSupported) ? X86_CPUID_VENDOR_INTEL_EBX : X86_CPUID_VENDOR_AMD_EBX), aRc);
855	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
856
857	if (RT_SUCCESS(rc))
858	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
859	#ifdef LOG_ENABLED
860	if (RT_FAILURE(rc))
861	SUPR0Printf("hwaccmR0PowerCallback HWACCMR0InitCPU failed with %d\n", rc);
862	#endif
863
864	if (HWACCMR0Globals.fGlobalInit)
865	{
866	/* Turn VT-x or AMD-V back on on all CPUs. */
867	rc = RTMpOnAll(hwaccmR0EnableCpuCallback, NULL, aRc);
868	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
869	}
870	/* else nothing to do here for the local init case */
871	}
872	}
873	if (enmEvent == RTPOWEREVENT_RESUME)
874	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, false);
875	}
876
877
878	/**
879	* Does Ring-0 per VM HWACCM initialization.
880	*
881	* This is mainly to check that the Host CPU mode is compatible
882	* with VMX.
883	*
884	* @returns VBox status code.
885	* @param pVM The VM to operate on.
886	*/
887	VMMR0DECL(int) HWACCMR0InitVM(PVM pVM)
888	{
889	int rc;
890
891	AssertReturn(pVM, VERR_INVALID_PARAMETER);
892
893	#ifdef LOG_ENABLED
894	SUPR0Printf("HWACCMR0InitVM: %p\n", pVM);
895	#endif
896
897	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
898	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
899	return VERR_HWACCM_SUSPEND_PENDING;
900
901	pVM->hwaccm.s.vmx.fSupported = HWACCMR0Globals.vmx.fSupported;
902	pVM->hwaccm.s.svm.fSupported = HWACCMR0Globals.svm.fSupported;
903
904	pVM->hwaccm.s.vmx.msr.feature_ctrl = HWACCMR0Globals.vmx.msr.feature_ctrl;
905	pVM->hwaccm.s.vmx.hostCR4 = HWACCMR0Globals.vmx.hostCR4;
906	pVM->hwaccm.s.vmx.hostEFER = HWACCMR0Globals.vmx.hostEFER;
907	pVM->hwaccm.s.vmx.msr.vmx_basic_info = HWACCMR0Globals.vmx.msr.vmx_basic_info;
908	pVM->hwaccm.s.vmx.msr.vmx_pin_ctls = HWACCMR0Globals.vmx.msr.vmx_pin_ctls;
909	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls = HWACCMR0Globals.vmx.msr.vmx_proc_ctls;
910	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2 = HWACCMR0Globals.vmx.msr.vmx_proc_ctls2;
911	pVM->hwaccm.s.vmx.msr.vmx_exit = HWACCMR0Globals.vmx.msr.vmx_exit;
912	pVM->hwaccm.s.vmx.msr.vmx_entry = HWACCMR0Globals.vmx.msr.vmx_entry;
913	pVM->hwaccm.s.vmx.msr.vmx_misc = HWACCMR0Globals.vmx.msr.vmx_misc;
914	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0;
915	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1;
916	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0;
917	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1;
918	pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum = HWACCMR0Globals.vmx.msr.vmx_vmcs_enum;
919	pVM->hwaccm.s.vmx.msr.vmx_eptcaps = HWACCMR0Globals.vmx.msr.vmx_eptcaps;
920	pVM->hwaccm.s.svm.msrHWCR = HWACCMR0Globals.svm.msrHWCR;
921	pVM->hwaccm.s.svm.u32Rev = HWACCMR0Globals.svm.u32Rev;
922	pVM->hwaccm.s.svm.u32Features = HWACCMR0Globals.svm.u32Features;
923	pVM->hwaccm.s.cpuid.u32AMDFeatureECX = HWACCMR0Globals.cpuid.u32AMDFeatureECX;
924	pVM->hwaccm.s.cpuid.u32AMDFeatureEDX = HWACCMR0Globals.cpuid.u32AMDFeatureEDX;
925	pVM->hwaccm.s.lLastError = HWACCMR0Globals.lLastError;
926
927	pVM->hwaccm.s.uMaxASID = HWACCMR0Globals.uMaxASID;
928
929
930	if (!pVM->hwaccm.s.cMaxResumeLoops) /* allow ring-3 overrides */
931	{
932	pVM->hwaccm.s.cMaxResumeLoops = 1024;
933	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
934	if (RTThreadPreemptIsPendingTrusty())
935	pVM->hwaccm.s.cMaxResumeLoops = 8192;
936	#endif
937	}
938
939	for (VMCPUID i = 0; i < pVM->cCpus; i++)
940	{
941	PVMCPU pVCpu = &pVM->aCpus[i];
942
943	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
944
945	/* Invalidate the last cpu we were running on. */
946	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
947
948	/* we'll aways increment this the first time (host uses ASID 0) */
949	pVCpu->hwaccm.s.uCurrentASID = 0;
950	}
951
952	RTCCUINTREG fFlags = ASMIntDisableFlags();
953	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
954
955	/* Note: Not correct as we can be rescheduled to a different cpu, but the fInUse case is mostly for debugging. */
956	ASMAtomicWriteBool(&pCpu->fInUse, true);
957	ASMSetFlags(fFlags);
958
959	/* Init a VT-x or AMD-V VM. */
960	rc = HWACCMR0Globals.pfnInitVM(pVM);
961
962	ASMAtomicWriteBool(&pCpu->fInUse, false);
963	return rc;
964	}
965
966
967	/**
968	* Does Ring-0 per VM HWACCM termination.
969	*
970	* @returns VBox status code.
971	* @param pVM The VM to operate on.
972	*/
973	VMMR0DECL(int) HWACCMR0TermVM(PVM pVM)
974	{
975	int rc;
976
977	AssertReturn(pVM, VERR_INVALID_PARAMETER);
978
979	#ifdef LOG_ENABLED
980	SUPR0Printf("HWACCMR0TermVM: %p\n", pVM);
981	#endif
982
983	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
984	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
985
986	/* @note Not correct as we can be rescheduled to a different cpu, but the fInUse case is mostly for debugging. */
987	RTCCUINTREG fFlags = ASMIntDisableFlags();
988	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
989
990	ASMAtomicWriteBool(&pCpu->fInUse, true);
991	ASMSetFlags(fFlags);
992
993	/* Terminate a VT-x or AMD-V VM. */
994	rc = HWACCMR0Globals.pfnTermVM(pVM);
995
996	ASMAtomicWriteBool(&pCpu->fInUse, false);
997	return rc;
998	}
999
1000
1001	/**
1002	* Sets up a VT-x or AMD-V session
1003	*
1004	* @returns VBox status code.
1005	* @param pVM The VM to operate on.
1006	*/
1007	VMMR0DECL(int) HWACCMR0SetupVM(PVM pVM)
1008	{
1009	int rc;
1010	RTCPUID idCpu = RTMpCpuId();
1011	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1012
1013	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1014
1015	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
1016	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1017
1018	#ifdef LOG_ENABLED
1019	SUPR0Printf("HWACCMR0SetupVM: %p\n", pVM);
1020	#endif
1021
1022	ASMAtomicWriteBool(&pCpu->fInUse, true);
1023
1024	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1025	{
1026	/* On first entry we'll sync everything. */
1027	pVM->aCpus[i].hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1028	}
1029
1030	/* Enable VT-x or AMD-V if local init is required. */
1031	if (!HWACCMR0Globals.fGlobalInit)
1032	{
1033	rc = hwaccmR0EnableCpu(pVM, idCpu);
1034	AssertRCReturn(rc, rc);
1035	}
1036
1037	/* Setup VT-x or AMD-V. */
1038	rc = HWACCMR0Globals.pfnSetupVM(pVM);
1039
1040	/* Disable VT-x or AMD-V if local init was done before. */
1041	if (!HWACCMR0Globals.fGlobalInit)
1042	{
1043	rc = hwaccmR0DisableCpu(idCpu);
1044	AssertRC(rc);
1045	}
1046
1047	ASMAtomicWriteBool(&pCpu->fInUse, false);
1048
1049	return rc;
1050	}
1051
1052
1053	/**
1054	* Enters the VT-x or AMD-V session
1055	*
1056	* @returns VBox status code.
1057	* @param pVM The VM to operate on.
1058	* @param pVCpu VMCPUD id.
1059	*/
1060	VMMR0DECL(int) HWACCMR0Enter(PVM pVM, PVMCPU pVCpu)
1061	{
1062	PCPUMCTX pCtx;
1063	int rc;
1064	RTCPUID idCpu = RTMpCpuId();
1065	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1066
1067	/* Make sure we can't enter a session after we've disabled hwaccm in preparation of a suspend. */
1068	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1069	ASMAtomicWriteBool(&pCpu->fInUse, true);
1070
1071	AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == NIL_RTCPUID, ("%d", (int)pVCpu->hwaccm.s.idEnteredCpu));
1072	pVCpu->hwaccm.s.idEnteredCpu = idCpu;
1073
1074	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1075
1076	/* Always load the guest's FPU/XMM state on-demand. */
1077	CPUMDeactivateGuestFPUState(pVCpu);
1078
1079	/* Always load the guest's debug state on-demand. */
1080	CPUMDeactivateGuestDebugState(pVCpu);
1081
1082	/* Always reload the host context and the guest's CR0 register. (!!!!) */
1083	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0 \| HWACCM_CHANGED_HOST_CONTEXT;
1084
1085	/* Setup the register and mask according to the current execution mode. */
1086	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1087	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFFFFFFFFFF);
1088	else
1089	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFF);
1090
1091	/* Enable VT-x or AMD-V if local init is required. */
1092	if (!HWACCMR0Globals.fGlobalInit)
1093	{
1094	rc = hwaccmR0EnableCpu(pVM, idCpu);
1095	AssertRCReturn(rc, rc);
1096	}
1097
1098	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1099	bool fStartedSet = PGMDynMapStartOrMigrateAutoSet(pVCpu);
1100	#endif
1101
1102	rc = HWACCMR0Globals.pfnEnterSession(pVM, pVCpu, pCpu);
1103	AssertRC(rc);
1104	/* We must save the host context here (VT-x) as we might be rescheduled on a different cpu after a long jump back to ring 3. */
1105	rc \|= HWACCMR0Globals.pfnSaveHostState(pVM, pVCpu);
1106	AssertRC(rc);
1107	rc \|= HWACCMR0Globals.pfnLoadGuestState(pVM, pVCpu, pCtx);
1108	AssertRC(rc);
1109
1110	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1111	if (fStartedSet)
1112	PGMDynMapReleaseAutoSet(pVCpu);
1113	#endif
1114
1115	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1116	if (RT_FAILURE(rc))
1117	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1118	return rc;
1119	}
1120
1121
1122	/**
1123	* Leaves the VT-x or AMD-V session
1124	*
1125	* @returns VBox status code.
1126	* @param pVM The VM to operate on.
1127	* @param pVCpu VMCPUD id.
1128	*/
1129	VMMR0DECL(int) HWACCMR0Leave(PVM pVM, PVMCPU pVCpu)
1130	{
1131	PCPUMCTX pCtx;
1132	int rc;
1133	RTCPUID idCpu = RTMpCpuId();
1134	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1135
1136	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1137
1138	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1139
1140	/* Note: It's rather tricky with longjmps done by e.g. Log statements or the page fault handler.
1141	* We must restore the host FPU here to make absolutely sure we don't leave the guest FPU state active
1142	* or trash somebody else's FPU state.
1143	*/
1144	/* Save the guest FPU and XMM state if necessary. */
1145	if (CPUMIsGuestFPUStateActive(pVCpu))
1146	{
1147	Log2(("CPUMR0SaveGuestFPU\n"));
1148	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
1149
1150	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1151	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1152	}
1153
1154	rc = HWACCMR0Globals.pfnLeaveSession(pVM, pVCpu, pCtx);
1155
1156	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1157	#ifdef RT_STRICT
1158	if (RT_UNLIKELY( pVCpu->hwaccm.s.idEnteredCpu != idCpu
1159	&& RT_FAILURE(rc)))
1160	{
1161	AssertMsgFailed(("Owner is %d, I'm %d", (int)pVCpu->hwaccm.s.idEnteredCpu, (int)idCpu));
1162	rc = VERR_INTERNAL_ERROR;
1163	}
1164	#endif
1165	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1166
1167	/* Disable VT-x or AMD-V if local init was done before. */
1168	if (!HWACCMR0Globals.fGlobalInit)
1169	{
1170	rc = hwaccmR0DisableCpu(idCpu);
1171	AssertRC(rc);
1172
1173	/* Reset these to force a TLB flush for the next entry. (-> EXPENSIVE) */
1174	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
1175	pVCpu->hwaccm.s.uCurrentASID = 0;
1176	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1177	}
1178
1179	ASMAtomicWriteBool(&pCpu->fInUse, false);
1180	return rc;
1181	}
1182
1183	/**
1184	* Runs guest code in a hardware accelerated VM.
1185	*
1186	* @returns VBox status code.
1187	* @param pVM The VM to operate on.
1188	* @param pVCpu VMCPUD id.
1189	*/
1190	VMMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1191	{
1192	CPUMCTX *pCtx;
1193	int rc;
1194	#ifdef VBOX_STRICT
1195	RTCPUID idCpu = RTMpCpuId(); NOREF(idCpu);
1196	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1197	#endif
1198
1199	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1200	Assert(HWACCMR0Globals.aCpuInfo[idCpu].fConfigured);
1201	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1202	Assert(ASMAtomicReadBool(&pCpu->fInUse) == true);
1203
1204	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1205	PGMDynMapStartAutoSet(pVCpu);
1206	#endif
1207
1208	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1209
1210	rc = HWACCMR0Globals.pfnRunGuestCode(pVM, pVCpu, pCtx);
1211
1212	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1213	PGMDynMapReleaseAutoSet(pVCpu);
1214	#endif
1215	return rc;
1216	}
1217
1218
1219	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1220	/**
1221	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1222	*
1223	* @returns VBox status code.
1224	* @param pVM VM handle.
1225	* @param pVCpu VMCPU handle.
1226	* @param pCtx CPU context
1227	*/
1228	VMMR0DECL(int) HWACCMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1229	{
1230	if (pVM->hwaccm.s.vmx.fSupported)
1231	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1232
1233	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1234	}
1235
1236	/**
1237	* Save guest debug state (64 bits guest mode & 32 bits host only)
1238	*
1239	* @returns VBox status code.
1240	* @param pVM VM handle.
1241	* @param pVCpu VMCPU handle.
1242	* @param pCtx CPU context
1243	*/
1244	VMMR0DECL(int) HWACCMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1245	{
1246	if (pVM->hwaccm.s.vmx.fSupported)
1247	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1248
1249	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1250	}
1251
1252	/**
1253	* Test the 32->64 bits switcher
1254	*
1255	* @returns VBox status code.
1256	* @param pVM VM handle.
1257	*/
1258	VMMR0DECL(int) HWACCMR0TestSwitcher3264(PVM pVM)
1259	{
1260	PVMCPU pVCpu = &pVM->aCpus[0];
1261	CPUMCTX *pCtx;
1262	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1263	int rc;
1264
1265	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1266
1267	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1268	if (pVM->hwaccm.s.vmx.fSupported)
1269	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1270	else
1271	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1272	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1273	return rc;
1274	}
1275
1276	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1277
1278	/**
1279	* Returns suspend status of the host
1280	*
1281	* @returns Suspend pending or not
1282	*/
1283	VMMR0DECL(bool) HWACCMR0SuspendPending()
1284	{
1285	return ASMAtomicReadBool(&HWACCMR0Globals.fSuspended);
1286	}
1287
1288	/**
1289	* Returns the cpu structure for the current cpu.
1290	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1291	*
1292	* @returns cpu structure pointer
1293	*/
1294	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu()
1295	{
1296	RTCPUID idCpu = RTMpCpuId();
1297
1298	return &HWACCMR0Globals.aCpuInfo[idCpu];
1299	}
1300
1301	/**
1302	* Returns the cpu structure for the current cpu.
1303	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1304	*
1305	* @returns cpu structure pointer
1306	* @param idCpu id of the VCPU
1307	*/
1308	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu)
1309	{
1310	return &HWACCMR0Globals.aCpuInfo[idCpu];
1311	}
1312
1313	/**
1314	* Returns the VMCPU of the current EMT thread.
1315	*
1316	* @param pVM The VM to operate on.
1317	*/
1318	VMMR0DECL(PVMCPU) HWACCMR0GetVMCPU(PVM pVM)
1319	{
1320	/* RTMpCpuId had better be cheap. */
1321	RTCPUID idHostCpu = RTMpCpuId();
1322
1323	/** @todo optimize for large number of VCPUs when that becomes more common. */
1324	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1325	{
1326	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1327
1328	if (pVCpu->hwaccm.s.idEnteredCpu == idHostCpu)
1329	return pVCpu;
1330	}
1331	return NULL;
1332	}
1333
1334	/**
1335	* Returns the VMCPU id of the current EMT thread.
1336	*
1337	* @param pVM The VM to operate on.
1338	*/
1339	VMMR0DECL(VMCPUID) HWACCMR0GetVMCPUId(PVM pVM)
1340	{
1341	PVMCPU pVCpu = HWACCMR0GetVMCPU(pVM);
1342	if (pVCpu)
1343	return pVCpu->idCpu;
1344
1345	return 0;
1346	}
1347
1348	/**
1349	* Save a pending IO read.
1350	*
1351	* @param pVCpu The VMCPU to operate on.
1352	* @param GCPtrRip Address of IO instruction
1353	* @param GCPtrRipNext Address of the next instruction
1354	* @param uPort Port address
1355	* @param uAndVal And mask for saving the result in eax
1356	* @param cbSize Read size
1357	*/
1358	VMMR0DECL(void) HWACCMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1359	{
1360	pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_PORT_READ;
1361	pVCpu->hwaccm.s.PendingIO.GCPtrRip = GCPtrRip;
1362	pVCpu->hwaccm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1363	pVCpu->hwaccm.s.PendingIO.s.Port.uPort = uPort;
1364	pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal = uAndVal;
1365	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize = cbSize;
1366	return;
1367	}
1368
1369	/**
1370	* Save a pending IO write.
1371	*
1372	* @param pVCpu The VMCPU to operate on.
1373	* @param GCPtrRIP Address of IO instruction
1374	* @param uPort Port address
1375	* @param uAndVal And mask for fetching the result from eax
1376	* @param cbSize Read size
1377	*/
1378	VMMR0DECL(void) HWACCMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1379	{
1380	pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_PORT_WRITE;
1381	pVCpu->hwaccm.s.PendingIO.GCPtrRip = GCPtrRip;
1382	pVCpu->hwaccm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1383	pVCpu->hwaccm.s.PendingIO.s.Port.uPort = uPort;
1384	pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal = uAndVal;
1385	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize = cbSize;
1386	return;
1387	}
1388
1389	/**
1390	* Disable VT-x if it's active and the current switcher turns off paging
1391	*
1392	* @returns VBox status code.
1393	* @param pVM VM handle.
1394	* @param pfVTxDisabled VT-x was disabled or not (out)
1395	*/
1396	VMMR0DECL(int) HWACCMR0EnterSwitcher(PVM pVM, bool *pfVTxDisabled)
1397	{
1398	Assert(!(ASMGetFlags() & X86_EFL_IF));
1399
1400	*pfVTxDisabled = false;
1401
1402	if ( HWACCMR0Globals.enmHwAccmState != HWACCMSTATE_ENABLED
1403	\|\| !HWACCMR0Globals.vmx.fSupported /* no such issues with AMD-V */
1404	\|\| !HWACCMR0Globals.fGlobalInit /* Local init implies the CPU is currently not in VMX root mode. */)
1405	return VINF_SUCCESS; /* nothing to do */
1406
1407	switch(VMMGetSwitcher(pVM))
1408	{
1409	case VMMSWITCHER_32_TO_32:
1410	case VMMSWITCHER_PAE_TO_PAE:
1411	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1412
1413	case VMMSWITCHER_32_TO_PAE:
1414	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1415	case VMMSWITCHER_AMD64_TO_32:
1416	case VMMSWITCHER_AMD64_TO_PAE:
1417	break; /* unsafe switchers */
1418
1419	default:
1420	AssertFailed();
1421	return VERR_INTERNAL_ERROR;
1422	}
1423
1424	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1425	void *pvPageCpu;
1426	RTHCPHYS pPageCpuPhys;
1427
1428	AssertReturn(pCpu && pCpu->pMemObj, VERR_INTERNAL_ERROR);
1429	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
1430	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
1431
1432	*pfVTxDisabled = true;
1433	return VMXR0DisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
1434	}
1435
1436	/**
1437	* Reeable VT-x if was active and the current switcher turned off paging
1438	*
1439	* @returns VBox status code.
1440	* @param pVM VM handle.
1441	* @param fVTxDisabled VT-x was disabled or not
1442	*/
1443	VMMR0DECL(int) HWACCMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1444	{
1445	Assert(!(ASMGetFlags() & X86_EFL_IF));
1446
1447	if (!fVTxDisabled)
1448	return VINF_SUCCESS; /* nothing to do */
1449
1450	Assert( HWACCMR0Globals.enmHwAccmState == HWACCMSTATE_ENABLED
1451	&& HWACCMR0Globals.vmx.fSupported
1452	&& HWACCMR0Globals.fGlobalInit);
1453
1454	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1455	void *pvPageCpu;
1456	RTHCPHYS pPageCpuPhys;
1457
1458	AssertReturn(pCpu && pCpu->pMemObj, VERR_INTERNAL_ERROR);
1459	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
1460	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
1461
1462	return VMXR0EnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
1463	}
1464
1465	#ifdef VBOX_STRICT
1466	/**
1467	* Dumps a descriptor.
1468	*
1469	* @param pDesc Descriptor to dump.
1470	* @param Sel Selector number.
1471	* @param pszMsg Message to prepend the log entry with.
1472	*/
1473	VMMR0DECL(void) HWACCMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1474	{
1475	/*
1476	* Make variable description string.
1477	*/
1478	static struct
1479	{
1480	unsigned cch;
1481	const char *psz;
1482	} const s_aTypes[32] =
1483	{
1484	# define STRENTRY(str) { sizeof(str) - 1, str }
1485
1486	/* system */
1487	# if HC_ARCH_BITS == 64
1488	STRENTRY("Reserved0 "), /* 0x00 */
1489	STRENTRY("Reserved1 "), /* 0x01 */
1490	STRENTRY("LDT "), /* 0x02 */
1491	STRENTRY("Reserved3 "), /* 0x03 */
1492	STRENTRY("Reserved4 "), /* 0x04 */
1493	STRENTRY("Reserved5 "), /* 0x05 */
1494	STRENTRY("Reserved6 "), /* 0x06 */
1495	STRENTRY("Reserved7 "), /* 0x07 */
1496	STRENTRY("Reserved8 "), /* 0x08 */
1497	STRENTRY("TSS64Avail "), /* 0x09 */
1498	STRENTRY("ReservedA "), /* 0x0a */
1499	STRENTRY("TSS64Busy "), /* 0x0b */
1500	STRENTRY("Call64 "), /* 0x0c */
1501	STRENTRY("ReservedD "), /* 0x0d */
1502	STRENTRY("Int64 "), /* 0x0e */
1503	STRENTRY("Trap64 "), /* 0x0f */
1504	# else
1505	STRENTRY("Reserved0 "), /* 0x00 */
1506	STRENTRY("TSS16Avail "), /* 0x01 */
1507	STRENTRY("LDT "), /* 0x02 */
1508	STRENTRY("TSS16Busy "), /* 0x03 */
1509	STRENTRY("Call16 "), /* 0x04 */
1510	STRENTRY("Task "), /* 0x05 */
1511	STRENTRY("Int16 "), /* 0x06 */
1512	STRENTRY("Trap16 "), /* 0x07 */
1513	STRENTRY("Reserved8 "), /* 0x08 */
1514	STRENTRY("TSS32Avail "), /* 0x09 */
1515	STRENTRY("ReservedA "), /* 0x0a */
1516	STRENTRY("TSS32Busy "), /* 0x0b */
1517	STRENTRY("Call32 "), /* 0x0c */
1518	STRENTRY("ReservedD "), /* 0x0d */
1519	STRENTRY("Int32 "), /* 0x0e */
1520	STRENTRY("Trap32 "), /* 0x0f */
1521	# endif
1522	/* non system */
1523	STRENTRY("DataRO "), /* 0x10 */
1524	STRENTRY("DataRO Accessed "), /* 0x11 */
1525	STRENTRY("DataRW "), /* 0x12 */
1526	STRENTRY("DataRW Accessed "), /* 0x13 */
1527	STRENTRY("DataDownRO "), /* 0x14 */
1528	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1529	STRENTRY("DataDownRW "), /* 0x16 */
1530	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1531	STRENTRY("CodeEO "), /* 0x18 */
1532	STRENTRY("CodeEO Accessed "), /* 0x19 */
1533	STRENTRY("CodeER "), /* 0x1a */
1534	STRENTRY("CodeER Accessed "), /* 0x1b */
1535	STRENTRY("CodeConfEO "), /* 0x1c */
1536	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1537	STRENTRY("CodeConfER "), /* 0x1e */
1538	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1539	# undef SYSENTRY
1540	};
1541	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1542	char szMsg[128];
1543	char *psz = &szMsg[0];
1544	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1545	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1546	psz += s_aTypes[i].cch;
1547
1548	if (pDesc->Gen.u1Present)
1549	ADD_STR(psz, "Present ");
1550	else
1551	ADD_STR(psz, "Not-Present ");
1552	# if HC_ARCH_BITS == 64
1553	if (pDesc->Gen.u1Long)
1554	ADD_STR(psz, "64-bit ");
1555	else
1556	ADD_STR(psz, "Comp ");
1557	# else
1558	if (pDesc->Gen.u1Granularity)
1559	ADD_STR(psz, "Page ");
1560	if (pDesc->Gen.u1DefBig)
1561	ADD_STR(psz, "32-bit ");
1562	else
1563	ADD_STR(psz, "16-bit ");
1564	# endif
1565	# undef ADD_STR
1566	*psz = '\0';
1567
1568	/*
1569	* Limit and Base and format the output.
1570	*/
1571	uint32_t u32Limit = X86DESC_LIMIT(*pDesc);
1572	if (pDesc->Gen.u1Granularity)
1573	u32Limit = u32Limit << PAGE_SHIFT \| PAGE_OFFSET_MASK;
1574
1575	# if HC_ARCH_BITS == 64
1576	uint64_t u32Base = X86DESC64_BASE(*pDesc);
1577
1578	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1579	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1580	# else
1581	uint32_t u32Base = X86DESC_BASE(*pDesc);
1582
1583	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1584	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1585	# endif
1586	}
1587
1588	/**
1589	* Formats a full register dump.
1590	*
1591	* @param pVM The VM to operate on.
1592	* @param pVCpu The VMCPU to operate on.
1593	* @param pCtx The context to format.
1594	*/
1595	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1596	{
1597	/*
1598	* Format the flags.
1599	*/
1600	static struct
1601	{
1602	const char pszSet; const char pszClear; uint32_t fFlag;
1603	} aFlags[] =
1604	{
1605	{ "vip",NULL, X86_EFL_VIP },
1606	{ "vif",NULL, X86_EFL_VIF },
1607	{ "ac", NULL, X86_EFL_AC },
1608	{ "vm", NULL, X86_EFL_VM },
1609	{ "rf", NULL, X86_EFL_RF },
1610	{ "nt", NULL, X86_EFL_NT },
1611	{ "ov", "nv", X86_EFL_OF },
1612	{ "dn", "up", X86_EFL_DF },
1613	{ "ei", "di", X86_EFL_IF },
1614	{ "tf", NULL, X86_EFL_TF },
1615	{ "nt", "pl", X86_EFL_SF },
1616	{ "nz", "zr", X86_EFL_ZF },
1617	{ "ac", "na", X86_EFL_AF },
1618	{ "po", "pe", X86_EFL_PF },
1619	{ "cy", "nc", X86_EFL_CF },
1620	};
1621	char szEFlags[80];
1622	char *psz = szEFlags;
1623	uint32_t efl = pCtx->eflags.u32;
1624	for (unsigned i = 0; i < RT_ELEMENTS(aFlags); i++)
1625	{
1626	const char *pszAdd = aFlags[i].fFlag & efl ? aFlags[i].pszSet : aFlags[i].pszClear;
1627	if (pszAdd)
1628	{
1629	strcpy(psz, pszAdd);
1630	psz += strlen(pszAdd);
1631	*psz++ = ' ';
1632	}
1633	}
1634	psz[-1] = '\0';
1635
1636
1637	/*
1638	* Format the registers.
1639	*/
1640	if (CPUMIsGuestIn64BitCode(pVCpu, CPUMCTX2CORE(pCtx)))
1641	{
1642	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1643	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1644	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1645	"r14=%016RX64 r15=%016RX64\n"
1646	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1647	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1648	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1649	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1650	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1651	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1652	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1653	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1654	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1655	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1656	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1657	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1658	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1659	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1660	,
1661	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1662	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1663	pCtx->r14, pCtx->r15,
1664	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1665	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1666	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1667	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1668	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1669	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1670	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1671	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1672	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1673	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1674	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1675	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1676	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1677	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1678	}
1679	else
1680	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1681	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1682	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1683	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1684	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1685	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1686	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1687	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1688	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1689	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1690	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1691	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1692	,
1693	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1694	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1695	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr[0], pCtx->dr[1],
1696	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr[2], pCtx->dr[3],
1697	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr[4], pCtx->dr[5],
1698	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr[6], pCtx->dr[7],
1699	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0, pCtx->cr2,
1700	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3, pCtx->cr4,
1701	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1702	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1703	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1704	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1705
1706	Log(("FPU:\n"
1707	"FCW=%04x FSW=%04x FTW=%02x\n"
1708	"FOP=%04x FPUIP=%08x CS=%04x Rsvrd1=%04x\n"
1709	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1710	,
1711	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
1712	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsvrd1,
1713	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
1714	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
1715
1716
1717	Log(("MSR:\n"
1718	"EFER =%016RX64\n"
1719	"PAT =%016RX64\n"
1720	"STAR =%016RX64\n"
1721	"CSTAR =%016RX64\n"
1722	"LSTAR =%016RX64\n"
1723	"SFMASK =%016RX64\n"
1724	"KERNELGSBASE =%016RX64\n",
1725	pCtx->msrEFER,
1726	pCtx->msrPAT,
1727	pCtx->msrSTAR,
1728	pCtx->msrCSTAR,
1729	pCtx->msrLSTAR,
1730	pCtx->msrSFMASK,
1731	pCtx->msrKERNELGSBASE));
1732
1733	}
1734	#endif /* VBOX_STRICT */
1735
1736	/* Dummy callback handlers. */
1737	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
1738	{
1739	return VINF_SUCCESS;
1740	}
1741
1742	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1743	{
1744	return VINF_SUCCESS;
1745	}
1746
1747	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1748	{
1749	return VINF_SUCCESS;
1750	}
1751
1752	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1753	{
1754	return VINF_SUCCESS;
1755	}
1756
1757	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM)
1758	{
1759	return VINF_SUCCESS;
1760	}
1761
1762	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM)
1763	{
1764	return VINF_SUCCESS;
1765	}
1766
1767	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM)
1768	{
1769	return VINF_SUCCESS;
1770	}
1771
1772	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1773	{
1774	return VINF_SUCCESS;
1775	}
1776
1777	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
1778	{
1779	return VINF_SUCCESS;
1780	}
1781
1782	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1783	{
1784	return VINF_SUCCESS;
1785	}

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp@ 28137

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