HWACCMR0.cpp@ 30757

Last change on this file since 30757 was 30241, checked in by vboxsync, 15 years ago
VMMGetCpu was completely broken in the context of GMMR0CheckSharedModules
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File size: 65.0 KB

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1	/* $Id: HWACCMR0.cpp 30241 2010-06-16 12:33:44Z vboxsync $ */
2	/** @file
3	* HWACCM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HWACCM
23	#include <VBox/hwaccm.h>
24	#include <VBox/pgm.h>
25	#include "HWACCMInternal.h"
26	#include <VBox/vm.h>
27	#include <VBox/x86.h>
28	#include <VBox/hwacc_vmx.h>
29	#include <VBox/hwacc_svm.h>
30	#include <VBox/err.h>
31	#include <VBox/log.h>
32	#include <iprt/assert.h>
33	#include <iprt/asm.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/cpuset.h>
36	#include <iprt/memobj.h>
37	#include <iprt/param.h>
38	#include <iprt/power.h>
39	#include <iprt/string.h>
40	#include <iprt/thread.h>
41	#include "HWVMXR0.h"
42	#include "HWSVMR0.h"
43
44	/*******************************************************************************
45	* Internal Functions *
46	*******************************************************************************/
47	static DECLCALLBACK(void) hwaccmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
48	static DECLCALLBACK(void) hwaccmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
49	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
50	static int hwaccmR0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu);
51	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
52
53	/*******************************************************************************
54	* Global Variables *
55	*******************************************************************************/
56
57	static struct
58	{
59	HWACCM_CPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
60
61	/** Ring 0 handlers for VT-x and AMD-V. */
62	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu));
63	DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
64	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
65	DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
66	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
67	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
68	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
69	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
70	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
71	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVM pVM));
72
73	/** Maximum ASID allowed. */
74	uint32_t uMaxASID;
75
76	struct
77	{
78	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
79	bool fSupported;
80	/** Whether we're using SUPR0EnableVTx or not. */
81	bool fUsingSUPR0EnableVTx;
82
83	/** Host CR4 value (set by ring-0 VMX init) */
84	uint64_t hostCR4;
85
86	/** Host EFER value (set by ring-0 VMX init) */
87	uint64_t hostEFER;
88
89	/** VMX MSR values */
90	struct
91	{
92	uint64_t feature_ctrl;
93	uint64_t vmx_basic_info;
94	VMX_CAPABILITY vmx_pin_ctls;
95	VMX_CAPABILITY vmx_proc_ctls;
96	VMX_CAPABILITY vmx_proc_ctls2;
97	VMX_CAPABILITY vmx_exit;
98	VMX_CAPABILITY vmx_entry;
99	uint64_t vmx_misc;
100	uint64_t vmx_cr0_fixed0;
101	uint64_t vmx_cr0_fixed1;
102	uint64_t vmx_cr4_fixed0;
103	uint64_t vmx_cr4_fixed1;
104	uint64_t vmx_vmcs_enum;
105	uint64_t vmx_eptcaps;
106	} msr;
107	/* Last instruction error */
108	uint32_t ulLastInstrError;
109	} vmx;
110	struct
111	{
112	/* HWCR msr (for diagnostics) */
113	uint64_t msrHWCR;
114
115	/** SVM revision. */
116	uint32_t u32Rev;
117
118	/** SVM feature bits from cpuid 0x8000000a */
119	uint32_t u32Features;
120
121	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
122	bool fSupported;
123	} svm;
124	/** Saved error from detection */
125	int32_t lLastError;
126
127	struct
128	{
129	uint32_t u32AMDFeatureECX;
130	uint32_t u32AMDFeatureEDX;
131	} cpuid;
132
133	HWACCMSTATE enmHwAccmState;
134
135	bool fGlobalInit;
136	volatile bool fSuspended;
137	} HWACCMR0Globals;
138
139
140
141	/**
142	* Does global Ring-0 HWACCM initialization.
143	*
144	* @returns VBox status code.
145	*/
146	VMMR0DECL(int) HWACCMR0Init(void)
147	{
148	int rc;
149	bool fAMDVPresent = false;
150
151	memset(&HWACCMR0Globals, 0, sizeof(HWACCMR0Globals));
152	HWACCMR0Globals.enmHwAccmState = HWACCMSTATE_UNINITIALIZED;
153	for (unsigned i = 0; i < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); i++)
154	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
155
156	/* Fill in all callbacks with placeholders. */
157	HWACCMR0Globals.pfnEnterSession = HWACCMR0DummyEnter;
158	HWACCMR0Globals.pfnLeaveSession = HWACCMR0DummyLeave;
159	HWACCMR0Globals.pfnSaveHostState = HWACCMR0DummySaveHostState;
160	HWACCMR0Globals.pfnLoadGuestState = HWACCMR0DummyLoadGuestState;
161	HWACCMR0Globals.pfnRunGuestCode = HWACCMR0DummyRunGuestCode;
162	HWACCMR0Globals.pfnEnableCpu = HWACCMR0DummyEnableCpu;
163	HWACCMR0Globals.pfnDisableCpu = HWACCMR0DummyDisableCpu;
164	HWACCMR0Globals.pfnInitVM = HWACCMR0DummyInitVM;
165	HWACCMR0Globals.pfnTermVM = HWACCMR0DummyTermVM;
166	HWACCMR0Globals.pfnSetupVM = HWACCMR0DummySetupVM;
167
168	/* Default is global VT-x/AMD-V init */
169	HWACCMR0Globals.fGlobalInit = true;
170
171	/*
172	* Check for VT-x and AMD-V capabilities
173	*/
174	if (ASMHasCpuId())
175	{
176	uint32_t u32FeaturesECX;
177	uint32_t u32Dummy;
178	uint32_t u32FeaturesEDX;
179	uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
180
181	ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
182	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
183	/* Query AMD features. */
184	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy, &HWACCMR0Globals.cpuid.u32AMDFeatureECX, &HWACCMR0Globals.cpuid.u32AMDFeatureEDX);
185
186	if ( u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
187	&& u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
188	&& u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX
189	)
190	{
191	/*
192	* Read all VMX MSRs if VMX is available. (same goes for RDMSR/WRMSR)
193	* We also assume all VMX-enabled CPUs support fxsave/fxrstor.
194	*/
195	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
196	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
197	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
198	)
199	{
200	int aRc[RTCPUSET_MAX_CPUS];
201	RTCPUID idCpu = 0;
202
203	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
204
205	/*
206	* First try use native kernel API for controlling VT-x.
207	* (This is only supported by some Mac OS X kernels atm.)
208	*/
209	HWACCMR0Globals.lLastError = rc = SUPR0EnableVTx(true /* fEnable */);
210	if (rc != VERR_NOT_SUPPORTED)
211	{
212	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
213	HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx = true;
214	if (RT_SUCCESS(rc))
215	{
216	HWACCMR0Globals.vmx.fSupported = true;
217	rc = SUPR0EnableVTx(false /* fEnable */);
218	AssertRC(rc);
219	}
220	}
221	else
222	{
223	HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx = false;
224
225	/* We need to check if VT-x has been properly initialized on all CPUs. Some BIOSes do a lousy job. */
226	memset(aRc, 0, sizeof(aRc));
227	HWACCMR0Globals.lLastError = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
228
229	/* Check the return code of all invocations. */
230	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
231	HWACCMR0Globals.lLastError = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
232	}
233	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
234	{
235	/* Reread in case we've changed it. */
236	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
237
238	if ( (HWACCMR0Globals.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
239	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
240	{
241	RTR0MEMOBJ pScatchMemObj;
242	void *pvScatchPage;
243	RTHCPHYS pScatchPagePhys;
244
245	HWACCMR0Globals.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
246	HWACCMR0Globals.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
247	HWACCMR0Globals.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
248	HWACCMR0Globals.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
249	HWACCMR0Globals.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
250	HWACCMR0Globals.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
251	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
252	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
253	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
254	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
255	HWACCMR0Globals.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
256	/* VPID 16 bits ASID. */
257	HWACCMR0Globals.uMaxASID = 0x10000; /* exclusive */
258
259	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
260	{
261	HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
262	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT\|VMX_VMCS_CTRL_PROC_EXEC2_VPID))
263	HWACCMR0Globals.vmx.msr.vmx_eptcaps = ASMRdMsr(MSR_IA32_VMX_EPT_CAPS);
264	}
265
266	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
267	{
268	HWACCMR0Globals.vmx.hostCR4 = ASMGetCR4();
269	HWACCMR0Globals.vmx.hostEFER = ASMRdMsr(MSR_K6_EFER);
270
271	rc = RTR0MemObjAllocCont(&pScatchMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
272	if (RT_FAILURE(rc))
273	return rc;
274
275	pvScatchPage = RTR0MemObjAddress(pScatchMemObj);
276	pScatchPagePhys = RTR0MemObjGetPagePhysAddr(pScatchMemObj, 0);
277	memset(pvScatchPage, 0, PAGE_SIZE);
278
279	/* Set revision dword at the beginning of the structure. */
280	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(HWACCMR0Globals.vmx.msr.vmx_basic_info);
281
282	/* Make sure we don't get rescheduled to another cpu during this probe. */
283	RTCCUINTREG fFlags = ASMIntDisableFlags();
284
285	/*
286	* Check CR4.VMXE
287	*/
288	if (!(HWACCMR0Globals.vmx.hostCR4 & X86_CR4_VMXE))
289	{
290	/* In theory this bit could be cleared behind our back. Which would cause #UD faults when we
291	* try to execute the VMX instructions...
292	*/
293	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4 \| X86_CR4_VMXE);
294	}
295
296	/* Enter VMX Root Mode */
297	rc = VMXEnable(pScatchPagePhys);
298	if (RT_FAILURE(rc))
299	{
300	/* KVM leaves the CPU in VMX root mode. Not only is this not allowed, it will crash the host when we enter raw mode, because
301	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify this bit)
302	* (b) turning off paging causes a #GP (unavoidable when switching from long to 32 bits mode or 32 bits to PAE)
303	*
304	* They should fix their code, but until they do we simply refuse to run.
305	*/
306	HWACCMR0Globals.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
307	}
308	else
309	{
310	HWACCMR0Globals.vmx.fSupported = true;
311	VMXDisable();
312	}
313
314	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it wasn't so before (some software could incorrectly think it's in VMX mode) */
315	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4);
316	ASMSetFlags(fFlags);
317
318	RTR0MemObjFree(pScatchMemObj, false);
319	if (RT_FAILURE(HWACCMR0Globals.lLastError))
320	return HWACCMR0Globals.lLastError;
321	}
322	}
323	else
324	{
325	AssertFailed(); /* can't hit this case anymore */
326	HWACCMR0Globals.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
327	}
328	}
329	#ifdef LOG_ENABLED
330	else
331	SUPR0Printf("HWACCMR0InitCPU failed with rc=%d\n", HWACCMR0Globals.lLastError);
332	#endif
333	}
334	else
335	HWACCMR0Globals.lLastError = VERR_VMX_NO_VMX;
336	}
337	else
338	if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
339	&& u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
340	&& u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX
341	)
342	{
343	/*
344	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
345	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
346	*/
347	if ( (HWACCMR0Globals.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
348	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
349	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
350	)
351	{
352	int aRc[RTCPUSET_MAX_CPUS];
353	RTCPUID idCpu = 0;
354
355	fAMDVPresent = true;
356
357	/* Query AMD features. */
358	ASMCpuId(0x8000000A, &HWACCMR0Globals.svm.u32Rev, &HWACCMR0Globals.uMaxASID, &u32Dummy, &HWACCMR0Globals.svm.u32Features);
359
360	/* We need to check if AMD-V has been properly initialized on all CPUs. Some BIOSes might do a poor job. */
361	memset(aRc, 0, sizeof(aRc));
362	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
363	AssertRC(rc);
364
365	/* Check the return code of all invocations. */
366	if (RT_SUCCESS(rc))
367	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
368
369	#ifndef DEBUG_bird
370	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE, ("HWACCMR0InitCPU failed for cpu %d with rc=%d\n", idCpu, rc));
371	#endif
372	if (RT_SUCCESS(rc))
373	{
374	/* Read the HWCR msr for diagnostics. */
375	HWACCMR0Globals.svm.msrHWCR = ASMRdMsr(MSR_K8_HWCR);
376	HWACCMR0Globals.svm.fSupported = true;
377	}
378	else
379	HWACCMR0Globals.lLastError = rc;
380	}
381	else
382	HWACCMR0Globals.lLastError = VERR_SVM_NO_SVM;
383	}
384	else
385	HWACCMR0Globals.lLastError = VERR_HWACCM_UNKNOWN_CPU;
386	}
387	else
388	HWACCMR0Globals.lLastError = VERR_HWACCM_NO_CPUID;
389
390	if (HWACCMR0Globals.vmx.fSupported)
391	{
392	HWACCMR0Globals.pfnEnterSession = VMXR0Enter;
393	HWACCMR0Globals.pfnLeaveSession = VMXR0Leave;
394	HWACCMR0Globals.pfnSaveHostState = VMXR0SaveHostState;
395	HWACCMR0Globals.pfnLoadGuestState = VMXR0LoadGuestState;
396	HWACCMR0Globals.pfnRunGuestCode = VMXR0RunGuestCode;
397	HWACCMR0Globals.pfnEnableCpu = VMXR0EnableCpu;
398	HWACCMR0Globals.pfnDisableCpu = VMXR0DisableCpu;
399	HWACCMR0Globals.pfnInitVM = VMXR0InitVM;
400	HWACCMR0Globals.pfnTermVM = VMXR0TermVM;
401	HWACCMR0Globals.pfnSetupVM = VMXR0SetupVM;
402	}
403	else
404	if (fAMDVPresent)
405	{
406	HWACCMR0Globals.pfnEnterSession = SVMR0Enter;
407	HWACCMR0Globals.pfnLeaveSession = SVMR0Leave;
408	HWACCMR0Globals.pfnSaveHostState = SVMR0SaveHostState;
409	HWACCMR0Globals.pfnLoadGuestState = SVMR0LoadGuestState;
410	HWACCMR0Globals.pfnRunGuestCode = SVMR0RunGuestCode;
411	HWACCMR0Globals.pfnEnableCpu = SVMR0EnableCpu;
412	HWACCMR0Globals.pfnDisableCpu = SVMR0DisableCpu;
413	HWACCMR0Globals.pfnInitVM = SVMR0InitVM;
414	HWACCMR0Globals.pfnTermVM = SVMR0TermVM;
415	HWACCMR0Globals.pfnSetupVM = SVMR0SetupVM;
416	}
417
418	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
419	{
420	rc = RTPowerNotificationRegister(hwaccmR0PowerCallback, 0);
421	AssertRC(rc);
422	}
423
424	return VINF_SUCCESS;
425	}
426
427
428	/**
429	* Checks the error code array filled in for each cpu in the system.
430	*
431	* @returns VBox status code.
432	* @param paRc Error code array
433	* @param cErrorCodes Array size
434	* @param pidCpu Value of the first cpu that set an error (out)
435	*/
436	static int hwaccmR0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu)
437	{
438	int rc = VINF_SUCCESS;
439
440	Assert(cErrorCodes == RTCPUSET_MAX_CPUS);
441
442	for (unsigned i=0;i<cErrorCodes;i++)
443	{
444	if (RTMpIsCpuOnline(i))
445	{
446	if (RT_FAILURE(paRc[i]))
447	{
448	rc = paRc[i];
449	*pidCpu = i;
450	break;
451	}
452	}
453	}
454	return rc;
455	}
456
457	/**
458	* Does global Ring-0 HWACCM termination.
459	*
460	* @returns VBox status code.
461	*/
462	VMMR0DECL(int) HWACCMR0Term(void)
463	{
464	int rc;
465	if ( HWACCMR0Globals.vmx.fSupported
466	&& HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
467	{
468	Assert(HWACCMR0Globals.fGlobalInit);
469	rc = SUPR0EnableVTx(false /* fEnable */);
470	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); iCpu++)
471	{
472	HWACCMR0Globals.aCpuInfo[iCpu].fConfigured = false;
473	Assert(HWACCMR0Globals.aCpuInfo[iCpu].pMemObj == NIL_RTR0MEMOBJ);
474	}
475	}
476	else
477	{
478	Assert(!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
479	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
480	{
481	rc = RTPowerNotificationDeregister(hwaccmR0PowerCallback, 0);
482	AssertRC(rc);
483	}
484	else
485	rc = VINF_SUCCESS;
486
487	/* Only disable VT-x/AMD-V on all CPUs if we enabled it before. */
488	if (HWACCMR0Globals.fGlobalInit)
489	{
490	int aRc[RTCPUSET_MAX_CPUS];
491
492	memset(aRc, 0, sizeof(aRc));
493	rc = RTMpOnAll(hwaccmR0DisableCpuCallback, aRc, NULL);
494	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
495	#ifdef VBOX_STRICT
496	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
497	AssertMsgRC(aRc[i], ("hwaccmR0DisableCpuCallback failed for cpu %d with rc=%d\n", i, aRc[i]));
498	#endif
499	}
500
501	/* Free the per-cpu pages used for VT-x and AMD-V */
502	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
503	{
504	if (HWACCMR0Globals.aCpuInfo[i].pMemObj != NIL_RTR0MEMOBJ)
505	{
506	RTR0MemObjFree(HWACCMR0Globals.aCpuInfo[i].pMemObj, false);
507	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
508	}
509	}
510	}
511	return rc;
512	}
513
514
515	/**
516	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
517	* is to be called on the target cpus.
518	*
519	* @param idCpu The identifier for the CPU the function is called on.
520	* @param pvUser1 The 1st user argument.
521	* @param pvUser2 The 2nd user argument.
522	*/
523	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
524	{
525	unsigned u32VendorEBX = (uintptr_t)pvUser1;
526	int paRc = (int )pvUser2;
527	uint64_t val;
528
529	#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
530	SUPR0Printf("HWACCMR0InitCPU cpu %d\n", idCpu);
531	#endif
532	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
533
534	if (u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX)
535	{
536	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
537
538	/*
539	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
540	* Once the lock bit is set, this MSR can no longer be modified.
541	*/
542	if ( !(val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
543	\|\| ((val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK)) == MSR_IA32_FEATURE_CONTROL_VMXON) /* Some BIOSes forget to set the locked bit. */
544	)
545	{
546	/* MSR is not yet locked; we can change it ourselves here */
547	ASMWrMsr(MSR_IA32_FEATURE_CONTROL, HWACCMR0Globals.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
548	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
549	}
550	if ( (val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
551	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
552	paRc[idCpu] = VINF_SUCCESS;
553	else
554	paRc[idCpu] = VERR_VMX_MSR_LOCKED_OR_DISABLED;
555	}
556	else
557	if (u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX)
558	{
559	/* Check if SVM is disabled */
560	val = ASMRdMsr(MSR_K8_VM_CR);
561	if (!(val & MSR_K8_VM_CR_SVM_DISABLE))
562	{
563	/* Turn on SVM in the EFER MSR. */
564	val = ASMRdMsr(MSR_K6_EFER);
565	if (val & MSR_K6_EFER_SVME)
566	{
567	paRc[idCpu] = VERR_SVM_IN_USE;
568	}
569	else
570	{
571	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
572
573	/* Paranoia. */
574	val = ASMRdMsr(MSR_K6_EFER);
575	if (val & MSR_K6_EFER_SVME)
576	{
577	/* Restore previous value. */
578	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
579	paRc[idCpu] = VINF_SUCCESS;
580	}
581	else
582	paRc[idCpu] = VERR_SVM_ILLEGAL_EFER_MSR;
583	}
584	}
585	else
586	paRc[idCpu] = VERR_SVM_DISABLED;
587	}
588	else
589	AssertFailed(); /* can't happen */
590	return;
591	}
592
593
594	/**
595	* Sets up HWACCM on all cpus.
596	*
597	* @returns VBox status code.
598	* @param pVM The VM to operate on.
599	*
600	*/
601	VMMR0DECL(int) HWACCMR0EnableAllCpus(PVM pVM)
602	{
603	AssertCompile(sizeof(HWACCMR0Globals.enmHwAccmState) == sizeof(uint32_t));
604
605	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
606	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
607	return VERR_HWACCM_SUSPEND_PENDING;
608
609	if (ASMAtomicCmpXchgU32((volatile uint32_t *)&HWACCMR0Globals.enmHwAccmState, HWACCMSTATE_ENABLED, HWACCMSTATE_UNINITIALIZED))
610	{
611	int rc;
612
613	HWACCMR0Globals.fGlobalInit = pVM->hwaccm.s.fGlobalInit;
614
615	if ( HWACCMR0Globals.vmx.fSupported
616	&& HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
617	{
618	rc = SUPR0EnableVTx(true /* fEnable */);
619	if (RT_SUCCESS(rc))
620	{
621	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); iCpu++)
622	{
623	HWACCMR0Globals.aCpuInfo[iCpu].fConfigured = true;
624	Assert(HWACCMR0Globals.aCpuInfo[iCpu].pMemObj == NIL_RTR0MEMOBJ);
625	}
626	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
627	HWACCMR0Globals.fGlobalInit = pVM->hwaccm.s.fGlobalInit = true;
628	}
629	else
630	AssertMsgFailed(("HWACCMR0EnableAllCpus/SUPR0EnableVTx: rc=%Rrc\n", rc));
631	}
632	else
633	{
634	int aRc[RTCPUSET_MAX_CPUS];
635	RTCPUID idCpu = 0;
636
637	memset(aRc, 0, sizeof(aRc));
638
639	/* Allocate one page per cpu for the global vt-x and amd-v pages */
640	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
641	{
642	Assert(!HWACCMR0Globals.aCpuInfo[i].pMemObj);
643
644	/** @todo this is rather dangerous if cpus can be taken offline; we don't care for now */
645	if (RTMpIsCpuOnline(i))
646	{
647	rc = RTR0MemObjAllocCont(&HWACCMR0Globals.aCpuInfo[i].pMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
648	AssertRC(rc);
649	if (RT_FAILURE(rc))
650	return rc;
651
652	void *pvR0 = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[i].pMemObj);
653	Assert(pvR0);
654	ASMMemZeroPage(pvR0);
655
656	#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
657	SUPR0Printf("address %x phys %x\n", pvR0, (uint32_t)RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[i].pMemObj, 0));
658	#endif
659	}
660	}
661	if (HWACCMR0Globals.fGlobalInit)
662	{
663	/* First time, so initialize each cpu/core */
664	rc = RTMpOnAll(hwaccmR0EnableCpuCallback, (void *)pVM, aRc);
665
666	/* Check the return code of all invocations. */
667	if (RT_SUCCESS(rc))
668	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
669	AssertMsgRC(rc, ("HWACCMR0EnableAllCpus failed for cpu %d with rc=%d\n", idCpu, rc));
670	}
671	else
672	rc = VINF_SUCCESS;
673	}
674
675	return rc;
676	}
677	return VINF_SUCCESS;
678	}
679
680	/**
681	* Disable VT-x or AMD-V on the current CPU
682	*
683	* @returns VBox status code.
684	* @param pVM VM handle (can be 0!)
685	* @param idCpu The identifier for the CPU the function is called on.
686	*/
687	static int hwaccmR0EnableCpu(PVM pVM, RTCPUID idCpu)
688	{
689	void *pvPageCpu;
690	RTHCPHYS pPageCpuPhys;
691	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
692
693	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
694	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
695	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
696	Assert(!pCpu->fConfigured);
697	Assert(!HWACCMR0Globals.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
698
699	pCpu->idCpu = idCpu;
700
701	/* Make sure we start with a clean TLB. */
702	pCpu->fFlushTLB = true;
703
704	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
705	pCpu->cTLBFlushes = 0;
706
707	/* Should never happen */
708	if (!pCpu->pMemObj)
709	{
710	AssertFailed();
711	return VERR_INTERNAL_ERROR;
712	}
713
714	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
715	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
716
717	int rc = HWACCMR0Globals.pfnEnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
718	AssertRC(rc);
719	if (RT_SUCCESS(rc))
720	pCpu->fConfigured = true;
721
722	return rc;
723	}
724
725
726	/**
727	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
728	* is to be called on the target cpus.
729	*
730	* @param idCpu The identifier for the CPU the function is called on.
731	* @param pvUser1 The 1st user argument.
732	* @param pvUser2 The 2nd user argument.
733	*/
734	static DECLCALLBACK(void) hwaccmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
735	{
736	PVM pVM = (PVM)pvUser1; /* can be NULL! */
737	int paRc = (int )pvUser2;
738
739	if (!HWACCMR0Globals.fGlobalInit)
740	{
741	paRc[idCpu] = VINF_SUCCESS;
742	AssertFailed();
743	return;
744	}
745
746	paRc[idCpu] = hwaccmR0EnableCpu(pVM, idCpu);
747	}
748
749
750	/**
751	* Disable VT-x or AMD-V on the current CPU
752	*
753	* @returns VBox status code.
754	* @param idCpu The identifier for the CPU the function is called on.
755	*/
756	static int hwaccmR0DisableCpu(RTCPUID idCpu)
757	{
758	void *pvPageCpu;
759	RTHCPHYS pPageCpuPhys;
760	int rc;
761	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
762
763	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
764	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
765	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
766	Assert(!HWACCMR0Globals.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
767	Assert(!pCpu->fConfigured \|\| pCpu->pMemObj);
768
769	if (!pCpu->pMemObj)
770	return (pCpu->fConfigured) ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
771
772	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
773	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
774
775	if (pCpu->fConfigured)
776	{
777	rc = HWACCMR0Globals.pfnDisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
778	AssertRC(rc);
779	pCpu->fConfigured = false;
780	}
781	else
782	rc = VINF_SUCCESS; /* nothing to do */
783
784	pCpu->uCurrentASID = 0;
785	return rc;
786	}
787
788	/**
789	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
790	* is to be called on the target cpus.
791	*
792	* @param idCpu The identifier for the CPU the function is called on.
793	* @param pvUser1 The 1st user argument.
794	* @param pvUser2 The 2nd user argument.
795	*/
796	static DECLCALLBACK(void) hwaccmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
797	{
798	int paRc = (int )pvUser1;
799
800	if (!HWACCMR0Globals.fGlobalInit)
801	{
802	paRc[idCpu] = VINF_SUCCESS;
803	AssertFailed();
804	return;
805	}
806
807	paRc[idCpu] = hwaccmR0DisableCpu(idCpu);
808	}
809
810	/**
811	* Called whenever a system power state change occurs.
812	*
813	* @param enmEvent Power event
814	* @param pvUser User argument
815	*/
816	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
817	{
818	NOREF(pvUser);
819	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
820
821	#ifdef LOG_ENABLED
822	if (enmEvent == RTPOWEREVENT_SUSPEND)
823	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
824	else
825	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_RESUME\n");
826	#endif
827
828	if (enmEvent == RTPOWEREVENT_SUSPEND)
829	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, true);
830
831	if (HWACCMR0Globals.enmHwAccmState == HWACCMSTATE_ENABLED)
832	{
833	int aRc[RTCPUSET_MAX_CPUS];
834	int rc;
835	RTCPUID idCpu;
836
837	memset(aRc, 0, sizeof(aRc));
838	if (enmEvent == RTPOWEREVENT_SUSPEND)
839	{
840	if (HWACCMR0Globals.fGlobalInit)
841	{
842	/* Turn off VT-x or AMD-V on all CPUs. */
843	rc = RTMpOnAll(hwaccmR0DisableCpuCallback, aRc, NULL);
844	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
845	}
846	/* else nothing to do here for the local init case */
847	}
848	else
849	{
850	/* Reinit the CPUs from scratch as the suspend state might have messed with the MSRs. (lousy BIOSes as usual) */
851	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)((HWACCMR0Globals.vmx.fSupported) ? X86_CPUID_VENDOR_INTEL_EBX : X86_CPUID_VENDOR_AMD_EBX), aRc);
852	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
853
854	if (RT_SUCCESS(rc))
855	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
856	#ifdef LOG_ENABLED
857	if (RT_FAILURE(rc))
858	SUPR0Printf("hwaccmR0PowerCallback HWACCMR0InitCPU failed with %d\n", rc);
859	#endif
860
861	if (HWACCMR0Globals.fGlobalInit)
862	{
863	/* Turn VT-x or AMD-V back on on all CPUs. */
864	rc = RTMpOnAll(hwaccmR0EnableCpuCallback, NULL, aRc);
865	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
866	}
867	/* else nothing to do here for the local init case */
868	}
869	}
870	if (enmEvent == RTPOWEREVENT_RESUME)
871	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, false);
872	}
873
874
875	/**
876	* Does Ring-0 per VM HWACCM initialization.
877	*
878	* This is mainly to check that the Host CPU mode is compatible
879	* with VMX.
880	*
881	* @returns VBox status code.
882	* @param pVM The VM to operate on.
883	*/
884	VMMR0DECL(int) HWACCMR0InitVM(PVM pVM)
885	{
886	int rc;
887
888	AssertReturn(pVM, VERR_INVALID_PARAMETER);
889
890	#ifdef LOG_ENABLED
891	SUPR0Printf("HWACCMR0InitVM: %p\n", pVM);
892	#endif
893
894	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
895	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
896	return VERR_HWACCM_SUSPEND_PENDING;
897
898	pVM->hwaccm.s.vmx.fSupported = HWACCMR0Globals.vmx.fSupported;
899	pVM->hwaccm.s.svm.fSupported = HWACCMR0Globals.svm.fSupported;
900
901	pVM->hwaccm.s.vmx.msr.feature_ctrl = HWACCMR0Globals.vmx.msr.feature_ctrl;
902	pVM->hwaccm.s.vmx.hostCR4 = HWACCMR0Globals.vmx.hostCR4;
903	pVM->hwaccm.s.vmx.hostEFER = HWACCMR0Globals.vmx.hostEFER;
904	pVM->hwaccm.s.vmx.msr.vmx_basic_info = HWACCMR0Globals.vmx.msr.vmx_basic_info;
905	pVM->hwaccm.s.vmx.msr.vmx_pin_ctls = HWACCMR0Globals.vmx.msr.vmx_pin_ctls;
906	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls = HWACCMR0Globals.vmx.msr.vmx_proc_ctls;
907	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2 = HWACCMR0Globals.vmx.msr.vmx_proc_ctls2;
908	pVM->hwaccm.s.vmx.msr.vmx_exit = HWACCMR0Globals.vmx.msr.vmx_exit;
909	pVM->hwaccm.s.vmx.msr.vmx_entry = HWACCMR0Globals.vmx.msr.vmx_entry;
910	pVM->hwaccm.s.vmx.msr.vmx_misc = HWACCMR0Globals.vmx.msr.vmx_misc;
911	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0;
912	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1;
913	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0;
914	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1;
915	pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum = HWACCMR0Globals.vmx.msr.vmx_vmcs_enum;
916	pVM->hwaccm.s.vmx.msr.vmx_eptcaps = HWACCMR0Globals.vmx.msr.vmx_eptcaps;
917	pVM->hwaccm.s.svm.msrHWCR = HWACCMR0Globals.svm.msrHWCR;
918	pVM->hwaccm.s.svm.u32Rev = HWACCMR0Globals.svm.u32Rev;
919	pVM->hwaccm.s.svm.u32Features = HWACCMR0Globals.svm.u32Features;
920	pVM->hwaccm.s.cpuid.u32AMDFeatureECX = HWACCMR0Globals.cpuid.u32AMDFeatureECX;
921	pVM->hwaccm.s.cpuid.u32AMDFeatureEDX = HWACCMR0Globals.cpuid.u32AMDFeatureEDX;
922	pVM->hwaccm.s.lLastError = HWACCMR0Globals.lLastError;
923
924	pVM->hwaccm.s.uMaxASID = HWACCMR0Globals.uMaxASID;
925
926
927	if (!pVM->hwaccm.s.cMaxResumeLoops) /* allow ring-3 overrides */
928	{
929	pVM->hwaccm.s.cMaxResumeLoops = 1024;
930	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
931	if (RTThreadPreemptIsPendingTrusty())
932	pVM->hwaccm.s.cMaxResumeLoops = 8192;
933	#endif
934	}
935
936	for (VMCPUID i = 0; i < pVM->cCpus; i++)
937	{
938	PVMCPU pVCpu = &pVM->aCpus[i];
939
940	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
941
942	/* Invalidate the last cpu we were running on. */
943	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
944
945	/* we'll aways increment this the first time (host uses ASID 0) */
946	pVCpu->hwaccm.s.uCurrentASID = 0;
947	}
948
949	RTCCUINTREG fFlags = ASMIntDisableFlags();
950	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
951
952	/* Note: Not correct as we can be rescheduled to a different cpu, but the fInUse case is mostly for debugging. */
953	ASMAtomicWriteBool(&pCpu->fInUse, true);
954	ASMSetFlags(fFlags);
955
956	/* Init a VT-x or AMD-V VM. */
957	rc = HWACCMR0Globals.pfnInitVM(pVM);
958
959	ASMAtomicWriteBool(&pCpu->fInUse, false);
960	return rc;
961	}
962
963
964	/**
965	* Does Ring-0 per VM HWACCM termination.
966	*
967	* @returns VBox status code.
968	* @param pVM The VM to operate on.
969	*/
970	VMMR0DECL(int) HWACCMR0TermVM(PVM pVM)
971	{
972	int rc;
973
974	AssertReturn(pVM, VERR_INVALID_PARAMETER);
975
976	#ifdef LOG_ENABLED
977	SUPR0Printf("HWACCMR0TermVM: %p\n", pVM);
978	#endif
979
980	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
981	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
982
983	/* @note Not correct as we can be rescheduled to a different cpu, but the fInUse case is mostly for debugging. */
984	RTCCUINTREG fFlags = ASMIntDisableFlags();
985	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
986
987	ASMAtomicWriteBool(&pCpu->fInUse, true);
988	ASMSetFlags(fFlags);
989
990	/* Terminate a VT-x or AMD-V VM. */
991	rc = HWACCMR0Globals.pfnTermVM(pVM);
992
993	ASMAtomicWriteBool(&pCpu->fInUse, false);
994	return rc;
995	}
996
997
998	/**
999	* Sets up a VT-x or AMD-V session
1000	*
1001	* @returns VBox status code.
1002	* @param pVM The VM to operate on.
1003	*/
1004	VMMR0DECL(int) HWACCMR0SetupVM(PVM pVM)
1005	{
1006	int rc;
1007	RTCPUID idCpu = RTMpCpuId();
1008	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1009
1010	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1011
1012	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
1013	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1014
1015	#ifdef LOG_ENABLED
1016	SUPR0Printf("HWACCMR0SetupVM: %p\n", pVM);
1017	#endif
1018
1019	ASMAtomicWriteBool(&pCpu->fInUse, true);
1020
1021	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1022	{
1023	/* On first entry we'll sync everything. */
1024	pVM->aCpus[i].hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1025	}
1026
1027	/* Enable VT-x or AMD-V if local init is required. */
1028	if (!HWACCMR0Globals.fGlobalInit)
1029	{
1030	rc = hwaccmR0EnableCpu(pVM, idCpu);
1031	AssertRCReturn(rc, rc);
1032	}
1033
1034	/* Setup VT-x or AMD-V. */
1035	rc = HWACCMR0Globals.pfnSetupVM(pVM);
1036
1037	/* Disable VT-x or AMD-V if local init was done before. */
1038	if (!HWACCMR0Globals.fGlobalInit)
1039	{
1040	rc = hwaccmR0DisableCpu(idCpu);
1041	AssertRC(rc);
1042	}
1043
1044	ASMAtomicWriteBool(&pCpu->fInUse, false);
1045
1046	return rc;
1047	}
1048
1049
1050	/**
1051	* Enters the VT-x or AMD-V session
1052	*
1053	* @returns VBox status code.
1054	* @param pVM The VM to operate on.
1055	* @param pVCpu VMCPUD id.
1056	*/
1057	VMMR0DECL(int) HWACCMR0Enter(PVM pVM, PVMCPU pVCpu)
1058	{
1059	PCPUMCTX pCtx;
1060	int rc;
1061	RTCPUID idCpu = RTMpCpuId();
1062	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1063
1064	/* Make sure we can't enter a session after we've disabled hwaccm in preparation of a suspend. */
1065	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1066	ASMAtomicWriteBool(&pCpu->fInUse, true);
1067
1068	AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == NIL_RTCPUID, ("%d", (int)pVCpu->hwaccm.s.idEnteredCpu));
1069	pVCpu->hwaccm.s.idEnteredCpu = idCpu;
1070
1071	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1072
1073	/* Always load the guest's FPU/XMM state on-demand. */
1074	CPUMDeactivateGuestFPUState(pVCpu);
1075
1076	/* Always load the guest's debug state on-demand. */
1077	CPUMDeactivateGuestDebugState(pVCpu);
1078
1079	/* Always reload the host context and the guest's CR0 register. (!!!!) */
1080	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0 \| HWACCM_CHANGED_HOST_CONTEXT;
1081
1082	/* Setup the register and mask according to the current execution mode. */
1083	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1084	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFFFFFFFFFF);
1085	else
1086	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFF);
1087
1088	/* Enable VT-x or AMD-V if local init is required. */
1089	if (!HWACCMR0Globals.fGlobalInit)
1090	{
1091	rc = hwaccmR0EnableCpu(pVM, idCpu);
1092	AssertRCReturn(rc, rc);
1093	}
1094
1095	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1096	bool fStartedSet = PGMDynMapStartOrMigrateAutoSet(pVCpu);
1097	#endif
1098
1099	rc = HWACCMR0Globals.pfnEnterSession(pVM, pVCpu, pCpu);
1100	AssertRC(rc);
1101	/* We must save the host context here (VT-x) as we might be rescheduled on a different cpu after a long jump back to ring 3. */
1102	rc \|= HWACCMR0Globals.pfnSaveHostState(pVM, pVCpu);
1103	AssertRC(rc);
1104	rc \|= HWACCMR0Globals.pfnLoadGuestState(pVM, pVCpu, pCtx);
1105	AssertRC(rc);
1106
1107	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1108	if (fStartedSet)
1109	PGMDynMapReleaseAutoSet(pVCpu);
1110	#endif
1111
1112	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1113	if (RT_FAILURE(rc))
1114	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1115	return rc;
1116	}
1117
1118
1119	/**
1120	* Leaves the VT-x or AMD-V session
1121	*
1122	* @returns VBox status code.
1123	* @param pVM The VM to operate on.
1124	* @param pVCpu VMCPUD id.
1125	*/
1126	VMMR0DECL(int) HWACCMR0Leave(PVM pVM, PVMCPU pVCpu)
1127	{
1128	PCPUMCTX pCtx;
1129	int rc;
1130	RTCPUID idCpu = RTMpCpuId();
1131	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1132
1133	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1134
1135	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1136
1137	/* Note: It's rather tricky with longjmps done by e.g. Log statements or the page fault handler.
1138	* We must restore the host FPU here to make absolutely sure we don't leave the guest FPU state active
1139	* or trash somebody else's FPU state.
1140	*/
1141	/* Save the guest FPU and XMM state if necessary. */
1142	if (CPUMIsGuestFPUStateActive(pVCpu))
1143	{
1144	Log2(("CPUMR0SaveGuestFPU\n"));
1145	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
1146
1147	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1148	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1149	}
1150
1151	rc = HWACCMR0Globals.pfnLeaveSession(pVM, pVCpu, pCtx);
1152
1153	/* We don't pass on invlpg information to the recompiler for nested paging guests, so we must make sure the recompiler flushes its TLB
1154	* the next time it executes code.
1155	*/
1156	if ( pVM->hwaccm.s.fNestedPaging
1157	&& CPUMIsGuestInPagedProtectedModeEx(pCtx))
1158	{
1159	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
1160	}
1161
1162	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1163	#ifdef RT_STRICT
1164	if (RT_UNLIKELY( pVCpu->hwaccm.s.idEnteredCpu != idCpu
1165	&& RT_FAILURE(rc)))
1166	{
1167	AssertMsgFailed(("Owner is %d, I'm %d", (int)pVCpu->hwaccm.s.idEnteredCpu, (int)idCpu));
1168	rc = VERR_INTERNAL_ERROR;
1169	}
1170	#endif
1171	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1172
1173	/* Disable VT-x or AMD-V if local init was done before. */
1174	if (!HWACCMR0Globals.fGlobalInit)
1175	{
1176	rc = hwaccmR0DisableCpu(idCpu);
1177	AssertRC(rc);
1178
1179	/* Reset these to force a TLB flush for the next entry. (-> EXPENSIVE) */
1180	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
1181	pVCpu->hwaccm.s.uCurrentASID = 0;
1182	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1183	}
1184
1185	ASMAtomicWriteBool(&pCpu->fInUse, false);
1186	return rc;
1187	}
1188
1189	/**
1190	* Runs guest code in a hardware accelerated VM.
1191	*
1192	* @returns VBox status code.
1193	* @param pVM The VM to operate on.
1194	* @param pVCpu VMCPUD id.
1195	*/
1196	VMMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1197	{
1198	CPUMCTX *pCtx;
1199	int rc;
1200	#ifdef VBOX_STRICT
1201	RTCPUID idCpu = RTMpCpuId(); NOREF(idCpu);
1202	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1203	#endif
1204
1205	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1206	Assert(HWACCMR0Globals.aCpuInfo[idCpu].fConfigured);
1207	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1208	Assert(ASMAtomicReadBool(&pCpu->fInUse) == true);
1209
1210	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1211	PGMDynMapStartAutoSet(pVCpu);
1212	#endif
1213
1214	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1215
1216	rc = HWACCMR0Globals.pfnRunGuestCode(pVM, pVCpu, pCtx);
1217
1218	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1219	PGMDynMapReleaseAutoSet(pVCpu);
1220	#endif
1221	return rc;
1222	}
1223
1224
1225	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1226	/**
1227	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1228	*
1229	* @returns VBox status code.
1230	* @param pVM VM handle.
1231	* @param pVCpu VMCPU handle.
1232	* @param pCtx CPU context
1233	*/
1234	VMMR0DECL(int) HWACCMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1235	{
1236	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFpu64SwitchBack);
1237	if (pVM->hwaccm.s.vmx.fSupported)
1238	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1239
1240	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1241	}
1242
1243	/**
1244	* Save guest debug state (64 bits guest mode & 32 bits host only)
1245	*
1246	* @returns VBox status code.
1247	* @param pVM VM handle.
1248	* @param pVCpu VMCPU handle.
1249	* @param pCtx CPU context
1250	*/
1251	VMMR0DECL(int) HWACCMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1252	{
1253	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDebug64SwitchBack);
1254	if (pVM->hwaccm.s.vmx.fSupported)
1255	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1256
1257	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1258	}
1259
1260	/**
1261	* Test the 32->64 bits switcher
1262	*
1263	* @returns VBox status code.
1264	* @param pVM VM handle.
1265	*/
1266	VMMR0DECL(int) HWACCMR0TestSwitcher3264(PVM pVM)
1267	{
1268	PVMCPU pVCpu = &pVM->aCpus[0];
1269	CPUMCTX *pCtx;
1270	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1271	int rc;
1272
1273	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1274
1275	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1276	if (pVM->hwaccm.s.vmx.fSupported)
1277	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1278	else
1279	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1280	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1281	return rc;
1282	}
1283
1284	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1285
1286	/**
1287	* Returns suspend status of the host
1288	*
1289	* @returns Suspend pending or not
1290	*/
1291	VMMR0DECL(bool) HWACCMR0SuspendPending()
1292	{
1293	return ASMAtomicReadBool(&HWACCMR0Globals.fSuspended);
1294	}
1295
1296	/**
1297	* Returns the cpu structure for the current cpu.
1298	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1299	*
1300	* @returns cpu structure pointer
1301	*/
1302	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu()
1303	{
1304	RTCPUID idCpu = RTMpCpuId();
1305
1306	return &HWACCMR0Globals.aCpuInfo[idCpu];
1307	}
1308
1309	/**
1310	* Returns the cpu structure for the current cpu.
1311	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1312	*
1313	* @returns cpu structure pointer
1314	* @param idCpu id of the VCPU
1315	*/
1316	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu)
1317	{
1318	return &HWACCMR0Globals.aCpuInfo[idCpu];
1319	}
1320
1321	/**
1322	* Save a pending IO read.
1323	*
1324	* @param pVCpu The VMCPU to operate on.
1325	* @param GCPtrRip Address of IO instruction
1326	* @param GCPtrRipNext Address of the next instruction
1327	* @param uPort Port address
1328	* @param uAndVal And mask for saving the result in eax
1329	* @param cbSize Read size
1330	*/
1331	VMMR0DECL(void) HWACCMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1332	{
1333	pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_PORT_READ;
1334	pVCpu->hwaccm.s.PendingIO.GCPtrRip = GCPtrRip;
1335	pVCpu->hwaccm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1336	pVCpu->hwaccm.s.PendingIO.s.Port.uPort = uPort;
1337	pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal = uAndVal;
1338	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize = cbSize;
1339	return;
1340	}
1341
1342	/**
1343	* Save a pending IO write.
1344	*
1345	* @param pVCpu The VMCPU to operate on.
1346	* @param GCPtrRIP Address of IO instruction
1347	* @param uPort Port address
1348	* @param uAndVal And mask for fetching the result from eax
1349	* @param cbSize Read size
1350	*/
1351	VMMR0DECL(void) HWACCMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1352	{
1353	pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_PORT_WRITE;
1354	pVCpu->hwaccm.s.PendingIO.GCPtrRip = GCPtrRip;
1355	pVCpu->hwaccm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1356	pVCpu->hwaccm.s.PendingIO.s.Port.uPort = uPort;
1357	pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal = uAndVal;
1358	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize = cbSize;
1359	return;
1360	}
1361
1362	/**
1363	* Disable VT-x if it's active and the current switcher turns off paging
1364	*
1365	* @returns VBox status code.
1366	* @param pVM VM handle.
1367	* @param pfVTxDisabled VT-x was disabled or not (out)
1368	*/
1369	VMMR0DECL(int) HWACCMR0EnterSwitcher(PVM pVM, bool *pfVTxDisabled)
1370	{
1371	Assert(!(ASMGetFlags() & X86_EFL_IF));
1372
1373	*pfVTxDisabled = false;
1374
1375	if ( HWACCMR0Globals.enmHwAccmState != HWACCMSTATE_ENABLED
1376	\|\| !HWACCMR0Globals.vmx.fSupported /* no such issues with AMD-V */
1377	\|\| !HWACCMR0Globals.fGlobalInit /* Local init implies the CPU is currently not in VMX root mode. */)
1378	return VINF_SUCCESS; /* nothing to do */
1379
1380	switch(VMMGetSwitcher(pVM))
1381	{
1382	case VMMSWITCHER_32_TO_32:
1383	case VMMSWITCHER_PAE_TO_PAE:
1384	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1385
1386	case VMMSWITCHER_32_TO_PAE:
1387	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1388	case VMMSWITCHER_AMD64_TO_32:
1389	case VMMSWITCHER_AMD64_TO_PAE:
1390	break; /* unsafe switchers */
1391
1392	default:
1393	AssertFailed();
1394	return VERR_INTERNAL_ERROR;
1395	}
1396
1397	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1398	void *pvPageCpu;
1399	RTHCPHYS pPageCpuPhys;
1400
1401	AssertReturn(pCpu && pCpu->pMemObj, VERR_INTERNAL_ERROR);
1402	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
1403	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
1404
1405	*pfVTxDisabled = true;
1406	return VMXR0DisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
1407	}
1408
1409	/**
1410	* Reeable VT-x if was active and the current switcher turned off paging
1411	*
1412	* @returns VBox status code.
1413	* @param pVM VM handle.
1414	* @param fVTxDisabled VT-x was disabled or not
1415	*/
1416	VMMR0DECL(int) HWACCMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1417	{
1418	Assert(!(ASMGetFlags() & X86_EFL_IF));
1419
1420	if (!fVTxDisabled)
1421	return VINF_SUCCESS; /* nothing to do */
1422
1423	Assert( HWACCMR0Globals.enmHwAccmState == HWACCMSTATE_ENABLED
1424	&& HWACCMR0Globals.vmx.fSupported
1425	&& HWACCMR0Globals.fGlobalInit);
1426
1427	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1428	void *pvPageCpu;
1429	RTHCPHYS pPageCpuPhys;
1430
1431	AssertReturn(pCpu && pCpu->pMemObj, VERR_INTERNAL_ERROR);
1432	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
1433	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
1434
1435	return VMXR0EnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
1436	}
1437
1438	#ifdef VBOX_STRICT
1439	/**
1440	* Dumps a descriptor.
1441	*
1442	* @param pDesc Descriptor to dump.
1443	* @param Sel Selector number.
1444	* @param pszMsg Message to prepend the log entry with.
1445	*/
1446	VMMR0DECL(void) HWACCMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1447	{
1448	/*
1449	* Make variable description string.
1450	*/
1451	static struct
1452	{
1453	unsigned cch;
1454	const char *psz;
1455	} const s_aTypes[32] =
1456	{
1457	# define STRENTRY(str) { sizeof(str) - 1, str }
1458
1459	/* system */
1460	# if HC_ARCH_BITS == 64
1461	STRENTRY("Reserved0 "), /* 0x00 */
1462	STRENTRY("Reserved1 "), /* 0x01 */
1463	STRENTRY("LDT "), /* 0x02 */
1464	STRENTRY("Reserved3 "), /* 0x03 */
1465	STRENTRY("Reserved4 "), /* 0x04 */
1466	STRENTRY("Reserved5 "), /* 0x05 */
1467	STRENTRY("Reserved6 "), /* 0x06 */
1468	STRENTRY("Reserved7 "), /* 0x07 */
1469	STRENTRY("Reserved8 "), /* 0x08 */
1470	STRENTRY("TSS64Avail "), /* 0x09 */
1471	STRENTRY("ReservedA "), /* 0x0a */
1472	STRENTRY("TSS64Busy "), /* 0x0b */
1473	STRENTRY("Call64 "), /* 0x0c */
1474	STRENTRY("ReservedD "), /* 0x0d */
1475	STRENTRY("Int64 "), /* 0x0e */
1476	STRENTRY("Trap64 "), /* 0x0f */
1477	# else
1478	STRENTRY("Reserved0 "), /* 0x00 */
1479	STRENTRY("TSS16Avail "), /* 0x01 */
1480	STRENTRY("LDT "), /* 0x02 */
1481	STRENTRY("TSS16Busy "), /* 0x03 */
1482	STRENTRY("Call16 "), /* 0x04 */
1483	STRENTRY("Task "), /* 0x05 */
1484	STRENTRY("Int16 "), /* 0x06 */
1485	STRENTRY("Trap16 "), /* 0x07 */
1486	STRENTRY("Reserved8 "), /* 0x08 */
1487	STRENTRY("TSS32Avail "), /* 0x09 */
1488	STRENTRY("ReservedA "), /* 0x0a */
1489	STRENTRY("TSS32Busy "), /* 0x0b */
1490	STRENTRY("Call32 "), /* 0x0c */
1491	STRENTRY("ReservedD "), /* 0x0d */
1492	STRENTRY("Int32 "), /* 0x0e */
1493	STRENTRY("Trap32 "), /* 0x0f */
1494	# endif
1495	/* non system */
1496	STRENTRY("DataRO "), /* 0x10 */
1497	STRENTRY("DataRO Accessed "), /* 0x11 */
1498	STRENTRY("DataRW "), /* 0x12 */
1499	STRENTRY("DataRW Accessed "), /* 0x13 */
1500	STRENTRY("DataDownRO "), /* 0x14 */
1501	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1502	STRENTRY("DataDownRW "), /* 0x16 */
1503	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1504	STRENTRY("CodeEO "), /* 0x18 */
1505	STRENTRY("CodeEO Accessed "), /* 0x19 */
1506	STRENTRY("CodeER "), /* 0x1a */
1507	STRENTRY("CodeER Accessed "), /* 0x1b */
1508	STRENTRY("CodeConfEO "), /* 0x1c */
1509	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1510	STRENTRY("CodeConfER "), /* 0x1e */
1511	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1512	# undef SYSENTRY
1513	};
1514	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1515	char szMsg[128];
1516	char *psz = &szMsg[0];
1517	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1518	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1519	psz += s_aTypes[i].cch;
1520
1521	if (pDesc->Gen.u1Present)
1522	ADD_STR(psz, "Present ");
1523	else
1524	ADD_STR(psz, "Not-Present ");
1525	# if HC_ARCH_BITS == 64
1526	if (pDesc->Gen.u1Long)
1527	ADD_STR(psz, "64-bit ");
1528	else
1529	ADD_STR(psz, "Comp ");
1530	# else
1531	if (pDesc->Gen.u1Granularity)
1532	ADD_STR(psz, "Page ");
1533	if (pDesc->Gen.u1DefBig)
1534	ADD_STR(psz, "32-bit ");
1535	else
1536	ADD_STR(psz, "16-bit ");
1537	# endif
1538	# undef ADD_STR
1539	*psz = '\0';
1540
1541	/*
1542	* Limit and Base and format the output.
1543	*/
1544	uint32_t u32Limit = X86DESC_LIMIT(*pDesc);
1545	if (pDesc->Gen.u1Granularity)
1546	u32Limit = u32Limit << PAGE_SHIFT \| PAGE_OFFSET_MASK;
1547
1548	# if HC_ARCH_BITS == 64
1549	uint64_t u32Base = X86DESC64_BASE(*pDesc);
1550
1551	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1552	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1553	# else
1554	uint32_t u32Base = X86DESC_BASE(*pDesc);
1555
1556	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1557	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1558	# endif
1559	}
1560
1561	/**
1562	* Formats a full register dump.
1563	*
1564	* @param pVM The VM to operate on.
1565	* @param pVCpu The VMCPU to operate on.
1566	* @param pCtx The context to format.
1567	*/
1568	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1569	{
1570	/*
1571	* Format the flags.
1572	*/
1573	static struct
1574	{
1575	const char pszSet; const char pszClear; uint32_t fFlag;
1576	} aFlags[] =
1577	{
1578	{ "vip",NULL, X86_EFL_VIP },
1579	{ "vif",NULL, X86_EFL_VIF },
1580	{ "ac", NULL, X86_EFL_AC },
1581	{ "vm", NULL, X86_EFL_VM },
1582	{ "rf", NULL, X86_EFL_RF },
1583	{ "nt", NULL, X86_EFL_NT },
1584	{ "ov", "nv", X86_EFL_OF },
1585	{ "dn", "up", X86_EFL_DF },
1586	{ "ei", "di", X86_EFL_IF },
1587	{ "tf", NULL, X86_EFL_TF },
1588	{ "nt", "pl", X86_EFL_SF },
1589	{ "nz", "zr", X86_EFL_ZF },
1590	{ "ac", "na", X86_EFL_AF },
1591	{ "po", "pe", X86_EFL_PF },
1592	{ "cy", "nc", X86_EFL_CF },
1593	};
1594	char szEFlags[80];
1595	char *psz = szEFlags;
1596	uint32_t efl = pCtx->eflags.u32;
1597	for (unsigned i = 0; i < RT_ELEMENTS(aFlags); i++)
1598	{
1599	const char *pszAdd = aFlags[i].fFlag & efl ? aFlags[i].pszSet : aFlags[i].pszClear;
1600	if (pszAdd)
1601	{
1602	strcpy(psz, pszAdd);
1603	psz += strlen(pszAdd);
1604	*psz++ = ' ';
1605	}
1606	}
1607	psz[-1] = '\0';
1608
1609
1610	/*
1611	* Format the registers.
1612	*/
1613	if (CPUMIsGuestIn64BitCode(pVCpu, CPUMCTX2CORE(pCtx)))
1614	{
1615	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1616	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1617	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1618	"r14=%016RX64 r15=%016RX64\n"
1619	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1620	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1621	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1622	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1623	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1624	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1625	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1626	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1627	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1628	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1629	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1630	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1631	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1632	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1633	,
1634	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1635	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1636	pCtx->r14, pCtx->r15,
1637	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1638	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1639	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1640	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1641	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1642	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1643	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1644	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1645	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1646	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1647	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1648	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1649	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1650	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1651	}
1652	else
1653	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1654	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1655	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1656	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1657	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1658	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1659	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1660	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1661	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1662	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1663	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1664	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1665	,
1666	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1667	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1668	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr[0], pCtx->dr[1],
1669	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr[2], pCtx->dr[3],
1670	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr[4], pCtx->dr[5],
1671	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr[6], pCtx->dr[7],
1672	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0, pCtx->cr2,
1673	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3, pCtx->cr4,
1674	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1675	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1676	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1677	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1678
1679	Log(("FPU:\n"
1680	"FCW=%04x FSW=%04x FTW=%02x\n"
1681	"FOP=%04x FPUIP=%08x CS=%04x Rsvrd1=%04x\n"
1682	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1683	,
1684	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
1685	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsvrd1,
1686	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
1687	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
1688
1689
1690	Log(("MSR:\n"
1691	"EFER =%016RX64\n"
1692	"PAT =%016RX64\n"
1693	"STAR =%016RX64\n"
1694	"CSTAR =%016RX64\n"
1695	"LSTAR =%016RX64\n"
1696	"SFMASK =%016RX64\n"
1697	"KERNELGSBASE =%016RX64\n",
1698	pCtx->msrEFER,
1699	pCtx->msrPAT,
1700	pCtx->msrSTAR,
1701	pCtx->msrCSTAR,
1702	pCtx->msrLSTAR,
1703	pCtx->msrSFMASK,
1704	pCtx->msrKERNELGSBASE));
1705
1706	}
1707	#endif /* VBOX_STRICT */
1708
1709	/* Dummy callback handlers. */
1710	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
1711	{
1712	return VINF_SUCCESS;
1713	}
1714
1715	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1716	{
1717	return VINF_SUCCESS;
1718	}
1719
1720	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1721	{
1722	return VINF_SUCCESS;
1723	}
1724
1725	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1726	{
1727	return VINF_SUCCESS;
1728	}
1729
1730	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM)
1731	{
1732	return VINF_SUCCESS;
1733	}
1734
1735	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM)
1736	{
1737	return VINF_SUCCESS;
1738	}
1739
1740	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM)
1741	{
1742	return VINF_SUCCESS;
1743	}
1744
1745	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1746	{
1747	return VINF_SUCCESS;
1748	}
1749
1750	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
1751	{
1752	return VINF_SUCCESS;
1753	}
1754
1755	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1756	{
1757	return VINF_SUCCESS;
1758	}

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp@ 30757

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