HWACCMR0.cpp@ 36877

Last change on this file since 36877 was 36858, checked in by vboxsync, 14 years ago
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1	/* $Id: HWACCMR0.cpp 36858 2011-04-27 15:05:06Z vboxsync $ */
2	/** @file
3	* HWACCM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HWACCM
23	#include <VBox/vmm/hwaccm.h>
24	#include <VBox/vmm/pgm.h>
25	#include "HWACCMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include <VBox/x86.h>
28	#include <VBox/vmm/hwacc_vmx.h>
29	#include <VBox/vmm/hwacc_svm.h>
30	#include <VBox/err.h>
31	#include <VBox/log.h>
32	#include <iprt/assert.h>
33	#include <iprt/asm.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/cpuset.h>
36	#include <iprt/mem.h>
37	#include <iprt/memobj.h>
38	#include <iprt/param.h>
39	#include <iprt/power.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42	#include "HWVMXR0.h"
43	#include "HWSVMR0.h"
44
45	/*******************************************************************************
46	* Internal Functions *
47	*******************************************************************************/
48	static DECLCALLBACK(void) hwaccmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
49	static DECLCALLBACK(void) hwaccmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
50	static DECLCALLBACK(void) hwaccmR0InitCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static bool hwaccmR0IsSubjectToVmxPreemptionTimerErratum(void);
52	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
53
54	/*******************************************************************************
55	* Global Variables *
56	*******************************************************************************/
57
58	static struct
59	{
60	HWACCM_CPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
61
62	/** Ring 0 handlers for VT-x and AMD-V. */
63	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu));
64	DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
65	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
66	DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
67	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
68	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
69	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
70	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
71	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
72	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVM pVM));
73
74	/** Maximum ASID allowed. */
75	uint32_t uMaxASID;
76
77	struct
78	{
79	/** Set to by us to indicate VMX is supported by the CPU. */
80	bool fSupported;
81	/** Whether we're using SUPR0EnableVTx or not. */
82	bool fUsingSUPR0EnableVTx;
83	/** Whether we're using the preemption timer or not. */
84	bool fUsePreemptTimer;
85	/** The shift mask employed by the VMX-Preemption timer. */
86	uint8_t cPreemptTimerShift;
87
88	/** Host CR4 value (set by ring-0 VMX init) */
89	uint64_t hostCR4;
90
91	/** Host EFER value (set by ring-0 VMX init) */
92	uint64_t hostEFER;
93
94	/** VMX MSR values */
95	struct
96	{
97	uint64_t feature_ctrl;
98	uint64_t vmx_basic_info;
99	VMX_CAPABILITY vmx_pin_ctls;
100	VMX_CAPABILITY vmx_proc_ctls;
101	VMX_CAPABILITY vmx_proc_ctls2;
102	VMX_CAPABILITY vmx_exit;
103	VMX_CAPABILITY vmx_entry;
104	uint64_t vmx_misc;
105	uint64_t vmx_cr0_fixed0;
106	uint64_t vmx_cr0_fixed1;
107	uint64_t vmx_cr4_fixed0;
108	uint64_t vmx_cr4_fixed1;
109	uint64_t vmx_vmcs_enum;
110	uint64_t vmx_eptcaps;
111	} msr;
112	/* Last instruction error */
113	uint32_t ulLastInstrError;
114	} vmx;
115	struct
116	{
117	/* HWCR msr (for diagnostics) */
118	uint64_t msrHWCR;
119
120	/** SVM revision. */
121	uint32_t u32Rev;
122
123	/** SVM feature bits from cpuid 0x8000000a */
124	uint32_t u32Features;
125
126	/** Set by us to indicate SVM is supported by the CPU. */
127	bool fSupported;
128	} svm;
129	/** Saved error from detection */
130	int32_t lLastError;
131
132	struct
133	{
134	uint32_t u32AMDFeatureECX;
135	uint32_t u32AMDFeatureEDX;
136	} cpuid;
137
138	HWACCMSTATE enmHwAccmState;
139
140	bool fGlobalInit;
141	volatile bool fSuspended;
142	} HWACCMR0Globals;
143
144
145	/**
146	* This is used to manage the status code of a RTMpOnAll in HWACCM.
147	*/
148	typedef struct HWACCMR0FIRSTRC
149	{
150	/** The status code. */
151	int32_t volatile rc;
152	/** The ID of the CPU reporting the first failure. */
153	RTCPUID volatile idCpu;
154	} HWACCMR0FIRSTRC;
155	/** Pointer to a first return code structure. */
156	typedef HWACCMR0FIRSTRC *PHWACCMR0FIRSTRC;
157
158
159	/**
160	* Initializes a first return code structure.
161	*
162	* @param pFirstRc The structure to init.
163	*/
164	static void hwaccmR0FirstRcInit(PHWACCMR0FIRSTRC pFirstRc)
165	{
166	pFirstRc->rc = VINF_SUCCESS;
167	pFirstRc->idCpu = NIL_RTCPUID;
168	}
169
170
171	/**
172	* Try se the status code (success ignored).
173	*
174	* @param pFirstRc The first return code structure.
175	* @param rc The status code.
176	*/
177	static void hwaccmR0FirstRcSetStatus(PHWACCMR0FIRSTRC pFirstRc, int rc)
178	{
179	if ( RT_FAILURE(rc)
180	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
181	pFirstRc->idCpu = RTMpCpuId();
182	}
183
184
185	/**
186	* Get the status code of a first return code structure.
187	*
188	* @returns The status code; VINF_SUCCESS or error status, no informational or
189	* warning errors.
190	* @param pFirstRc The first return code structure.
191	*/
192	static int hwaccmR0FirstRcGetStatus(PHWACCMR0FIRSTRC pFirstRc)
193	{
194	return pFirstRc->rc;
195	}
196
197
198	/**
199	* Get the CPU ID on which the failure status code was reported.
200	*
201	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
202	* @param pFirstRc The first return code structure.
203	*/
204	static RTCPUID hwaccmR0FirstRcGetCpuId(PHWACCMR0FIRSTRC pFirstRc)
205	{
206	return pFirstRc->idCpu;
207	}
208
209
210	/**
211	* Does global Ring-0 HWACCM initialization.
212	*
213	* @returns VBox status code.
214	*/
215	VMMR0DECL(int) HWACCMR0Init(void)
216	{
217	int rc;
218	bool fAMDVPresent = false;
219
220	HWACCMR0Globals.enmHwAccmState = HWACCMSTATE_UNINITIALIZED;
221	for (unsigned i = 0; i < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); i++)
222	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
223
224	/* Fill in all callbacks with placeholders. */
225	HWACCMR0Globals.pfnEnterSession = HWACCMR0DummyEnter;
226	HWACCMR0Globals.pfnLeaveSession = HWACCMR0DummyLeave;
227	HWACCMR0Globals.pfnSaveHostState = HWACCMR0DummySaveHostState;
228	HWACCMR0Globals.pfnLoadGuestState = HWACCMR0DummyLoadGuestState;
229	HWACCMR0Globals.pfnRunGuestCode = HWACCMR0DummyRunGuestCode;
230	HWACCMR0Globals.pfnEnableCpu = HWACCMR0DummyEnableCpu;
231	HWACCMR0Globals.pfnDisableCpu = HWACCMR0DummyDisableCpu;
232	HWACCMR0Globals.pfnInitVM = HWACCMR0DummyInitVM;
233	HWACCMR0Globals.pfnTermVM = HWACCMR0DummyTermVM;
234	HWACCMR0Globals.pfnSetupVM = HWACCMR0DummySetupVM;
235
236	/* Default is global VT-x/AMD-V init */
237	HWACCMR0Globals.fGlobalInit = true;
238
239	/*
240	* Make sure aCpuInfo is big enough for all the CPUs on this system.
241	*/
242	if (RTMpGetArraySize() > RT_ELEMENTS(HWACCMR0Globals.aCpuInfo))
243	{
244	LogRel(("HWACCM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(HWACCMR0Globals.aCpuInfo)));
245	return VERR_TOO_MANY_CPUS;
246	}
247
248	/*
249	* Check for VT-x and AMD-V capabilities
250	*/
251	if (ASMHasCpuId())
252	{
253	uint32_t u32FeaturesECX;
254	uint32_t u32Dummy;
255	uint32_t u32FeaturesEDX;
256	uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
257
258	ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
259	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
260	/* Query AMD features. */
261	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy, &HWACCMR0Globals.cpuid.u32AMDFeatureECX, &HWACCMR0Globals.cpuid.u32AMDFeatureEDX);
262
263	if ( u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
264	&& u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
265	&& u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX
266	)
267	{
268	/*
269	* Read all VMX MSRs if VMX is available. (same goes for RDMSR/WRMSR)
270	* We also assume all VMX-enabled CPUs support fxsave/fxrstor.
271	*/
272	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
273	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
274	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
275	)
276	{
277	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
278
279	/*
280	* First try use native kernel API for controlling VT-x.
281	* (This is only supported by some Mac OS X kernels atm.)
282	*/
283	HWACCMR0Globals.lLastError = rc = SUPR0EnableVTx(true /* fEnable */);
284	if (rc != VERR_NOT_SUPPORTED)
285	{
286	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
287	HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx = true;
288	if (RT_SUCCESS(rc))
289	{
290	HWACCMR0Globals.vmx.fSupported = true;
291	rc = SUPR0EnableVTx(false /* fEnable */);
292	AssertRC(rc);
293	}
294	}
295	else
296	{
297	HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx = false;
298
299	/* We need to check if VT-x has been properly initialized on all CPUs. Some BIOSes do a lousy job. */
300	HWACCMR0FIRSTRC FirstRc;
301	hwaccmR0FirstRcInit(&FirstRc);
302	HWACCMR0Globals.lLastError = RTMpOnAll(hwaccmR0InitCpu, (void *)u32VendorEBX, &FirstRc);
303	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
304	HWACCMR0Globals.lLastError = hwaccmR0FirstRcGetStatus(&FirstRc);
305	}
306	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
307	{
308	/* Reread in case we've changed it. */
309	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
310
311	if ( (HWACCMR0Globals.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
312	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
313	{
314	RTR0MEMOBJ pScatchMemObj;
315	void *pvScatchPage;
316	RTHCPHYS pScatchPagePhys;
317
318	HWACCMR0Globals.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
319	HWACCMR0Globals.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
320	HWACCMR0Globals.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
321	HWACCMR0Globals.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
322	HWACCMR0Globals.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
323	HWACCMR0Globals.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
324	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
325	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
326	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
327	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
328	HWACCMR0Globals.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
329	/* VPID 16 bits ASID. */
330	HWACCMR0Globals.uMaxASID = 0x10000; /* exclusive */
331
332	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
333	{
334	HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
335	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT\|VMX_VMCS_CTRL_PROC_EXEC2_VPID))
336	HWACCMR0Globals.vmx.msr.vmx_eptcaps = ASMRdMsr(MSR_IA32_VMX_EPT_CAPS);
337	}
338
339	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
340	{
341	HWACCMR0Globals.vmx.hostCR4 = ASMGetCR4();
342	HWACCMR0Globals.vmx.hostEFER = ASMRdMsr(MSR_K6_EFER);
343
344	rc = RTR0MemObjAllocCont(&pScatchMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
345	if (RT_FAILURE(rc))
346	return rc;
347
348	pvScatchPage = RTR0MemObjAddress(pScatchMemObj);
349	pScatchPagePhys = RTR0MemObjGetPagePhysAddr(pScatchMemObj, 0);
350	memset(pvScatchPage, 0, PAGE_SIZE);
351
352	/* Set revision dword at the beginning of the structure. */
353	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(HWACCMR0Globals.vmx.msr.vmx_basic_info);
354
355	/* Make sure we don't get rescheduled to another cpu during this probe. */
356	RTCCUINTREG fFlags = ASMIntDisableFlags();
357
358	/*
359	* Check CR4.VMXE
360	*/
361	if (!(HWACCMR0Globals.vmx.hostCR4 & X86_CR4_VMXE))
362	{
363	/* In theory this bit could be cleared behind our back. Which would cause #UD faults when we
364	* try to execute the VMX instructions...
365	*/
366	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4 \| X86_CR4_VMXE);
367	}
368
369	/* Enter VMX Root Mode */
370	rc = VMXEnable(pScatchPagePhys);
371	if (RT_FAILURE(rc))
372	{
373	/* KVM leaves the CPU in VMX root mode. Not only is this not allowed, it will crash the host when we enter raw mode, because
374	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify this bit)
375	* (b) turning off paging causes a #GP (unavoidable when switching from long to 32 bits mode or 32 bits to PAE)
376	*
377	* They should fix their code, but until they do we simply refuse to run.
378	*/
379	HWACCMR0Globals.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
380	}
381	else
382	{
383	HWACCMR0Globals.vmx.fSupported = true;
384	VMXDisable();
385
386	/*
387	* Check for the VMX-Preemption Timer and adjust for the
388	* "VMX-Preemption Timer Does Not Count Down at the Rate Specified" erratum.
389	*/
390	if ( HWACCMR0Globals.vmx.msr.vmx_pin_ctls.n.allowed1
391	& VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
392	{
393	HWACCMR0Globals.vmx.fUsePreemptTimer = true;
394	HWACCMR0Globals.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(HWACCMR0Globals.vmx.msr.vmx_misc);
395	if (hwaccmR0IsSubjectToVmxPreemptionTimerErratum())
396	HWACCMR0Globals.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
397	}
398	}
399
400	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it wasn't so before (some software could incorrectly think it's in VMX mode) */
401	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4);
402	ASMSetFlags(fFlags);
403
404	RTR0MemObjFree(pScatchMemObj, false);
405	if (RT_FAILURE(HWACCMR0Globals.lLastError))
406	return HWACCMR0Globals.lLastError;
407	}
408	}
409	else
410	{
411	AssertFailed(); /* can't hit this case anymore */
412	HWACCMR0Globals.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
413	}
414	}
415	#ifdef LOG_ENABLED
416	else
417	SUPR0Printf("hwaccmR0InitCpu failed with rc=%d\n", HWACCMR0Globals.lLastError);
418	#endif
419	}
420	else
421	HWACCMR0Globals.lLastError = VERR_VMX_NO_VMX;
422	}
423	else
424	if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
425	&& u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
426	&& u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX
427	)
428	{
429	/*
430	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
431	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
432	*/
433	if ( (HWACCMR0Globals.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
434	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
435	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
436	)
437	{
438	fAMDVPresent = true;
439
440	/* Query AMD features. */
441	ASMCpuId(0x8000000A, &HWACCMR0Globals.svm.u32Rev, &HWACCMR0Globals.uMaxASID, &u32Dummy, &HWACCMR0Globals.svm.u32Features);
442
443	/* We need to check if AMD-V has been properly initialized on all CPUs. Some BIOSes might do a poor job. */
444	HWACCMR0FIRSTRC FirstRc;
445	hwaccmR0FirstRcInit(&FirstRc);
446	rc = RTMpOnAll(hwaccmR0InitCpu, (void *)u32VendorEBX, &FirstRc); AssertRC(rc);
447	if (RT_SUCCESS(rc))
448	rc = hwaccmR0FirstRcGetStatus(&FirstRc);
449	#ifndef DEBUG_bird
450	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE, ("hwaccmR0InitCpu failed for cpu %d with rc=%d\n", hwaccmR0FirstRcGetCpuId(&FirstRc), rc));
451	#endif
452	if (RT_SUCCESS(rc))
453	{
454	/* Read the HWCR msr for diagnostics. */
455	HWACCMR0Globals.svm.msrHWCR = ASMRdMsr(MSR_K8_HWCR);
456	HWACCMR0Globals.svm.fSupported = true;
457	}
458	else
459	HWACCMR0Globals.lLastError = rc;
460	}
461	else
462	HWACCMR0Globals.lLastError = VERR_SVM_NO_SVM;
463	}
464	else
465	HWACCMR0Globals.lLastError = VERR_HWACCM_UNKNOWN_CPU;
466	}
467	else
468	HWACCMR0Globals.lLastError = VERR_HWACCM_NO_CPUID;
469
470	if (HWACCMR0Globals.vmx.fSupported)
471	{
472	HWACCMR0Globals.pfnEnterSession = VMXR0Enter;
473	HWACCMR0Globals.pfnLeaveSession = VMXR0Leave;
474	HWACCMR0Globals.pfnSaveHostState = VMXR0SaveHostState;
475	HWACCMR0Globals.pfnLoadGuestState = VMXR0LoadGuestState;
476	HWACCMR0Globals.pfnRunGuestCode = VMXR0RunGuestCode;
477	HWACCMR0Globals.pfnEnableCpu = VMXR0EnableCpu;
478	HWACCMR0Globals.pfnDisableCpu = VMXR0DisableCpu;
479	HWACCMR0Globals.pfnInitVM = VMXR0InitVM;
480	HWACCMR0Globals.pfnTermVM = VMXR0TermVM;
481	HWACCMR0Globals.pfnSetupVM = VMXR0SetupVM;
482	}
483	else
484	if (fAMDVPresent)
485	{
486	HWACCMR0Globals.pfnEnterSession = SVMR0Enter;
487	HWACCMR0Globals.pfnLeaveSession = SVMR0Leave;
488	HWACCMR0Globals.pfnSaveHostState = SVMR0SaveHostState;
489	HWACCMR0Globals.pfnLoadGuestState = SVMR0LoadGuestState;
490	HWACCMR0Globals.pfnRunGuestCode = SVMR0RunGuestCode;
491	HWACCMR0Globals.pfnEnableCpu = SVMR0EnableCpu;
492	HWACCMR0Globals.pfnDisableCpu = SVMR0DisableCpu;
493	HWACCMR0Globals.pfnInitVM = SVMR0InitVM;
494	HWACCMR0Globals.pfnTermVM = SVMR0TermVM;
495	HWACCMR0Globals.pfnSetupVM = SVMR0SetupVM;
496	}
497
498	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
499	{
500	rc = RTPowerNotificationRegister(hwaccmR0PowerCallback, 0);
501	AssertRC(rc);
502	}
503
504	return VINF_SUCCESS;
505	}
506
507
508	/**
509	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
510	* Down at the Rate Specified" erratum.
511	*
512	* Errata names and related steppings:
513	* - BA86 - D0.
514	* - AAX65 - C2.
515	* - AAU65 - C2, K0.
516	* - AAO95 - B1.
517	* - AAT59 - C2.
518	* - AAK139 - D0.
519	* - AAM126 - C0, C1, D0.
520	* - AAN92 - B1.
521	* - AAJ124 - C0, D0.
522	*
523	* - AAP86 - B1.
524	*
525	* Steppings: B1, C0, C1, C2, D0, K0.
526	*
527	* @returns true if subject to it, false if not.
528	*/
529	static bool hwaccmR0IsSubjectToVmxPreemptionTimerErratum(void)
530	{
531	uint32_t u = ASMCpuId_EAX(1);
532	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
533	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
534	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
535	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
536	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
537	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
538	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
539	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
540	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
541	\|\| u == UINT32_C(0x000106A0) /?321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification /
542	\|\| u == UINT32_C(0x000106A1) /?321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification /
543	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
544	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
545	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
546	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
547	)
548	return true;
549	return false;
550	}
551
552
553	/**
554	* Does global Ring-0 HWACCM termination.
555	*
556	* @returns VBox status code.
557	*/
558	VMMR0DECL(int) HWACCMR0Term(void)
559	{
560	int rc;
561	if ( HWACCMR0Globals.vmx.fSupported
562	&& HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
563	{
564	Assert(HWACCMR0Globals.fGlobalInit);
565	rc = SUPR0EnableVTx(false /* fEnable */);
566	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); iCpu++)
567	{
568	HWACCMR0Globals.aCpuInfo[iCpu].fConfigured = false;
569	Assert(HWACCMR0Globals.aCpuInfo[iCpu].pMemObj == NIL_RTR0MEMOBJ);
570	}
571	}
572	else
573	{
574	Assert(!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
575	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
576	{
577	rc = RTPowerNotificationDeregister(hwaccmR0PowerCallback, 0);
578	AssertRC(rc);
579	}
580	else
581	rc = VINF_SUCCESS;
582
583	/* Only disable VT-x/AMD-V on all CPUs if we enabled it before. */
584	if (HWACCMR0Globals.fGlobalInit)
585	{
586	HWACCMR0FIRSTRC FirstRc;
587	hwaccmR0FirstRcInit(&FirstRc);
588	rc = RTMpOnAll(hwaccmR0DisableCpuCallback, NULL, &FirstRc);
589	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
590	if (RT_SUCCESS(rc))
591	{
592	rc = hwaccmR0FirstRcGetStatus(&FirstRc);
593	AssertMsgRC(rc, ("%u: %Rrc\n", hwaccmR0FirstRcGetCpuId(&FirstRc), rc));
594	}
595	}
596
597	/* Free the per-cpu pages used for VT-x and AMD-V */
598	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
599	{
600	if (HWACCMR0Globals.aCpuInfo[i].pMemObj != NIL_RTR0MEMOBJ)
601	{
602	RTR0MemObjFree(HWACCMR0Globals.aCpuInfo[i].pMemObj, false);
603	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
604	}
605	}
606	}
607	return rc;
608	}
609
610
611	/**
612	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
613	* is to be called on the target cpus.
614	*
615	* @param idCpu The identifier for the CPU the function is called on.
616	* @param pvUser1 The 1st user argument.
617	* @param pvUser2 The 2nd user argument.
618	*/
619	static DECLCALLBACK(void) hwaccmR0InitCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
620	{
621	unsigned u32VendorEBX = (uintptr_t)pvUser1;
622	PHWACCMR0FIRSTRC pFirstRc = (PHWACCMR0FIRSTRC)pvUser2;
623	uint64_t val;
624	int rc;
625
626	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
627
628	if (u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX)
629	{
630	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
631
632	/*
633	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
634	* Once the lock bit is set, this MSR can no longer be modified.
635	*/
636	if ( !(val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
637	\|\| ((val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK)) == MSR_IA32_FEATURE_CONTROL_VMXON) /* Some BIOSes forget to set the locked bit. */
638	)
639	{
640	/* MSR is not yet locked; we can change it ourselves here */
641	ASMWrMsr(MSR_IA32_FEATURE_CONTROL, HWACCMR0Globals.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
642	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
643	}
644	if ( (val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
645	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
646	rc = VINF_SUCCESS;
647	else
648	rc = VERR_VMX_MSR_LOCKED_OR_DISABLED;
649	}
650	else if (u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX)
651	{
652	/* Check if SVM is disabled */
653	val = ASMRdMsr(MSR_K8_VM_CR);
654	if (!(val & MSR_K8_VM_CR_SVM_DISABLE))
655	{
656	/* Turn on SVM in the EFER MSR. */
657	val = ASMRdMsr(MSR_K6_EFER);
658	if (val & MSR_K6_EFER_SVME)
659	rc = VERR_SVM_IN_USE;
660	else
661	{
662	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
663
664	/* Paranoia. */
665	val = ASMRdMsr(MSR_K6_EFER);
666	if (val & MSR_K6_EFER_SVME)
667	{
668	/* Restore previous value. */
669	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
670	rc = VINF_SUCCESS;
671	}
672	else
673	rc = VERR_SVM_ILLEGAL_EFER_MSR;
674	}
675	}
676	else
677	rc = VERR_SVM_DISABLED;
678	}
679	else
680	{
681	AssertFailed(); /* can't happen */
682	rc = VERR_INTERNAL_ERROR_5;
683	}
684
685	hwaccmR0FirstRcSetStatus(pFirstRc, rc);
686	}
687
688
689	/**
690	* Sets up HWACCM on all cpus.
691	*
692	* @returns VBox status code.
693	* @param pVM The VM to operate on.
694	*
695	*/
696	VMMR0DECL(int) HWACCMR0EnableAllCpus(PVM pVM)
697	{
698	AssertCompile(sizeof(HWACCMR0Globals.enmHwAccmState) == sizeof(uint32_t));
699
700	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
701	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
702	return VERR_HWACCM_SUSPEND_PENDING;
703
704	if (ASMAtomicCmpXchgU32((volatile uint32_t *)&HWACCMR0Globals.enmHwAccmState, HWACCMSTATE_ENABLED, HWACCMSTATE_UNINITIALIZED))
705	{
706	int rc;
707
708	HWACCMR0Globals.fGlobalInit = pVM->hwaccm.s.fGlobalInit;
709
710	if ( HWACCMR0Globals.vmx.fSupported
711	&& HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
712	{
713	rc = SUPR0EnableVTx(true /* fEnable */);
714	if (RT_SUCCESS(rc))
715	{
716	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); iCpu++)
717	{
718	HWACCMR0Globals.aCpuInfo[iCpu].fConfigured = true;
719	Assert(HWACCMR0Globals.aCpuInfo[iCpu].pMemObj == NIL_RTR0MEMOBJ);
720	}
721	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
722	HWACCMR0Globals.fGlobalInit = pVM->hwaccm.s.fGlobalInit = true;
723	}
724	else
725	AssertMsgFailed(("HWACCMR0EnableAllCpus/SUPR0EnableVTx: rc=%Rrc\n", rc));
726	}
727	else
728	{
729	/* Allocate one page per cpu for the global vt-x and amd-v pages */
730	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
731	{
732	Assert(!HWACCMR0Globals.aCpuInfo[i].pMemObj);
733
734	/** @todo this is rather dangerous if cpus can be taken offline; we don't care for now */
735	if (RTMpIsCpuOnline(i))
736	{
737	rc = RTR0MemObjAllocCont(&HWACCMR0Globals.aCpuInfo[i].pMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
738	AssertRC(rc);
739	if (RT_FAILURE(rc))
740	return rc;
741
742	void *pvR0 = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[i].pMemObj);
743	Assert(pvR0);
744	ASMMemZeroPage(pvR0);
745
746	#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
747	SUPR0Printf("address %x phys %x\n", pvR0, (uint32_t)RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[i].pMemObj, 0));
748	#endif
749	}
750	}
751	if (HWACCMR0Globals.fGlobalInit)
752	{
753	/* First time, so initialize each cpu/core */
754	HWACCMR0FIRSTRC FirstRc;
755	hwaccmR0FirstRcInit(&FirstRc);
756	rc = RTMpOnAll(hwaccmR0EnableCpuCallback, (void *)pVM, &FirstRc);
757	if (RT_SUCCESS(rc))
758	rc = hwaccmR0FirstRcGetStatus(&FirstRc);
759	AssertMsgRC(rc, ("HWACCMR0EnableAllCpus failed for cpu %d with rc=%d\n", hwaccmR0FirstRcGetCpuId(&FirstRc), rc));
760	}
761	else
762	rc = VINF_SUCCESS;
763	}
764
765	return rc;
766	}
767	return VINF_SUCCESS;
768	}
769
770	/**
771	* Disable VT-x or AMD-V on the current CPU
772	*
773	* @returns VBox status code.
774	* @param pVM VM handle (can be 0!)
775	* @param idCpu The identifier for the CPU the function is called on.
776	*/
777	static int hwaccmR0EnableCpu(PVM pVM, RTCPUID idCpu)
778	{
779	void *pvPageCpu;
780	RTHCPHYS pPageCpuPhys;
781	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
782
783	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
784	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
785	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
786	Assert(!pCpu->fConfigured);
787	Assert(!HWACCMR0Globals.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
788
789	pCpu->idCpu = idCpu;
790
791	/* Make sure we start with a clean TLB. */
792	pCpu->fFlushTLB = true;
793
794	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
795	pCpu->cTLBFlushes = 0;
796
797	/* Should never happen */
798	if (!pCpu->pMemObj)
799	{
800	AssertFailed();
801	return VERR_INTERNAL_ERROR;
802	}
803
804	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
805	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
806
807	int rc = HWACCMR0Globals.pfnEnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
808	AssertRC(rc);
809	if (RT_SUCCESS(rc))
810	pCpu->fConfigured = true;
811
812	return rc;
813	}
814
815
816	/**
817	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
818	* is to be called on the target cpus.
819	*
820	* @param idCpu The identifier for the CPU the function is called on.
821	* @param pvUser1 The 1st user argument.
822	* @param pvUser2 The 2nd user argument.
823	*/
824	static DECLCALLBACK(void) hwaccmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
825	{
826	PVM pVM = (PVM)pvUser1; /* can be NULL! */
827	PHWACCMR0FIRSTRC pFirstRc = (PHWACCMR0FIRSTRC)pvUser2;
828	AssertReturnVoid(HWACCMR0Globals.fGlobalInit);
829	hwaccmR0FirstRcSetStatus(pFirstRc, hwaccmR0EnableCpu(pVM, idCpu));
830	}
831
832
833	/**
834	* Disable VT-x or AMD-V on the current CPU
835	*
836	* @returns VBox status code.
837	* @param idCpu The identifier for the CPU the function is called on.
838	*/
839	static int hwaccmR0DisableCpu(RTCPUID idCpu)
840	{
841	void *pvPageCpu;
842	RTHCPHYS pPageCpuPhys;
843	int rc;
844	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
845
846	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
847	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
848	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
849	Assert(!HWACCMR0Globals.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
850	Assert(!pCpu->fConfigured \|\| pCpu->pMemObj);
851
852	if (!pCpu->pMemObj)
853	return (pCpu->fConfigured) ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
854
855	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
856	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
857
858	if (pCpu->fConfigured)
859	{
860	rc = HWACCMR0Globals.pfnDisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
861	AssertRC(rc);
862	pCpu->fConfigured = false;
863	}
864	else
865	rc = VINF_SUCCESS; /* nothing to do */
866
867	pCpu->uCurrentASID = 0;
868	return rc;
869	}
870
871	/**
872	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
873	* is to be called on the target cpus.
874	*
875	* @param idCpu The identifier for the CPU the function is called on.
876	* @param pvUser1 The 1st user argument.
877	* @param pvUser2 The 2nd user argument.
878	*/
879	static DECLCALLBACK(void) hwaccmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
880	{
881	PHWACCMR0FIRSTRC pFirstRc = (PHWACCMR0FIRSTRC)pvUser2;
882	AssertReturnVoid(HWACCMR0Globals.fGlobalInit);
883	hwaccmR0FirstRcSetStatus(pFirstRc, hwaccmR0DisableCpu(idCpu));
884	}
885
886	/**
887	* Called whenever a system power state change occurs.
888	*
889	* @param enmEvent Power event
890	* @param pvUser User argument
891	*/
892	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
893	{
894	NOREF(pvUser);
895	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
896
897	#ifdef LOG_ENABLED
898	if (enmEvent == RTPOWEREVENT_SUSPEND)
899	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
900	else
901	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_RESUME\n");
902	#endif
903
904	if (enmEvent == RTPOWEREVENT_SUSPEND)
905	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, true);
906
907	if (HWACCMR0Globals.enmHwAccmState == HWACCMSTATE_ENABLED)
908	{
909	int rc;
910	HWACCMR0FIRSTRC FirstRc;
911	hwaccmR0FirstRcInit(&FirstRc);
912
913	if (enmEvent == RTPOWEREVENT_SUSPEND)
914	{
915	if (HWACCMR0Globals.fGlobalInit)
916	{
917	/* Turn off VT-x or AMD-V on all CPUs. */
918	rc = RTMpOnAll(hwaccmR0DisableCpuCallback, NULL, &FirstRc);
919	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
920	}
921	/* else nothing to do here for the local init case */
922	}
923	else
924	{
925	/* Reinit the CPUs from scratch as the suspend state might have messed with the MSRs. (lousy BIOSes as usual) */
926	uintptr_t uFirstArg = HWACCMR0Globals.vmx.fSupported ? X86_CPUID_VENDOR_INTEL_EBX : X86_CPUID_VENDOR_AMD_EBX;
927	rc = RTMpOnAll(hwaccmR0InitCpu, (void *)uFirstArg , &FirstRc);
928	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
929	if (RT_SUCCESS(rc))
930	rc = hwaccmR0FirstRcGetStatus(&FirstRc);
931	#ifdef LOG_ENABLED
932	if (RT_FAILURE(rc))
933	SUPR0Printf("hwaccmR0PowerCallback hwaccmR0InitCpu failed with %Rc\n", rc);
934	#endif
935
936	if (HWACCMR0Globals.fGlobalInit)
937	{
938	/* Turn VT-x or AMD-V back on on all CPUs. */
939	rc = RTMpOnAll(hwaccmR0EnableCpuCallback, NULL, &FirstRc /* output ignored */);
940	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
941	}
942	/* else nothing to do here for the local init case */
943	}
944	}
945	if (enmEvent == RTPOWEREVENT_RESUME)
946	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, false);
947	}
948
949
950	/**
951	* Does Ring-0 per VM HWACCM initialization.
952	*
953	* This is mainly to check that the Host CPU mode is compatible
954	* with VMX.
955	*
956	* @returns VBox status code.
957	* @param pVM The VM to operate on.
958	*/
959	VMMR0DECL(int) HWACCMR0InitVM(PVM pVM)
960	{
961	int rc;
962
963	AssertReturn(pVM, VERR_INVALID_PARAMETER);
964
965	#ifdef LOG_ENABLED
966	SUPR0Printf("HWACCMR0InitVM: %p\n", pVM);
967	#endif
968
969	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
970	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
971	return VERR_HWACCM_SUSPEND_PENDING;
972
973	pVM->hwaccm.s.vmx.fSupported = HWACCMR0Globals.vmx.fSupported;
974	pVM->hwaccm.s.svm.fSupported = HWACCMR0Globals.svm.fSupported;
975
976	pVM->hwaccm.s.vmx.fUsePreemptTimer = HWACCMR0Globals.vmx.fUsePreemptTimer;
977	pVM->hwaccm.s.vmx.cPreemptTimerShift = HWACCMR0Globals.vmx.cPreemptTimerShift;
978	pVM->hwaccm.s.vmx.msr.feature_ctrl = HWACCMR0Globals.vmx.msr.feature_ctrl;
979	pVM->hwaccm.s.vmx.hostCR4 = HWACCMR0Globals.vmx.hostCR4;
980	pVM->hwaccm.s.vmx.hostEFER = HWACCMR0Globals.vmx.hostEFER;
981	pVM->hwaccm.s.vmx.msr.vmx_basic_info = HWACCMR0Globals.vmx.msr.vmx_basic_info;
982	pVM->hwaccm.s.vmx.msr.vmx_pin_ctls = HWACCMR0Globals.vmx.msr.vmx_pin_ctls;
983	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls = HWACCMR0Globals.vmx.msr.vmx_proc_ctls;
984	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2 = HWACCMR0Globals.vmx.msr.vmx_proc_ctls2;
985	pVM->hwaccm.s.vmx.msr.vmx_exit = HWACCMR0Globals.vmx.msr.vmx_exit;
986	pVM->hwaccm.s.vmx.msr.vmx_entry = HWACCMR0Globals.vmx.msr.vmx_entry;
987	pVM->hwaccm.s.vmx.msr.vmx_misc = HWACCMR0Globals.vmx.msr.vmx_misc;
988	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0;
989	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1;
990	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0;
991	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1;
992	pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum = HWACCMR0Globals.vmx.msr.vmx_vmcs_enum;
993	pVM->hwaccm.s.vmx.msr.vmx_eptcaps = HWACCMR0Globals.vmx.msr.vmx_eptcaps;
994	pVM->hwaccm.s.svm.msrHWCR = HWACCMR0Globals.svm.msrHWCR;
995	pVM->hwaccm.s.svm.u32Rev = HWACCMR0Globals.svm.u32Rev;
996	pVM->hwaccm.s.svm.u32Features = HWACCMR0Globals.svm.u32Features;
997	pVM->hwaccm.s.cpuid.u32AMDFeatureECX = HWACCMR0Globals.cpuid.u32AMDFeatureECX;
998	pVM->hwaccm.s.cpuid.u32AMDFeatureEDX = HWACCMR0Globals.cpuid.u32AMDFeatureEDX;
999	pVM->hwaccm.s.lLastError = HWACCMR0Globals.lLastError;
1000
1001	pVM->hwaccm.s.uMaxASID = HWACCMR0Globals.uMaxASID;
1002
1003
1004	if (!pVM->hwaccm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1005	{
1006	pVM->hwaccm.s.cMaxResumeLoops = 1024;
1007	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1008	if (RTThreadPreemptIsPendingTrusty())
1009	pVM->hwaccm.s.cMaxResumeLoops = 8192;
1010	#endif
1011	}
1012
1013	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1014	{
1015	PVMCPU pVCpu = &pVM->aCpus[i];
1016
1017	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1018
1019	/* Invalidate the last cpu we were running on. */
1020	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
1021
1022	/* we'll aways increment this the first time (host uses ASID 0) */
1023	pVCpu->hwaccm.s.uCurrentASID = 0;
1024	}
1025
1026	RTCCUINTREG fFlags = ASMIntDisableFlags();
1027	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1028
1029	/* Note: Not correct as we can be rescheduled to a different cpu, but the fInUse case is mostly for debugging. */
1030	ASMAtomicWriteBool(&pCpu->fInUse, true);
1031	ASMSetFlags(fFlags);
1032
1033	/* Init a VT-x or AMD-V VM. */
1034	rc = HWACCMR0Globals.pfnInitVM(pVM);
1035
1036	ASMAtomicWriteBool(&pCpu->fInUse, false);
1037	return rc;
1038	}
1039
1040
1041	/**
1042	* Does Ring-0 per VM HWACCM termination.
1043	*
1044	* @returns VBox status code.
1045	* @param pVM The VM to operate on.
1046	*/
1047	VMMR0DECL(int) HWACCMR0TermVM(PVM pVM)
1048	{
1049	int rc;
1050
1051	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1052
1053	#ifdef LOG_ENABLED
1054	SUPR0Printf("HWACCMR0TermVM: %p\n", pVM);
1055	#endif
1056
1057	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
1058	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1059
1060	/* @note Not correct as we can be rescheduled to a different cpu, but the fInUse case is mostly for debugging. */
1061	RTCCUINTREG fFlags = ASMIntDisableFlags();
1062	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1063
1064	ASMAtomicWriteBool(&pCpu->fInUse, true);
1065	ASMSetFlags(fFlags);
1066
1067	/* Terminate a VT-x or AMD-V VM. */
1068	rc = HWACCMR0Globals.pfnTermVM(pVM);
1069
1070	ASMAtomicWriteBool(&pCpu->fInUse, false);
1071	return rc;
1072	}
1073
1074
1075	/**
1076	* Sets up a VT-x or AMD-V session
1077	*
1078	* @returns VBox status code.
1079	* @param pVM The VM to operate on.
1080	*/
1081	VMMR0DECL(int) HWACCMR0SetupVM(PVM pVM)
1082	{
1083	int rc;
1084	RTCPUID idCpu = RTMpCpuId();
1085	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1086
1087	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1088
1089	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
1090	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1091
1092	#ifdef LOG_ENABLED
1093	SUPR0Printf("HWACCMR0SetupVM: %p\n", pVM);
1094	#endif
1095
1096	ASMAtomicWriteBool(&pCpu->fInUse, true);
1097
1098	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1099	{
1100	/* On first entry we'll sync everything. */
1101	pVM->aCpus[i].hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1102	}
1103
1104	/* Enable VT-x or AMD-V if local init is required. */
1105	if (!HWACCMR0Globals.fGlobalInit)
1106	{
1107	rc = hwaccmR0EnableCpu(pVM, idCpu);
1108	AssertRCReturn(rc, rc);
1109	}
1110
1111	/* Setup VT-x or AMD-V. */
1112	rc = HWACCMR0Globals.pfnSetupVM(pVM);
1113
1114	/* Disable VT-x or AMD-V if local init was done before. */
1115	if (!HWACCMR0Globals.fGlobalInit)
1116	{
1117	rc = hwaccmR0DisableCpu(idCpu);
1118	AssertRC(rc);
1119	}
1120
1121	ASMAtomicWriteBool(&pCpu->fInUse, false);
1122
1123	return rc;
1124	}
1125
1126
1127	/**
1128	* Enters the VT-x or AMD-V session
1129	*
1130	* @returns VBox status code.
1131	* @param pVM The VM to operate on.
1132	* @param pVCpu VMCPUD id.
1133	*/
1134	VMMR0DECL(int) HWACCMR0Enter(PVM pVM, PVMCPU pVCpu)
1135	{
1136	PCPUMCTX pCtx;
1137	int rc;
1138	RTCPUID idCpu = RTMpCpuId();
1139	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1140
1141	/* Make sure we can't enter a session after we've disabled hwaccm in preparation of a suspend. */
1142	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1143	ASMAtomicWriteBool(&pCpu->fInUse, true);
1144
1145	AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == NIL_RTCPUID, ("%d", (int)pVCpu->hwaccm.s.idEnteredCpu));
1146	pVCpu->hwaccm.s.idEnteredCpu = idCpu;
1147
1148	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1149
1150	/* Always load the guest's FPU/XMM state on-demand. */
1151	CPUMDeactivateGuestFPUState(pVCpu);
1152
1153	/* Always load the guest's debug state on-demand. */
1154	CPUMDeactivateGuestDebugState(pVCpu);
1155
1156	/* Always reload the host context and the guest's CR0 register. (!!!!) */
1157	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0 \| HWACCM_CHANGED_HOST_CONTEXT;
1158
1159	/* Setup the register and mask according to the current execution mode. */
1160	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1161	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFFFFFFFFFF);
1162	else
1163	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFF);
1164
1165	/* Enable VT-x or AMD-V if local init is required. */
1166	if (!HWACCMR0Globals.fGlobalInit)
1167	{
1168	rc = hwaccmR0EnableCpu(pVM, idCpu);
1169	AssertRCReturn(rc, rc);
1170	}
1171
1172	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1173	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1174	#endif
1175
1176	rc = HWACCMR0Globals.pfnEnterSession(pVM, pVCpu, pCpu);
1177	AssertRC(rc);
1178	/* We must save the host context here (VT-x) as we might be rescheduled on a different cpu after a long jump back to ring 3. */
1179	rc \|= HWACCMR0Globals.pfnSaveHostState(pVM, pVCpu);
1180	AssertRC(rc);
1181	rc \|= HWACCMR0Globals.pfnLoadGuestState(pVM, pVCpu, pCtx);
1182	AssertRC(rc);
1183
1184	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1185	if (fStartedSet)
1186	PGMRZDynMapReleaseAutoSet(pVCpu);
1187	#endif
1188
1189	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1190	if (RT_FAILURE(rc))
1191	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1192	return rc;
1193	}
1194
1195
1196	/**
1197	* Leaves the VT-x or AMD-V session
1198	*
1199	* @returns VBox status code.
1200	* @param pVM The VM to operate on.
1201	* @param pVCpu VMCPUD id.
1202	*/
1203	VMMR0DECL(int) HWACCMR0Leave(PVM pVM, PVMCPU pVCpu)
1204	{
1205	PCPUMCTX pCtx;
1206	int rc;
1207	RTCPUID idCpu = RTMpCpuId();
1208	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1209
1210	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1211
1212	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1213
1214	/* Note: It's rather tricky with longjmps done by e.g. Log statements or the page fault handler.
1215	* We must restore the host FPU here to make absolutely sure we don't leave the guest FPU state active
1216	* or trash somebody else's FPU state.
1217	*/
1218	/* Save the guest FPU and XMM state if necessary. */
1219	if (CPUMIsGuestFPUStateActive(pVCpu))
1220	{
1221	Log2(("CPUMR0SaveGuestFPU\n"));
1222	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
1223
1224	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1225	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1226	}
1227
1228	rc = HWACCMR0Globals.pfnLeaveSession(pVM, pVCpu, pCtx);
1229
1230	/* We don't pass on invlpg information to the recompiler for nested paging guests, so we must make sure the recompiler flushes its TLB
1231	* the next time it executes code.
1232	*/
1233	if ( pVM->hwaccm.s.fNestedPaging
1234	&& CPUMIsGuestInPagedProtectedModeEx(pCtx))
1235	{
1236	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
1237	}
1238
1239	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1240	#ifdef RT_STRICT
1241	if (RT_UNLIKELY( pVCpu->hwaccm.s.idEnteredCpu != idCpu
1242	&& RT_FAILURE(rc)))
1243	{
1244	AssertMsgFailed(("Owner is %d, I'm %d", (int)pVCpu->hwaccm.s.idEnteredCpu, (int)idCpu));
1245	rc = VERR_INTERNAL_ERROR;
1246	}
1247	#endif
1248	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1249
1250	/* Disable VT-x or AMD-V if local init was done before. */
1251	if (!HWACCMR0Globals.fGlobalInit)
1252	{
1253	rc = hwaccmR0DisableCpu(idCpu);
1254	AssertRC(rc);
1255
1256	/* Reset these to force a TLB flush for the next entry. (-> EXPENSIVE) */
1257	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
1258	pVCpu->hwaccm.s.uCurrentASID = 0;
1259	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1260	}
1261
1262	ASMAtomicWriteBool(&pCpu->fInUse, false);
1263	return rc;
1264	}
1265
1266	/**
1267	* Runs guest code in a hardware accelerated VM.
1268	*
1269	* @returns VBox status code.
1270	* @param pVM The VM to operate on.
1271	* @param pVCpu VMCPUD id.
1272	*/
1273	VMMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1274	{
1275	CPUMCTX *pCtx;
1276	int rc;
1277	#ifdef VBOX_STRICT
1278	RTCPUID idCpu = RTMpCpuId(); NOREF(idCpu);
1279	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1280	#endif
1281
1282	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1283	Assert(HWACCMR0Globals.aCpuInfo[idCpu].fConfigured);
1284	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1285	Assert(ASMAtomicReadBool(&pCpu->fInUse) == true);
1286
1287	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1288	PGMRZDynMapStartAutoSet(pVCpu);
1289	#endif
1290
1291	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1292
1293	rc = HWACCMR0Globals.pfnRunGuestCode(pVM, pVCpu, pCtx);
1294
1295	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1296	PGMRZDynMapReleaseAutoSet(pVCpu);
1297	#endif
1298	return rc;
1299	}
1300
1301
1302	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1303	/**
1304	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1305	*
1306	* @returns VBox status code.
1307	* @param pVM VM handle.
1308	* @param pVCpu VMCPU handle.
1309	* @param pCtx CPU context
1310	*/
1311	VMMR0DECL(int) HWACCMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1312	{
1313	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFpu64SwitchBack);
1314	if (pVM->hwaccm.s.vmx.fSupported)
1315	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1316
1317	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1318	}
1319
1320	/**
1321	* Save guest debug state (64 bits guest mode & 32 bits host only)
1322	*
1323	* @returns VBox status code.
1324	* @param pVM VM handle.
1325	* @param pVCpu VMCPU handle.
1326	* @param pCtx CPU context
1327	*/
1328	VMMR0DECL(int) HWACCMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1329	{
1330	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDebug64SwitchBack);
1331	if (pVM->hwaccm.s.vmx.fSupported)
1332	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1333
1334	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1335	}
1336
1337	/**
1338	* Test the 32->64 bits switcher
1339	*
1340	* @returns VBox status code.
1341	* @param pVM VM handle.
1342	*/
1343	VMMR0DECL(int) HWACCMR0TestSwitcher3264(PVM pVM)
1344	{
1345	PVMCPU pVCpu = &pVM->aCpus[0];
1346	CPUMCTX *pCtx;
1347	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1348	int rc;
1349
1350	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1351
1352	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1353	if (pVM->hwaccm.s.vmx.fSupported)
1354	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1355	else
1356	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1357	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1358	return rc;
1359	}
1360
1361	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1362
1363	/**
1364	* Returns suspend status of the host
1365	*
1366	* @returns Suspend pending or not
1367	*/
1368	VMMR0DECL(bool) HWACCMR0SuspendPending()
1369	{
1370	return ASMAtomicReadBool(&HWACCMR0Globals.fSuspended);
1371	}
1372
1373	/**
1374	* Returns the cpu structure for the current cpu.
1375	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1376	*
1377	* @returns cpu structure pointer
1378	*/
1379	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu()
1380	{
1381	RTCPUID idCpu = RTMpCpuId();
1382
1383	return &HWACCMR0Globals.aCpuInfo[idCpu];
1384	}
1385
1386	/**
1387	* Returns the cpu structure for the current cpu.
1388	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1389	*
1390	* @returns cpu structure pointer
1391	* @param idCpu id of the VCPU
1392	*/
1393	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu)
1394	{
1395	return &HWACCMR0Globals.aCpuInfo[idCpu];
1396	}
1397
1398	/**
1399	* Save a pending IO read.
1400	*
1401	* @param pVCpu The VMCPU to operate on.
1402	* @param GCPtrRip Address of IO instruction
1403	* @param GCPtrRipNext Address of the next instruction
1404	* @param uPort Port address
1405	* @param uAndVal And mask for saving the result in eax
1406	* @param cbSize Read size
1407	*/
1408	VMMR0DECL(void) HWACCMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1409	{
1410	pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_PORT_READ;
1411	pVCpu->hwaccm.s.PendingIO.GCPtrRip = GCPtrRip;
1412	pVCpu->hwaccm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1413	pVCpu->hwaccm.s.PendingIO.s.Port.uPort = uPort;
1414	pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal = uAndVal;
1415	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize = cbSize;
1416	return;
1417	}
1418
1419	/**
1420	* Save a pending IO write.
1421	*
1422	* @param pVCpu The VMCPU to operate on.
1423	* @param GCPtrRIP Address of IO instruction
1424	* @param uPort Port address
1425	* @param uAndVal And mask for fetching the result from eax
1426	* @param cbSize Read size
1427	*/
1428	VMMR0DECL(void) HWACCMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1429	{
1430	pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_PORT_WRITE;
1431	pVCpu->hwaccm.s.PendingIO.GCPtrRip = GCPtrRip;
1432	pVCpu->hwaccm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1433	pVCpu->hwaccm.s.PendingIO.s.Port.uPort = uPort;
1434	pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal = uAndVal;
1435	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize = cbSize;
1436	return;
1437	}
1438
1439	/**
1440	* Disable VT-x if it's active and the current switcher turns off paging
1441	*
1442	* @returns VBox status code.
1443	* @param pVM VM handle.
1444	* @param pfVTxDisabled VT-x was disabled or not (out)
1445	*/
1446	VMMR0DECL(int) HWACCMR0EnterSwitcher(PVM pVM, bool *pfVTxDisabled)
1447	{
1448	Assert(!(ASMGetFlags() & X86_EFL_IF) \|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1449
1450	*pfVTxDisabled = false;
1451
1452	if ( HWACCMR0Globals.enmHwAccmState != HWACCMSTATE_ENABLED
1453	\|\| !HWACCMR0Globals.vmx.fSupported /* no such issues with AMD-V */
1454	\|\| !HWACCMR0Globals.fGlobalInit /* Local init implies the CPU is currently not in VMX root mode. */)
1455	return VINF_SUCCESS; /* nothing to do */
1456
1457	switch(VMMGetSwitcher(pVM))
1458	{
1459	case VMMSWITCHER_32_TO_32:
1460	case VMMSWITCHER_PAE_TO_PAE:
1461	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1462
1463	case VMMSWITCHER_32_TO_PAE:
1464	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1465	case VMMSWITCHER_AMD64_TO_32:
1466	case VMMSWITCHER_AMD64_TO_PAE:
1467	break; /* unsafe switchers */
1468
1469	default:
1470	AssertFailed();
1471	return VERR_INTERNAL_ERROR;
1472	}
1473
1474	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1475	void *pvPageCpu;
1476	RTHCPHYS pPageCpuPhys;
1477
1478	AssertReturn(pCpu && pCpu->pMemObj, VERR_INTERNAL_ERROR);
1479	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
1480	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
1481
1482	*pfVTxDisabled = true;
1483	return VMXR0DisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
1484	}
1485
1486	/**
1487	* Enable VT-x if was active and the current switcher turned off paging
1488	*
1489	* @returns VBox status code.
1490	* @param pVM VM handle.
1491	* @param fVTxDisabled VT-x was disabled or not
1492	*/
1493	VMMR0DECL(int) HWACCMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1494	{
1495	Assert(!(ASMGetFlags() & X86_EFL_IF));
1496
1497	if (!fVTxDisabled)
1498	return VINF_SUCCESS; /* nothing to do */
1499
1500	Assert( HWACCMR0Globals.enmHwAccmState == HWACCMSTATE_ENABLED
1501	&& HWACCMR0Globals.vmx.fSupported
1502	&& HWACCMR0Globals.fGlobalInit);
1503
1504	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1505	void *pvPageCpu;
1506	RTHCPHYS pPageCpuPhys;
1507
1508	AssertReturn(pCpu && pCpu->pMemObj, VERR_INTERNAL_ERROR);
1509	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
1510	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
1511
1512	return VMXR0EnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
1513	}
1514
1515	#ifdef VBOX_STRICT
1516	/**
1517	* Dumps a descriptor.
1518	*
1519	* @param pDesc Descriptor to dump.
1520	* @param Sel Selector number.
1521	* @param pszMsg Message to prepend the log entry with.
1522	*/
1523	VMMR0DECL(void) HWACCMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1524	{
1525	/*
1526	* Make variable description string.
1527	*/
1528	static struct
1529	{
1530	unsigned cch;
1531	const char *psz;
1532	} const s_aTypes[32] =
1533	{
1534	# define STRENTRY(str) { sizeof(str) - 1, str }
1535
1536	/* system */
1537	# if HC_ARCH_BITS == 64
1538	STRENTRY("Reserved0 "), /* 0x00 */
1539	STRENTRY("Reserved1 "), /* 0x01 */
1540	STRENTRY("LDT "), /* 0x02 */
1541	STRENTRY("Reserved3 "), /* 0x03 */
1542	STRENTRY("Reserved4 "), /* 0x04 */
1543	STRENTRY("Reserved5 "), /* 0x05 */
1544	STRENTRY("Reserved6 "), /* 0x06 */
1545	STRENTRY("Reserved7 "), /* 0x07 */
1546	STRENTRY("Reserved8 "), /* 0x08 */
1547	STRENTRY("TSS64Avail "), /* 0x09 */
1548	STRENTRY("ReservedA "), /* 0x0a */
1549	STRENTRY("TSS64Busy "), /* 0x0b */
1550	STRENTRY("Call64 "), /* 0x0c */
1551	STRENTRY("ReservedD "), /* 0x0d */
1552	STRENTRY("Int64 "), /* 0x0e */
1553	STRENTRY("Trap64 "), /* 0x0f */
1554	# else
1555	STRENTRY("Reserved0 "), /* 0x00 */
1556	STRENTRY("TSS16Avail "), /* 0x01 */
1557	STRENTRY("LDT "), /* 0x02 */
1558	STRENTRY("TSS16Busy "), /* 0x03 */
1559	STRENTRY("Call16 "), /* 0x04 */
1560	STRENTRY("Task "), /* 0x05 */
1561	STRENTRY("Int16 "), /* 0x06 */
1562	STRENTRY("Trap16 "), /* 0x07 */
1563	STRENTRY("Reserved8 "), /* 0x08 */
1564	STRENTRY("TSS32Avail "), /* 0x09 */
1565	STRENTRY("ReservedA "), /* 0x0a */
1566	STRENTRY("TSS32Busy "), /* 0x0b */
1567	STRENTRY("Call32 "), /* 0x0c */
1568	STRENTRY("ReservedD "), /* 0x0d */
1569	STRENTRY("Int32 "), /* 0x0e */
1570	STRENTRY("Trap32 "), /* 0x0f */
1571	# endif
1572	/* non system */
1573	STRENTRY("DataRO "), /* 0x10 */
1574	STRENTRY("DataRO Accessed "), /* 0x11 */
1575	STRENTRY("DataRW "), /* 0x12 */
1576	STRENTRY("DataRW Accessed "), /* 0x13 */
1577	STRENTRY("DataDownRO "), /* 0x14 */
1578	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1579	STRENTRY("DataDownRW "), /* 0x16 */
1580	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1581	STRENTRY("CodeEO "), /* 0x18 */
1582	STRENTRY("CodeEO Accessed "), /* 0x19 */
1583	STRENTRY("CodeER "), /* 0x1a */
1584	STRENTRY("CodeER Accessed "), /* 0x1b */
1585	STRENTRY("CodeConfEO "), /* 0x1c */
1586	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1587	STRENTRY("CodeConfER "), /* 0x1e */
1588	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1589	# undef SYSENTRY
1590	};
1591	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1592	char szMsg[128];
1593	char *psz = &szMsg[0];
1594	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1595	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1596	psz += s_aTypes[i].cch;
1597
1598	if (pDesc->Gen.u1Present)
1599	ADD_STR(psz, "Present ");
1600	else
1601	ADD_STR(psz, "Not-Present ");
1602	# if HC_ARCH_BITS == 64
1603	if (pDesc->Gen.u1Long)
1604	ADD_STR(psz, "64-bit ");
1605	else
1606	ADD_STR(psz, "Comp ");
1607	# else
1608	if (pDesc->Gen.u1Granularity)
1609	ADD_STR(psz, "Page ");
1610	if (pDesc->Gen.u1DefBig)
1611	ADD_STR(psz, "32-bit ");
1612	else
1613	ADD_STR(psz, "16-bit ");
1614	# endif
1615	# undef ADD_STR
1616	*psz = '\0';
1617
1618	/*
1619	* Limit and Base and format the output.
1620	*/
1621	uint32_t u32Limit = X86DESC_LIMIT(*pDesc);
1622	if (pDesc->Gen.u1Granularity)
1623	u32Limit = u32Limit << PAGE_SHIFT \| PAGE_OFFSET_MASK;
1624
1625	# if HC_ARCH_BITS == 64
1626	uint64_t u32Base = X86DESC64_BASE(*pDesc);
1627
1628	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1629	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1630	# else
1631	uint32_t u32Base = X86DESC_BASE(*pDesc);
1632
1633	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1634	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1635	# endif
1636	}
1637
1638	/**
1639	* Formats a full register dump.
1640	*
1641	* @param pVM The VM to operate on.
1642	* @param pVCpu The VMCPU to operate on.
1643	* @param pCtx The context to format.
1644	*/
1645	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1646	{
1647	/*
1648	* Format the flags.
1649	*/
1650	static struct
1651	{
1652	const char pszSet; const char pszClear; uint32_t fFlag;
1653	} aFlags[] =
1654	{
1655	{ "vip",NULL, X86_EFL_VIP },
1656	{ "vif",NULL, X86_EFL_VIF },
1657	{ "ac", NULL, X86_EFL_AC },
1658	{ "vm", NULL, X86_EFL_VM },
1659	{ "rf", NULL, X86_EFL_RF },
1660	{ "nt", NULL, X86_EFL_NT },
1661	{ "ov", "nv", X86_EFL_OF },
1662	{ "dn", "up", X86_EFL_DF },
1663	{ "ei", "di", X86_EFL_IF },
1664	{ "tf", NULL, X86_EFL_TF },
1665	{ "nt", "pl", X86_EFL_SF },
1666	{ "nz", "zr", X86_EFL_ZF },
1667	{ "ac", "na", X86_EFL_AF },
1668	{ "po", "pe", X86_EFL_PF },
1669	{ "cy", "nc", X86_EFL_CF },
1670	};
1671	char szEFlags[80];
1672	char *psz = szEFlags;
1673	uint32_t efl = pCtx->eflags.u32;
1674	for (unsigned i = 0; i < RT_ELEMENTS(aFlags); i++)
1675	{
1676	const char *pszAdd = aFlags[i].fFlag & efl ? aFlags[i].pszSet : aFlags[i].pszClear;
1677	if (pszAdd)
1678	{
1679	strcpy(psz, pszAdd);
1680	psz += strlen(pszAdd);
1681	*psz++ = ' ';
1682	}
1683	}
1684	psz[-1] = '\0';
1685
1686
1687	/*
1688	* Format the registers.
1689	*/
1690	if (CPUMIsGuestIn64BitCode(pVCpu, CPUMCTX2CORE(pCtx)))
1691	{
1692	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1693	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1694	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1695	"r14=%016RX64 r15=%016RX64\n"
1696	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1697	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1698	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1699	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1700	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1701	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1702	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1703	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1704	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1705	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1706	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1707	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1708	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1709	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1710	,
1711	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1712	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1713	pCtx->r14, pCtx->r15,
1714	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1715	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1716	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1717	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1718	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1719	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1720	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1721	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1722	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1723	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1724	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1725	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1726	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1727	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1728	}
1729	else
1730	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1731	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1732	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1733	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1734	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1735	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1736	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1737	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1738	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1739	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1740	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1741	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1742	,
1743	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1744	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1745	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr[0], pCtx->dr[1],
1746	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr[2], pCtx->dr[3],
1747	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr[4], pCtx->dr[5],
1748	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr[6], pCtx->dr[7],
1749	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0, pCtx->cr2,
1750	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3, pCtx->cr4,
1751	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1752	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1753	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1754	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1755
1756	Log(("FPU:\n"
1757	"FCW=%04x FSW=%04x FTW=%02x\n"
1758	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
1759	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1760	,
1761	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
1762	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsrvd1,
1763	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
1764	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
1765
1766
1767	Log(("MSR:\n"
1768	"EFER =%016RX64\n"
1769	"PAT =%016RX64\n"
1770	"STAR =%016RX64\n"
1771	"CSTAR =%016RX64\n"
1772	"LSTAR =%016RX64\n"
1773	"SFMASK =%016RX64\n"
1774	"KERNELGSBASE =%016RX64\n",
1775	pCtx->msrEFER,
1776	pCtx->msrPAT,
1777	pCtx->msrSTAR,
1778	pCtx->msrCSTAR,
1779	pCtx->msrLSTAR,
1780	pCtx->msrSFMASK,
1781	pCtx->msrKERNELGSBASE));
1782
1783	}
1784	#endif /* VBOX_STRICT */
1785
1786	/* Dummy callback handlers. */
1787	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
1788	{
1789	return VINF_SUCCESS;
1790	}
1791
1792	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1793	{
1794	return VINF_SUCCESS;
1795	}
1796
1797	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1798	{
1799	return VINF_SUCCESS;
1800	}
1801
1802	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1803	{
1804	return VINF_SUCCESS;
1805	}
1806
1807	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM)
1808	{
1809	return VINF_SUCCESS;
1810	}
1811
1812	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM)
1813	{
1814	return VINF_SUCCESS;
1815	}
1816
1817	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM)
1818	{
1819	return VINF_SUCCESS;
1820	}
1821
1822	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1823	{
1824	return VINF_SUCCESS;
1825	}
1826
1827	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
1828	{
1829	return VINF_SUCCESS;
1830	}
1831
1832	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1833	{
1834	return VINF_SUCCESS;
1835	}

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp@ 36877

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