HWACCMR0.cpp@ 37182

Last change on this file since 37182 was 37062, checked in by vboxsync, 14 years ago
VMM: Support for online/offlining of CPUs.
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1	/* $Id: HWACCMR0.cpp 37062 2011-05-13 10:18:29Z vboxsync $ */
2	/** @file
3	* HWACCM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HWACCM
23	#include <VBox/vmm/hwaccm.h>
24	#include <VBox/vmm/pgm.h>
25	#include "HWACCMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include <VBox/x86.h>
28	#include <VBox/vmm/hwacc_vmx.h>
29	#include <VBox/vmm/hwacc_svm.h>
30	#include <VBox/err.h>
31	#include <VBox/log.h>
32	#include <iprt/assert.h>
33	#include <iprt/asm.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/cpuset.h>
36	#include <iprt/mem.h>
37	#include <iprt/memobj.h>
38	#include <iprt/param.h>
39	#include <iprt/power.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42	#include "HWVMXR0.h"
43	#include "HWSVMR0.h"
44
45	/*******************************************************************************
46	* Internal Functions *
47	*******************************************************************************/
48	static DECLCALLBACK(void) hwaccmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
49	static DECLCALLBACK(void) hwaccmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
50	static DECLCALLBACK(void) hwaccmR0InitCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static bool hwaccmR0IsSubjectToVmxPreemptionTimerErratum(void);
52	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
53	static DECLCALLBACK(void) hwaccmR0CpuCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
54
55	/*******************************************************************************
56	* Global Variables *
57	*******************************************************************************/
58
59	static struct
60	{
61	HWACCM_CPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
62
63	/** Ring 0 handlers for VT-x and AMD-V. */
64	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu));
65	DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
66	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
67	DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
68	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
69	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
70	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
71	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
72	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
73	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVM pVM));
74
75	/** Maximum ASID allowed. */
76	uint32_t uMaxASID;
77
78	struct
79	{
80	/** Set to by us to indicate VMX is supported by the CPU. */
81	bool fSupported;
82	/** Whether we're using SUPR0EnableVTx or not. */
83	bool fUsingSUPR0EnableVTx;
84	/** Whether we're using the preemption timer or not. */
85	bool fUsePreemptTimer;
86	/** The shift mask employed by the VMX-Preemption timer. */
87	uint8_t cPreemptTimerShift;
88
89	/** Host CR4 value (set by ring-0 VMX init) */
90	uint64_t hostCR4;
91
92	/** Host EFER value (set by ring-0 VMX init) */
93	uint64_t hostEFER;
94
95	/** VMX MSR values */
96	struct
97	{
98	uint64_t feature_ctrl;
99	uint64_t vmx_basic_info;
100	VMX_CAPABILITY vmx_pin_ctls;
101	VMX_CAPABILITY vmx_proc_ctls;
102	VMX_CAPABILITY vmx_proc_ctls2;
103	VMX_CAPABILITY vmx_exit;
104	VMX_CAPABILITY vmx_entry;
105	uint64_t vmx_misc;
106	uint64_t vmx_cr0_fixed0;
107	uint64_t vmx_cr0_fixed1;
108	uint64_t vmx_cr4_fixed0;
109	uint64_t vmx_cr4_fixed1;
110	uint64_t vmx_vmcs_enum;
111	uint64_t vmx_eptcaps;
112	} msr;
113	/* Last instruction error */
114	uint32_t ulLastInstrError;
115	} vmx;
116	struct
117	{
118	/* HWCR msr (for diagnostics) */
119	uint64_t msrHWCR;
120
121	/** SVM revision. */
122	uint32_t u32Rev;
123
124	/** SVM feature bits from cpuid 0x8000000a */
125	uint32_t u32Features;
126
127	/** Set by us to indicate SVM is supported by the CPU. */
128	bool fSupported;
129	} svm;
130	/** Saved error from detection */
131	int32_t lLastError;
132
133	struct
134	{
135	uint32_t u32AMDFeatureECX;
136	uint32_t u32AMDFeatureEDX;
137	} cpuid;
138
139	HWACCMSTATE enmHwAccmState;
140
141	bool fGlobalInit;
142	volatile bool fSuspended;
143	} HWACCMR0Globals;
144
145
146	/**
147	* This is used to manage the status code of a RTMpOnAll in HWACCM.
148	*/
149	typedef struct HWACCMR0FIRSTRC
150	{
151	/** The status code. */
152	int32_t volatile rc;
153	/** The ID of the CPU reporting the first failure. */
154	RTCPUID volatile idCpu;
155	} HWACCMR0FIRSTRC;
156	/** Pointer to a first return code structure. */
157	typedef HWACCMR0FIRSTRC *PHWACCMR0FIRSTRC;
158
159
160	/**
161	* Initializes a first return code structure.
162	*
163	* @param pFirstRc The structure to init.
164	*/
165	static void hwaccmR0FirstRcInit(PHWACCMR0FIRSTRC pFirstRc)
166	{
167	pFirstRc->rc = VINF_SUCCESS;
168	pFirstRc->idCpu = NIL_RTCPUID;
169	}
170
171
172	/**
173	* Try se the status code (success ignored).
174	*
175	* @param pFirstRc The first return code structure.
176	* @param rc The status code.
177	*/
178	static void hwaccmR0FirstRcSetStatus(PHWACCMR0FIRSTRC pFirstRc, int rc)
179	{
180	if ( RT_FAILURE(rc)
181	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
182	pFirstRc->idCpu = RTMpCpuId();
183	}
184
185
186	/**
187	* Get the status code of a first return code structure.
188	*
189	* @returns The status code; VINF_SUCCESS or error status, no informational or
190	* warning errors.
191	* @param pFirstRc The first return code structure.
192	*/
193	static int hwaccmR0FirstRcGetStatus(PHWACCMR0FIRSTRC pFirstRc)
194	{
195	return pFirstRc->rc;
196	}
197
198
199	/**
200	* Get the CPU ID on which the failure status code was reported.
201	*
202	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
203	* @param pFirstRc The first return code structure.
204	*/
205	static RTCPUID hwaccmR0FirstRcGetCpuId(PHWACCMR0FIRSTRC pFirstRc)
206	{
207	return pFirstRc->idCpu;
208	}
209
210
211	/**
212	* Does global Ring-0 HWACCM initialization.
213	*
214	* @returns VBox status code.
215	*/
216	VMMR0DECL(int) HWACCMR0Init(void)
217	{
218	int rc;
219	bool fAMDVPresent = false;
220
221	HWACCMR0Globals.enmHwAccmState = HWACCMSTATE_UNINITIALIZED;
222	for (unsigned i = 0; i < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); i++)
223	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
224
225	/* Fill in all callbacks with placeholders. */
226	HWACCMR0Globals.pfnEnterSession = HWACCMR0DummyEnter;
227	HWACCMR0Globals.pfnLeaveSession = HWACCMR0DummyLeave;
228	HWACCMR0Globals.pfnSaveHostState = HWACCMR0DummySaveHostState;
229	HWACCMR0Globals.pfnLoadGuestState = HWACCMR0DummyLoadGuestState;
230	HWACCMR0Globals.pfnRunGuestCode = HWACCMR0DummyRunGuestCode;
231	HWACCMR0Globals.pfnEnableCpu = HWACCMR0DummyEnableCpu;
232	HWACCMR0Globals.pfnDisableCpu = HWACCMR0DummyDisableCpu;
233	HWACCMR0Globals.pfnInitVM = HWACCMR0DummyInitVM;
234	HWACCMR0Globals.pfnTermVM = HWACCMR0DummyTermVM;
235	HWACCMR0Globals.pfnSetupVM = HWACCMR0DummySetupVM;
236
237	/* Default is global VT-x/AMD-V init */
238	HWACCMR0Globals.fGlobalInit = true;
239
240	/*
241	* Make sure aCpuInfo is big enough for all the CPUs on this system.
242	*/
243	if (RTMpGetArraySize() > RT_ELEMENTS(HWACCMR0Globals.aCpuInfo))
244	{
245	LogRel(("HWACCM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(HWACCMR0Globals.aCpuInfo)));
246	return VERR_TOO_MANY_CPUS;
247	}
248
249	/*
250	* Check for VT-x and AMD-V capabilities
251	*/
252	if (ASMHasCpuId())
253	{
254	uint32_t u32FeaturesECX;
255	uint32_t u32Dummy;
256	uint32_t u32FeaturesEDX;
257	uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
258
259	ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
260	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
261	/* Query AMD features. */
262	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy, &HWACCMR0Globals.cpuid.u32AMDFeatureECX, &HWACCMR0Globals.cpuid.u32AMDFeatureEDX);
263
264	if ( u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
265	&& u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
266	&& u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX
267	)
268	{
269	/*
270	* Read all VMX MSRs if VMX is available. (same goes for RDMSR/WRMSR)
271	* We also assume all VMX-enabled CPUs support fxsave/fxrstor.
272	*/
273	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
274	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
275	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
276	)
277	{
278	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
279
280	/*
281	* First try use native kernel API for controlling VT-x.
282	* (This is only supported by some Mac OS X kernels atm.)
283	*/
284	HWACCMR0Globals.lLastError = rc = SUPR0EnableVTx(true /* fEnable */);
285	if (rc != VERR_NOT_SUPPORTED)
286	{
287	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
288	HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx = true;
289	if (RT_SUCCESS(rc))
290	{
291	HWACCMR0Globals.vmx.fSupported = true;
292	rc = SUPR0EnableVTx(false /* fEnable */);
293	AssertRC(rc);
294	}
295	}
296	else
297	{
298	HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx = false;
299
300	/* We need to check if VT-x has been properly initialized on all CPUs. Some BIOSes do a lousy job. */
301	HWACCMR0FIRSTRC FirstRc;
302	hwaccmR0FirstRcInit(&FirstRc);
303	HWACCMR0Globals.lLastError = RTMpOnAll(hwaccmR0InitCpu, (void *)(uintptr_t)u32VendorEBX, &FirstRc);
304	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
305	HWACCMR0Globals.lLastError = hwaccmR0FirstRcGetStatus(&FirstRc);
306	}
307	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
308	{
309	/* Reread in case we've changed it. */
310	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
311
312	if ( (HWACCMR0Globals.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
313	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
314	{
315	RTR0MEMOBJ pScatchMemObj;
316	void *pvScatchPage;
317	RTHCPHYS pScatchPagePhys;
318
319	HWACCMR0Globals.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
320	HWACCMR0Globals.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
321	HWACCMR0Globals.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
322	HWACCMR0Globals.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
323	HWACCMR0Globals.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
324	HWACCMR0Globals.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
325	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
326	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
327	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
328	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
329	HWACCMR0Globals.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
330	/* VPID 16 bits ASID. */
331	HWACCMR0Globals.uMaxASID = 0x10000; /* exclusive */
332
333	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
334	{
335	HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
336	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT\|VMX_VMCS_CTRL_PROC_EXEC2_VPID))
337	HWACCMR0Globals.vmx.msr.vmx_eptcaps = ASMRdMsr(MSR_IA32_VMX_EPT_CAPS);
338	}
339
340	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
341	{
342	HWACCMR0Globals.vmx.hostCR4 = ASMGetCR4();
343	HWACCMR0Globals.vmx.hostEFER = ASMRdMsr(MSR_K6_EFER);
344
345	rc = RTR0MemObjAllocCont(&pScatchMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
346	if (RT_FAILURE(rc))
347	return rc;
348
349	pvScatchPage = RTR0MemObjAddress(pScatchMemObj);
350	pScatchPagePhys = RTR0MemObjGetPagePhysAddr(pScatchMemObj, 0);
351	memset(pvScatchPage, 0, PAGE_SIZE);
352
353	/* Set revision dword at the beginning of the structure. */
354	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(HWACCMR0Globals.vmx.msr.vmx_basic_info);
355
356	/* Make sure we don't get rescheduled to another cpu during this probe. */
357	RTCCUINTREG fFlags = ASMIntDisableFlags();
358
359	/*
360	* Check CR4.VMXE
361	*/
362	if (!(HWACCMR0Globals.vmx.hostCR4 & X86_CR4_VMXE))
363	{
364	/* In theory this bit could be cleared behind our back. Which would cause #UD faults when we
365	* try to execute the VMX instructions...
366	*/
367	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4 \| X86_CR4_VMXE);
368	}
369
370	/* Enter VMX Root Mode */
371	rc = VMXEnable(pScatchPagePhys);
372	if (RT_FAILURE(rc))
373	{
374	/* KVM leaves the CPU in VMX root mode. Not only is this not allowed, it will crash the host when we enter raw mode, because
375	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify this bit)
376	* (b) turning off paging causes a #GP (unavoidable when switching from long to 32 bits mode or 32 bits to PAE)
377	*
378	* They should fix their code, but until they do we simply refuse to run.
379	*/
380	HWACCMR0Globals.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
381	}
382	else
383	{
384	HWACCMR0Globals.vmx.fSupported = true;
385	VMXDisable();
386
387	/*
388	* Check for the VMX-Preemption Timer and adjust for the
389	* "VMX-Preemption Timer Does Not Count Down at the Rate Specified" erratum.
390	*/
391	if ( HWACCMR0Globals.vmx.msr.vmx_pin_ctls.n.allowed1
392	& VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
393	{
394	HWACCMR0Globals.vmx.fUsePreemptTimer = true;
395	HWACCMR0Globals.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(HWACCMR0Globals.vmx.msr.vmx_misc);
396	if (hwaccmR0IsSubjectToVmxPreemptionTimerErratum())
397	HWACCMR0Globals.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
398	}
399	}
400
401	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it wasn't so before (some software could incorrectly think it's in VMX mode) */
402	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4);
403	ASMSetFlags(fFlags);
404
405	RTR0MemObjFree(pScatchMemObj, false);
406	if (RT_FAILURE(HWACCMR0Globals.lLastError))
407	return HWACCMR0Globals.lLastError;
408	}
409	}
410	else
411	{
412	AssertFailed(); /* can't hit this case anymore */
413	HWACCMR0Globals.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
414	}
415	}
416	#ifdef LOG_ENABLED
417	else
418	SUPR0Printf("hwaccmR0InitCpu failed with rc=%d\n", HWACCMR0Globals.lLastError);
419	#endif
420	}
421	else
422	HWACCMR0Globals.lLastError = VERR_VMX_NO_VMX;
423	}
424	else
425	if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
426	&& u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
427	&& u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX
428	)
429	{
430	/*
431	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
432	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
433	*/
434	if ( (HWACCMR0Globals.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
435	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
436	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
437	)
438	{
439	fAMDVPresent = true;
440
441	/* Query AMD features. */
442	ASMCpuId(0x8000000A, &HWACCMR0Globals.svm.u32Rev, &HWACCMR0Globals.uMaxASID, &u32Dummy, &HWACCMR0Globals.svm.u32Features);
443
444	/* We need to check if AMD-V has been properly initialized on all CPUs. Some BIOSes might do a poor job. */
445	HWACCMR0FIRSTRC FirstRc;
446	hwaccmR0FirstRcInit(&FirstRc);
447	rc = RTMpOnAll(hwaccmR0InitCpu, (void *)(uintptr_t)u32VendorEBX, &FirstRc); AssertRC(rc);
448	if (RT_SUCCESS(rc))
449	rc = hwaccmR0FirstRcGetStatus(&FirstRc);
450	#ifndef DEBUG_bird
451	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE, ("hwaccmR0InitCpu failed for cpu %d with rc=%d\n", hwaccmR0FirstRcGetCpuId(&FirstRc), rc));
452	#endif
453	if (RT_SUCCESS(rc))
454	{
455	/* Read the HWCR msr for diagnostics. */
456	HWACCMR0Globals.svm.msrHWCR = ASMRdMsr(MSR_K8_HWCR);
457	HWACCMR0Globals.svm.fSupported = true;
458	}
459	else
460	HWACCMR0Globals.lLastError = rc;
461	}
462	else
463	HWACCMR0Globals.lLastError = VERR_SVM_NO_SVM;
464	}
465	else
466	HWACCMR0Globals.lLastError = VERR_HWACCM_UNKNOWN_CPU;
467	}
468	else
469	HWACCMR0Globals.lLastError = VERR_HWACCM_NO_CPUID;
470
471	if (HWACCMR0Globals.vmx.fSupported)
472	{
473	HWACCMR0Globals.pfnEnterSession = VMXR0Enter;
474	HWACCMR0Globals.pfnLeaveSession = VMXR0Leave;
475	HWACCMR0Globals.pfnSaveHostState = VMXR0SaveHostState;
476	HWACCMR0Globals.pfnLoadGuestState = VMXR0LoadGuestState;
477	HWACCMR0Globals.pfnRunGuestCode = VMXR0RunGuestCode;
478	HWACCMR0Globals.pfnEnableCpu = VMXR0EnableCpu;
479	HWACCMR0Globals.pfnDisableCpu = VMXR0DisableCpu;
480	HWACCMR0Globals.pfnInitVM = VMXR0InitVM;
481	HWACCMR0Globals.pfnTermVM = VMXR0TermVM;
482	HWACCMR0Globals.pfnSetupVM = VMXR0SetupVM;
483	}
484	else
485	if (fAMDVPresent)
486	{
487	HWACCMR0Globals.pfnEnterSession = SVMR0Enter;
488	HWACCMR0Globals.pfnLeaveSession = SVMR0Leave;
489	HWACCMR0Globals.pfnSaveHostState = SVMR0SaveHostState;
490	HWACCMR0Globals.pfnLoadGuestState = SVMR0LoadGuestState;
491	HWACCMR0Globals.pfnRunGuestCode = SVMR0RunGuestCode;
492	HWACCMR0Globals.pfnEnableCpu = SVMR0EnableCpu;
493	HWACCMR0Globals.pfnDisableCpu = SVMR0DisableCpu;
494	HWACCMR0Globals.pfnInitVM = SVMR0InitVM;
495	HWACCMR0Globals.pfnTermVM = SVMR0TermVM;
496	HWACCMR0Globals.pfnSetupVM = SVMR0SetupVM;
497	}
498
499	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
500	{
501	rc = RTMpNotificationRegister(hwaccmR0CpuCallback, 0);
502	AssertRC(rc);
503
504	rc = RTPowerNotificationRegister(hwaccmR0PowerCallback, 0);
505	AssertRC(rc);
506	}
507
508	return VINF_SUCCESS;
509	}
510
511
512	/**
513	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
514	* Down at the Rate Specified" erratum.
515	*
516	* Errata names and related steppings:
517	* - BA86 - D0.
518	* - AAX65 - C2.
519	* - AAU65 - C2, K0.
520	* - AAO95 - B1.
521	* - AAT59 - C2.
522	* - AAK139 - D0.
523	* - AAM126 - C0, C1, D0.
524	* - AAN92 - B1.
525	* - AAJ124 - C0, D0.
526	*
527	* - AAP86 - B1.
528	*
529	* Steppings: B1, C0, C1, C2, D0, K0.
530	*
531	* @returns true if subject to it, false if not.
532	*/
533	static bool hwaccmR0IsSubjectToVmxPreemptionTimerErratum(void)
534	{
535	uint32_t u = ASMCpuId_EAX(1);
536	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
537	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
538	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
539	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
540	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
541	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
542	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
543	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
544	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
545	\|\| u == UINT32_C(0x000106A0) /?321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification /
546	\|\| u == UINT32_C(0x000106A1) /?321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification /
547	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
548	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
549	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
550	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
551	)
552	return true;
553	return false;
554	}
555
556
557	/**
558	* Does global Ring-0 HWACCM termination.
559	*
560	* @returns VBox status code.
561	*/
562	VMMR0DECL(int) HWACCMR0Term(void)
563	{
564	int rc;
565	if ( HWACCMR0Globals.vmx.fSupported
566	&& HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
567	{
568	Assert(HWACCMR0Globals.fGlobalInit);
569	rc = SUPR0EnableVTx(false /* fEnable */);
570	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); iCpu++)
571	{
572	HWACCMR0Globals.aCpuInfo[iCpu].fConfigured = false;
573	Assert(HWACCMR0Globals.aCpuInfo[iCpu].pMemObj == NIL_RTR0MEMOBJ);
574	}
575	}
576	else
577	{
578	Assert(!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
579	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
580	{
581	/* Doesn't really matter if this fails. */
582	rc = RTMpNotificationDeregister(hwaccmR0CpuCallback, 0);
583	AssertRC(rc);
584	rc = RTPowerNotificationDeregister(hwaccmR0PowerCallback, 0);
585	AssertRC(rc);
586	}
587	else
588	rc = VINF_SUCCESS;
589
590	/* Only disable VT-x/AMD-V on all CPUs if we enabled it before. */
591	if (HWACCMR0Globals.fGlobalInit)
592	{
593	HWACCMR0FIRSTRC FirstRc;
594	hwaccmR0FirstRcInit(&FirstRc);
595	rc = RTMpOnAll(hwaccmR0DisableCpuCallback, NULL, &FirstRc);
596	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
597	if (RT_SUCCESS(rc))
598	{
599	rc = hwaccmR0FirstRcGetStatus(&FirstRc);
600	AssertMsgRC(rc, ("%u: %Rrc\n", hwaccmR0FirstRcGetCpuId(&FirstRc), rc));
601	}
602	}
603
604	/* Free the per-cpu pages used for VT-x and AMD-V */
605	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
606	{
607	if (HWACCMR0Globals.aCpuInfo[i].pMemObj != NIL_RTR0MEMOBJ)
608	{
609	RTR0MemObjFree(HWACCMR0Globals.aCpuInfo[i].pMemObj, false);
610	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
611	}
612	}
613	}
614	return rc;
615	}
616
617
618	/**
619	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
620	* is to be called on the target cpus.
621	*
622	* @param idCpu The identifier for the CPU the function is called on.
623	* @param pvUser1 The 1st user argument.
624	* @param pvUser2 The 2nd user argument.
625	*/
626	static DECLCALLBACK(void) hwaccmR0InitCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
627	{
628	unsigned u32VendorEBX = (uintptr_t)pvUser1;
629	PHWACCMR0FIRSTRC pFirstRc = (PHWACCMR0FIRSTRC)pvUser2;
630	uint64_t val;
631	int rc;
632
633	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
634
635	if (u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX)
636	{
637	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
638
639	/*
640	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
641	* Once the lock bit is set, this MSR can no longer be modified.
642	*/
643	if ( !(val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
644	\|\| ((val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK)) == MSR_IA32_FEATURE_CONTROL_VMXON) /* Some BIOSes forget to set the locked bit. */
645	)
646	{
647	/* MSR is not yet locked; we can change it ourselves here */
648	ASMWrMsr(MSR_IA32_FEATURE_CONTROL, HWACCMR0Globals.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
649	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
650	}
651	if ( (val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
652	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
653	rc = VINF_SUCCESS;
654	else
655	rc = VERR_VMX_MSR_LOCKED_OR_DISABLED;
656	}
657	else if (u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX)
658	{
659	/* Check if SVM is disabled */
660	val = ASMRdMsr(MSR_K8_VM_CR);
661	if (!(val & MSR_K8_VM_CR_SVM_DISABLE))
662	{
663	/* Turn on SVM in the EFER MSR. */
664	val = ASMRdMsr(MSR_K6_EFER);
665	if (val & MSR_K6_EFER_SVME)
666	rc = VERR_SVM_IN_USE;
667	else
668	{
669	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
670
671	/* Paranoia. */
672	val = ASMRdMsr(MSR_K6_EFER);
673	if (val & MSR_K6_EFER_SVME)
674	{
675	/* Restore previous value. */
676	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
677	rc = VINF_SUCCESS;
678	}
679	else
680	rc = VERR_SVM_ILLEGAL_EFER_MSR;
681	}
682	}
683	else
684	rc = VERR_SVM_DISABLED;
685	}
686	else
687	{
688	AssertFailed(); /* can't happen */
689	rc = VERR_INTERNAL_ERROR_5;
690	}
691
692	hwaccmR0FirstRcSetStatus(pFirstRc, rc);
693	}
694
695
696	/**
697	* Sets up HWACCM on all cpus.
698	*
699	* @returns VBox status code.
700	* @param pVM The VM to operate on.
701	*
702	*/
703	VMMR0DECL(int) HWACCMR0EnableAllCpus(PVM pVM)
704	{
705	AssertCompile(sizeof(HWACCMR0Globals.enmHwAccmState) == sizeof(uint32_t));
706
707	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
708	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
709	return VERR_HWACCM_SUSPEND_PENDING;
710
711	if (ASMAtomicCmpXchgU32((volatile uint32_t *)&HWACCMR0Globals.enmHwAccmState, HWACCMSTATE_ENABLED, HWACCMSTATE_UNINITIALIZED))
712	{
713	int rc;
714
715	HWACCMR0Globals.fGlobalInit = pVM->hwaccm.s.fGlobalInit;
716
717	if ( HWACCMR0Globals.vmx.fSupported
718	&& HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
719	{
720	rc = SUPR0EnableVTx(true /* fEnable */);
721	if (RT_SUCCESS(rc))
722	{
723	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); iCpu++)
724	{
725	HWACCMR0Globals.aCpuInfo[iCpu].fConfigured = true;
726	Assert(HWACCMR0Globals.aCpuInfo[iCpu].pMemObj == NIL_RTR0MEMOBJ);
727	}
728	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
729	HWACCMR0Globals.fGlobalInit = pVM->hwaccm.s.fGlobalInit = true;
730	}
731	else
732	AssertMsgFailed(("HWACCMR0EnableAllCpus/SUPR0EnableVTx: rc=%Rrc\n", rc));
733	}
734	else
735	{
736	/* Allocate one page per cpu for the global vt-x and amd-v pages */
737	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
738	{
739	Assert(!HWACCMR0Globals.aCpuInfo[i].pMemObj);
740
741	if (RTMpIsCpuPossible(RTMpCpuId()))
742	{
743	rc = RTR0MemObjAllocCont(&HWACCMR0Globals.aCpuInfo[i].pMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
744	AssertRC(rc);
745	if (RT_FAILURE(rc))
746	return rc;
747
748	void *pvR0 = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[i].pMemObj);
749	Assert(pvR0);
750	ASMMemZeroPage(pvR0);
751
752	#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
753	SUPR0Printf("address %x phys %x\n", pvR0, (uint32_t)RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[i].pMemObj, 0));
754	#endif
755	}
756	HWACCMR0Globals.aCpuInfo[i].fConfigured = false;
757	}
758	if (HWACCMR0Globals.fGlobalInit)
759	{
760	/* First time, so initialize each cpu/core */
761	HWACCMR0FIRSTRC FirstRc;
762	hwaccmR0FirstRcInit(&FirstRc);
763	rc = RTMpOnAll(hwaccmR0EnableCpuCallback, (void *)pVM, &FirstRc);
764	if (RT_SUCCESS(rc))
765	rc = hwaccmR0FirstRcGetStatus(&FirstRc);
766	AssertMsgRC(rc, ("HWACCMR0EnableAllCpus failed for cpu %d with rc=%d\n", hwaccmR0FirstRcGetCpuId(&FirstRc), rc));
767	}
768	else
769	rc = VINF_SUCCESS;
770	}
771
772	return rc;
773	}
774	return VINF_SUCCESS;
775	}
776
777	/**
778	* Disable VT-x or AMD-V on the current CPU
779	*
780	* @returns VBox status code.
781	* @param pVM VM handle (can be 0!)
782	* @param idCpu The identifier for the CPU the function is called on.
783	*/
784	static int hwaccmR0EnableCpu(PVM pVM, RTCPUID idCpu)
785	{
786	void *pvPageCpu;
787	RTHCPHYS pPageCpuPhys;
788	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
789
790	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
791	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
792	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
793	Assert(!pCpu->fConfigured);
794	Assert(!HWACCMR0Globals.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
795
796	pCpu->idCpu = idCpu;
797
798	/* Make sure we start with a clean TLB. */
799	pCpu->fFlushTLB = true;
800
801	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
802	pCpu->cTLBFlushes = 0;
803
804	/* Should never happen */
805	if (!pCpu->pMemObj)
806	{
807	LogRel(("HWACCMR0: hwaccmR0EnableCpu failed idCpu=%d.\n", idCpu));
808	AssertFailed();
809	return VERR_INTERNAL_ERROR;
810	}
811
812	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
813	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
814
815	int rc = HWACCMR0Globals.pfnEnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
816	AssertRC(rc);
817	if (RT_SUCCESS(rc))
818	pCpu->fConfigured = true;
819
820	return rc;
821	}
822
823
824	/**
825	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
826	* is to be called on the target cpus.
827	*
828	* @param idCpu The identifier for the CPU the function is called on.
829	* @param pvUser1 The 1st user argument.
830	* @param pvUser2 The 2nd user argument.
831	*/
832	static DECLCALLBACK(void) hwaccmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
833	{
834	PVM pVM = (PVM)pvUser1; /* can be NULL! */
835	PHWACCMR0FIRSTRC pFirstRc = (PHWACCMR0FIRSTRC)pvUser2;
836	AssertReturnVoid(HWACCMR0Globals.fGlobalInit);
837	hwaccmR0FirstRcSetStatus(pFirstRc, hwaccmR0EnableCpu(pVM, idCpu));
838	}
839
840
841	/**
842	* Disable VT-x or AMD-V on the current CPU
843	*
844	* @returns VBox status code.
845	* @param idCpu The identifier for the CPU the function is called on.
846	*/
847	static int hwaccmR0DisableCpu(RTCPUID idCpu)
848	{
849	void *pvPageCpu;
850	RTHCPHYS pPageCpuPhys;
851	int rc;
852	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
853
854	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
855	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
856	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
857	Assert(!HWACCMR0Globals.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
858	Assert(!pCpu->fConfigured \|\| pCpu->pMemObj);
859
860	if (!pCpu->pMemObj)
861	return (pCpu->fConfigured) ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
862
863	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
864	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
865
866	if (pCpu->fConfigured)
867	{
868	rc = HWACCMR0Globals.pfnDisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
869	AssertRC(rc);
870	pCpu->fConfigured = false;
871	}
872	else
873	rc = VINF_SUCCESS; /* nothing to do */
874
875	pCpu->uCurrentASID = 0;
876	return rc;
877	}
878
879	/**
880	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
881	* is to be called on the target cpus.
882	*
883	* @param idCpu The identifier for the CPU the function is called on.
884	* @param pvUser1 The 1st user argument.
885	* @param pvUser2 The 2nd user argument.
886	*/
887	static DECLCALLBACK(void) hwaccmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
888	{
889	PHWACCMR0FIRSTRC pFirstRc = (PHWACCMR0FIRSTRC)pvUser2;
890	AssertReturnVoid(HWACCMR0Globals.fGlobalInit);
891	hwaccmR0FirstRcSetStatus(pFirstRc, hwaccmR0DisableCpu(idCpu));
892	}
893
894
895	/**
896	* Callback function invoked when a cpu goes online or offline.
897	*
898	* @param enmEvent The Mp event.
899	* @param idCpu The identifier for the CPU the function is called on.
900	* @param pvData Opaque data (PVM pointer).
901	*/
902	static DECLCALLBACK(void) hwaccmR0CpuCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
903	{
904	/*
905	* We only care about uninitializing a CPU that is going offline. When a
906	* CPU comes online, the initialization is done lazily in HWACCMR0Enter().
907	*/
908	AssertRelease(idCpu == RTMpCpuId());
909	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
910	switch (enmEvent)
911	{
912	case RTMPEVENT_OFFLINE:
913	{
914	int rc = hwaccmR0DisableCpu(idCpu);
915	AssertRC(rc);
916	break;
917	}
918
919	default:
920	break;
921	}
922	}
923
924
925	/**
926	* Called whenever a system power state change occurs.
927	*
928	* @param enmEvent Power event
929	* @param pvUser User argument
930	*/
931	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
932	{
933	NOREF(pvUser);
934	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
935
936	#ifdef LOG_ENABLED
937	if (enmEvent == RTPOWEREVENT_SUSPEND)
938	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
939	else
940	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_RESUME\n");
941	#endif
942
943	if (enmEvent == RTPOWEREVENT_SUSPEND)
944	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, true);
945
946	if (HWACCMR0Globals.enmHwAccmState == HWACCMSTATE_ENABLED)
947	{
948	int rc;
949	HWACCMR0FIRSTRC FirstRc;
950	hwaccmR0FirstRcInit(&FirstRc);
951
952	if (enmEvent == RTPOWEREVENT_SUSPEND)
953	{
954	if (HWACCMR0Globals.fGlobalInit)
955	{
956	/* Turn off VT-x or AMD-V on all CPUs. */
957	rc = RTMpOnAll(hwaccmR0DisableCpuCallback, NULL, &FirstRc);
958	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
959	}
960	/* else nothing to do here for the local init case */
961	}
962	else
963	{
964	/* Reinit the CPUs from scratch as the suspend state might have messed with the MSRs. (lousy BIOSes as usual) */
965	uintptr_t uFirstArg = HWACCMR0Globals.vmx.fSupported ? X86_CPUID_VENDOR_INTEL_EBX : X86_CPUID_VENDOR_AMD_EBX;
966	rc = RTMpOnAll(hwaccmR0InitCpu, (void *)uFirstArg , &FirstRc);
967	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
968	if (RT_SUCCESS(rc))
969	rc = hwaccmR0FirstRcGetStatus(&FirstRc);
970	#ifdef LOG_ENABLED
971	if (RT_FAILURE(rc))
972	SUPR0Printf("hwaccmR0PowerCallback hwaccmR0InitCpu failed with %Rc\n", rc);
973	#endif
974
975	if (HWACCMR0Globals.fGlobalInit)
976	{
977	/* Turn VT-x or AMD-V back on on all CPUs. */
978	rc = RTMpOnAll(hwaccmR0EnableCpuCallback, NULL, &FirstRc /* output ignored */);
979	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
980	}
981	/* else nothing to do here for the local init case */
982	}
983	}
984	if (enmEvent == RTPOWEREVENT_RESUME)
985	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, false);
986	}
987
988
989	/**
990	* Does Ring-0 per VM HWACCM initialization.
991	*
992	* This is mainly to check that the Host CPU mode is compatible
993	* with VMX.
994	*
995	* @returns VBox status code.
996	* @param pVM The VM to operate on.
997	*/
998	VMMR0DECL(int) HWACCMR0InitVM(PVM pVM)
999	{
1000	int rc;
1001
1002	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1003
1004	#ifdef LOG_ENABLED
1005	SUPR0Printf("HWACCMR0InitVM: %p\n", pVM);
1006	#endif
1007
1008	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
1009	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
1010	return VERR_HWACCM_SUSPEND_PENDING;
1011
1012	pVM->hwaccm.s.vmx.fSupported = HWACCMR0Globals.vmx.fSupported;
1013	pVM->hwaccm.s.svm.fSupported = HWACCMR0Globals.svm.fSupported;
1014
1015	pVM->hwaccm.s.vmx.fUsePreemptTimer = HWACCMR0Globals.vmx.fUsePreemptTimer;
1016	pVM->hwaccm.s.vmx.cPreemptTimerShift = HWACCMR0Globals.vmx.cPreemptTimerShift;
1017	pVM->hwaccm.s.vmx.msr.feature_ctrl = HWACCMR0Globals.vmx.msr.feature_ctrl;
1018	pVM->hwaccm.s.vmx.hostCR4 = HWACCMR0Globals.vmx.hostCR4;
1019	pVM->hwaccm.s.vmx.hostEFER = HWACCMR0Globals.vmx.hostEFER;
1020	pVM->hwaccm.s.vmx.msr.vmx_basic_info = HWACCMR0Globals.vmx.msr.vmx_basic_info;
1021	pVM->hwaccm.s.vmx.msr.vmx_pin_ctls = HWACCMR0Globals.vmx.msr.vmx_pin_ctls;
1022	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls = HWACCMR0Globals.vmx.msr.vmx_proc_ctls;
1023	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2 = HWACCMR0Globals.vmx.msr.vmx_proc_ctls2;
1024	pVM->hwaccm.s.vmx.msr.vmx_exit = HWACCMR0Globals.vmx.msr.vmx_exit;
1025	pVM->hwaccm.s.vmx.msr.vmx_entry = HWACCMR0Globals.vmx.msr.vmx_entry;
1026	pVM->hwaccm.s.vmx.msr.vmx_misc = HWACCMR0Globals.vmx.msr.vmx_misc;
1027	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0;
1028	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1;
1029	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0;
1030	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1;
1031	pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum = HWACCMR0Globals.vmx.msr.vmx_vmcs_enum;
1032	pVM->hwaccm.s.vmx.msr.vmx_eptcaps = HWACCMR0Globals.vmx.msr.vmx_eptcaps;
1033	pVM->hwaccm.s.svm.msrHWCR = HWACCMR0Globals.svm.msrHWCR;
1034	pVM->hwaccm.s.svm.u32Rev = HWACCMR0Globals.svm.u32Rev;
1035	pVM->hwaccm.s.svm.u32Features = HWACCMR0Globals.svm.u32Features;
1036	pVM->hwaccm.s.cpuid.u32AMDFeatureECX = HWACCMR0Globals.cpuid.u32AMDFeatureECX;
1037	pVM->hwaccm.s.cpuid.u32AMDFeatureEDX = HWACCMR0Globals.cpuid.u32AMDFeatureEDX;
1038	pVM->hwaccm.s.lLastError = HWACCMR0Globals.lLastError;
1039
1040	pVM->hwaccm.s.uMaxASID = HWACCMR0Globals.uMaxASID;
1041
1042
1043	if (!pVM->hwaccm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1044	{
1045	pVM->hwaccm.s.cMaxResumeLoops = 1024;
1046	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1047	if (RTThreadPreemptIsPendingTrusty())
1048	pVM->hwaccm.s.cMaxResumeLoops = 8192;
1049	#endif
1050	}
1051
1052	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1053	{
1054	PVMCPU pVCpu = &pVM->aCpus[i];
1055
1056	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1057
1058	/* Invalidate the last cpu we were running on. */
1059	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
1060
1061	/* we'll aways increment this the first time (host uses ASID 0) */
1062	pVCpu->hwaccm.s.uCurrentASID = 0;
1063	}
1064
1065	RTCCUINTREG fFlags = ASMIntDisableFlags();
1066	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1067
1068	/* Note: Not correct as we can be rescheduled to a different cpu, but the fInUse case is mostly for debugging. */
1069	ASMAtomicWriteBool(&pCpu->fInUse, true);
1070	ASMSetFlags(fFlags);
1071
1072	/* Init a VT-x or AMD-V VM. */
1073	rc = HWACCMR0Globals.pfnInitVM(pVM);
1074
1075	ASMAtomicWriteBool(&pCpu->fInUse, false);
1076	return rc;
1077	}
1078
1079
1080	/**
1081	* Does Ring-0 per VM HWACCM termination.
1082	*
1083	* @returns VBox status code.
1084	* @param pVM The VM to operate on.
1085	*/
1086	VMMR0DECL(int) HWACCMR0TermVM(PVM pVM)
1087	{
1088	int rc;
1089
1090	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1091
1092	#ifdef LOG_ENABLED
1093	SUPR0Printf("HWACCMR0TermVM: %p\n", pVM);
1094	#endif
1095
1096	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
1097	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1098
1099	/* @note Not correct as we can be rescheduled to a different cpu, but the fInUse case is mostly for debugging. */
1100	RTCCUINTREG fFlags = ASMIntDisableFlags();
1101	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1102
1103	ASMAtomicWriteBool(&pCpu->fInUse, true);
1104	ASMSetFlags(fFlags);
1105
1106	/* Terminate a VT-x or AMD-V VM. */
1107	rc = HWACCMR0Globals.pfnTermVM(pVM);
1108
1109	ASMAtomicWriteBool(&pCpu->fInUse, false);
1110	return rc;
1111	}
1112
1113
1114	/**
1115	* Sets up a VT-x or AMD-V session
1116	*
1117	* @returns VBox status code.
1118	* @param pVM The VM to operate on.
1119	*/
1120	VMMR0DECL(int) HWACCMR0SetupVM(PVM pVM)
1121	{
1122	int rc;
1123	RTCPUID idCpu = RTMpCpuId();
1124	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1125
1126	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1127
1128	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
1129	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1130
1131	#ifdef LOG_ENABLED
1132	SUPR0Printf("HWACCMR0SetupVM: %p\n", pVM);
1133	#endif
1134
1135	ASMAtomicWriteBool(&pCpu->fInUse, true);
1136
1137	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1138	{
1139	/* On first entry we'll sync everything. */
1140	pVM->aCpus[i].hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1141	}
1142
1143	/* Enable VT-x or AMD-V if local init is required. */
1144	if (!HWACCMR0Globals.fGlobalInit)
1145	{
1146	rc = hwaccmR0EnableCpu(pVM, idCpu);
1147	AssertRCReturn(rc, rc);
1148	}
1149
1150	/* Setup VT-x or AMD-V. */
1151	rc = HWACCMR0Globals.pfnSetupVM(pVM);
1152
1153	/* Disable VT-x or AMD-V if local init was done before. */
1154	if (!HWACCMR0Globals.fGlobalInit)
1155	{
1156	rc = hwaccmR0DisableCpu(idCpu);
1157	AssertRC(rc);
1158	}
1159
1160	ASMAtomicWriteBool(&pCpu->fInUse, false);
1161
1162	return rc;
1163	}
1164
1165
1166	/**
1167	* Enters the VT-x or AMD-V session
1168	*
1169	* @returns VBox status code.
1170	* @param pVM The VM to operate on.
1171	* @param pVCpu VMCPU handle.
1172	*/
1173	VMMR0DECL(int) HWACCMR0Enter(PVM pVM, PVMCPU pVCpu)
1174	{
1175	PCPUMCTX pCtx;
1176	int rc;
1177	RTCPUID idCpu = RTMpCpuId();
1178	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1179
1180	/* Make sure we can't enter a session after we've disabled hwaccm in preparation of a suspend. */
1181	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1182	ASMAtomicWriteBool(&pCpu->fInUse, true);
1183
1184	AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == NIL_RTCPUID, ("%d", (int)pVCpu->hwaccm.s.idEnteredCpu));
1185	pVCpu->hwaccm.s.idEnteredCpu = idCpu;
1186
1187	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1188
1189	/* Always load the guest's FPU/XMM state on-demand. */
1190	CPUMDeactivateGuestFPUState(pVCpu);
1191
1192	/* Always load the guest's debug state on-demand. */
1193	CPUMDeactivateGuestDebugState(pVCpu);
1194
1195	/* Always reload the host context and the guest's CR0 register. (!!!!) */
1196	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0 \| HWACCM_CHANGED_HOST_CONTEXT;
1197
1198	/* Setup the register and mask according to the current execution mode. */
1199	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1200	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFFFFFFFFFF);
1201	else
1202	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFF);
1203
1204	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1205	if ( !pCpu->fConfigured
1206	\|\| !HWACCMR0Globals.fGlobalInit)
1207	{
1208	rc = hwaccmR0EnableCpu(pVM, idCpu);
1209	AssertRCReturn(rc, rc);
1210	}
1211
1212	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1213	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1214	#endif
1215
1216	rc = HWACCMR0Globals.pfnEnterSession(pVM, pVCpu, pCpu);
1217	AssertRC(rc);
1218	/* We must save the host context here (VT-x) as we might be rescheduled on a different cpu after a long jump back to ring 3. */
1219	rc \|= HWACCMR0Globals.pfnSaveHostState(pVM, pVCpu);
1220	AssertRC(rc);
1221	rc \|= HWACCMR0Globals.pfnLoadGuestState(pVM, pVCpu, pCtx);
1222	AssertRC(rc);
1223
1224	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1225	if (fStartedSet)
1226	PGMRZDynMapReleaseAutoSet(pVCpu);
1227	#endif
1228
1229	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1230	if (RT_FAILURE(rc))
1231	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1232	return rc;
1233	}
1234
1235
1236	/**
1237	* Leaves the VT-x or AMD-V session
1238	*
1239	* @returns VBox status code.
1240	* @param pVM The VM to operate on.
1241	* @param pVCpu VMCPU handle.
1242	*/
1243	VMMR0DECL(int) HWACCMR0Leave(PVM pVM, PVMCPU pVCpu)
1244	{
1245	PCPUMCTX pCtx;
1246	int rc;
1247	RTCPUID idCpu = RTMpCpuId();
1248	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1249
1250	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1251
1252	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1253
1254	/* Note: It's rather tricky with longjmps done by e.g. Log statements or the page fault handler.
1255	* We must restore the host FPU here to make absolutely sure we don't leave the guest FPU state active
1256	* or trash somebody else's FPU state.
1257	*/
1258	/* Save the guest FPU and XMM state if necessary. */
1259	if (CPUMIsGuestFPUStateActive(pVCpu))
1260	{
1261	Log2(("CPUMR0SaveGuestFPU\n"));
1262	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
1263
1264	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1265	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1266	}
1267
1268	rc = HWACCMR0Globals.pfnLeaveSession(pVM, pVCpu, pCtx);
1269
1270	/* We don't pass on invlpg information to the recompiler for nested paging guests, so we must make sure the recompiler flushes its TLB
1271	* the next time it executes code.
1272	*/
1273	if ( pVM->hwaccm.s.fNestedPaging
1274	&& CPUMIsGuestInPagedProtectedModeEx(pCtx))
1275	{
1276	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
1277	}
1278
1279	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1280	#ifdef RT_STRICT
1281	if (RT_UNLIKELY( pVCpu->hwaccm.s.idEnteredCpu != idCpu
1282	&& RT_FAILURE(rc)))
1283	{
1284	AssertMsgFailed(("Owner is %d, I'm %d", (int)pVCpu->hwaccm.s.idEnteredCpu, (int)idCpu));
1285	rc = VERR_INTERNAL_ERROR;
1286	}
1287	#endif
1288	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1289
1290	/* Disable VT-x or AMD-V if local init was done before. */
1291	if (!HWACCMR0Globals.fGlobalInit)
1292	{
1293	rc = hwaccmR0DisableCpu(idCpu);
1294	AssertRC(rc);
1295
1296	/* Reset these to force a TLB flush for the next entry. (-> EXPENSIVE) */
1297	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
1298	pVCpu->hwaccm.s.uCurrentASID = 0;
1299	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1300	}
1301
1302	ASMAtomicWriteBool(&pCpu->fInUse, false);
1303	return rc;
1304	}
1305
1306	/**
1307	* Runs guest code in a hardware accelerated VM.
1308	*
1309	* @returns VBox status code.
1310	* @param pVM The VM to operate on.
1311	* @param pVCpu VMCPUD id.
1312	*/
1313	VMMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1314	{
1315	CPUMCTX *pCtx;
1316	int rc;
1317	#ifdef VBOX_STRICT
1318	RTCPUID idCpu = RTMpCpuId(); NOREF(idCpu);
1319	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1320	#endif
1321
1322	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1323	Assert(HWACCMR0Globals.aCpuInfo[idCpu].fConfigured);
1324	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1325	Assert(ASMAtomicReadBool(&pCpu->fInUse) == true);
1326
1327	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1328	PGMRZDynMapStartAutoSet(pVCpu);
1329	#endif
1330
1331	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1332
1333	rc = HWACCMR0Globals.pfnRunGuestCode(pVM, pVCpu, pCtx);
1334
1335	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1336	PGMRZDynMapReleaseAutoSet(pVCpu);
1337	#endif
1338	return rc;
1339	}
1340
1341
1342	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1343	/**
1344	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1345	*
1346	* @returns VBox status code.
1347	* @param pVM VM handle.
1348	* @param pVCpu VMCPU handle.
1349	* @param pCtx CPU context
1350	*/
1351	VMMR0DECL(int) HWACCMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1352	{
1353	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFpu64SwitchBack);
1354	if (pVM->hwaccm.s.vmx.fSupported)
1355	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1356
1357	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1358	}
1359
1360	/**
1361	* Save guest debug state (64 bits guest mode & 32 bits host only)
1362	*
1363	* @returns VBox status code.
1364	* @param pVM VM handle.
1365	* @param pVCpu VMCPU handle.
1366	* @param pCtx CPU context
1367	*/
1368	VMMR0DECL(int) HWACCMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1369	{
1370	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDebug64SwitchBack);
1371	if (pVM->hwaccm.s.vmx.fSupported)
1372	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1373
1374	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1375	}
1376
1377	/**
1378	* Test the 32->64 bits switcher
1379	*
1380	* @returns VBox status code.
1381	* @param pVM VM handle.
1382	*/
1383	VMMR0DECL(int) HWACCMR0TestSwitcher3264(PVM pVM)
1384	{
1385	PVMCPU pVCpu = &pVM->aCpus[0];
1386	CPUMCTX *pCtx;
1387	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1388	int rc;
1389
1390	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1391
1392	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1393	if (pVM->hwaccm.s.vmx.fSupported)
1394	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1395	else
1396	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1397	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1398	return rc;
1399	}
1400
1401	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1402
1403	/**
1404	* Returns suspend status of the host
1405	*
1406	* @returns Suspend pending or not
1407	*/
1408	VMMR0DECL(bool) HWACCMR0SuspendPending()
1409	{
1410	return ASMAtomicReadBool(&HWACCMR0Globals.fSuspended);
1411	}
1412
1413	/**
1414	* Returns the cpu structure for the current cpu.
1415	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1416	*
1417	* @returns cpu structure pointer
1418	*/
1419	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu()
1420	{
1421	RTCPUID idCpu = RTMpCpuId();
1422
1423	return &HWACCMR0Globals.aCpuInfo[idCpu];
1424	}
1425
1426	/**
1427	* Returns the cpu structure for the current cpu.
1428	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1429	*
1430	* @returns cpu structure pointer
1431	* @param idCpu id of the VCPU
1432	*/
1433	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu)
1434	{
1435	return &HWACCMR0Globals.aCpuInfo[idCpu];
1436	}
1437
1438	/**
1439	* Save a pending IO read.
1440	*
1441	* @param pVCpu The VMCPU to operate on.
1442	* @param GCPtrRip Address of IO instruction
1443	* @param GCPtrRipNext Address of the next instruction
1444	* @param uPort Port address
1445	* @param uAndVal And mask for saving the result in eax
1446	* @param cbSize Read size
1447	*/
1448	VMMR0DECL(void) HWACCMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1449	{
1450	pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_PORT_READ;
1451	pVCpu->hwaccm.s.PendingIO.GCPtrRip = GCPtrRip;
1452	pVCpu->hwaccm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1453	pVCpu->hwaccm.s.PendingIO.s.Port.uPort = uPort;
1454	pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal = uAndVal;
1455	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize = cbSize;
1456	return;
1457	}
1458
1459	/**
1460	* Save a pending IO write.
1461	*
1462	* @param pVCpu The VMCPU to operate on.
1463	* @param GCPtrRIP Address of IO instruction
1464	* @param uPort Port address
1465	* @param uAndVal And mask for fetching the result from eax
1466	* @param cbSize Read size
1467	*/
1468	VMMR0DECL(void) HWACCMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1469	{
1470	pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_PORT_WRITE;
1471	pVCpu->hwaccm.s.PendingIO.GCPtrRip = GCPtrRip;
1472	pVCpu->hwaccm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1473	pVCpu->hwaccm.s.PendingIO.s.Port.uPort = uPort;
1474	pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal = uAndVal;
1475	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize = cbSize;
1476	return;
1477	}
1478
1479	/**
1480	* Disable VT-x if it's active and the current switcher turns off paging
1481	*
1482	* @returns VBox status code.
1483	* @param pVM VM handle.
1484	* @param pfVTxDisabled VT-x was disabled or not (out)
1485	*/
1486	VMMR0DECL(int) HWACCMR0EnterSwitcher(PVM pVM, bool *pfVTxDisabled)
1487	{
1488	Assert(!(ASMGetFlags() & X86_EFL_IF) \|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1489
1490	*pfVTxDisabled = false;
1491
1492	if ( HWACCMR0Globals.enmHwAccmState != HWACCMSTATE_ENABLED
1493	\|\| !HWACCMR0Globals.vmx.fSupported /* no such issues with AMD-V */
1494	\|\| !HWACCMR0Globals.fGlobalInit /* Local init implies the CPU is currently not in VMX root mode. */)
1495	return VINF_SUCCESS; /* nothing to do */
1496
1497	switch(VMMGetSwitcher(pVM))
1498	{
1499	case VMMSWITCHER_32_TO_32:
1500	case VMMSWITCHER_PAE_TO_PAE:
1501	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1502
1503	case VMMSWITCHER_32_TO_PAE:
1504	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1505	case VMMSWITCHER_AMD64_TO_32:
1506	case VMMSWITCHER_AMD64_TO_PAE:
1507	break; /* unsafe switchers */
1508
1509	default:
1510	AssertFailed();
1511	return VERR_INTERNAL_ERROR;
1512	}
1513
1514	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1515	void *pvPageCpu;
1516	RTHCPHYS pPageCpuPhys;
1517
1518	AssertReturn(pCpu && pCpu->pMemObj, VERR_INTERNAL_ERROR);
1519	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
1520	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
1521
1522	*pfVTxDisabled = true;
1523	return VMXR0DisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
1524	}
1525
1526	/**
1527	* Enable VT-x if was active and the current switcher turned off paging
1528	*
1529	* @returns VBox status code.
1530	* @param pVM VM handle.
1531	* @param fVTxDisabled VT-x was disabled or not
1532	*/
1533	VMMR0DECL(int) HWACCMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1534	{
1535	Assert(!(ASMGetFlags() & X86_EFL_IF));
1536
1537	if (!fVTxDisabled)
1538	return VINF_SUCCESS; /* nothing to do */
1539
1540	Assert( HWACCMR0Globals.enmHwAccmState == HWACCMSTATE_ENABLED
1541	&& HWACCMR0Globals.vmx.fSupported
1542	&& HWACCMR0Globals.fGlobalInit);
1543
1544	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1545	void *pvPageCpu;
1546	RTHCPHYS pPageCpuPhys;
1547
1548	AssertReturn(pCpu && pCpu->pMemObj, VERR_INTERNAL_ERROR);
1549	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
1550	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
1551
1552	return VMXR0EnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
1553	}
1554
1555	#ifdef VBOX_STRICT
1556	/**
1557	* Dumps a descriptor.
1558	*
1559	* @param pDesc Descriptor to dump.
1560	* @param Sel Selector number.
1561	* @param pszMsg Message to prepend the log entry with.
1562	*/
1563	VMMR0DECL(void) HWACCMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1564	{
1565	/*
1566	* Make variable description string.
1567	*/
1568	static struct
1569	{
1570	unsigned cch;
1571	const char *psz;
1572	} const s_aTypes[32] =
1573	{
1574	# define STRENTRY(str) { sizeof(str) - 1, str }
1575
1576	/* system */
1577	# if HC_ARCH_BITS == 64
1578	STRENTRY("Reserved0 "), /* 0x00 */
1579	STRENTRY("Reserved1 "), /* 0x01 */
1580	STRENTRY("LDT "), /* 0x02 */
1581	STRENTRY("Reserved3 "), /* 0x03 */
1582	STRENTRY("Reserved4 "), /* 0x04 */
1583	STRENTRY("Reserved5 "), /* 0x05 */
1584	STRENTRY("Reserved6 "), /* 0x06 */
1585	STRENTRY("Reserved7 "), /* 0x07 */
1586	STRENTRY("Reserved8 "), /* 0x08 */
1587	STRENTRY("TSS64Avail "), /* 0x09 */
1588	STRENTRY("ReservedA "), /* 0x0a */
1589	STRENTRY("TSS64Busy "), /* 0x0b */
1590	STRENTRY("Call64 "), /* 0x0c */
1591	STRENTRY("ReservedD "), /* 0x0d */
1592	STRENTRY("Int64 "), /* 0x0e */
1593	STRENTRY("Trap64 "), /* 0x0f */
1594	# else
1595	STRENTRY("Reserved0 "), /* 0x00 */
1596	STRENTRY("TSS16Avail "), /* 0x01 */
1597	STRENTRY("LDT "), /* 0x02 */
1598	STRENTRY("TSS16Busy "), /* 0x03 */
1599	STRENTRY("Call16 "), /* 0x04 */
1600	STRENTRY("Task "), /* 0x05 */
1601	STRENTRY("Int16 "), /* 0x06 */
1602	STRENTRY("Trap16 "), /* 0x07 */
1603	STRENTRY("Reserved8 "), /* 0x08 */
1604	STRENTRY("TSS32Avail "), /* 0x09 */
1605	STRENTRY("ReservedA "), /* 0x0a */
1606	STRENTRY("TSS32Busy "), /* 0x0b */
1607	STRENTRY("Call32 "), /* 0x0c */
1608	STRENTRY("ReservedD "), /* 0x0d */
1609	STRENTRY("Int32 "), /* 0x0e */
1610	STRENTRY("Trap32 "), /* 0x0f */
1611	# endif
1612	/* non system */
1613	STRENTRY("DataRO "), /* 0x10 */
1614	STRENTRY("DataRO Accessed "), /* 0x11 */
1615	STRENTRY("DataRW "), /* 0x12 */
1616	STRENTRY("DataRW Accessed "), /* 0x13 */
1617	STRENTRY("DataDownRO "), /* 0x14 */
1618	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1619	STRENTRY("DataDownRW "), /* 0x16 */
1620	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1621	STRENTRY("CodeEO "), /* 0x18 */
1622	STRENTRY("CodeEO Accessed "), /* 0x19 */
1623	STRENTRY("CodeER "), /* 0x1a */
1624	STRENTRY("CodeER Accessed "), /* 0x1b */
1625	STRENTRY("CodeConfEO "), /* 0x1c */
1626	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1627	STRENTRY("CodeConfER "), /* 0x1e */
1628	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1629	# undef SYSENTRY
1630	};
1631	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1632	char szMsg[128];
1633	char *psz = &szMsg[0];
1634	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1635	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1636	psz += s_aTypes[i].cch;
1637
1638	if (pDesc->Gen.u1Present)
1639	ADD_STR(psz, "Present ");
1640	else
1641	ADD_STR(psz, "Not-Present ");
1642	# if HC_ARCH_BITS == 64
1643	if (pDesc->Gen.u1Long)
1644	ADD_STR(psz, "64-bit ");
1645	else
1646	ADD_STR(psz, "Comp ");
1647	# else
1648	if (pDesc->Gen.u1Granularity)
1649	ADD_STR(psz, "Page ");
1650	if (pDesc->Gen.u1DefBig)
1651	ADD_STR(psz, "32-bit ");
1652	else
1653	ADD_STR(psz, "16-bit ");
1654	# endif
1655	# undef ADD_STR
1656	*psz = '\0';
1657
1658	/*
1659	* Limit and Base and format the output.
1660	*/
1661	uint32_t u32Limit = X86DESC_LIMIT(*pDesc);
1662	if (pDesc->Gen.u1Granularity)
1663	u32Limit = u32Limit << PAGE_SHIFT \| PAGE_OFFSET_MASK;
1664
1665	# if HC_ARCH_BITS == 64
1666	uint64_t u32Base = X86DESC64_BASE(*pDesc);
1667
1668	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1669	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1670	# else
1671	uint32_t u32Base = X86DESC_BASE(*pDesc);
1672
1673	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1674	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1675	# endif
1676	}
1677
1678	/**
1679	* Formats a full register dump.
1680	*
1681	* @param pVM The VM to operate on.
1682	* @param pVCpu The VMCPU to operate on.
1683	* @param pCtx The context to format.
1684	*/
1685	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1686	{
1687	/*
1688	* Format the flags.
1689	*/
1690	static struct
1691	{
1692	const char pszSet; const char pszClear; uint32_t fFlag;
1693	} aFlags[] =
1694	{
1695	{ "vip",NULL, X86_EFL_VIP },
1696	{ "vif",NULL, X86_EFL_VIF },
1697	{ "ac", NULL, X86_EFL_AC },
1698	{ "vm", NULL, X86_EFL_VM },
1699	{ "rf", NULL, X86_EFL_RF },
1700	{ "nt", NULL, X86_EFL_NT },
1701	{ "ov", "nv", X86_EFL_OF },
1702	{ "dn", "up", X86_EFL_DF },
1703	{ "ei", "di", X86_EFL_IF },
1704	{ "tf", NULL, X86_EFL_TF },
1705	{ "nt", "pl", X86_EFL_SF },
1706	{ "nz", "zr", X86_EFL_ZF },
1707	{ "ac", "na", X86_EFL_AF },
1708	{ "po", "pe", X86_EFL_PF },
1709	{ "cy", "nc", X86_EFL_CF },
1710	};
1711	char szEFlags[80];
1712	char *psz = szEFlags;
1713	uint32_t efl = pCtx->eflags.u32;
1714	for (unsigned i = 0; i < RT_ELEMENTS(aFlags); i++)
1715	{
1716	const char *pszAdd = aFlags[i].fFlag & efl ? aFlags[i].pszSet : aFlags[i].pszClear;
1717	if (pszAdd)
1718	{
1719	strcpy(psz, pszAdd);
1720	psz += strlen(pszAdd);
1721	*psz++ = ' ';
1722	}
1723	}
1724	psz[-1] = '\0';
1725
1726
1727	/*
1728	* Format the registers.
1729	*/
1730	if (CPUMIsGuestIn64BitCode(pVCpu, CPUMCTX2CORE(pCtx)))
1731	{
1732	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1733	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1734	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1735	"r14=%016RX64 r15=%016RX64\n"
1736	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1737	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1738	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1739	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1740	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1741	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1742	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1743	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1744	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1745	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1746	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1747	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1748	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1749	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1750	,
1751	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1752	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1753	pCtx->r14, pCtx->r15,
1754	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1755	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1756	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1757	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1758	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1759	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1760	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1761	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1762	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1763	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1764	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1765	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1766	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1767	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1768	}
1769	else
1770	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1771	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1772	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1773	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1774	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1775	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1776	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1777	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1778	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1779	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1780	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1781	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1782	,
1783	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1784	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1785	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr[0], pCtx->dr[1],
1786	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr[2], pCtx->dr[3],
1787	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr[4], pCtx->dr[5],
1788	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr[6], pCtx->dr[7],
1789	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0, pCtx->cr2,
1790	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3, pCtx->cr4,
1791	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1792	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1793	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1794	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1795
1796	Log(("FPU:\n"
1797	"FCW=%04x FSW=%04x FTW=%02x\n"
1798	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
1799	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1800	,
1801	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
1802	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsrvd1,
1803	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
1804	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
1805
1806
1807	Log(("MSR:\n"
1808	"EFER =%016RX64\n"
1809	"PAT =%016RX64\n"
1810	"STAR =%016RX64\n"
1811	"CSTAR =%016RX64\n"
1812	"LSTAR =%016RX64\n"
1813	"SFMASK =%016RX64\n"
1814	"KERNELGSBASE =%016RX64\n",
1815	pCtx->msrEFER,
1816	pCtx->msrPAT,
1817	pCtx->msrSTAR,
1818	pCtx->msrCSTAR,
1819	pCtx->msrLSTAR,
1820	pCtx->msrSFMASK,
1821	pCtx->msrKERNELGSBASE));
1822
1823	}
1824	#endif /* VBOX_STRICT */
1825
1826	/* Dummy callback handlers. */
1827	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
1828	{
1829	return VINF_SUCCESS;
1830	}
1831
1832	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1833	{
1834	return VINF_SUCCESS;
1835	}
1836
1837	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1838	{
1839	return VINF_SUCCESS;
1840	}
1841
1842	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1843	{
1844	return VINF_SUCCESS;
1845	}
1846
1847	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM)
1848	{
1849	return VINF_SUCCESS;
1850	}
1851
1852	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM)
1853	{
1854	return VINF_SUCCESS;
1855	}
1856
1857	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM)
1858	{
1859	return VINF_SUCCESS;
1860	}
1861
1862	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1863	{
1864	return VINF_SUCCESS;
1865	}
1866
1867	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
1868	{
1869	return VINF_SUCCESS;
1870	}
1871
1872	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1873	{
1874	return VINF_SUCCESS;
1875	}

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp@ 37182

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