HWACCMR0.cpp@ 39070

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1	/* $Id: HWACCMR0.cpp 39070 2011-10-21 09:41:18Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2011 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HWACCM
23	#include <VBox/vmm/hwaccm.h>
24	#include <VBox/vmm/pgm.h>
25	#include "HWACCMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include <VBox/vmm/hwacc_vmx.h>
28	#include <VBox/vmm/hwacc_svm.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mem.h>
36	#include <iprt/memobj.h>
37	#include <iprt/once.h>
38	#include <iprt/param.h>
39	#include <iprt/power.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42	#include <iprt/x86.h>
43	#include "HWVMXR0.h"
44	#include "HWSVMR0.h"
45
46
47	/*******************************************************************************
48	* Internal Functions *
49	*******************************************************************************/
50	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
55	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* This is used to manage the status code of a RTMpOnAll in HM.
63	*/
64	typedef struct HMR0FIRSTRC
65	{
66	/** The status code. */
67	int32_t volatile rc;
68	/** The ID of the CPU reporting the first failure. */
69	RTCPUID volatile idCpu;
70	} HMR0FIRSTRC;
71	/** Pointer to a first return code structure. */
72	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
73
74
75	/*******************************************************************************
76	* Global Variables *
77	*******************************************************************************/
78	/**
79	* Global data.
80	*/
81	static struct
82	{
83	/** Per CPU globals. */
84	HMGLOBLCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
85
86	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
87	* @{ */
88	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHMGLOBLCPUINFO pCpu));
89	DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
90	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
91	DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
92	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
93	DECLR0CALLBACKMEMBER(int, pfnEnableCpu,(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
94	DECLR0CALLBACKMEMBER(int, pfnDisableCpu,(PHMGLOBLCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
95	DECLR0CALLBACKMEMBER(int, pfnInitVM,(PVM pVM));
96	DECLR0CALLBACKMEMBER(int, pfnTermVM,(PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnSetupVM,(PVM pVM));
98	/** @} */
99
100	/** Maximum ASID allowed. */
101	uint32_t uMaxASID;
102
103	/** VT-x data. */
104	struct
105	{
106	/** Set to by us to indicate VMX is supported by the CPU. */
107	bool fSupported;
108	/** Whether we're using SUPR0EnableVTx or not. */
109	bool fUsingSUPR0EnableVTx;
110	/** Whether we're using the preemption timer or not. */
111	bool fUsePreemptTimer;
112	/** The shift mask employed by the VMX-Preemption timer. */
113	uint8_t cPreemptTimerShift;
114
115	/** Host CR4 value (set by ring-0 VMX init) */
116	uint64_t hostCR4;
117
118	/** Host EFER value (set by ring-0 VMX init) */
119	uint64_t hostEFER;
120
121	/** VMX MSR values */
122	struct
123	{
124	uint64_t feature_ctrl;
125	uint64_t vmx_basic_info;
126	VMX_CAPABILITY vmx_pin_ctls;
127	VMX_CAPABILITY vmx_proc_ctls;
128	VMX_CAPABILITY vmx_proc_ctls2;
129	VMX_CAPABILITY vmx_exit;
130	VMX_CAPABILITY vmx_entry;
131	uint64_t vmx_misc;
132	uint64_t vmx_cr0_fixed0;
133	uint64_t vmx_cr0_fixed1;
134	uint64_t vmx_cr4_fixed0;
135	uint64_t vmx_cr4_fixed1;
136	uint64_t vmx_vmcs_enum;
137	uint64_t vmx_eptcaps;
138	} msr;
139	/* Last instruction error */
140	uint32_t ulLastInstrError;
141	} vmx;
142
143	/** AMD-V information. */
144	struct
145	{
146	/* HWCR msr (for diagnostics) */
147	uint64_t msrHWCR;
148
149	/** SVM revision. */
150	uint32_t u32Rev;
151
152	/** SVM feature bits from cpuid 0x8000000a */
153	uint32_t u32Features;
154
155	/** Set by us to indicate SVM is supported by the CPU. */
156	bool fSupported;
157	} svm;
158	/** Saved error from detection */
159	int32_t lLastError;
160
161	struct
162	{
163	uint32_t u32AMDFeatureECX;
164	uint32_t u32AMDFeatureEDX;
165	} cpuid;
166
167	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
168	* enabled and disabled each time it's used to execute guest code. */
169	bool fGlobalInit;
170	/** Indicates whether the host is suspending or not. We'll refuse a few
171	* actions when the host is being suspended to speed up the suspending and
172	* avoid trouble. */
173	volatile bool fSuspended;
174
175	/** Whether we've already initialized all CPUs.
176	* @remarks We could check the EnableAllCpusOnce state, but this is
177	* simpler and hopefully easier to understand. */
178	bool fEnabled;
179	/** Serialize initialization in HWACCMR0EnableAllCpus. */
180	RTONCE EnableAllCpusOnce;
181	} g_HvmR0;
182
183
184
185	/**
186	* Initializes a first return code structure.
187	*
188	* @param pFirstRc The structure to init.
189	*/
190	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
191	{
192	pFirstRc->rc = VINF_SUCCESS;
193	pFirstRc->idCpu = NIL_RTCPUID;
194	}
195
196
197	/**
198	* Try se the status code (success ignored).
199	*
200	* @param pFirstRc The first return code structure.
201	* @param rc The status code.
202	*/
203	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
204	{
205	if ( RT_FAILURE(rc)
206	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
207	pFirstRc->idCpu = RTMpCpuId();
208	}
209
210
211	/**
212	* Get the status code of a first return code structure.
213	*
214	* @returns The status code; VINF_SUCCESS or error status, no informational or
215	* warning errors.
216	* @param pFirstRc The first return code structure.
217	*/
218	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
219	{
220	return pFirstRc->rc;
221	}
222
223
224	#ifdef VBOX_STRICT
225	/**
226	* Get the CPU ID on which the failure status code was reported.
227	*
228	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
229	* @param pFirstRc The first return code structure.
230	*/
231	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
232	{
233	return pFirstRc->idCpu;
234	}
235	#endif /* VBOX_STRICT */
236
237
238	/** @name Dummy callback handlers.
239	* @{ */
240
241	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBLCPUINFO pCpu)
242	{
243	return VINF_SUCCESS;
244	}
245
246	static DECLCALLBACK(int) hmR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
247	{
248	return VINF_SUCCESS;
249	}
250
251	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
252	{
253	return VINF_SUCCESS;
254	}
255
256	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBLCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
257	{
258	return VINF_SUCCESS;
259	}
260
261	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
262	{
263	return VINF_SUCCESS;
264	}
265
266	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
267	{
268	return VINF_SUCCESS;
269	}
270
271	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
272	{
273	return VINF_SUCCESS;
274	}
275
276	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
277	{
278	return VINF_SUCCESS;
279	}
280
281	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
282	{
283	return VINF_SUCCESS;
284	}
285
286	static DECLCALLBACK(int) hmR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
287	{
288	return VINF_SUCCESS;
289	}
290
291	/** @} */
292
293
294	/**
295	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
296	* Down at the Rate Specified" erratum.
297	*
298	* Errata names and related steppings:
299	* - BA86 - D0.
300	* - AAX65 - C2.
301	* - AAU65 - C2, K0.
302	* - AAO95 - B1.
303	* - AAT59 - C2.
304	* - AAK139 - D0.
305	* - AAM126 - C0, C1, D0.
306	* - AAN92 - B1.
307	* - AAJ124 - C0, D0.
308	*
309	* - AAP86 - B1.
310	*
311	* Steppings: B1, C0, C1, C2, D0, K0.
312	*
313	* @returns true if subject to it, false if not.
314	*/
315	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
316	{
317	uint32_t u = ASMCpuId_EAX(1);
318	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
319	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
320	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
321	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
322	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
323	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
324	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
325	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
326	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
327	\|\| u == UINT32_C(0x000106A0) /?321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification /
328	\|\| u == UINT32_C(0x000106A1) /?321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification /
329	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
330	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
331	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
332	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
333	)
334	return true;
335	return false;
336	}
337
338
339	/**
340	* Intel specific initialization code.
341	*
342	* @returns VBox status code (will only fail if out of memory).
343	*/
344	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
345	{
346	/*
347	* Check that all the required VT-x features are present.
348	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
349	*/
350	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
351	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
352	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
353	)
354	{
355	/** @todo move this into a separate function. */
356	g_HvmR0.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
357
358	/*
359	* First try use native kernel API for controlling VT-x.
360	* (This is only supported by some Mac OS X kernels atm.)
361	*/
362	int rc = g_HvmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
363	g_HvmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
364	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
365	{
366	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
367	if (RT_SUCCESS(rc))
368	{
369	g_HvmR0.vmx.fSupported = true;
370	rc = SUPR0EnableVTx(false /* fEnable */);
371	AssertRC(rc);
372	}
373	}
374	else
375	{
376	/* We need to check if VT-x has been properly initialized on all
377	CPUs. Some BIOSes do a lousy job. */
378	HMR0FIRSTRC FirstRc;
379	hmR0FirstRcInit(&FirstRc);
380	g_HvmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
381	if (RT_SUCCESS(g_HvmR0.lLastError))
382	g_HvmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
383	}
384	if (RT_SUCCESS(g_HvmR0.lLastError))
385	{
386	/* Reread in case we've changed it. */
387	g_HvmR0.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
388
389	if ( (g_HvmR0.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
390	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
391	{
392	/*
393	* Read all relevant MSR.
394	*/
395	g_HvmR0.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
396	g_HvmR0.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
397	g_HvmR0.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
398	g_HvmR0.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
399	g_HvmR0.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
400	g_HvmR0.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
401	g_HvmR0.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
402	g_HvmR0.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
403	g_HvmR0.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
404	g_HvmR0.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
405	g_HvmR0.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
406	g_HvmR0.vmx.hostCR4 = ASMGetCR4();
407	g_HvmR0.vmx.hostEFER = ASMRdMsr(MSR_K6_EFER);
408	/* VPID 16 bits ASID. */
409	g_HvmR0.uMaxASID = 0x10000; /* exclusive */
410
411	if (g_HvmR0.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
412	{
413	g_HvmR0.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
414	if ( g_HvmR0.vmx.msr.vmx_proc_ctls2.n.allowed1
415	& (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
416	g_HvmR0.vmx.msr.vmx_eptcaps = ASMRdMsr(MSR_IA32_VMX_EPT_CAPS);
417	}
418
419	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
420	{
421	/*
422	* Enter root mode
423	*/
424	RTR0MEMOBJ hScatchMemObj;
425	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, true /* executable R0 mapping */);
426	if (RT_FAILURE(rc))
427	return rc;
428
429	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
430	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
431	ASMMemZeroPage(pvScatchPage);
432
433	/* Set revision dword at the beginning of the structure. */
434	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HvmR0.vmx.msr.vmx_basic_info);
435
436	/* Make sure we don't get rescheduled to another cpu during this probe. */
437	RTCCUINTREG fFlags = ASMIntDisableFlags();
438
439	/*
440	* Check CR4.VMXE
441	*/
442	g_HvmR0.vmx.hostCR4 = ASMGetCR4();
443	if (!(g_HvmR0.vmx.hostCR4 & X86_CR4_VMXE))
444	{
445	/* In theory this bit could be cleared behind our back. Which would cause
446	#UD faults when we try to execute the VMX instructions... */
447	ASMSetCR4(g_HvmR0.vmx.hostCR4 \| X86_CR4_VMXE);
448	}
449
450	/* Enter VMX Root Mode */
451	rc = VMXEnable(HCPhysScratchPage);
452	if (RT_SUCCESS(rc))
453	{
454	g_HvmR0.vmx.fSupported = true;
455	VMXDisable();
456
457	/*
458	* Check for the VMX-Preemption Timer and adjust for the * "VMX-Preemption
459	* Timer Does Not Count Down at the Rate Specified" erratum.
460	*/
461	if ( g_HvmR0.vmx.msr.vmx_pin_ctls.n.allowed1
462	& VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
463	{
464	g_HvmR0.vmx.fUsePreemptTimer = true;
465	g_HvmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HvmR0.vmx.msr.vmx_misc);
466	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
467	g_HvmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
468	}
469	}
470	else
471	{
472	/*
473	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
474	* it will crash the host when we enter raw mode, because:
475	*
476	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
477	* this bit), and
478	* (b) turning off paging causes a #GP (unavoidable when switching
479	* from long to 32 bits mode or 32 bits to PAE).
480	*
481	* They should fix their code, but until they do we simply refuse to run.
482	*/
483	g_HvmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
484	}
485
486	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
487	if it wasn't so before (some software could incorrectly
488	think it's in VMX mode). */
489	ASMSetCR4(g_HvmR0.vmx.hostCR4);
490	ASMSetFlags(fFlags);
491
492	RTR0MemObjFree(hScatchMemObj, false);
493	}
494	}
495	else
496	{
497	AssertFailed(); /* can't hit this case anymore */
498	g_HvmR0.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
499	}
500
501	/*
502	* Install the VT-x methods.
503	*/
504	if (g_HvmR0.vmx.fSupported)
505	{
506	g_HvmR0.pfnEnterSession = VMXR0Enter;
507	g_HvmR0.pfnLeaveSession = VMXR0Leave;
508	g_HvmR0.pfnSaveHostState = VMXR0SaveHostState;
509	g_HvmR0.pfnLoadGuestState = VMXR0LoadGuestState;
510	g_HvmR0.pfnRunGuestCode = VMXR0RunGuestCode;
511	g_HvmR0.pfnEnableCpu = VMXR0EnableCpu;
512	g_HvmR0.pfnDisableCpu = VMXR0DisableCpu;
513	g_HvmR0.pfnInitVM = VMXR0InitVM;
514	g_HvmR0.pfnTermVM = VMXR0TermVM;
515	g_HvmR0.pfnSetupVM = VMXR0SetupVM;
516	}
517	}
518	#ifdef LOG_ENABLED
519	else
520	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HvmR0.lLastError);
521	#endif
522	}
523	else
524	g_HvmR0.lLastError = VERR_VMX_NO_VMX;
525	return VINF_SUCCESS;
526	}
527
528
529	/**
530	* AMD specific initialization code.
531	*/
532	static void hmR0InitAmd(uint32_t u32FeaturesEDX)
533	{
534	/*
535	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
536	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
537	*/
538	if ( (g_HvmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
539	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
540	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
541	)
542	{
543	g_HvmR0.pfnEnterSession = SVMR0Enter;
544	g_HvmR0.pfnLeaveSession = SVMR0Leave;
545	g_HvmR0.pfnSaveHostState = SVMR0SaveHostState;
546	g_HvmR0.pfnLoadGuestState = SVMR0LoadGuestState;
547	g_HvmR0.pfnRunGuestCode = SVMR0RunGuestCode;
548	g_HvmR0.pfnEnableCpu = SVMR0EnableCpu;
549	g_HvmR0.pfnDisableCpu = SVMR0DisableCpu;
550	g_HvmR0.pfnInitVM = SVMR0InitVM;
551	g_HvmR0.pfnTermVM = SVMR0TermVM;
552	g_HvmR0.pfnSetupVM = SVMR0SetupVM;
553
554	/* Query AMD features. */
555	uint32_t u32Dummy;
556	ASMCpuId(0x8000000A, &g_HvmR0.svm.u32Rev, &g_HvmR0.uMaxASID,
557	&u32Dummy, &g_HvmR0.svm.u32Features);
558
559	/*
560	* We need to check if AMD-V has been properly initialized on all CPUs.
561	* Some BIOSes might do a poor job.
562	*/
563	HMR0FIRSTRC FirstRc;
564	hmR0FirstRcInit(&FirstRc);
565	int rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
566	AssertRC(rc);
567	if (RT_SUCCESS(rc))
568	rc = hmR0FirstRcGetStatus(&FirstRc);
569	#ifndef DEBUG_bird
570	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
571	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
572	#endif
573	if (RT_SUCCESS(rc))
574	{
575	/* Read the HWCR msr for diagnostics. */
576	g_HvmR0.svm.msrHWCR = ASMRdMsr(MSR_K8_HWCR);
577	g_HvmR0.svm.fSupported = true;
578	}
579	else
580	g_HvmR0.lLastError = rc;
581	}
582	else
583	g_HvmR0.lLastError = VERR_SVM_NO_SVM;
584	}
585
586
587	/**
588	* Does global Ring-0 HM initialization (at module init).
589	*
590	* @returns VBox status code.
591	*/
592	VMMR0DECL(int) HWACCMR0Init(void)
593	{
594	/*
595	* Initialize the globals.
596	*/
597	g_HvmR0.fEnabled = false;
598	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
599	g_HvmR0.EnableAllCpusOnce = s_OnceInit;
600	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
601	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
602
603	/* Fill in all callbacks with placeholders. */
604	g_HvmR0.pfnEnterSession = hmR0DummyEnter;
605	g_HvmR0.pfnLeaveSession = hmR0DummyLeave;
606	g_HvmR0.pfnSaveHostState = hmR0DummySaveHostState;
607	g_HvmR0.pfnLoadGuestState = hmR0DummyLoadGuestState;
608	g_HvmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
609	g_HvmR0.pfnEnableCpu = hmR0DummyEnableCpu;
610	g_HvmR0.pfnDisableCpu = hmR0DummyDisableCpu;
611	g_HvmR0.pfnInitVM = hmR0DummyInitVM;
612	g_HvmR0.pfnTermVM = hmR0DummyTermVM;
613	g_HvmR0.pfnSetupVM = hmR0DummySetupVM;
614
615	/* Default is global VT-x/AMD-V init */
616	g_HvmR0.fGlobalInit = true;
617
618	/*
619	* Make sure aCpuInfo is big enough for all the CPUs on this system.
620	*/
621	if (RTMpGetArraySize() > RT_ELEMENTS(g_HvmR0.aCpuInfo))
622	{
623	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HvmR0.aCpuInfo)));
624	return VERR_TOO_MANY_CPUS;
625	}
626
627	/*
628	* Check for VT-x and AMD-V capabilities
629	*/
630	int rc;
631	if (ASMHasCpuId())
632	{
633	uint32_t u32FeaturesECX, u32FeaturesEDX;
634	uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
635	uint32_t u32Dummy;
636
637	/* Standard features. */
638	ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
639	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
640
641	/* Query AMD features. */
642	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
643	&g_HvmR0.cpuid.u32AMDFeatureECX,
644	&g_HvmR0.cpuid.u32AMDFeatureEDX);
645
646	/* Go to CPU specific initialization code. */
647	if ( u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
648	&& u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
649	&& u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX)
650	{
651	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
652	if (RT_FAILURE(rc))
653	return rc;
654	}
655	else if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
656	&& u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
657	&& u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX)
658	hmR0InitAmd(u32FeaturesEDX);
659	else
660	g_HvmR0.lLastError = VERR_HWACCM_UNKNOWN_CPU;
661	}
662	else
663	g_HvmR0.lLastError = VERR_HWACCM_NO_CPUID;
664
665	/*
666	* Register notification callbacks that we can use to disable/enable CPUs
667	* when brought offline/online or suspending/resuming.
668	*/
669	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
670	{
671	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
672	AssertRC(rc);
673
674	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
675	AssertRC(rc);
676	}
677
678	/* We return success here because module init shall not fail if HM
679	fails to initialize. */
680	return VINF_SUCCESS;
681	}
682
683
684	/**
685	* Does global Ring-0 HM termination (at module termination).
686	*
687	* @returns VBox status code.
688	*/
689	VMMR0DECL(int) HWACCMR0Term(void)
690	{
691	int rc;
692	if ( g_HvmR0.vmx.fSupported
693	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
694	{
695	/*
696	* Simple if the host OS manages VT-x.
697	*/
698	Assert(g_HvmR0.fGlobalInit);
699	rc = SUPR0EnableVTx(false /* fEnable */);
700
701	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo); iCpu++)
702	{
703	g_HvmR0.aCpuInfo[iCpu].fConfigured = false;
704	Assert(g_HvmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
705	}
706	}
707	else
708	{
709	Assert(!g_HvmR0.vmx.fUsingSUPR0EnableVTx);
710	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
711	{
712	/* Doesn't really matter if this fails. */
713	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
714	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
715	}
716	else
717	rc = VINF_SUCCESS;
718
719	/*
720	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
721	*/
722	if (g_HvmR0.fGlobalInit)
723	{
724	HMR0FIRSTRC FirstRc;
725	hmR0FirstRcInit(&FirstRc);
726	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL, &FirstRc);
727	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
728	if (RT_SUCCESS(rc))
729	{
730	rc = hmR0FirstRcGetStatus(&FirstRc);
731	AssertMsgRC(rc, ("%u: %Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
732	}
733	}
734
735	/*
736	* Free the per-cpu pages used for VT-x and AMD-V.
737	*/
738	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
739	{
740	if (g_HvmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
741	{
742	RTR0MemObjFree(g_HvmR0.aCpuInfo[i].hMemObj, false);
743	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
744	}
745	}
746	}
747	return rc;
748	}
749
750
751	/**
752	* Worker function used by hmR0PowerCallback and HWACCMR0Init to initalize
753	* VT-x on a CPU.
754	*
755	* @param idCpu The identifier for the CPU the function is called on.
756	* @param pvUser1 Pointer to the first RC structure.
757	* @param pvUser2 Ignored.
758	*/
759	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
760	{
761	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
762	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
763	NOREF(pvUser2);
764
765	/*
766	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
767	* Once the lock bit is set, this MSR can no longer be modified.
768	*/
769	uint64_t fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
770	if ( !(fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
771	\|\| ( (fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
772	== MSR_IA32_FEATURE_CONTROL_VMXON ) /* Some BIOSes forget to set the locked bit. */
773	)
774	{
775	/* MSR is not yet locked; we can change it ourselves here */
776	ASMWrMsr(MSR_IA32_FEATURE_CONTROL,
777	g_HvmR0.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
778	fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
779	}
780
781	int rc;
782	if ( (fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
783	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
784	rc = VINF_SUCCESS;
785	else
786	rc = VERR_VMX_MSR_LOCKED_OR_DISABLED;
787
788	hmR0FirstRcSetStatus(pFirstRc, rc);
789	}
790
791
792	/**
793	* Worker function used by hmR0PowerCallback and HWACCMR0Init to initalize
794	* VT-x / AMD-V on a CPU.
795	*
796	* @param idCpu The identifier for the CPU the function is called on.
797	* @param pvUser1 Pointer to the first RC structure.
798	* @param pvUser2 Ignored.
799	*/
800	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
801	{
802	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
803	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
804	NOREF(pvUser2);
805
806	/* Check if SVM is disabled. */
807	int rc;
808	uint64_t fVmCr = ASMRdMsr(MSR_K8_VM_CR);
809	if (!(fVmCr & MSR_K8_VM_CR_SVM_DISABLE))
810	{
811	/* Turn on SVM in the EFER MSR. */
812	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
813	if (fEfer & MSR_K6_EFER_SVME)
814	rc = VERR_SVM_IN_USE;
815	else
816	{
817	ASMWrMsr(MSR_K6_EFER, fEfer \| MSR_K6_EFER_SVME);
818
819	/* Paranoia. */
820	fEfer = ASMRdMsr(MSR_K6_EFER);
821	if (fEfer & MSR_K6_EFER_SVME)
822	{
823	/* Restore previous value. */
824	ASMWrMsr(MSR_K6_EFER, fEfer & ~MSR_K6_EFER_SVME);
825	rc = VINF_SUCCESS;
826	}
827	else
828	rc = VERR_SVM_ILLEGAL_EFER_MSR;
829	}
830	}
831	else
832	rc = VERR_SVM_DISABLED;
833
834	hmR0FirstRcSetStatus(pFirstRc, rc);
835	}
836
837
838
839	/**
840	* Disable VT-x or AMD-V on the current CPU
841	*
842	* @returns VBox status code.
843	* @param pVM VM handle (can be 0!)
844	* @param idCpu The identifier for the CPU the function is called on.
845	*/
846	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
847	{
848	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
849
850	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
851	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
852	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
853	Assert(!pCpu->fConfigured);
854	Assert(!g_HvmR0.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
855
856	pCpu->idCpu = idCpu;
857
858	/* Make sure we start with a clean TLB. */
859	pCpu->fFlushTLB = true;
860
861	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
862	pCpu->cTLBFlushes = 0;
863
864	/* Should never happen */
865	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
866	{
867	AssertLogRelMsgFailed(("hmR0EnableCpu failed idCpu=%u.\n", idCpu));
868	return VERR_INTERNAL_ERROR;
869	}
870
871	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
872	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
873
874	int rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage);
875	AssertRC(rc);
876	if (RT_SUCCESS(rc))
877	pCpu->fConfigured = true;
878
879	return rc;
880	}
881
882
883	/**
884	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
885	* is to be called on the target cpus.
886	*
887	* @param idCpu The identifier for the CPU the function is called on.
888	* @param pvUser1 The 1st user argument.
889	* @param pvUser2 The 2nd user argument.
890	*/
891	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
892	{
893	PVM pVM = (PVM)pvUser1; /* can be NULL! */
894	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
895	AssertReturnVoid(g_HvmR0.fGlobalInit);
896	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
897	}
898
899
900	/**
901	* RTOnce callback employed by HWACCMR0EnableAllCpus.
902	*
903	* @returns VBox status code
904	* @param pvUser The VM handle.
905	* @param pvUserIgnore NULL, ignored.
906	*/
907	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void pvUser, void pvUserIgnore)
908	{
909	PVM pVM = (PVM)pvUser;
910	NOREF(pvUserIgnore);
911
912	/*
913	* Indicate that we've initialized.
914	*
915	* Note! There is a potential race between this function and the suspend
916	* notification. Kind of unlikely though, so ignored for now.
917	*/
918	AssertReturn(!g_HvmR0.fEnabled, VERR_INTERNAL_ERROR_3);
919	ASMAtomicWriteBool(&g_HvmR0.fEnabled, true);
920
921	/*
922	* The global init variable is set by the first VM.
923	*/
924	g_HvmR0.fGlobalInit = pVM->hwaccm.s.fGlobalInit;
925
926	int rc;
927	if ( g_HvmR0.vmx.fSupported
928	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
929	{
930	/*
931	* Global VT-x initialization API (only darwin for now).
932	*/
933	rc = SUPR0EnableVTx(true /* fEnable */);
934	if (RT_SUCCESS(rc))
935	{
936	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo); iCpu++)
937	{
938	g_HvmR0.aCpuInfo[iCpu].fConfigured = true;
939	Assert(g_HvmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
940	}
941
942	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
943	g_HvmR0.fGlobalInit = pVM->hwaccm.s.fGlobalInit = true;
944	}
945	else
946	AssertMsgFailed(("HWACCMR0EnableAllCpus/SUPR0EnableVTx: rc=%Rrc\n", rc));
947	}
948	else
949	{
950	/*
951	* We're doing the job ourselves.
952	*/
953	/* Allocate one page per cpu for the global vt-x and amd-v pages */
954	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
955	{
956	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
957
958	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
959	{
960	rc = RTR0MemObjAllocCont(&g_HvmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, true /* executable R0 mapping */);
961	AssertLogRelRCReturn(rc, rc);
962
963	void *pvR0 = RTR0MemObjAddress(g_HvmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
964	ASMMemZeroPage(pvR0);
965	}
966	g_HvmR0.aCpuInfo[i].fConfigured = false;
967	}
968
969	if (g_HvmR0.fGlobalInit)
970	{
971	/* First time, so initialize each cpu/core. */
972	HMR0FIRSTRC FirstRc;
973	hmR0FirstRcInit(&FirstRc);
974	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
975	if (RT_SUCCESS(rc))
976	rc = hmR0FirstRcGetStatus(&FirstRc);
977	AssertMsgRC(rc, ("HWACCMR0EnableAllCpus failed for cpu %d with rc=%d\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
978	}
979	else
980	rc = VINF_SUCCESS;
981	}
982
983	return rc;
984	}
985
986
987	/**
988	* Sets up HWACCM on all cpus.
989	*
990	* @returns VBox status code.
991	* @param pVM The VM handle.
992	*/
993	VMMR0DECL(int) HWACCMR0EnableAllCpus(PVM pVM)
994	{
995	/* Make sure we don't touch hwaccm after we've disabled hwaccm in
996	preparation of a suspend. */
997	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
998	return VERR_HWACCM_SUSPEND_PENDING;
999
1000	return RTOnce(&g_HvmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM, NULL);
1001	}
1002
1003
1004	/**
1005	* Disable VT-x or AMD-V on the current CPU
1006	*
1007	* @returns VBox status code.
1008	* @param idCpu The identifier for the CPU the function is called on.
1009	*/
1010	static int hmR0DisableCpu(RTCPUID idCpu)
1011	{
1012	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1013
1014	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1015	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
1016	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1017	Assert(!g_HvmR0.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
1018	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1019
1020	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1021	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1022
1023	int rc;
1024	if (pCpu->fConfigured)
1025	{
1026	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1027	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1028	rc = g_HvmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1029	AssertRC(rc);
1030	pCpu->fConfigured = false;
1031	}
1032	else
1033	rc = VINF_SUCCESS; /* nothing to do */
1034
1035	pCpu->uCurrentASID = 0;
1036	return rc;
1037	}
1038
1039
1040	/**
1041	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
1042	* is to be called on the target cpus.
1043	*
1044	* @param idCpu The identifier for the CPU the function is called on.
1045	* @param pvUser1 The 1st user argument.
1046	* @param pvUser2 The 2nd user argument.
1047	*/
1048	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1049	{
1050	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
1051	AssertReturnVoid(g_HvmR0.fGlobalInit);
1052	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1053	}
1054
1055
1056	/**
1057	* Callback function invoked when a cpu goes online or offline.
1058	*
1059	* @param enmEvent The Mp event.
1060	* @param idCpu The identifier for the CPU the function is called on.
1061	* @param pvData Opaque data (PVM pointer).
1062	*/
1063	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1064	{
1065	/*
1066	* We only care about uninitializing a CPU that is going offline. When a
1067	* CPU comes online, the initialization is done lazily in HWACCMR0Enter().
1068	*/
1069	AssertRelease(idCpu == RTMpCpuId());
1070	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1071	switch (enmEvent)
1072	{
1073	case RTMPEVENT_OFFLINE:
1074	{
1075	int rc = hmR0DisableCpu(idCpu);
1076	AssertRC(rc);
1077	break;
1078	}
1079
1080	default:
1081	break;
1082	}
1083	}
1084
1085
1086	/**
1087	* Called whenever a system power state change occurs.
1088	*
1089	* @param enmEvent Power event
1090	* @param pvUser User argument
1091	*/
1092	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1093	{
1094	NOREF(pvUser);
1095	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1096
1097	#ifdef LOG_ENABLED
1098	if (enmEvent == RTPOWEREVENT_SUSPEND)
1099	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1100	else
1101	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1102	#endif
1103
1104	if (enmEvent == RTPOWEREVENT_SUSPEND)
1105	ASMAtomicWriteBool(&g_HvmR0.fSuspended, true);
1106
1107	if (g_HvmR0.fEnabled)
1108	{
1109	int rc;
1110	HMR0FIRSTRC FirstRc;
1111	hmR0FirstRcInit(&FirstRc);
1112
1113	if (enmEvent == RTPOWEREVENT_SUSPEND)
1114	{
1115	if (g_HvmR0.fGlobalInit)
1116	{
1117	/* Turn off VT-x or AMD-V on all CPUs. */
1118	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL, &FirstRc);
1119	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1120	}
1121	/* else nothing to do here for the local init case */
1122	}
1123	else
1124	{
1125	/* Reinit the CPUs from scratch as the suspend state might have
1126	messed with the MSRs. (lousy BIOSes as usual) */
1127	if (g_HvmR0.vmx.fSupported)
1128	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1129	else
1130	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1131	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1132	if (RT_SUCCESS(rc))
1133	rc = hmR0FirstRcGetStatus(&FirstRc);
1134	#ifdef LOG_ENABLED
1135	if (RT_FAILURE(rc))
1136	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1137	#endif
1138	if (g_HvmR0.fGlobalInit)
1139	{
1140	/* Turn VT-x or AMD-V back on on all CPUs. */
1141	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL, &FirstRc /* output ignored */);
1142	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1143	}
1144	/* else nothing to do here for the local init case */
1145	}
1146	}
1147
1148	if (enmEvent == RTPOWEREVENT_RESUME)
1149	ASMAtomicWriteBool(&g_HvmR0.fSuspended, false);
1150	}
1151
1152
1153	/**
1154	* Does Ring-0 per VM HM initialization.
1155	*
1156	* This will copy HM global into the VM structure and call the CPU specific
1157	* init routine which will allocate resources for each virtual CPU and such.
1158	*
1159	* @returns VBox status code.
1160	* @param pVM The VM to operate on.
1161	*/
1162	VMMR0DECL(int) HWACCMR0InitVM(PVM pVM)
1163	{
1164	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1165
1166	#ifdef LOG_ENABLED
1167	SUPR0Printf("HWACCMR0InitVM: %p\n", pVM);
1168	#endif
1169
1170	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
1171	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1172	return VERR_HWACCM_SUSPEND_PENDING;
1173
1174	/*
1175	* Copy globals to the VM structure.
1176	*/
1177	pVM->hwaccm.s.vmx.fSupported = g_HvmR0.vmx.fSupported;
1178	pVM->hwaccm.s.svm.fSupported = g_HvmR0.svm.fSupported;
1179
1180	pVM->hwaccm.s.vmx.fUsePreemptTimer = g_HvmR0.vmx.fUsePreemptTimer;
1181	pVM->hwaccm.s.vmx.cPreemptTimerShift = g_HvmR0.vmx.cPreemptTimerShift;
1182	pVM->hwaccm.s.vmx.msr.feature_ctrl = g_HvmR0.vmx.msr.feature_ctrl;
1183	pVM->hwaccm.s.vmx.hostCR4 = g_HvmR0.vmx.hostCR4;
1184	pVM->hwaccm.s.vmx.hostEFER = g_HvmR0.vmx.hostEFER;
1185	pVM->hwaccm.s.vmx.msr.vmx_basic_info = g_HvmR0.vmx.msr.vmx_basic_info;
1186	pVM->hwaccm.s.vmx.msr.vmx_pin_ctls = g_HvmR0.vmx.msr.vmx_pin_ctls;
1187	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls = g_HvmR0.vmx.msr.vmx_proc_ctls;
1188	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2 = g_HvmR0.vmx.msr.vmx_proc_ctls2;
1189	pVM->hwaccm.s.vmx.msr.vmx_exit = g_HvmR0.vmx.msr.vmx_exit;
1190	pVM->hwaccm.s.vmx.msr.vmx_entry = g_HvmR0.vmx.msr.vmx_entry;
1191	pVM->hwaccm.s.vmx.msr.vmx_misc = g_HvmR0.vmx.msr.vmx_misc;
1192	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0 = g_HvmR0.vmx.msr.vmx_cr0_fixed0;
1193	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1 = g_HvmR0.vmx.msr.vmx_cr0_fixed1;
1194	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0 = g_HvmR0.vmx.msr.vmx_cr4_fixed0;
1195	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1 = g_HvmR0.vmx.msr.vmx_cr4_fixed1;
1196	pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum = g_HvmR0.vmx.msr.vmx_vmcs_enum;
1197	pVM->hwaccm.s.vmx.msr.vmx_eptcaps = g_HvmR0.vmx.msr.vmx_eptcaps;
1198	pVM->hwaccm.s.svm.msrHWCR = g_HvmR0.svm.msrHWCR;
1199	pVM->hwaccm.s.svm.u32Rev = g_HvmR0.svm.u32Rev;
1200	pVM->hwaccm.s.svm.u32Features = g_HvmR0.svm.u32Features;
1201	pVM->hwaccm.s.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureECX;
1202	pVM->hwaccm.s.cpuid.u32AMDFeatureEDX = g_HvmR0.cpuid.u32AMDFeatureEDX;
1203	pVM->hwaccm.s.lLastError = g_HvmR0.lLastError;
1204
1205	pVM->hwaccm.s.uMaxASID = g_HvmR0.uMaxASID;
1206
1207
1208	if (!pVM->hwaccm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1209	{
1210	pVM->hwaccm.s.cMaxResumeLoops = 1024;
1211	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1212	if (RTThreadPreemptIsPendingTrusty())
1213	pVM->hwaccm.s.cMaxResumeLoops = 8192;
1214	#endif
1215	}
1216
1217	/*
1218	* Initialize some per CPU fields.
1219	*/
1220	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1221	{
1222	PVMCPU pVCpu = &pVM->aCpus[i];
1223
1224	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1225
1226	/* Invalidate the last cpu we were running on. */
1227	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
1228
1229	/* we'll aways increment this the first time (host uses ASID 0) */
1230	pVCpu->hwaccm.s.uCurrentASID = 0;
1231	}
1232
1233	/*
1234	* Call the hardware specific initialization method.
1235	*
1236	* Note! The fInUse handling here isn't correct as we can we can be
1237	* rescheduled to a different cpu, but the fInUse case is mostly for
1238	* debugging... Disabling preemption isn't an option when allocating
1239	* memory, so we'll let it slip for now.
1240	*/
1241	RTCCUINTREG fFlags = ASMIntDisableFlags();
1242	PHMGLOBLCPUINFO pCpu = HWACCMR0GetCurrentCpu();
1243	ASMAtomicWriteBool(&pCpu->fInUse, true);
1244	ASMSetFlags(fFlags);
1245
1246	int rc = g_HvmR0.pfnInitVM(pVM);
1247
1248	ASMAtomicWriteBool(&pCpu->fInUse, false);
1249	return rc;
1250	}
1251
1252
1253	/**
1254	* Does Ring-0 per VM HM termination.
1255	*
1256	* @returns VBox status code.
1257	* @param pVM The VM to operate on.
1258	*/
1259	VMMR0DECL(int) HWACCMR0TermVM(PVM pVM)
1260	{
1261	Log(("HWACCMR0TermVM: %p\n", pVM));
1262	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1263
1264	/* Make sure we don't touch hm after we've disabled hwaccm in preparation
1265	of a suspend. */
1266	/** @todo r=bird: This cannot be right, the termination functions are
1267	* just freeing memory and resetting pVM/pVCpu members...
1268	* ==> memory leak. */
1269	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1270
1271	/*
1272	* Call the hardware specific method.
1273	*
1274	* Note! Not correct as we can be rescheduled to a different cpu, but the
1275	* fInUse case is mostly for debugging.
1276	*/
1277	RTCCUINTREG fFlags = ASMIntDisableFlags();
1278	PHMGLOBLCPUINFO pCpu = HWACCMR0GetCurrentCpu();
1279	ASMAtomicWriteBool(&pCpu->fInUse, true);
1280	ASMSetFlags(fFlags);
1281
1282	int rc = g_HvmR0.pfnTermVM(pVM);
1283
1284	ASMAtomicWriteBool(&pCpu->fInUse, false);
1285	return rc;
1286	}
1287
1288
1289	/**
1290	* Sets up a VT-x or AMD-V session.
1291	*
1292	* This is mostly about setting up the hardware VM state.
1293	*
1294	* @returns VBox status code.
1295	* @param pVM The VM to operate on.
1296	*/
1297	VMMR0DECL(int) HWACCMR0SetupVM(PVM pVM)
1298	{
1299	Log(("HWACCMR0SetupVM: %p\n", pVM));
1300	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1301
1302	/* Make sure we don't touch hwaccm after we've disabled hwaccm in
1303	preparation of a suspend. */
1304	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1305
1306
1307	/*
1308	* Call the hardware specific setup VM method. This requires the CPU to be
1309	* enabled for AMD-V/VT-x and preemption to be prevented.
1310	*/
1311	RTCCUINTREG fFlags = ASMIntDisableFlags();
1312	RTCPUID idCpu = RTMpCpuId();
1313	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1314	ASMAtomicWriteBool(&pCpu->fInUse, true);
1315
1316	/* On first entry we'll sync everything. */
1317	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1318	pVM->aCpus[i].hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1319
1320	/* Enable VT-x or AMD-V if local init is required. */
1321	int rc;
1322	if (!g_HvmR0.fGlobalInit)
1323	{
1324	rc = hmR0EnableCpu(pVM, idCpu);
1325	AssertReturnStmt(RT_SUCCESS_NP(rc), ASMSetFlags(fFlags), rc);
1326	}
1327
1328	/* Setup VT-x or AMD-V. */
1329	rc = g_HvmR0.pfnSetupVM(pVM);
1330
1331	/* Disable VT-x or AMD-V if local init was done before. */
1332	if (!g_HvmR0.fGlobalInit)
1333	{
1334	int rc2 = hmR0DisableCpu(idCpu);
1335	AssertRC(rc2);
1336	}
1337
1338	ASMAtomicWriteBool(&pCpu->fInUse, false);
1339	ASMSetFlags(fFlags);
1340
1341	return rc;
1342	}
1343
1344
1345	/**
1346	* Enters the VT-x or AMD-V session
1347	*
1348	* @returns VBox status code.
1349	* @param pVM The VM to operate on.
1350	* @param pVCpu VMCPU handle.
1351	*
1352	* @remarks This is called with preemption disabled.
1353	*/
1354	VMMR0DECL(int) HWACCMR0Enter(PVM pVM, PVMCPU pVCpu)
1355	{
1356	RTCPUID idCpu = RTMpCpuId();
1357	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1358
1359	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1360	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1361	ASMAtomicWriteBool(&pCpu->fInUse, true);
1362
1363	AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == NIL_RTCPUID, ("%d", (int)pVCpu->hwaccm.s.idEnteredCpu));
1364	pVCpu->hwaccm.s.idEnteredCpu = idCpu;
1365
1366	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1367
1368	/* Always load the guest's FPU/XMM state on-demand. */
1369	CPUMDeactivateGuestFPUState(pVCpu);
1370
1371	/* Always load the guest's debug state on-demand. */
1372	CPUMDeactivateGuestDebugState(pVCpu);
1373
1374	/* Always reload the host context and the guest's CR0 register. (!!!!) */
1375	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0 \| HWACCM_CHANGED_HOST_CONTEXT;
1376
1377	/* Setup the register and mask according to the current execution mode. */
1378	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1379	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFFFFFFFFFF);
1380	else
1381	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFF);
1382
1383	/* Enable VT-x or AMD-V if local init is required, or enable if it's a
1384	freshly onlined CPU. */
1385	int rc;
1386	if ( !pCpu->fConfigured
1387	\|\| !g_HvmR0.fGlobalInit)
1388	{
1389	rc = hmR0EnableCpu(pVM, idCpu);
1390	AssertRCReturn(rc, rc);
1391	}
1392
1393	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1394	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1395	#endif
1396
1397	rc = g_HvmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1398	AssertRC(rc);
1399	/* We must save the host context here (VT-x) as we might be rescheduled on
1400	a different cpu after a long jump back to ring 3. */
1401	rc \|= g_HvmR0.pfnSaveHostState(pVM, pVCpu);
1402	AssertRC(rc);
1403	rc \|= g_HvmR0.pfnLoadGuestState(pVM, pVCpu, pCtx);
1404	AssertRC(rc);
1405
1406	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1407	if (fStartedSet)
1408	PGMRZDynMapReleaseAutoSet(pVCpu);
1409	#endif
1410
1411	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
1412	and ring-3 calls. */
1413	if (RT_FAILURE(rc))
1414	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1415	return rc;
1416	}
1417
1418
1419	/**
1420	* Leaves the VT-x or AMD-V session
1421	*
1422	* @returns VBox status code.
1423	* @param pVM The VM to operate on.
1424	* @param pVCpu VMCPU handle.
1425	*
1426	* @remarks Called with preemption disabled just like HWACCMR0Enter, our
1427	* counterpart.
1428	*/
1429	VMMR0DECL(int) HWACCMR0Leave(PVM pVM, PVMCPU pVCpu)
1430	{
1431	int rc;
1432	RTCPUID idCpu = RTMpCpuId();
1433	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1434	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1435
1436	/** @todo r=bird: This can't be entirely right? */
1437	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1438
1439	/*
1440	* Save the guest FPU and XMM state if necessary.
1441	*
1442	* Note! It's rather tricky with longjmps done by e.g. Log statements or
1443	* the page fault handler. We must restore the host FPU here to make
1444	* absolutely sure we don't leave the guest FPU state active or trash
1445	* somebody else's FPU state.
1446	*/
1447	if (CPUMIsGuestFPUStateActive(pVCpu))
1448	{
1449	Log2(("CPUMR0SaveGuestFPU\n"));
1450	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
1451
1452	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1453	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1454	}
1455
1456	rc = g_HvmR0.pfnLeaveSession(pVM, pVCpu, pCtx);
1457
1458	/* We don't pass on invlpg information to the recompiler for nested paging
1459	guests, so we must make sure the recompiler flushes its TLB the next
1460	time it executes code. */
1461	if ( pVM->hwaccm.s.fNestedPaging
1462	&& CPUMIsGuestInPagedProtectedModeEx(pCtx))
1463	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
1464
1465	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
1466	and ring-3 calls. */
1467	#ifdef RT_STRICT
1468	if (RT_UNLIKELY( pVCpu->hwaccm.s.idEnteredCpu != idCpu
1469	&& RT_FAILURE(rc)))
1470	{
1471	AssertMsgFailed(("Owner is %d, I'm %d", (int)pVCpu->hwaccm.s.idEnteredCpu, (int)idCpu));
1472	rc = VERR_INTERNAL_ERROR;
1473	}
1474	#endif
1475	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1476
1477	/*
1478	* Disable VT-x or AMD-V if local init was done before.
1479	*/
1480	if (!g_HvmR0.fGlobalInit)
1481	{
1482	rc = hmR0DisableCpu(idCpu);
1483	AssertRC(rc);
1484
1485	/* Reset these to force a TLB flush for the next entry. (-> EXPENSIVE) */
1486	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
1487	pVCpu->hwaccm.s.uCurrentASID = 0;
1488	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1489	}
1490
1491	ASMAtomicWriteBool(&pCpu->fInUse, false);
1492	return rc;
1493	}
1494
1495
1496	/**
1497	* Runs guest code in a hardware accelerated VM.
1498	*
1499	* @returns VBox status code.
1500	* @param pVM The VM to operate on.
1501	* @param pVCpu VMCPUD id.
1502	*
1503	* @remarks Called with preemption disabled and after first having called
1504	* HWACCMR0Enter.
1505	*/
1506	VMMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1507	{
1508	#ifdef VBOX_STRICT
1509	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[RTMpCpuId()];
1510	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1511	Assert(pCpu->fConfigured);
1512	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1513	Assert(ASMAtomicReadBool(&pCpu->fInUse) == true);
1514	#endif
1515
1516	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1517	PGMRZDynMapStartAutoSet(pVCpu);
1518	#endif
1519
1520	int rc = g_HvmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1521
1522	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1523	PGMRZDynMapReleaseAutoSet(pVCpu);
1524	#endif
1525	return rc;
1526	}
1527
1528	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1529
1530	/**
1531	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1532	*
1533	* @returns VBox status code.
1534	* @param pVM VM handle.
1535	* @param pVCpu VMCPU handle.
1536	* @param pCtx CPU context
1537	*/
1538	VMMR0DECL(int) HWACCMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1539	{
1540	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFpu64SwitchBack);
1541	if (pVM->hwaccm.s.vmx.fSupported)
1542	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1543	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1544	}
1545
1546
1547	/**
1548	* Save guest debug state (64 bits guest mode & 32 bits host only)
1549	*
1550	* @returns VBox status code.
1551	* @param pVM VM handle.
1552	* @param pVCpu VMCPU handle.
1553	* @param pCtx CPU context
1554	*/
1555	VMMR0DECL(int) HWACCMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1556	{
1557	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDebug64SwitchBack);
1558	if (pVM->hwaccm.s.vmx.fSupported)
1559	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1560	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1561	}
1562
1563
1564	/**
1565	* Test the 32->64 bits switcher
1566	*
1567	* @returns VBox status code.
1568	* @param pVM VM handle.
1569	*/
1570	VMMR0DECL(int) HWACCMR0TestSwitcher3264(PVM pVM)
1571	{
1572	PVMCPU pVCpu = &pVM->aCpus[0];
1573	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1574	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1575	int rc;
1576
1577	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1578	if (pVM->hwaccm.s.vmx.fSupported)
1579	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1580	else
1581	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1582	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1583
1584	return rc;
1585	}
1586
1587	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1588
1589	/**
1590	* Returns suspend status of the host
1591	*
1592	* @returns Suspend pending or not
1593	*/
1594	VMMR0DECL(bool) HWACCMR0SuspendPending(void)
1595	{
1596	return ASMAtomicReadBool(&g_HvmR0.fSuspended);
1597	}
1598
1599
1600	/**
1601	* Returns the cpu structure for the current cpu.
1602	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1603	*
1604	* @returns cpu structure pointer
1605	*/
1606	VMMR0DECL(PHMGLOBLCPUINFO) HWACCMR0GetCurrentCpu(void)
1607	{
1608	RTCPUID idCpu = RTMpCpuId();
1609	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1610	return &g_HvmR0.aCpuInfo[idCpu];
1611	}
1612
1613
1614	/**
1615	* Returns the cpu structure for the current cpu.
1616	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1617	*
1618	* @returns cpu structure pointer
1619	* @param idCpu id of the VCPU
1620	*/
1621	VMMR0DECL(PHMGLOBLCPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu)
1622	{
1623	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1624	return &g_HvmR0.aCpuInfo[idCpu];
1625	}
1626
1627
1628	/**
1629	* Save a pending IO read.
1630	*
1631	* @param pVCpu The VMCPU to operate on.
1632	* @param GCPtrRip Address of IO instruction
1633	* @param GCPtrRipNext Address of the next instruction
1634	* @param uPort Port address
1635	* @param uAndVal And mask for saving the result in eax
1636	* @param cbSize Read size
1637	*/
1638	VMMR0DECL(void) HWACCMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1639	{
1640	pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_PORT_READ;
1641	pVCpu->hwaccm.s.PendingIO.GCPtrRip = GCPtrRip;
1642	pVCpu->hwaccm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1643	pVCpu->hwaccm.s.PendingIO.s.Port.uPort = uPort;
1644	pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal = uAndVal;
1645	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize = cbSize;
1646	return;
1647	}
1648
1649
1650	/**
1651	* Save a pending IO write.
1652	*
1653	* @param pVCpu The VMCPU to operate on.
1654	* @param GCPtrRIP Address of IO instruction
1655	* @param uPort Port address
1656	* @param uAndVal And mask for fetching the result from eax
1657	* @param cbSize Read size
1658	*/
1659	VMMR0DECL(void) HWACCMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1660	{
1661	pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_PORT_WRITE;
1662	pVCpu->hwaccm.s.PendingIO.GCPtrRip = GCPtrRip;
1663	pVCpu->hwaccm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1664	pVCpu->hwaccm.s.PendingIO.s.Port.uPort = uPort;
1665	pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal = uAndVal;
1666	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize = cbSize;
1667	return;
1668	}
1669
1670
1671	/**
1672	* Raw-mode switcher hook - disable VT-x if it's active and the current
1673	* switcher turns off paging.
1674	*
1675	* @returns VBox status code.
1676	* @param pVM VM handle.
1677	* @param pfVTxDisabled VT-x was disabled or not (out).
1678	*/
1679	VMMR0DECL(int) HWACCMR0EnterSwitcher(PVM pVM, bool *pfVTxDisabled)
1680	{
1681	Assert(!(ASMGetFlags() & X86_EFL_IF) \|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1682
1683	*pfVTxDisabled = false;
1684
1685	if ( !g_HvmR0.fEnabled
1686	\|\| !g_HvmR0.vmx.fSupported /* no such issues with AMD-V */
1687	\|\| !g_HvmR0.fGlobalInit /* Local init implies the CPU is currently not in VMX root mode. */)
1688	return VINF_SUCCESS; /* nothing to do */
1689
1690	switch (VMMGetSwitcher(pVM))
1691	{
1692	case VMMSWITCHER_32_TO_32:
1693	case VMMSWITCHER_PAE_TO_PAE:
1694	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1695
1696	case VMMSWITCHER_32_TO_PAE:
1697	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1698	case VMMSWITCHER_AMD64_TO_32:
1699	case VMMSWITCHER_AMD64_TO_PAE:
1700	break; /* unsafe switchers */
1701
1702	default:
1703	AssertFailed();
1704	return VERR_INTERNAL_ERROR;
1705	}
1706
1707	PHMGLOBLCPUINFO pCpu = HWACCMR0GetCurrentCpu();
1708	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_INTERNAL_ERROR);
1709
1710	*pfVTxDisabled = true;
1711	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1712	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1713	return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1714	}
1715
1716
1717	/**
1718	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1719	* switcher turned off paging.
1720	*
1721	* @returns VBox status code.
1722	* @param pVM VM handle.
1723	* @param fVTxDisabled VT-x was disabled or not.
1724	*/
1725	VMMR0DECL(int) HWACCMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1726	{
1727	Assert(!(ASMGetFlags() & X86_EFL_IF));
1728
1729	if (!fVTxDisabled)
1730	return VINF_SUCCESS; /* nothing to do */
1731
1732	Assert(g_HvmR0.fEnabled);
1733	Assert(g_HvmR0.vmx.fSupported);
1734	Assert(g_HvmR0.fGlobalInit);
1735
1736	PHMGLOBLCPUINFO pCpu = HWACCMR0GetCurrentCpu();
1737	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_INTERNAL_ERROR);
1738
1739	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1740	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1741	return VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage);
1742	}
1743
1744	#ifdef VBOX_STRICT
1745
1746	/**
1747	* Dumps a descriptor.
1748	*
1749	* @param pDesc Descriptor to dump.
1750	* @param Sel Selector number.
1751	* @param pszMsg Message to prepend the log entry with.
1752	*/
1753	VMMR0DECL(void) HWACCMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1754	{
1755	/*
1756	* Make variable description string.
1757	*/
1758	static struct
1759	{
1760	unsigned cch;
1761	const char *psz;
1762	} const s_aTypes[32] =
1763	{
1764	# define STRENTRY(str) { sizeof(str) - 1, str }
1765
1766	/* system */
1767	# if HC_ARCH_BITS == 64
1768	STRENTRY("Reserved0 "), /* 0x00 */
1769	STRENTRY("Reserved1 "), /* 0x01 */
1770	STRENTRY("LDT "), /* 0x02 */
1771	STRENTRY("Reserved3 "), /* 0x03 */
1772	STRENTRY("Reserved4 "), /* 0x04 */
1773	STRENTRY("Reserved5 "), /* 0x05 */
1774	STRENTRY("Reserved6 "), /* 0x06 */
1775	STRENTRY("Reserved7 "), /* 0x07 */
1776	STRENTRY("Reserved8 "), /* 0x08 */
1777	STRENTRY("TSS64Avail "), /* 0x09 */
1778	STRENTRY("ReservedA "), /* 0x0a */
1779	STRENTRY("TSS64Busy "), /* 0x0b */
1780	STRENTRY("Call64 "), /* 0x0c */
1781	STRENTRY("ReservedD "), /* 0x0d */
1782	STRENTRY("Int64 "), /* 0x0e */
1783	STRENTRY("Trap64 "), /* 0x0f */
1784	# else
1785	STRENTRY("Reserved0 "), /* 0x00 */
1786	STRENTRY("TSS16Avail "), /* 0x01 */
1787	STRENTRY("LDT "), /* 0x02 */
1788	STRENTRY("TSS16Busy "), /* 0x03 */
1789	STRENTRY("Call16 "), /* 0x04 */
1790	STRENTRY("Task "), /* 0x05 */
1791	STRENTRY("Int16 "), /* 0x06 */
1792	STRENTRY("Trap16 "), /* 0x07 */
1793	STRENTRY("Reserved8 "), /* 0x08 */
1794	STRENTRY("TSS32Avail "), /* 0x09 */
1795	STRENTRY("ReservedA "), /* 0x0a */
1796	STRENTRY("TSS32Busy "), /* 0x0b */
1797	STRENTRY("Call32 "), /* 0x0c */
1798	STRENTRY("ReservedD "), /* 0x0d */
1799	STRENTRY("Int32 "), /* 0x0e */
1800	STRENTRY("Trap32 "), /* 0x0f */
1801	# endif
1802	/* non system */
1803	STRENTRY("DataRO "), /* 0x10 */
1804	STRENTRY("DataRO Accessed "), /* 0x11 */
1805	STRENTRY("DataRW "), /* 0x12 */
1806	STRENTRY("DataRW Accessed "), /* 0x13 */
1807	STRENTRY("DataDownRO "), /* 0x14 */
1808	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1809	STRENTRY("DataDownRW "), /* 0x16 */
1810	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1811	STRENTRY("CodeEO "), /* 0x18 */
1812	STRENTRY("CodeEO Accessed "), /* 0x19 */
1813	STRENTRY("CodeER "), /* 0x1a */
1814	STRENTRY("CodeER Accessed "), /* 0x1b */
1815	STRENTRY("CodeConfEO "), /* 0x1c */
1816	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1817	STRENTRY("CodeConfER "), /* 0x1e */
1818	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1819	# undef SYSENTRY
1820	};
1821	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1822	char szMsg[128];
1823	char *psz = &szMsg[0];
1824	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1825	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1826	psz += s_aTypes[i].cch;
1827
1828	if (pDesc->Gen.u1Present)
1829	ADD_STR(psz, "Present ");
1830	else
1831	ADD_STR(psz, "Not-Present ");
1832	# if HC_ARCH_BITS == 64
1833	if (pDesc->Gen.u1Long)
1834	ADD_STR(psz, "64-bit ");
1835	else
1836	ADD_STR(psz, "Comp ");
1837	# else
1838	if (pDesc->Gen.u1Granularity)
1839	ADD_STR(psz, "Page ");
1840	if (pDesc->Gen.u1DefBig)
1841	ADD_STR(psz, "32-bit ");
1842	else
1843	ADD_STR(psz, "16-bit ");
1844	# endif
1845	# undef ADD_STR
1846	*psz = '\0';
1847
1848	/*
1849	* Limit and Base and format the output.
1850	*/
1851	uint32_t u32Limit = X86DESC_LIMIT(*pDesc);
1852	if (pDesc->Gen.u1Granularity)
1853	u32Limit = u32Limit << PAGE_SHIFT \| PAGE_OFFSET_MASK;
1854
1855	# if HC_ARCH_BITS == 64
1856	uint64_t u32Base = X86DESC64_BASE(*pDesc);
1857
1858	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1859	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1860	# else
1861	uint32_t u32Base = X86DESC_BASE(*pDesc);
1862
1863	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1864	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1865	# endif
1866	}
1867
1868
1869	/**
1870	* Formats a full register dump.
1871	*
1872	* @param pVM The VM to operate on.
1873	* @param pVCpu The VMCPU to operate on.
1874	* @param pCtx The context to format.
1875	*/
1876	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1877	{
1878	/*
1879	* Format the flags.
1880	*/
1881	static struct
1882	{
1883	const char pszSet; const char pszClear; uint32_t fFlag;
1884	} aFlags[] =
1885	{
1886	{ "vip",NULL, X86_EFL_VIP },
1887	{ "vif",NULL, X86_EFL_VIF },
1888	{ "ac", NULL, X86_EFL_AC },
1889	{ "vm", NULL, X86_EFL_VM },
1890	{ "rf", NULL, X86_EFL_RF },
1891	{ "nt", NULL, X86_EFL_NT },
1892	{ "ov", "nv", X86_EFL_OF },
1893	{ "dn", "up", X86_EFL_DF },
1894	{ "ei", "di", X86_EFL_IF },
1895	{ "tf", NULL, X86_EFL_TF },
1896	{ "nt", "pl", X86_EFL_SF },
1897	{ "nz", "zr", X86_EFL_ZF },
1898	{ "ac", "na", X86_EFL_AF },
1899	{ "po", "pe", X86_EFL_PF },
1900	{ "cy", "nc", X86_EFL_CF },
1901	};
1902	char szEFlags[80];
1903	char *psz = szEFlags;
1904	uint32_t efl = pCtx->eflags.u32;
1905	for (unsigned i = 0; i < RT_ELEMENTS(aFlags); i++)
1906	{
1907	const char *pszAdd = aFlags[i].fFlag & efl ? aFlags[i].pszSet : aFlags[i].pszClear;
1908	if (pszAdd)
1909	{
1910	strcpy(psz, pszAdd);
1911	psz += strlen(pszAdd);
1912	*psz++ = ' ';
1913	}
1914	}
1915	psz[-1] = '\0';
1916
1917
1918	/*
1919	* Format the registers.
1920	*/
1921	if (CPUMIsGuestIn64BitCode(pVCpu, CPUMCTX2CORE(pCtx)))
1922	{
1923	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1924	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1925	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1926	"r14=%016RX64 r15=%016RX64\n"
1927	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1928	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1929	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1930	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1931	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1932	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1933	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1934	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1935	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1936	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1937	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1938	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1939	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1940	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1941	,
1942	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1943	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1944	pCtx->r14, pCtx->r15,
1945	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1946	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1947	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1948	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1949	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1950	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1951	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1952	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1953	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1954	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1955	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1956	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1957	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1958	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1959	}
1960	else
1961	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1962	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1963	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1964	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1965	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1966	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1967	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1968	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1969	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1970	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1971	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1972	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1973	,
1974	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1975	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1976	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr[0], pCtx->dr[1],
1977	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr[2], pCtx->dr[3],
1978	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr[4], pCtx->dr[5],
1979	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr[6], pCtx->dr[7],
1980	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0, pCtx->cr2,
1981	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3, pCtx->cr4,
1982	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1983	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1984	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1985	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1986
1987	Log(("FPU:\n"
1988	"FCW=%04x FSW=%04x FTW=%02x\n"
1989	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
1990	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1991	,
1992	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
1993	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsrvd1,
1994	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
1995	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
1996
1997
1998	Log(("MSR:\n"
1999	"EFER =%016RX64\n"
2000	"PAT =%016RX64\n"
2001	"STAR =%016RX64\n"
2002	"CSTAR =%016RX64\n"
2003	"LSTAR =%016RX64\n"
2004	"SFMASK =%016RX64\n"
2005	"KERNELGSBASE =%016RX64\n",
2006	pCtx->msrEFER,
2007	pCtx->msrPAT,
2008	pCtx->msrSTAR,
2009	pCtx->msrCSTAR,
2010	pCtx->msrLSTAR,
2011	pCtx->msrSFMASK,
2012	pCtx->msrKERNELGSBASE));
2013
2014	}
2015
2016	#endif /* VBOX_STRICT */
2017

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp@ 39070

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