HWACCMR0.cpp@ 40806

Last change on this file since 40806 was 40227, checked in by vboxsync, 13 years ago
VMM/VMMR0 SupDrv Solaris/MpNotification: Fix guru meditation/panics when host CPUs are dynamically offline'd/online'd. More flexibility if offline notifications don't fire on the desired CPU.
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1	/* $Id: HWACCMR0.cpp 40227 2012-02-23 11:15:37Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2011 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HWACCM
23	#include <VBox/vmm/hwaccm.h>
24	#include <VBox/vmm/pgm.h>
25	#include "HWACCMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include <VBox/vmm/hwacc_vmx.h>
28	#include <VBox/vmm/hwacc_svm.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mem.h>
36	#include <iprt/memobj.h>
37	#include <iprt/once.h>
38	#include <iprt/param.h>
39	#include <iprt/power.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42	#include <iprt/x86.h>
43	#include "HWVMXR0.h"
44	#include "HWSVMR0.h"
45
46
47	/*******************************************************************************
48	* Internal Functions *
49	*******************************************************************************/
50	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
55	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* This is used to manage the status code of a RTMpOnAll in HM.
63	*/
64	typedef struct HMR0FIRSTRC
65	{
66	/** The status code. */
67	int32_t volatile rc;
68	/** The ID of the CPU reporting the first failure. */
69	RTCPUID volatile idCpu;
70	} HMR0FIRSTRC;
71	/** Pointer to a first return code structure. */
72	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
73
74
75	/*******************************************************************************
76	* Global Variables *
77	*******************************************************************************/
78	/**
79	* Global data.
80	*/
81	static struct
82	{
83	/** Per CPU globals. */
84	HMGLOBLCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
85
86	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
87	* @{ */
88	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHMGLOBLCPUINFO pCpu));
89	DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
90	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
91	DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
92	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
93	DECLR0CALLBACKMEMBER(int, pfnEnableCpu,(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
94	DECLR0CALLBACKMEMBER(int, pfnDisableCpu,(PHMGLOBLCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
95	DECLR0CALLBACKMEMBER(int, pfnInitVM,(PVM pVM));
96	DECLR0CALLBACKMEMBER(int, pfnTermVM,(PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnSetupVM,(PVM pVM));
98	/** @} */
99
100	/** Maximum ASID allowed. */
101	uint32_t uMaxASID;
102
103	/** VT-x data. */
104	struct
105	{
106	/** Set to by us to indicate VMX is supported by the CPU. */
107	bool fSupported;
108	/** Whether we're using SUPR0EnableVTx or not. */
109	bool fUsingSUPR0EnableVTx;
110	/** Whether we're using the preemption timer or not. */
111	bool fUsePreemptTimer;
112	/** The shift mask employed by the VMX-Preemption timer. */
113	uint8_t cPreemptTimerShift;
114
115	/** Host CR4 value (set by ring-0 VMX init) */
116	uint64_t hostCR4;
117
118	/** Host EFER value (set by ring-0 VMX init) */
119	uint64_t hostEFER;
120
121	/** VMX MSR values */
122	struct
123	{
124	uint64_t feature_ctrl;
125	uint64_t vmx_basic_info;
126	VMX_CAPABILITY vmx_pin_ctls;
127	VMX_CAPABILITY vmx_proc_ctls;
128	VMX_CAPABILITY vmx_proc_ctls2;
129	VMX_CAPABILITY vmx_exit;
130	VMX_CAPABILITY vmx_entry;
131	uint64_t vmx_misc;
132	uint64_t vmx_cr0_fixed0;
133	uint64_t vmx_cr0_fixed1;
134	uint64_t vmx_cr4_fixed0;
135	uint64_t vmx_cr4_fixed1;
136	uint64_t vmx_vmcs_enum;
137	uint64_t vmx_eptcaps;
138	} msr;
139	/* Last instruction error */
140	uint32_t ulLastInstrError;
141	} vmx;
142
143	/** AMD-V information. */
144	struct
145	{
146	/* HWCR msr (for diagnostics) */
147	uint64_t msrHWCR;
148
149	/** SVM revision. */
150	uint32_t u32Rev;
151
152	/** SVM feature bits from cpuid 0x8000000a */
153	uint32_t u32Features;
154
155	/** Set by us to indicate SVM is supported by the CPU. */
156	bool fSupported;
157	} svm;
158	/** Saved error from detection */
159	int32_t lLastError;
160
161	struct
162	{
163	uint32_t u32AMDFeatureECX;
164	uint32_t u32AMDFeatureEDX;
165	} cpuid;
166
167	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
168	* enabled and disabled each time it's used to execute guest code. */
169	bool fGlobalInit;
170	/** Indicates whether the host is suspending or not. We'll refuse a few
171	* actions when the host is being suspended to speed up the suspending and
172	* avoid trouble. */
173	volatile bool fSuspended;
174
175	/** Whether we've already initialized all CPUs.
176	* @remarks We could check the EnableAllCpusOnce state, but this is
177	* simpler and hopefully easier to understand. */
178	bool fEnabled;
179	/** Serialize initialization in HWACCMR0EnableAllCpus. */
180	RTONCE EnableAllCpusOnce;
181	} g_HvmR0;
182
183
184
185	/**
186	* Initializes a first return code structure.
187	*
188	* @param pFirstRc The structure to init.
189	*/
190	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
191	{
192	pFirstRc->rc = VINF_SUCCESS;
193	pFirstRc->idCpu = NIL_RTCPUID;
194	}
195
196
197	/**
198	* Try se the status code (success ignored).
199	*
200	* @param pFirstRc The first return code structure.
201	* @param rc The status code.
202	*/
203	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
204	{
205	if ( RT_FAILURE(rc)
206	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
207	pFirstRc->idCpu = RTMpCpuId();
208	}
209
210
211	/**
212	* Get the status code of a first return code structure.
213	*
214	* @returns The status code; VINF_SUCCESS or error status, no informational or
215	* warning errors.
216	* @param pFirstRc The first return code structure.
217	*/
218	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
219	{
220	return pFirstRc->rc;
221	}
222
223
224	#ifdef VBOX_STRICT
225	/**
226	* Get the CPU ID on which the failure status code was reported.
227	*
228	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
229	* @param pFirstRc The first return code structure.
230	*/
231	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
232	{
233	return pFirstRc->idCpu;
234	}
235	#endif /* VBOX_STRICT */
236
237
238	/** @name Dummy callback handlers.
239	* @{ */
240
241	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBLCPUINFO pCpu)
242	{
243	NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
244	return VINF_SUCCESS;
245	}
246
247	static DECLCALLBACK(int) hmR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
248	{
249	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
250	return VINF_SUCCESS;
251	}
252
253	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
254	{
255	NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
256	return VINF_SUCCESS;
257	}
258
259	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBLCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
260	{
261	NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
262	return VINF_SUCCESS;
263	}
264
265	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
266	{
267	NOREF(pVM);
268	return VINF_SUCCESS;
269	}
270
271	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
272	{
273	NOREF(pVM);
274	return VINF_SUCCESS;
275	}
276
277	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
278	{
279	NOREF(pVM);
280	return VINF_SUCCESS;
281	}
282
283	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
284	{
285	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
286	return VINF_SUCCESS;
287	}
288
289	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
290	{
291	NOREF(pVM); NOREF(pVCpu);
292	return VINF_SUCCESS;
293	}
294
295	static DECLCALLBACK(int) hmR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
296	{
297	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
298	return VINF_SUCCESS;
299	}
300
301	/** @} */
302
303
304	/**
305	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
306	* Down at the Rate Specified" erratum.
307	*
308	* Errata names and related steppings:
309	* - BA86 - D0.
310	* - AAX65 - C2.
311	* - AAU65 - C2, K0.
312	* - AAO95 - B1.
313	* - AAT59 - C2.
314	* - AAK139 - D0.
315	* - AAM126 - C0, C1, D0.
316	* - AAN92 - B1.
317	* - AAJ124 - C0, D0.
318	*
319	* - AAP86 - B1.
320	*
321	* Steppings: B1, C0, C1, C2, D0, K0.
322	*
323	* @returns true if subject to it, false if not.
324	*/
325	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
326	{
327	uint32_t u = ASMCpuId_EAX(1);
328	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
329	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
330	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
331	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
332	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
333	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
334	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
335	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
336	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
337	\|\| u == UINT32_C(0x000106A0) /?321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification /
338	\|\| u == UINT32_C(0x000106A1) /?321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification /
339	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
340	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
341	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
342	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
343	)
344	return true;
345	return false;
346	}
347
348
349	/**
350	* Intel specific initialization code.
351	*
352	* @returns VBox status code (will only fail if out of memory).
353	*/
354	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
355	{
356	/*
357	* Check that all the required VT-x features are present.
358	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
359	*/
360	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
361	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
362	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
363	)
364	{
365	/** @todo move this into a separate function. */
366	g_HvmR0.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
367
368	/*
369	* First try use native kernel API for controlling VT-x.
370	* (This is only supported by some Mac OS X kernels atm.)
371	*/
372	int rc = g_HvmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
373	g_HvmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
374	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
375	{
376	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
377	if (RT_SUCCESS(rc))
378	{
379	g_HvmR0.vmx.fSupported = true;
380	rc = SUPR0EnableVTx(false /* fEnable */);
381	AssertRC(rc);
382	}
383	}
384	else
385	{
386	/* We need to check if VT-x has been properly initialized on all
387	CPUs. Some BIOSes do a lousy job. */
388	HMR0FIRSTRC FirstRc;
389	hmR0FirstRcInit(&FirstRc);
390	g_HvmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
391	if (RT_SUCCESS(g_HvmR0.lLastError))
392	g_HvmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
393	}
394	if (RT_SUCCESS(g_HvmR0.lLastError))
395	{
396	/* Reread in case we've changed it. */
397	g_HvmR0.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
398
399	if ( (g_HvmR0.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
400	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
401	{
402	/*
403	* Read all relevant MSR.
404	*/
405	g_HvmR0.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
406	g_HvmR0.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
407	g_HvmR0.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
408	g_HvmR0.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
409	g_HvmR0.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
410	g_HvmR0.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
411	g_HvmR0.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
412	g_HvmR0.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
413	g_HvmR0.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
414	g_HvmR0.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
415	g_HvmR0.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
416	g_HvmR0.vmx.hostCR4 = ASMGetCR4();
417	g_HvmR0.vmx.hostEFER = ASMRdMsr(MSR_K6_EFER);
418	/* VPID 16 bits ASID. */
419	g_HvmR0.uMaxASID = 0x10000; /* exclusive */
420
421	if (g_HvmR0.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
422	{
423	g_HvmR0.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
424	if ( g_HvmR0.vmx.msr.vmx_proc_ctls2.n.allowed1
425	& (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
426	g_HvmR0.vmx.msr.vmx_eptcaps = ASMRdMsr(MSR_IA32_VMX_EPT_CAPS);
427	}
428
429	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
430	{
431	/*
432	* Enter root mode
433	*/
434	RTR0MEMOBJ hScatchMemObj;
435	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, true /* executable R0 mapping */);
436	if (RT_FAILURE(rc))
437	return rc;
438
439	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
440	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
441	ASMMemZeroPage(pvScatchPage);
442
443	/* Set revision dword at the beginning of the structure. */
444	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HvmR0.vmx.msr.vmx_basic_info);
445
446	/* Make sure we don't get rescheduled to another cpu during this probe. */
447	RTCCUINTREG fFlags = ASMIntDisableFlags();
448
449	/*
450	* Check CR4.VMXE
451	*/
452	g_HvmR0.vmx.hostCR4 = ASMGetCR4();
453	if (!(g_HvmR0.vmx.hostCR4 & X86_CR4_VMXE))
454	{
455	/* In theory this bit could be cleared behind our back. Which would cause
456	#UD faults when we try to execute the VMX instructions... */
457	ASMSetCR4(g_HvmR0.vmx.hostCR4 \| X86_CR4_VMXE);
458	}
459
460	/* Enter VMX Root Mode */
461	rc = VMXEnable(HCPhysScratchPage);
462	if (RT_SUCCESS(rc))
463	{
464	g_HvmR0.vmx.fSupported = true;
465	VMXDisable();
466
467	/*
468	* Check for the VMX-Preemption Timer and adjust for the * "VMX-Preemption
469	* Timer Does Not Count Down at the Rate Specified" erratum.
470	*/
471	if ( g_HvmR0.vmx.msr.vmx_pin_ctls.n.allowed1
472	& VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
473	{
474	g_HvmR0.vmx.fUsePreemptTimer = true;
475	g_HvmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HvmR0.vmx.msr.vmx_misc);
476	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
477	g_HvmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
478	}
479	}
480	else
481	{
482	/*
483	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
484	* it will crash the host when we enter raw mode, because:
485	*
486	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
487	* this bit), and
488	* (b) turning off paging causes a #GP (unavoidable when switching
489	* from long to 32 bits mode or 32 bits to PAE).
490	*
491	* They should fix their code, but until they do we simply refuse to run.
492	*/
493	g_HvmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
494	}
495
496	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
497	if it wasn't so before (some software could incorrectly
498	think it's in VMX mode). */
499	ASMSetCR4(g_HvmR0.vmx.hostCR4);
500	ASMSetFlags(fFlags);
501
502	RTR0MemObjFree(hScatchMemObj, false);
503	}
504	}
505	else
506	{
507	AssertFailed(); /* can't hit this case anymore */
508	g_HvmR0.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
509	}
510
511	/*
512	* Install the VT-x methods.
513	*/
514	if (g_HvmR0.vmx.fSupported)
515	{
516	g_HvmR0.pfnEnterSession = VMXR0Enter;
517	g_HvmR0.pfnLeaveSession = VMXR0Leave;
518	g_HvmR0.pfnSaveHostState = VMXR0SaveHostState;
519	g_HvmR0.pfnLoadGuestState = VMXR0LoadGuestState;
520	g_HvmR0.pfnRunGuestCode = VMXR0RunGuestCode;
521	g_HvmR0.pfnEnableCpu = VMXR0EnableCpu;
522	g_HvmR0.pfnDisableCpu = VMXR0DisableCpu;
523	g_HvmR0.pfnInitVM = VMXR0InitVM;
524	g_HvmR0.pfnTermVM = VMXR0TermVM;
525	g_HvmR0.pfnSetupVM = VMXR0SetupVM;
526	}
527	}
528	#ifdef LOG_ENABLED
529	else
530	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HvmR0.lLastError);
531	#endif
532	}
533	else
534	g_HvmR0.lLastError = VERR_VMX_NO_VMX;
535	return VINF_SUCCESS;
536	}
537
538
539	/**
540	* AMD specific initialization code.
541	*/
542	static void hmR0InitAmd(uint32_t u32FeaturesEDX)
543	{
544	/*
545	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
546	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
547	*/
548	if ( (g_HvmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
549	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
550	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
551	)
552	{
553	g_HvmR0.pfnEnterSession = SVMR0Enter;
554	g_HvmR0.pfnLeaveSession = SVMR0Leave;
555	g_HvmR0.pfnSaveHostState = SVMR0SaveHostState;
556	g_HvmR0.pfnLoadGuestState = SVMR0LoadGuestState;
557	g_HvmR0.pfnRunGuestCode = SVMR0RunGuestCode;
558	g_HvmR0.pfnEnableCpu = SVMR0EnableCpu;
559	g_HvmR0.pfnDisableCpu = SVMR0DisableCpu;
560	g_HvmR0.pfnInitVM = SVMR0InitVM;
561	g_HvmR0.pfnTermVM = SVMR0TermVM;
562	g_HvmR0.pfnSetupVM = SVMR0SetupVM;
563
564	/* Query AMD features. */
565	uint32_t u32Dummy;
566	ASMCpuId(0x8000000A, &g_HvmR0.svm.u32Rev, &g_HvmR0.uMaxASID,
567	&u32Dummy, &g_HvmR0.svm.u32Features);
568
569	/*
570	* We need to check if AMD-V has been properly initialized on all CPUs.
571	* Some BIOSes might do a poor job.
572	*/
573	HMR0FIRSTRC FirstRc;
574	hmR0FirstRcInit(&FirstRc);
575	int rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
576	AssertRC(rc);
577	if (RT_SUCCESS(rc))
578	rc = hmR0FirstRcGetStatus(&FirstRc);
579	#ifndef DEBUG_bird
580	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
581	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
582	#endif
583	if (RT_SUCCESS(rc))
584	{
585	/* Read the HWCR msr for diagnostics. */
586	g_HvmR0.svm.msrHWCR = ASMRdMsr(MSR_K8_HWCR);
587	g_HvmR0.svm.fSupported = true;
588	}
589	else
590	g_HvmR0.lLastError = rc;
591	}
592	else
593	g_HvmR0.lLastError = VERR_SVM_NO_SVM;
594	}
595
596
597	/**
598	* Does global Ring-0 HM initialization (at module init).
599	*
600	* @returns VBox status code.
601	*/
602	VMMR0DECL(int) HWACCMR0Init(void)
603	{
604	/*
605	* Initialize the globals.
606	*/
607	g_HvmR0.fEnabled = false;
608	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
609	g_HvmR0.EnableAllCpusOnce = s_OnceInit;
610	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
611	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
612
613	/* Fill in all callbacks with placeholders. */
614	g_HvmR0.pfnEnterSession = hmR0DummyEnter;
615	g_HvmR0.pfnLeaveSession = hmR0DummyLeave;
616	g_HvmR0.pfnSaveHostState = hmR0DummySaveHostState;
617	g_HvmR0.pfnLoadGuestState = hmR0DummyLoadGuestState;
618	g_HvmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
619	g_HvmR0.pfnEnableCpu = hmR0DummyEnableCpu;
620	g_HvmR0.pfnDisableCpu = hmR0DummyDisableCpu;
621	g_HvmR0.pfnInitVM = hmR0DummyInitVM;
622	g_HvmR0.pfnTermVM = hmR0DummyTermVM;
623	g_HvmR0.pfnSetupVM = hmR0DummySetupVM;
624
625	/* Default is global VT-x/AMD-V init */
626	g_HvmR0.fGlobalInit = true;
627
628	/*
629	* Make sure aCpuInfo is big enough for all the CPUs on this system.
630	*/
631	if (RTMpGetArraySize() > RT_ELEMENTS(g_HvmR0.aCpuInfo))
632	{
633	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HvmR0.aCpuInfo)));
634	return VERR_TOO_MANY_CPUS;
635	}
636
637	/*
638	* Check for VT-x and AMD-V capabilities
639	*/
640	int rc;
641	if (ASMHasCpuId())
642	{
643	uint32_t u32FeaturesECX, u32FeaturesEDX;
644	uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
645	uint32_t u32Dummy;
646
647	/* Standard features. */
648	ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
649	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
650
651	/* Query AMD features. */
652	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
653	&g_HvmR0.cpuid.u32AMDFeatureECX,
654	&g_HvmR0.cpuid.u32AMDFeatureEDX);
655
656	/* Go to CPU specific initialization code. */
657	if ( u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
658	&& u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
659	&& u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX)
660	{
661	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
662	if (RT_FAILURE(rc))
663	return rc;
664	}
665	else if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
666	&& u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
667	&& u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX)
668	hmR0InitAmd(u32FeaturesEDX);
669	else
670	g_HvmR0.lLastError = VERR_HWACCM_UNKNOWN_CPU;
671	}
672	else
673	g_HvmR0.lLastError = VERR_HWACCM_NO_CPUID;
674
675	/*
676	* Register notification callbacks that we can use to disable/enable CPUs
677	* when brought offline/online or suspending/resuming.
678	*/
679	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
680	{
681	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
682	AssertRC(rc);
683
684	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
685	AssertRC(rc);
686	}
687
688	/* We return success here because module init shall not fail if HM
689	fails to initialize. */
690	return VINF_SUCCESS;
691	}
692
693
694	/**
695	* Does global Ring-0 HM termination (at module termination).
696	*
697	* @returns VBox status code.
698	*/
699	VMMR0DECL(int) HWACCMR0Term(void)
700	{
701	int rc;
702	if ( g_HvmR0.vmx.fSupported
703	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
704	{
705	/*
706	* Simple if the host OS manages VT-x.
707	*/
708	Assert(g_HvmR0.fGlobalInit);
709	rc = SUPR0EnableVTx(false /* fEnable */);
710
711	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo); iCpu++)
712	{
713	g_HvmR0.aCpuInfo[iCpu].fConfigured = false;
714	Assert(g_HvmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
715	}
716	}
717	else
718	{
719	Assert(!g_HvmR0.vmx.fUsingSUPR0EnableVTx);
720	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
721	{
722	/* Doesn't really matter if this fails. */
723	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
724	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
725	}
726	else
727	rc = VINF_SUCCESS;
728
729	/*
730	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
731	*/
732	if (g_HvmR0.fGlobalInit)
733	{
734	HMR0FIRSTRC FirstRc;
735	hmR0FirstRcInit(&FirstRc);
736	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL, &FirstRc);
737	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
738	if (RT_SUCCESS(rc))
739	{
740	rc = hmR0FirstRcGetStatus(&FirstRc);
741	AssertMsgRC(rc, ("%u: %Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
742	}
743	}
744
745	/*
746	* Free the per-cpu pages used for VT-x and AMD-V.
747	*/
748	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
749	{
750	if (g_HvmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
751	{
752	RTR0MemObjFree(g_HvmR0.aCpuInfo[i].hMemObj, false);
753	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
754	}
755	}
756	}
757	return rc;
758	}
759
760
761	/**
762	* Worker function used by hmR0PowerCallback and HWACCMR0Init to initalize
763	* VT-x on a CPU.
764	*
765	* @param idCpu The identifier for the CPU the function is called on.
766	* @param pvUser1 Pointer to the first RC structure.
767	* @param pvUser2 Ignored.
768	*/
769	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
770	{
771	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
772	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
773	NOREF(pvUser2);
774
775	/*
776	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
777	* Once the lock bit is set, this MSR can no longer be modified.
778	*/
779	uint64_t fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
780	if ( !(fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
781	\|\| ( (fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
782	== MSR_IA32_FEATURE_CONTROL_VMXON ) /* Some BIOSes forget to set the locked bit. */
783	)
784	{
785	/* MSR is not yet locked; we can change it ourselves here */
786	ASMWrMsr(MSR_IA32_FEATURE_CONTROL,
787	g_HvmR0.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
788	fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
789	}
790
791	int rc;
792	if ( (fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
793	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
794	rc = VINF_SUCCESS;
795	else
796	rc = VERR_VMX_MSR_LOCKED_OR_DISABLED;
797
798	hmR0FirstRcSetStatus(pFirstRc, rc);
799	}
800
801
802	/**
803	* Worker function used by hmR0PowerCallback and HWACCMR0Init to initalize
804	* VT-x / AMD-V on a CPU.
805	*
806	* @param idCpu The identifier for the CPU the function is called on.
807	* @param pvUser1 Pointer to the first RC structure.
808	* @param pvUser2 Ignored.
809	*/
810	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
811	{
812	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
813	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
814	NOREF(pvUser2);
815
816	/* Check if SVM is disabled. */
817	int rc;
818	uint64_t fVmCr = ASMRdMsr(MSR_K8_VM_CR);
819	if (!(fVmCr & MSR_K8_VM_CR_SVM_DISABLE))
820	{
821	/* Turn on SVM in the EFER MSR. */
822	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
823	if (fEfer & MSR_K6_EFER_SVME)
824	rc = VERR_SVM_IN_USE;
825	else
826	{
827	ASMWrMsr(MSR_K6_EFER, fEfer \| MSR_K6_EFER_SVME);
828
829	/* Paranoia. */
830	fEfer = ASMRdMsr(MSR_K6_EFER);
831	if (fEfer & MSR_K6_EFER_SVME)
832	{
833	/* Restore previous value. */
834	ASMWrMsr(MSR_K6_EFER, fEfer & ~MSR_K6_EFER_SVME);
835	rc = VINF_SUCCESS;
836	}
837	else
838	rc = VERR_SVM_ILLEGAL_EFER_MSR;
839	}
840	}
841	else
842	rc = VERR_SVM_DISABLED;
843
844	hmR0FirstRcSetStatus(pFirstRc, rc);
845	}
846
847
848
849	/**
850	* Disable VT-x or AMD-V on the current CPU
851	*
852	* @returns VBox status code.
853	* @param pVM VM handle (can be 0!)
854	* @param idCpu The identifier for the CPU the function is called on.
855	*/
856	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
857	{
858	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
859
860	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
861	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
862	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
863	Assert(!pCpu->fConfigured);
864	Assert(!g_HvmR0.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
865
866	pCpu->idCpu = idCpu;
867
868	/* Make sure we start with a clean TLB. */
869	pCpu->fFlushTLB = true;
870
871	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
872	pCpu->cTLBFlushes = 0;
873
874	/* Should never happen */
875	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
876
877	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
878	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
879
880	int rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage);
881	AssertRC(rc);
882	if (RT_SUCCESS(rc))
883	pCpu->fConfigured = true;
884
885	return rc;
886	}
887
888
889	/**
890	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
891	* is to be called on the target cpus.
892	*
893	* @param idCpu The identifier for the CPU the function is called on.
894	* @param pvUser1 The 1st user argument.
895	* @param pvUser2 The 2nd user argument.
896	*/
897	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
898	{
899	PVM pVM = (PVM)pvUser1; /* can be NULL! */
900	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
901	AssertReturnVoid(g_HvmR0.fGlobalInit);
902	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
903	}
904
905
906	/**
907	* RTOnce callback employed by HWACCMR0EnableAllCpus.
908	*
909	* @returns VBox status code
910	* @param pvUser The VM handle.
911	* @param pvUserIgnore NULL, ignored.
912	*/
913	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void pvUser, void pvUserIgnore)
914	{
915	PVM pVM = (PVM)pvUser;
916	NOREF(pvUserIgnore);
917
918	/*
919	* Indicate that we've initialized.
920	*
921	* Note! There is a potential race between this function and the suspend
922	* notification. Kind of unlikely though, so ignored for now.
923	*/
924	AssertReturn(!g_HvmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
925	ASMAtomicWriteBool(&g_HvmR0.fEnabled, true);
926
927	/*
928	* The global init variable is set by the first VM.
929	*/
930	g_HvmR0.fGlobalInit = pVM->hwaccm.s.fGlobalInit;
931
932	int rc;
933	if ( g_HvmR0.vmx.fSupported
934	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
935	{
936	/*
937	* Global VT-x initialization API (only darwin for now).
938	*/
939	rc = SUPR0EnableVTx(true /* fEnable */);
940	if (RT_SUCCESS(rc))
941	{
942	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo); iCpu++)
943	{
944	g_HvmR0.aCpuInfo[iCpu].fConfigured = true;
945	Assert(g_HvmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
946	}
947
948	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
949	g_HvmR0.fGlobalInit = pVM->hwaccm.s.fGlobalInit = true;
950	}
951	else
952	AssertMsgFailed(("HWACCMR0EnableAllCpus/SUPR0EnableVTx: rc=%Rrc\n", rc));
953	}
954	else
955	{
956	/*
957	* We're doing the job ourselves.
958	*/
959	/* Allocate one page per cpu for the global vt-x and amd-v pages */
960	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
961	{
962	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
963
964	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
965	{
966	rc = RTR0MemObjAllocCont(&g_HvmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, true /* executable R0 mapping */);
967	AssertLogRelRCReturn(rc, rc);
968
969	void *pvR0 = RTR0MemObjAddress(g_HvmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
970	ASMMemZeroPage(pvR0);
971	}
972	g_HvmR0.aCpuInfo[i].fConfigured = false;
973	}
974
975	if (g_HvmR0.fGlobalInit)
976	{
977	/* First time, so initialize each cpu/core. */
978	HMR0FIRSTRC FirstRc;
979	hmR0FirstRcInit(&FirstRc);
980	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
981	if (RT_SUCCESS(rc))
982	rc = hmR0FirstRcGetStatus(&FirstRc);
983	AssertMsgRC(rc, ("HWACCMR0EnableAllCpus failed for cpu %d with rc=%d\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
984	}
985	else
986	rc = VINF_SUCCESS;
987	}
988
989	return rc;
990	}
991
992
993	/**
994	* Sets up HWACCM on all cpus.
995	*
996	* @returns VBox status code.
997	* @param pVM The VM handle.
998	*/
999	VMMR0DECL(int) HWACCMR0EnableAllCpus(PVM pVM)
1000	{
1001	/* Make sure we don't touch hwaccm after we've disabled hwaccm in
1002	preparation of a suspend. */
1003	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1004	return VERR_HWACCM_SUSPEND_PENDING;
1005
1006	return RTOnce(&g_HvmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM, NULL);
1007	}
1008
1009
1010	/**
1011	* Disable VT-x or AMD-V on the current CPU
1012	*
1013	* @returns VBox status code.
1014	* @param idCpu The identifier for the CPU the function is called on.
1015	*/
1016	static int hmR0DisableCpu(RTCPUID idCpu)
1017	{
1018	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1019
1020	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1021	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
1022	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1023	Assert(!g_HvmR0.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
1024	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1025
1026	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1027	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1028
1029	int rc;
1030	if (pCpu->fConfigured)
1031	{
1032	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1033	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1034	if (idCpu == RTMpCpuId())
1035	{
1036	rc = g_HvmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1037	AssertRC(rc);
1038	}
1039	else
1040	{
1041	pCpu->fIgnoreAMDVInUseError = true;
1042	rc = VINF_SUCCESS;
1043	}
1044
1045	pCpu->fConfigured = false;
1046	}
1047	else
1048	rc = VINF_SUCCESS; /* nothing to do */
1049
1050	pCpu->uCurrentASID = 0;
1051	return rc;
1052	}
1053
1054
1055	/**
1056	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
1057	* is to be called on the target cpus.
1058	*
1059	* @param idCpu The identifier for the CPU the function is called on.
1060	* @param pvUser1 The 1st user argument.
1061	* @param pvUser2 The 2nd user argument.
1062	*/
1063	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1064	{
1065	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1066	AssertReturnVoid(g_HvmR0.fGlobalInit);
1067	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1068	}
1069
1070
1071	/**
1072	* Callback function invoked when a cpu goes online or offline.
1073	*
1074	* @param enmEvent The Mp event.
1075	* @param idCpu The identifier for the CPU the function is called on.
1076	* @param pvData Opaque data (PVM pointer).
1077	*/
1078	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1079	{
1080	NOREF(pvData);
1081
1082	/*
1083	* We only care about uninitializing a CPU that is going offline. When a
1084	* CPU comes online, the initialization is done lazily in HWACCMR0Enter().
1085	*/
1086	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1087	switch (enmEvent)
1088	{
1089	case RTMPEVENT_OFFLINE:
1090	{
1091	int rc = hmR0DisableCpu(idCpu);
1092	AssertRC(rc);
1093	break;
1094	}
1095
1096	default:
1097	break;
1098	}
1099	}
1100
1101
1102	/**
1103	* Called whenever a system power state change occurs.
1104	*
1105	* @param enmEvent Power event
1106	* @param pvUser User argument
1107	*/
1108	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1109	{
1110	NOREF(pvUser);
1111	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1112
1113	#ifdef LOG_ENABLED
1114	if (enmEvent == RTPOWEREVENT_SUSPEND)
1115	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1116	else
1117	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1118	#endif
1119
1120	if (enmEvent == RTPOWEREVENT_SUSPEND)
1121	ASMAtomicWriteBool(&g_HvmR0.fSuspended, true);
1122
1123	if (g_HvmR0.fEnabled)
1124	{
1125	int rc;
1126	HMR0FIRSTRC FirstRc;
1127	hmR0FirstRcInit(&FirstRc);
1128
1129	if (enmEvent == RTPOWEREVENT_SUSPEND)
1130	{
1131	if (g_HvmR0.fGlobalInit)
1132	{
1133	/* Turn off VT-x or AMD-V on all CPUs. */
1134	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL, &FirstRc);
1135	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1136	}
1137	/* else nothing to do here for the local init case */
1138	}
1139	else
1140	{
1141	/* Reinit the CPUs from scratch as the suspend state might have
1142	messed with the MSRs. (lousy BIOSes as usual) */
1143	if (g_HvmR0.vmx.fSupported)
1144	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1145	else
1146	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1147	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1148	if (RT_SUCCESS(rc))
1149	rc = hmR0FirstRcGetStatus(&FirstRc);
1150	#ifdef LOG_ENABLED
1151	if (RT_FAILURE(rc))
1152	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1153	#endif
1154	if (g_HvmR0.fGlobalInit)
1155	{
1156	/* Turn VT-x or AMD-V back on on all CPUs. */
1157	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL, &FirstRc /* output ignored */);
1158	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1159	}
1160	/* else nothing to do here for the local init case */
1161	}
1162	}
1163
1164	if (enmEvent == RTPOWEREVENT_RESUME)
1165	ASMAtomicWriteBool(&g_HvmR0.fSuspended, false);
1166	}
1167
1168
1169	/**
1170	* Does Ring-0 per VM HM initialization.
1171	*
1172	* This will copy HM global into the VM structure and call the CPU specific
1173	* init routine which will allocate resources for each virtual CPU and such.
1174	*
1175	* @returns VBox status code.
1176	* @param pVM The VM to operate on.
1177	*/
1178	VMMR0DECL(int) HWACCMR0InitVM(PVM pVM)
1179	{
1180	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1181
1182	#ifdef LOG_ENABLED
1183	SUPR0Printf("HWACCMR0InitVM: %p\n", pVM);
1184	#endif
1185
1186	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
1187	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1188	return VERR_HWACCM_SUSPEND_PENDING;
1189
1190	/*
1191	* Copy globals to the VM structure.
1192	*/
1193	pVM->hwaccm.s.vmx.fSupported = g_HvmR0.vmx.fSupported;
1194	pVM->hwaccm.s.svm.fSupported = g_HvmR0.svm.fSupported;
1195
1196	pVM->hwaccm.s.vmx.fUsePreemptTimer = g_HvmR0.vmx.fUsePreemptTimer;
1197	pVM->hwaccm.s.vmx.cPreemptTimerShift = g_HvmR0.vmx.cPreemptTimerShift;
1198	pVM->hwaccm.s.vmx.msr.feature_ctrl = g_HvmR0.vmx.msr.feature_ctrl;
1199	pVM->hwaccm.s.vmx.hostCR4 = g_HvmR0.vmx.hostCR4;
1200	pVM->hwaccm.s.vmx.hostEFER = g_HvmR0.vmx.hostEFER;
1201	pVM->hwaccm.s.vmx.msr.vmx_basic_info = g_HvmR0.vmx.msr.vmx_basic_info;
1202	pVM->hwaccm.s.vmx.msr.vmx_pin_ctls = g_HvmR0.vmx.msr.vmx_pin_ctls;
1203	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls = g_HvmR0.vmx.msr.vmx_proc_ctls;
1204	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2 = g_HvmR0.vmx.msr.vmx_proc_ctls2;
1205	pVM->hwaccm.s.vmx.msr.vmx_exit = g_HvmR0.vmx.msr.vmx_exit;
1206	pVM->hwaccm.s.vmx.msr.vmx_entry = g_HvmR0.vmx.msr.vmx_entry;
1207	pVM->hwaccm.s.vmx.msr.vmx_misc = g_HvmR0.vmx.msr.vmx_misc;
1208	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0 = g_HvmR0.vmx.msr.vmx_cr0_fixed0;
1209	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1 = g_HvmR0.vmx.msr.vmx_cr0_fixed1;
1210	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0 = g_HvmR0.vmx.msr.vmx_cr4_fixed0;
1211	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1 = g_HvmR0.vmx.msr.vmx_cr4_fixed1;
1212	pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum = g_HvmR0.vmx.msr.vmx_vmcs_enum;
1213	pVM->hwaccm.s.vmx.msr.vmx_eptcaps = g_HvmR0.vmx.msr.vmx_eptcaps;
1214	pVM->hwaccm.s.svm.msrHWCR = g_HvmR0.svm.msrHWCR;
1215	pVM->hwaccm.s.svm.u32Rev = g_HvmR0.svm.u32Rev;
1216	pVM->hwaccm.s.svm.u32Features = g_HvmR0.svm.u32Features;
1217	pVM->hwaccm.s.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureECX;
1218	pVM->hwaccm.s.cpuid.u32AMDFeatureEDX = g_HvmR0.cpuid.u32AMDFeatureEDX;
1219	pVM->hwaccm.s.lLastError = g_HvmR0.lLastError;
1220
1221	pVM->hwaccm.s.uMaxASID = g_HvmR0.uMaxASID;
1222
1223
1224	if (!pVM->hwaccm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1225	{
1226	pVM->hwaccm.s.cMaxResumeLoops = 1024;
1227	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1228	if (RTThreadPreemptIsPendingTrusty())
1229	pVM->hwaccm.s.cMaxResumeLoops = 8192;
1230	#endif
1231	}
1232
1233	/*
1234	* Initialize some per CPU fields.
1235	*/
1236	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1237	{
1238	PVMCPU pVCpu = &pVM->aCpus[i];
1239
1240	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1241
1242	/* Invalidate the last cpu we were running on. */
1243	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
1244
1245	/* we'll aways increment this the first time (host uses ASID 0) */
1246	pVCpu->hwaccm.s.uCurrentASID = 0;
1247	}
1248
1249	/*
1250	* Call the hardware specific initialization method.
1251	*
1252	* Note! The fInUse handling here isn't correct as we can we can be
1253	* rescheduled to a different cpu, but the fInUse case is mostly for
1254	* debugging... Disabling preemption isn't an option when allocating
1255	* memory, so we'll let it slip for now.
1256	*/
1257	RTCCUINTREG fFlags = ASMIntDisableFlags();
1258	PHMGLOBLCPUINFO pCpu = HWACCMR0GetCurrentCpu();
1259	ASMAtomicWriteBool(&pCpu->fInUse, true);
1260	ASMSetFlags(fFlags);
1261
1262	int rc = g_HvmR0.pfnInitVM(pVM);
1263
1264	ASMAtomicWriteBool(&pCpu->fInUse, false);
1265	return rc;
1266	}
1267
1268
1269	/**
1270	* Does Ring-0 per VM HM termination.
1271	*
1272	* @returns VBox status code.
1273	* @param pVM The VM to operate on.
1274	*/
1275	VMMR0DECL(int) HWACCMR0TermVM(PVM pVM)
1276	{
1277	Log(("HWACCMR0TermVM: %p\n", pVM));
1278	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1279
1280	/* Make sure we don't touch hm after we've disabled hwaccm in preparation
1281	of a suspend. */
1282	/** @todo r=bird: This cannot be right, the termination functions are
1283	* just freeing memory and resetting pVM/pVCpu members...
1284	* ==> memory leak. */
1285	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1286
1287	/*
1288	* Call the hardware specific method.
1289	*
1290	* Note! Not correct as we can be rescheduled to a different cpu, but the
1291	* fInUse case is mostly for debugging.
1292	*/
1293	RTCCUINTREG fFlags = ASMIntDisableFlags();
1294	PHMGLOBLCPUINFO pCpu = HWACCMR0GetCurrentCpu();
1295	ASMAtomicWriteBool(&pCpu->fInUse, true);
1296	ASMSetFlags(fFlags);
1297
1298	int rc = g_HvmR0.pfnTermVM(pVM);
1299
1300	ASMAtomicWriteBool(&pCpu->fInUse, false);
1301	return rc;
1302	}
1303
1304
1305	/**
1306	* Sets up a VT-x or AMD-V session.
1307	*
1308	* This is mostly about setting up the hardware VM state.
1309	*
1310	* @returns VBox status code.
1311	* @param pVM The VM to operate on.
1312	*/
1313	VMMR0DECL(int) HWACCMR0SetupVM(PVM pVM)
1314	{
1315	Log(("HWACCMR0SetupVM: %p\n", pVM));
1316	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1317
1318	/* Make sure we don't touch hwaccm after we've disabled hwaccm in
1319	preparation of a suspend. */
1320	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1321
1322
1323	/*
1324	* Call the hardware specific setup VM method. This requires the CPU to be
1325	* enabled for AMD-V/VT-x and preemption to be prevented.
1326	*/
1327	RTCCUINTREG fFlags = ASMIntDisableFlags();
1328	RTCPUID idCpu = RTMpCpuId();
1329	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1330	ASMAtomicWriteBool(&pCpu->fInUse, true);
1331
1332	/* On first entry we'll sync everything. */
1333	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1334	pVM->aCpus[i].hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1335
1336	/* Enable VT-x or AMD-V if local init is required. */
1337	int rc;
1338	if (!g_HvmR0.fGlobalInit)
1339	{
1340	rc = hmR0EnableCpu(pVM, idCpu);
1341	AssertReturnStmt(RT_SUCCESS_NP(rc), ASMSetFlags(fFlags), rc);
1342	}
1343
1344	/* Setup VT-x or AMD-V. */
1345	rc = g_HvmR0.pfnSetupVM(pVM);
1346
1347	/* Disable VT-x or AMD-V if local init was done before. */
1348	if (!g_HvmR0.fGlobalInit)
1349	{
1350	int rc2 = hmR0DisableCpu(idCpu);
1351	AssertRC(rc2);
1352	}
1353
1354	ASMAtomicWriteBool(&pCpu->fInUse, false);
1355	ASMSetFlags(fFlags);
1356
1357	return rc;
1358	}
1359
1360
1361	/**
1362	* Enters the VT-x or AMD-V session
1363	*
1364	* @returns VBox status code.
1365	* @param pVM The VM to operate on.
1366	* @param pVCpu VMCPU handle.
1367	*
1368	* @remarks This is called with preemption disabled.
1369	*/
1370	VMMR0DECL(int) HWACCMR0Enter(PVM pVM, PVMCPU pVCpu)
1371	{
1372	RTCPUID idCpu = RTMpCpuId();
1373	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1374
1375	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1376	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1377	ASMAtomicWriteBool(&pCpu->fInUse, true);
1378
1379	AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == NIL_RTCPUID, ("%d", (int)pVCpu->hwaccm.s.idEnteredCpu));
1380	pVCpu->hwaccm.s.idEnteredCpu = idCpu;
1381
1382	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1383
1384	/* Always load the guest's FPU/XMM state on-demand. */
1385	CPUMDeactivateGuestFPUState(pVCpu);
1386
1387	/* Always load the guest's debug state on-demand. */
1388	CPUMDeactivateGuestDebugState(pVCpu);
1389
1390	/* Always reload the host context and the guest's CR0 register. (!!!!) */
1391	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0 \| HWACCM_CHANGED_HOST_CONTEXT;
1392
1393	/* Setup the register and mask according to the current execution mode. */
1394	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1395	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFFFFFFFFFF);
1396	else
1397	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFF);
1398
1399	/* Enable VT-x or AMD-V if local init is required, or enable if it's a
1400	freshly onlined CPU. */
1401	int rc;
1402	if ( !pCpu->fConfigured
1403	\|\| !g_HvmR0.fGlobalInit)
1404	{
1405	rc = hmR0EnableCpu(pVM, idCpu);
1406	AssertRCReturn(rc, rc);
1407	}
1408
1409	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1410	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1411	#endif
1412
1413	rc = g_HvmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1414	AssertRC(rc);
1415	/* We must save the host context here (VT-x) as we might be rescheduled on
1416	a different cpu after a long jump back to ring 3. */
1417	rc \|= g_HvmR0.pfnSaveHostState(pVM, pVCpu);
1418	AssertRC(rc);
1419	rc \|= g_HvmR0.pfnLoadGuestState(pVM, pVCpu, pCtx);
1420	AssertRC(rc);
1421
1422	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1423	if (fStartedSet)
1424	PGMRZDynMapReleaseAutoSet(pVCpu);
1425	#endif
1426
1427	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
1428	and ring-3 calls. */
1429	if (RT_FAILURE(rc))
1430	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1431	return rc;
1432	}
1433
1434
1435	/**
1436	* Leaves the VT-x or AMD-V session
1437	*
1438	* @returns VBox status code.
1439	* @param pVM The VM to operate on.
1440	* @param pVCpu VMCPU handle.
1441	*
1442	* @remarks Called with preemption disabled just like HWACCMR0Enter, our
1443	* counterpart.
1444	*/
1445	VMMR0DECL(int) HWACCMR0Leave(PVM pVM, PVMCPU pVCpu)
1446	{
1447	int rc;
1448	RTCPUID idCpu = RTMpCpuId();
1449	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1450	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1451
1452	/** @todo r=bird: This can't be entirely right? */
1453	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1454
1455	/*
1456	* Save the guest FPU and XMM state if necessary.
1457	*
1458	* Note! It's rather tricky with longjmps done by e.g. Log statements or
1459	* the page fault handler. We must restore the host FPU here to make
1460	* absolutely sure we don't leave the guest FPU state active or trash
1461	* somebody else's FPU state.
1462	*/
1463	if (CPUMIsGuestFPUStateActive(pVCpu))
1464	{
1465	Log2(("CPUMR0SaveGuestFPU\n"));
1466	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
1467
1468	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1469	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1470	}
1471
1472	rc = g_HvmR0.pfnLeaveSession(pVM, pVCpu, pCtx);
1473
1474	/* We don't pass on invlpg information to the recompiler for nested paging
1475	guests, so we must make sure the recompiler flushes its TLB the next
1476	time it executes code. */
1477	if ( pVM->hwaccm.s.fNestedPaging
1478	&& CPUMIsGuestInPagedProtectedModeEx(pCtx))
1479	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
1480
1481	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
1482	and ring-3 calls. */
1483	AssertMsgStmt( pVCpu->hwaccm.s.idEnteredCpu == idCpu
1484	\|\| RT_FAILURE_NP(rc),
1485	("Owner is %u, I'm %u", pVCpu->hwaccm.s.idEnteredCpu, idCpu),
1486	rc = VERR_HM_WRONG_CPU_1);
1487	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1488
1489	/*
1490	* Disable VT-x or AMD-V if local init was done before.
1491	*/
1492	if (!g_HvmR0.fGlobalInit)
1493	{
1494	rc = hmR0DisableCpu(idCpu);
1495	AssertRC(rc);
1496
1497	/* Reset these to force a TLB flush for the next entry. (-> EXPENSIVE) */
1498	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
1499	pVCpu->hwaccm.s.uCurrentASID = 0;
1500	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1501	}
1502
1503	ASMAtomicWriteBool(&pCpu->fInUse, false);
1504	return rc;
1505	}
1506
1507
1508	/**
1509	* Runs guest code in a hardware accelerated VM.
1510	*
1511	* @returns VBox status code.
1512	* @param pVM The VM to operate on.
1513	* @param pVCpu VMCPUD id.
1514	*
1515	* @remarks Called with preemption disabled and after first having called
1516	* HWACCMR0Enter.
1517	*/
1518	VMMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1519	{
1520	#ifdef VBOX_STRICT
1521	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[RTMpCpuId()];
1522	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1523	Assert(pCpu->fConfigured);
1524	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1525	Assert(ASMAtomicReadBool(&pCpu->fInUse) == true);
1526	#endif
1527
1528	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1529	PGMRZDynMapStartAutoSet(pVCpu);
1530	#endif
1531
1532	int rc = g_HvmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1533
1534	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1535	PGMRZDynMapReleaseAutoSet(pVCpu);
1536	#endif
1537	return rc;
1538	}
1539
1540	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1541
1542	/**
1543	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1544	*
1545	* @returns VBox status code.
1546	* @param pVM VM handle.
1547	* @param pVCpu VMCPU handle.
1548	* @param pCtx CPU context
1549	*/
1550	VMMR0DECL(int) HWACCMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1551	{
1552	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFpu64SwitchBack);
1553	if (pVM->hwaccm.s.vmx.fSupported)
1554	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1555	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1556	}
1557
1558
1559	/**
1560	* Save guest debug state (64 bits guest mode & 32 bits host only)
1561	*
1562	* @returns VBox status code.
1563	* @param pVM VM handle.
1564	* @param pVCpu VMCPU handle.
1565	* @param pCtx CPU context
1566	*/
1567	VMMR0DECL(int) HWACCMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1568	{
1569	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDebug64SwitchBack);
1570	if (pVM->hwaccm.s.vmx.fSupported)
1571	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1572	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1573	}
1574
1575
1576	/**
1577	* Test the 32->64 bits switcher
1578	*
1579	* @returns VBox status code.
1580	* @param pVM VM handle.
1581	*/
1582	VMMR0DECL(int) HWACCMR0TestSwitcher3264(PVM pVM)
1583	{
1584	PVMCPU pVCpu = &pVM->aCpus[0];
1585	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1586	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1587	int rc;
1588
1589	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1590	if (pVM->hwaccm.s.vmx.fSupported)
1591	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1592	else
1593	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1594	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1595
1596	return rc;
1597	}
1598
1599	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1600
1601	/**
1602	* Returns suspend status of the host
1603	*
1604	* @returns Suspend pending or not
1605	*/
1606	VMMR0DECL(bool) HWACCMR0SuspendPending(void)
1607	{
1608	return ASMAtomicReadBool(&g_HvmR0.fSuspended);
1609	}
1610
1611
1612	/**
1613	* Returns the cpu structure for the current cpu.
1614	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1615	*
1616	* @returns cpu structure pointer
1617	*/
1618	VMMR0DECL(PHMGLOBLCPUINFO) HWACCMR0GetCurrentCpu(void)
1619	{
1620	RTCPUID idCpu = RTMpCpuId();
1621	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1622	return &g_HvmR0.aCpuInfo[idCpu];
1623	}
1624
1625
1626	/**
1627	* Returns the cpu structure for the current cpu.
1628	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1629	*
1630	* @returns cpu structure pointer
1631	* @param idCpu id of the VCPU
1632	*/
1633	VMMR0DECL(PHMGLOBLCPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu)
1634	{
1635	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1636	return &g_HvmR0.aCpuInfo[idCpu];
1637	}
1638
1639
1640	/**
1641	* Save a pending IO read.
1642	*
1643	* @param pVCpu The VMCPU to operate on.
1644	* @param GCPtrRip Address of IO instruction
1645	* @param GCPtrRipNext Address of the next instruction
1646	* @param uPort Port address
1647	* @param uAndVal And mask for saving the result in eax
1648	* @param cbSize Read size
1649	*/
1650	VMMR0DECL(void) HWACCMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1651	{
1652	pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_PORT_READ;
1653	pVCpu->hwaccm.s.PendingIO.GCPtrRip = GCPtrRip;
1654	pVCpu->hwaccm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1655	pVCpu->hwaccm.s.PendingIO.s.Port.uPort = uPort;
1656	pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal = uAndVal;
1657	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize = cbSize;
1658	return;
1659	}
1660
1661
1662	/**
1663	* Save a pending IO write.
1664	*
1665	* @param pVCpu The VMCPU to operate on.
1666	* @param GCPtrRIP Address of IO instruction
1667	* @param uPort Port address
1668	* @param uAndVal And mask for fetching the result from eax
1669	* @param cbSize Read size
1670	*/
1671	VMMR0DECL(void) HWACCMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1672	{
1673	pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_PORT_WRITE;
1674	pVCpu->hwaccm.s.PendingIO.GCPtrRip = GCPtrRip;
1675	pVCpu->hwaccm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1676	pVCpu->hwaccm.s.PendingIO.s.Port.uPort = uPort;
1677	pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal = uAndVal;
1678	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize = cbSize;
1679	return;
1680	}
1681
1682
1683	/**
1684	* Raw-mode switcher hook - disable VT-x if it's active and the current
1685	* switcher turns off paging.
1686	*
1687	* @returns VBox status code.
1688	* @param pVM VM handle.
1689	* @param pfVTxDisabled VT-x was disabled or not (out).
1690	*/
1691	VMMR0DECL(int) HWACCMR0EnterSwitcher(PVM pVM, bool *pfVTxDisabled)
1692	{
1693	Assert(!(ASMGetFlags() & X86_EFL_IF) \|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1694
1695	*pfVTxDisabled = false;
1696
1697	if ( !g_HvmR0.fEnabled
1698	\|\| !g_HvmR0.vmx.fSupported /* no such issues with AMD-V */
1699	\|\| !g_HvmR0.fGlobalInit /* Local init implies the CPU is currently not in VMX root mode. */)
1700	return VINF_SUCCESS; /* nothing to do */
1701
1702	switch (VMMGetSwitcher(pVM))
1703	{
1704	case VMMSWITCHER_32_TO_32:
1705	case VMMSWITCHER_PAE_TO_PAE:
1706	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1707
1708	case VMMSWITCHER_32_TO_PAE:
1709	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1710	case VMMSWITCHER_AMD64_TO_32:
1711	case VMMSWITCHER_AMD64_TO_PAE:
1712	break; /* unsafe switchers */
1713
1714	default:
1715	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1716	}
1717
1718	PHMGLOBLCPUINFO pCpu = HWACCMR0GetCurrentCpu();
1719	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_HM_IPE_2);
1720
1721	*pfVTxDisabled = true;
1722	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1723	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1724	return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1725	}
1726
1727
1728	/**
1729	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1730	* switcher turned off paging.
1731	*
1732	* @returns VBox status code.
1733	* @param pVM VM handle.
1734	* @param fVTxDisabled VT-x was disabled or not.
1735	*/
1736	VMMR0DECL(int) HWACCMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1737	{
1738	Assert(!(ASMGetFlags() & X86_EFL_IF));
1739
1740	if (!fVTxDisabled)
1741	return VINF_SUCCESS; /* nothing to do */
1742
1743	Assert(g_HvmR0.fEnabled);
1744	Assert(g_HvmR0.vmx.fSupported);
1745	Assert(g_HvmR0.fGlobalInit);
1746
1747	PHMGLOBLCPUINFO pCpu = HWACCMR0GetCurrentCpu();
1748	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_HM_IPE_2);
1749
1750	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1751	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1752	return VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage);
1753	}
1754
1755	#ifdef VBOX_STRICT
1756
1757	/**
1758	* Dumps a descriptor.
1759	*
1760	* @param pDesc Descriptor to dump.
1761	* @param Sel Selector number.
1762	* @param pszMsg Message to prepend the log entry with.
1763	*/
1764	VMMR0DECL(void) HWACCMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1765	{
1766	/*
1767	* Make variable description string.
1768	*/
1769	static struct
1770	{
1771	unsigned cch;
1772	const char *psz;
1773	} const s_aTypes[32] =
1774	{
1775	# define STRENTRY(str) { sizeof(str) - 1, str }
1776
1777	/* system */
1778	# if HC_ARCH_BITS == 64
1779	STRENTRY("Reserved0 "), /* 0x00 */
1780	STRENTRY("Reserved1 "), /* 0x01 */
1781	STRENTRY("LDT "), /* 0x02 */
1782	STRENTRY("Reserved3 "), /* 0x03 */
1783	STRENTRY("Reserved4 "), /* 0x04 */
1784	STRENTRY("Reserved5 "), /* 0x05 */
1785	STRENTRY("Reserved6 "), /* 0x06 */
1786	STRENTRY("Reserved7 "), /* 0x07 */
1787	STRENTRY("Reserved8 "), /* 0x08 */
1788	STRENTRY("TSS64Avail "), /* 0x09 */
1789	STRENTRY("ReservedA "), /* 0x0a */
1790	STRENTRY("TSS64Busy "), /* 0x0b */
1791	STRENTRY("Call64 "), /* 0x0c */
1792	STRENTRY("ReservedD "), /* 0x0d */
1793	STRENTRY("Int64 "), /* 0x0e */
1794	STRENTRY("Trap64 "), /* 0x0f */
1795	# else
1796	STRENTRY("Reserved0 "), /* 0x00 */
1797	STRENTRY("TSS16Avail "), /* 0x01 */
1798	STRENTRY("LDT "), /* 0x02 */
1799	STRENTRY("TSS16Busy "), /* 0x03 */
1800	STRENTRY("Call16 "), /* 0x04 */
1801	STRENTRY("Task "), /* 0x05 */
1802	STRENTRY("Int16 "), /* 0x06 */
1803	STRENTRY("Trap16 "), /* 0x07 */
1804	STRENTRY("Reserved8 "), /* 0x08 */
1805	STRENTRY("TSS32Avail "), /* 0x09 */
1806	STRENTRY("ReservedA "), /* 0x0a */
1807	STRENTRY("TSS32Busy "), /* 0x0b */
1808	STRENTRY("Call32 "), /* 0x0c */
1809	STRENTRY("ReservedD "), /* 0x0d */
1810	STRENTRY("Int32 "), /* 0x0e */
1811	STRENTRY("Trap32 "), /* 0x0f */
1812	# endif
1813	/* non system */
1814	STRENTRY("DataRO "), /* 0x10 */
1815	STRENTRY("DataRO Accessed "), /* 0x11 */
1816	STRENTRY("DataRW "), /* 0x12 */
1817	STRENTRY("DataRW Accessed "), /* 0x13 */
1818	STRENTRY("DataDownRO "), /* 0x14 */
1819	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1820	STRENTRY("DataDownRW "), /* 0x16 */
1821	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1822	STRENTRY("CodeEO "), /* 0x18 */
1823	STRENTRY("CodeEO Accessed "), /* 0x19 */
1824	STRENTRY("CodeER "), /* 0x1a */
1825	STRENTRY("CodeER Accessed "), /* 0x1b */
1826	STRENTRY("CodeConfEO "), /* 0x1c */
1827	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1828	STRENTRY("CodeConfER "), /* 0x1e */
1829	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1830	# undef SYSENTRY
1831	};
1832	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1833	char szMsg[128];
1834	char *psz = &szMsg[0];
1835	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1836	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1837	psz += s_aTypes[i].cch;
1838
1839	if (pDesc->Gen.u1Present)
1840	ADD_STR(psz, "Present ");
1841	else
1842	ADD_STR(psz, "Not-Present ");
1843	# if HC_ARCH_BITS == 64
1844	if (pDesc->Gen.u1Long)
1845	ADD_STR(psz, "64-bit ");
1846	else
1847	ADD_STR(psz, "Comp ");
1848	# else
1849	if (pDesc->Gen.u1Granularity)
1850	ADD_STR(psz, "Page ");
1851	if (pDesc->Gen.u1DefBig)
1852	ADD_STR(psz, "32-bit ");
1853	else
1854	ADD_STR(psz, "16-bit ");
1855	# endif
1856	# undef ADD_STR
1857	*psz = '\0';
1858
1859	/*
1860	* Limit and Base and format the output.
1861	*/
1862	uint32_t u32Limit = X86DESC_LIMIT(*pDesc);
1863	if (pDesc->Gen.u1Granularity)
1864	u32Limit = u32Limit << PAGE_SHIFT \| PAGE_OFFSET_MASK;
1865
1866	# if HC_ARCH_BITS == 64
1867	uint64_t u32Base = X86DESC64_BASE(*pDesc);
1868
1869	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1870	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1871	# else
1872	uint32_t u32Base = X86DESC_BASE(*pDesc);
1873
1874	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1875	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1876	# endif
1877	}
1878
1879
1880	/**
1881	* Formats a full register dump.
1882	*
1883	* @param pVM The VM to operate on.
1884	* @param pVCpu The VMCPU to operate on.
1885	* @param pCtx The context to format.
1886	*/
1887	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1888	{
1889	NOREF(pVM);
1890
1891	/*
1892	* Format the flags.
1893	*/
1894	static struct
1895	{
1896	const char pszSet; const char pszClear; uint32_t fFlag;
1897	} const s_aFlags[] =
1898	{
1899	{ "vip",NULL, X86_EFL_VIP },
1900	{ "vif",NULL, X86_EFL_VIF },
1901	{ "ac", NULL, X86_EFL_AC },
1902	{ "vm", NULL, X86_EFL_VM },
1903	{ "rf", NULL, X86_EFL_RF },
1904	{ "nt", NULL, X86_EFL_NT },
1905	{ "ov", "nv", X86_EFL_OF },
1906	{ "dn", "up", X86_EFL_DF },
1907	{ "ei", "di", X86_EFL_IF },
1908	{ "tf", NULL, X86_EFL_TF },
1909	{ "nt", "pl", X86_EFL_SF },
1910	{ "nz", "zr", X86_EFL_ZF },
1911	{ "ac", "na", X86_EFL_AF },
1912	{ "po", "pe", X86_EFL_PF },
1913	{ "cy", "nc", X86_EFL_CF },
1914	};
1915	char szEFlags[80];
1916	char *psz = szEFlags;
1917	uint32_t efl = pCtx->eflags.u32;
1918	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1919	{
1920	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1921	if (pszAdd)
1922	{
1923	strcpy(psz, pszAdd);
1924	psz += strlen(pszAdd);
1925	*psz++ = ' ';
1926	}
1927	}
1928	psz[-1] = '\0';
1929
1930
1931	/*
1932	* Format the registers.
1933	*/
1934	if (CPUMIsGuestIn64BitCode(pVCpu, CPUMCTX2CORE(pCtx)))
1935	{
1936	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1937	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1938	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1939	"r14=%016RX64 r15=%016RX64\n"
1940	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1941	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1942	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1943	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1944	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1945	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1946	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1947	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1948	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1949	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1950	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1951	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1952	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1953	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1954	,
1955	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1956	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1957	pCtx->r14, pCtx->r15,
1958	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1959	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1960	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1961	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1962	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1963	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1964	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1965	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1966	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1967	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1968	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1969	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1970	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1971	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1972	}
1973	else
1974	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1975	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1976	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1977	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1978	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1979	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1980	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1981	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1982	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1983	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1984	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1985	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1986	,
1987	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1988	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1989	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr[0], pCtx->dr[1],
1990	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr[2], pCtx->dr[3],
1991	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr[4], pCtx->dr[5],
1992	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr[6], pCtx->dr[7],
1993	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0, pCtx->cr2,
1994	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3, pCtx->cr4,
1995	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1996	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1997	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1998	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1999
2000	Log(("FPU:\n"
2001	"FCW=%04x FSW=%04x FTW=%02x\n"
2002	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
2003	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
2004	,
2005	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
2006	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsrvd1,
2007	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
2008	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
2009
2010
2011	Log(("MSR:\n"
2012	"EFER =%016RX64\n"
2013	"PAT =%016RX64\n"
2014	"STAR =%016RX64\n"
2015	"CSTAR =%016RX64\n"
2016	"LSTAR =%016RX64\n"
2017	"SFMASK =%016RX64\n"
2018	"KERNELGSBASE =%016RX64\n",
2019	pCtx->msrEFER,
2020	pCtx->msrPAT,
2021	pCtx->msrSTAR,
2022	pCtx->msrCSTAR,
2023	pCtx->msrLSTAR,
2024	pCtx->msrSFMASK,
2025	pCtx->msrKERNELGSBASE));
2026
2027	}
2028
2029	#endif /* VBOX_STRICT */
2030

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp@ 40806

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