VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp@ 5474

Last change on this file since 5474 was 5442, checked in by vboxsync, 17 years ago

VT-x: Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it wasn't so before (some software could incorrectly think it's in VMX mode)
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1/* $Id: HWACCMR0.cpp 5442 2007-10-23 14:20:11Z vboxsync $ */
2/** @file
3 * HWACCM - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 innotek GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License as published by the Free Software Foundation,
13 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14 * distribution. VirtualBox OSE is distributed in the hope that it will
15 * be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_HWACCM
23#include <VBox/hwaccm.h>
24#include "HWACCMInternal.h"
25#include <VBox/vm.h>
26#include <VBox/x86.h>
27#include <VBox/hwacc_vmx.h>
28#include <VBox/hwacc_svm.h>
29#include <VBox/pgm.h>
30#include <VBox/pdm.h>
31#include <VBox/err.h>
32#include <VBox/log.h>
33#include <VBox/selm.h>
34#include <VBox/iom.h>
35#include <iprt/param.h>
36#include <iprt/assert.h>
37#include <iprt/asm.h>
38#include "HWVMXR0.h"
39#include "HWSVMR0.h"
40
41/**
42 * Does Ring-0 HWACCM initialization.
43 *
44 * This is mainly to check that the Host CPU mode is compatible
45 * with VMX.
46 *
47 * @returns VBox status code.
48 * @param pVM The VM to operate on.
49 */
50HWACCMR0DECL(int) HWACCMR0Init(PVM pVM)
51{
52 LogComFlow(("HWACCMR0Init: %p\n", pVM));
53
54 pVM->hwaccm.s.vmx.fSupported = false;;
55 pVM->hwaccm.s.svm.fSupported = false;;
56
57#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL /* paranoia */
58
59 pVM->hwaccm.s.fHWACCMR0Init = true;
60 pVM->hwaccm.s.lLastError = VINF_SUCCESS;
61
62 /*
63 * Check for VMX capabilities
64 */
65 if (ASMHasCpuId())
66 {
67 uint32_t u32FeaturesECX;
68 uint32_t u32Dummy;
69 uint32_t u32FeaturesEDX;
70 uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
71
72 ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
73 ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
74 /* Query AMD features. */
75 ASMCpuId(0x80000001, &u32Dummy, &u32Dummy, &pVM->hwaccm.s.cpuid.u32AMDFeatureECX, &pVM->hwaccm.s.cpuid.u32AMDFeatureEDX);
76
77 if ( u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
78 && u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
79 && u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX
80 )
81 {
82 /*
83 * Read all VMX MSRs if VMX is available. (same goes for RDMSR/WRMSR)
84 * We also assume all VMX-enabled CPUs support fxsave/fxrstor.
85 */
86 if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
87 && (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
88 && (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
89 )
90 {
91 pVM->hwaccm.s.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
92 /*
93 * Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
94 * Once the lock bit is set, this MSR can no longer be modified.
95 */
96 /** @todo need to check this for each cpu/core in the system!!!) */
97 if (!(pVM->hwaccm.s.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON|MSR_IA32_FEATURE_CONTROL_LOCK)))
98 {
99 /* MSR is not yet locked; we can change it ourselves here */
100 pVM->hwaccm.s.vmx.msr.feature_ctrl |= (MSR_IA32_FEATURE_CONTROL_VMXON|MSR_IA32_FEATURE_CONTROL_LOCK);
101 ASMWrMsr(MSR_IA32_FEATURE_CONTROL, pVM->hwaccm.s.vmx.msr.feature_ctrl);
102 }
103
104 if ( (pVM->hwaccm.s.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON|MSR_IA32_FEATURE_CONTROL_LOCK))
105 == (MSR_IA32_FEATURE_CONTROL_VMXON|MSR_IA32_FEATURE_CONTROL_LOCK))
106 {
107 pVM->hwaccm.s.vmx.fSupported = true;
108 pVM->hwaccm.s.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
109 pVM->hwaccm.s.vmx.msr.vmx_pin_ctls = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
110 pVM->hwaccm.s.vmx.msr.vmx_proc_ctls = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
111 pVM->hwaccm.s.vmx.msr.vmx_exit = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
112 pVM->hwaccm.s.vmx.msr.vmx_entry = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
113 pVM->hwaccm.s.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
114 pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
115 pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
116 pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
117 pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
118 pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
119
120 /*
121 * Check CR4.VMXE
122 */
123 pVM->hwaccm.s.vmx.hostCR4 = ASMGetCR4();
124 if (!(pVM->hwaccm.s.vmx.hostCR4 & X86_CR4_VMXE))
125 {
126 /* In theory this bit could be cleared behind our back. Which would cause #UD faults when we
127 * try to execute the VMX instructions...
128 */
129 ASMSetCR4(pVM->hwaccm.s.vmx.hostCR4 | X86_CR4_VMXE);
130 }
131
132 if ( pVM->hwaccm.s.vmx.pVMXONPhys
133 && pVM->hwaccm.s.vmx.pVMXON)
134 {
135 /* Set revision dword at the beginning of the structure. */
136 *(uint32_t *)pVM->hwaccm.s.vmx.pVMXON = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
137
138#if HC_ARCH_BITS == 64
139 /* Enter VMX Root Mode */
140 int rc = VMXEnable(pVM->hwaccm.s.vmx.pVMXONPhys);
141 if (VBOX_FAILURE(rc))
142 {
143 /* KVM leaves the CPU in VMX root mode. Not only is this not allowed, it will crash the host when we enter raw mode, because
144 * (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify this bit)
145 * (b) turning off paging causes a #GP (unavoidable when switching from long to 32 bits mode)
146 *
147 * They should fix their code, but until they do we simply refuse to run.
148 */
149 return VERR_VMX_IN_VMX_ROOT_MODE;
150 }
151 VMXDisable();
152#endif
153 }
154 /* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it wasn't so before (some software could incorrectly think it's in VMX mode) */
155 ASMSetCR4(pVM->hwaccm.s.vmx.hostCR4);
156 }
157 else
158 pVM->hwaccm.s.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
159 }
160 else
161 pVM->hwaccm.s.lLastError = VERR_VMX_NO_VMX;
162 }
163 else
164 if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
165 && u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
166 && u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX
167 )
168 {
169 /*
170 * Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
171 * We also assume all SVM-enabled CPUs support fxsave/fxrstor.
172 */
173 if ( (pVM->hwaccm.s.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
174 && (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
175 && (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
176 )
177 {
178 uint64_t val;
179
180 /* Check if SVM is disabled */
181 val = ASMRdMsr(MSR_K8_VM_CR);
182 if (!(val & MSR_K8_VM_CR_SVM_DISABLE))
183 {
184 /* Turn on SVM in the EFER MSR. */
185 val = ASMRdMsr(MSR_K6_EFER);
186 if (!(val & MSR_K6_EFER_SVME))
187 {
188 ASMWrMsr(MSR_K6_EFER, val | MSR_K6_EFER_SVME);
189 }
190 /* Paranoia. */
191 val = ASMRdMsr(MSR_K6_EFER);
192 if (val & MSR_K6_EFER_SVME)
193 {
194 /* Query AMD features. */
195 ASMCpuId(0x8000000A, &pVM->hwaccm.s.svm.u32Rev, &pVM->hwaccm.s.svm.u32MaxASID, &u32Dummy, &u32Dummy);
196
197 pVM->hwaccm.s.svm.fSupported = true;
198 }
199 else
200 {
201 pVM->hwaccm.s.lLastError = VERR_SVM_ILLEGAL_EFER_MSR;
202 AssertFailed();
203 }
204 }
205 else
206 pVM->hwaccm.s.lLastError = VERR_SVM_DISABLED;
207 }
208 else
209 pVM->hwaccm.s.lLastError = VERR_SVM_NO_SVM;
210 }
211 else
212 pVM->hwaccm.s.lLastError = VERR_HWACCM_UNKNOWN_CPU;
213 }
214 else
215 pVM->hwaccm.s.lLastError = VERR_HWACCM_NO_CPUID;
216
217#endif /* !VBOX_WITH_HYBIRD_32BIT_KERNEL */
218
219 return VINF_SUCCESS;
220}
221
222
223/**
224 * Sets up and activates VMX
225 *
226 * @returns VBox status code.
227 * @param pVM The VM to operate on.
228 */
229HWACCMR0DECL(int) HWACCMR0SetupVMX(PVM pVM)
230{
231 int rc = VINF_SUCCESS;
232
233 if (pVM == NULL)
234 return VERR_INVALID_PARAMETER;
235
236 /* Setup Intel VMX. */
237 if (pVM->hwaccm.s.vmx.fSupported)
238 rc = VMXR0Setup(pVM);
239 else
240 rc = SVMR0Setup(pVM);
241
242 return rc;
243}
244
245
246/**
247 * Enable VMX or SVN
248 *
249 * @returns VBox status code.
250 * @param pVM The VM to operate on.
251 */
252HWACCMR0DECL(int) HWACCMR0Enable(PVM pVM)
253{
254 CPUMCTX *pCtx;
255 int rc;
256
257 rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
258 if (VBOX_FAILURE(rc))
259 return rc;
260
261 /* Always load the guest's FPU/XMM state on-demand. */
262 CPUMDeactivateGuestFPUState(pVM);
263
264 /* Always reload the host context and the guest's CR0 register. (!!!!) */
265 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0 | HWACCM_CHANGED_HOST_CONTEXT;
266
267 if (pVM->hwaccm.s.vmx.fSupported)
268 {
269 rc = VMXR0Enable(pVM);
270 AssertRC(rc);
271 rc |= VMXR0SaveHostState(pVM);
272 AssertRC(rc);
273 rc |= VMXR0LoadGuestState(pVM, pCtx);
274 AssertRC(rc);
275 if (rc != VINF_SUCCESS)
276 return rc;
277 }
278 else
279 {
280 Assert(pVM->hwaccm.s.svm.fSupported);
281 rc = SVMR0Enable(pVM);
282 AssertRC(rc);
283 rc |= SVMR0LoadGuestState(pVM, pCtx);
284 AssertRC(rc);
285 if (rc != VINF_SUCCESS)
286 return rc;
287
288 }
289 return VINF_SUCCESS;
290}
291
292
293/**
294 * Disable VMX or SVN
295 *
296 * @returns VBox status code.
297 * @param pVM The VM to operate on.
298 */
299HWACCMR0DECL(int) HWACCMR0Disable(PVM pVM)
300{
301 CPUMCTX *pCtx;
302 int rc;
303
304 rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
305 if (VBOX_FAILURE(rc))
306 return rc;
307
308 /** @note It's rather tricky with longjmps done by e.g. Log statements or the page fault handler. */
309 /* We must restore the host FPU here to make absolutely sure we don't leave the guest FPU state active
310 * or trash somebody else's FPU state.
311 */
312
313 /* Restore host FPU and XMM state if necessary. */
314 if (CPUMIsGuestFPUStateActive(pVM))
315 {
316 Log2(("CPUMRestoreHostFPUState\n"));
317 /** @note CPUMRestoreHostFPUState keeps the current CR0 intact. */
318 CPUMRestoreHostFPUState(pVM);
319
320 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
321 }
322
323 if (pVM->hwaccm.s.vmx.fSupported)
324 {
325 return VMXR0Disable(pVM);
326 }
327 else
328 {
329 Assert(pVM->hwaccm.s.svm.fSupported);
330 return SVMR0Disable(pVM);
331 }
332}
333
334/**
335 * Runs guest code in a hardware accelerated VM.
336 *
337 * @returns VBox status code.
338 * @param pVM The VM to operate on.
339 */
340HWACCMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM)
341{
342 CPUMCTX *pCtx;
343 int rc;
344
345 rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
346 if (VBOX_FAILURE(rc))
347 return rc;
348
349 if (pVM->hwaccm.s.vmx.fSupported)
350 {
351 return VMXR0RunGuestCode(pVM, pCtx);
352 }
353 else
354 {
355 Assert(pVM->hwaccm.s.svm.fSupported);
356 return SVMR0RunGuestCode(pVM, pCtx);
357 }
358}
359
360
361#ifdef VBOX_STRICT
362#include <iprt/string.h>
363/**
364 * Dumps a descriptor.
365 *
366 * @param Desc Descriptor to dump.
367 * @param Sel Selector number.
368 * @param pszMsg Message to prepend the log entry with.
369 */
370HWACCMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg)
371{
372 /*
373 * Make variable description string.
374 */
375 static struct
376 {
377 unsigned cch;
378 const char *psz;
379 } const aTypes[32] =
380 {
381 #define STRENTRY(str) { sizeof(str) - 1, str }
382
383 /* system */
384#if HC_ARCH_BITS == 64
385 STRENTRY("Reserved0 "), /* 0x00 */
386 STRENTRY("Reserved1 "), /* 0x01 */
387 STRENTRY("LDT "), /* 0x02 */
388 STRENTRY("Reserved3 "), /* 0x03 */
389 STRENTRY("Reserved4 "), /* 0x04 */
390 STRENTRY("Reserved5 "), /* 0x05 */
391 STRENTRY("Reserved6 "), /* 0x06 */
392 STRENTRY("Reserved7 "), /* 0x07 */
393 STRENTRY("Reserved8 "), /* 0x08 */
394 STRENTRY("TSS64Avail "), /* 0x09 */
395 STRENTRY("ReservedA "), /* 0x0a */
396 STRENTRY("TSS64Busy "), /* 0x0b */
397 STRENTRY("Call64 "), /* 0x0c */
398 STRENTRY("ReservedD "), /* 0x0d */
399 STRENTRY("Int64 "), /* 0x0e */
400 STRENTRY("Trap64 "), /* 0x0f */
401#else
402 STRENTRY("Reserved0 "), /* 0x00 */
403 STRENTRY("TSS16Avail "), /* 0x01 */
404 STRENTRY("LDT "), /* 0x02 */
405 STRENTRY("TSS16Busy "), /* 0x03 */
406 STRENTRY("Call16 "), /* 0x04 */
407 STRENTRY("Task "), /* 0x05 */
408 STRENTRY("Int16 "), /* 0x06 */
409 STRENTRY("Trap16 "), /* 0x07 */
410 STRENTRY("Reserved8 "), /* 0x08 */
411 STRENTRY("TSS32Avail "), /* 0x09 */
412 STRENTRY("ReservedA "), /* 0x0a */
413 STRENTRY("TSS32Busy "), /* 0x0b */
414 STRENTRY("Call32 "), /* 0x0c */
415 STRENTRY("ReservedD "), /* 0x0d */
416 STRENTRY("Int32 "), /* 0x0e */
417 STRENTRY("Trap32 "), /* 0x0f */
418#endif
419 /* non system */
420 STRENTRY("DataRO "), /* 0x10 */
421 STRENTRY("DataRO Accessed "), /* 0x11 */
422 STRENTRY("DataRW "), /* 0x12 */
423 STRENTRY("DataRW Accessed "), /* 0x13 */
424 STRENTRY("DataDownRO "), /* 0x14 */
425 STRENTRY("DataDownRO Accessed "), /* 0x15 */
426 STRENTRY("DataDownRW "), /* 0x16 */
427 STRENTRY("DataDownRW Accessed "), /* 0x17 */
428 STRENTRY("CodeEO "), /* 0x18 */
429 STRENTRY("CodeEO Accessed "), /* 0x19 */
430 STRENTRY("CodeER "), /* 0x1a */
431 STRENTRY("CodeER Accessed "), /* 0x1b */
432 STRENTRY("CodeConfEO "), /* 0x1c */
433 STRENTRY("CodeConfEO Accessed "), /* 0x1d */
434 STRENTRY("CodeConfER "), /* 0x1e */
435 STRENTRY("CodeConfER Accessed ") /* 0x1f */
436 #undef SYSENTRY
437 };
438 #define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
439 char szMsg[128];
440 char *psz = &szMsg[0];
441 unsigned i = Desc->Gen.u1DescType << 4 | Desc->Gen.u4Type;
442 memcpy(psz, aTypes[i].psz, aTypes[i].cch);
443 psz += aTypes[i].cch;
444
445 if (Desc->Gen.u1Present)
446 ADD_STR(psz, "Present ");
447 else
448 ADD_STR(psz, "Not-Present ");
449#if HC_ARCH_BITS == 64
450 if (Desc->Gen.u1Long)
451 ADD_STR(psz, "64-bit ");
452 else
453 ADD_STR(psz, "Comp ");
454#else
455 if (Desc->Gen.u1Granularity)
456 ADD_STR(psz, "Page ");
457 if (Desc->Gen.u1DefBig)
458 ADD_STR(psz, "32-bit ");
459 else
460 ADD_STR(psz, "16-bit ");
461#endif
462 #undef ADD_STR
463 *psz = '\0';
464
465 /*
466 * Limit and Base and format the output.
467 */
468 uint32_t u32Limit = Desc->Gen.u4LimitHigh << 16 | Desc->Gen.u16LimitLow;
469 if (Desc->Gen.u1Granularity)
470 u32Limit = u32Limit << PAGE_SHIFT | PAGE_OFFSET_MASK;
471
472#if HC_ARCH_BITS == 64
473 uint64_t u32Base = ((uintptr_t)Desc->Gen.u32BaseHigh3 << 32ULL) | Desc->Gen.u8BaseHigh2 << 24ULL | Desc->Gen.u8BaseHigh1 << 16ULL | Desc->Gen.u16BaseLow;
474
475 Log(("%s %04x - %VX64 %VX64 - base=%VX64 limit=%08x dpl=%d %s\n", pszMsg,
476 Sel, Desc->au64[0], Desc->au64[1], u32Base, u32Limit, Desc->Gen.u2Dpl, szMsg));
477#else
478 uint32_t u32Base = Desc->Gen.u8BaseHigh2 << 24 | Desc->Gen.u8BaseHigh1 << 16 | Desc->Gen.u16BaseLow;
479
480 Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
481 Sel, Desc->au32[0], Desc->au32[1], u32Base, u32Limit, Desc->Gen.u2Dpl, szMsg));
482#endif
483}
484
485/**
486 * Formats a full register dump.
487 *
488 * @param pCtx The context to format.
489 */
490HWACCMR0DECL(void) HWACCMDumpRegs(PCPUMCTX pCtx)
491{
492 /*
493 * Format the flags.
494 */
495 static struct
496 {
497 const char *pszSet; const char *pszClear; uint32_t fFlag;
498 } aFlags[] =
499 {
500 { "vip",NULL, X86_EFL_VIP },
501 { "vif",NULL, X86_EFL_VIF },
502 { "ac", NULL, X86_EFL_AC },
503 { "vm", NULL, X86_EFL_VM },
504 { "rf", NULL, X86_EFL_RF },
505 { "nt", NULL, X86_EFL_NT },
506 { "ov", "nv", X86_EFL_OF },
507 { "dn", "up", X86_EFL_DF },
508 { "ei", "di", X86_EFL_IF },
509 { "tf", NULL, X86_EFL_TF },
510 { "nt", "pl", X86_EFL_SF },
511 { "nz", "zr", X86_EFL_ZF },
512 { "ac", "na", X86_EFL_AF },
513 { "po", "pe", X86_EFL_PF },
514 { "cy", "nc", X86_EFL_CF },
515 };
516 char szEFlags[80];
517 char *psz = szEFlags;
518 uint32_t efl = pCtx->eflags.u32;
519 for (unsigned i = 0; i < ELEMENTS(aFlags); i++)
520 {
521 const char *pszAdd = aFlags[i].fFlag & efl ? aFlags[i].pszSet : aFlags[i].pszClear;
522 if (pszAdd)
523 {
524 strcpy(psz, pszAdd);
525 psz += strlen(pszAdd);
526 *psz++ = ' ';
527 }
528 }
529 psz[-1] = '\0';
530
531
532 /*
533 * Format the registers.
534 */
535 Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
536 "eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
537 "cs={%04x base=%08x limit=%08x flags=%08x} dr0=%08x dr1=%08x\n"
538 "ds={%04x base=%08x limit=%08x flags=%08x} dr2=%08x dr3=%08x\n"
539 "es={%04x base=%08x limit=%08x flags=%08x} dr4=%08x dr5=%08x\n"
540 "fs={%04x base=%08x limit=%08x flags=%08x} dr6=%08x dr7=%08x\n"
541 ,
542 pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
543 pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
544 (RTSEL)pCtx->cs, pCtx->csHid.u32Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr0, pCtx->dr1,
545 (RTSEL)pCtx->ds, pCtx->dsHid.u32Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr2, pCtx->dr3,
546 (RTSEL)pCtx->es, pCtx->esHid.u32Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr4, pCtx->dr5,
547 (RTSEL)pCtx->fs, pCtx->fsHid.u32Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr6, pCtx->dr7));
548
549 Log(("gs={%04x base=%08x limit=%08x flags=%08x} cr0=%08x cr2=%08x\n"
550 "ss={%04x base=%08x limit=%08x flags=%08x} cr3=%08x cr4=%08x\n"
551 "gdtr=%08x:%04x idtr=%08x:%04x eflags=%08x\n"
552 "ldtr={%04x base=%08x limit=%08x flags=%08x}\n"
553 "tr ={%04x base=%08x limit=%08x flags=%08x}\n"
554 "SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
555 "FCW=%04x FSW=%04x FTW=%04x\n",
556 (RTSEL)pCtx->gs, pCtx->gsHid.u32Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0, pCtx->cr2,
557 (RTSEL)pCtx->ss, pCtx->ssHid.u32Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3, pCtx->cr4,
558 pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
559 (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u32Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
560 (RTSEL)pCtx->tr, pCtx->trHid.u32Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
561 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
562 pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW));
563
564
565}
566#endif
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