HWACCMR0.cpp@ 7503

Last change on this file since 7503 was 7503, checked in by vboxsync, 17 years ago
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1	/* $Id: HWACCMR0.cpp 7503 2008-03-19 13:42:34Z vboxsync $ */
2	/** @file
3	* HWACCM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HWACCM
23	#include <VBox/hwaccm.h>
24	#include "HWACCMInternal.h"
25	#include <VBox/vm.h>
26	#include <VBox/x86.h>
27	#include <VBox/hwacc_vmx.h>
28	#include <VBox/hwacc_svm.h>
29	#include <VBox/pgm.h>
30	#include <VBox/pdm.h>
31	#include <VBox/err.h>
32	#include <VBox/log.h>
33	#include <VBox/selm.h>
34	#include <VBox/iom.h>
35	#include <iprt/param.h>
36	#include <iprt/assert.h>
37	#include <iprt/asm.h>
38	#include <iprt/string.h>
39	#include <iprt/memobj.h>
40	#include <iprt/cpuset.h>
41	#include "HWVMXR0.h"
42	#include "HWSVMR0.h"
43
44	/*******************************************************************************
45	* Internal Functions *
46	*******************************************************************************/
47	static DECLCALLBACK(void) HWACCMR0EnableCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
48	static DECLCALLBACK(void) HWACCMR0DisableCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
49	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
50	static int hwaccmr0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu);
51
52	/*******************************************************************************
53	* Local Variables *
54	*******************************************************************************/
55	static struct
56	{
57	struct
58	{
59	RTR0MEMOBJ pMemObj;
60	bool fVMXConfigured;
61	bool fSVMConfigured;
62	} aCpuInfo[RTCPUSET_MAX_CPUS];
63
64	struct
65	{
66	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
67	bool fSupported;
68
69	/** Host CR4 value (set by ring-0 VMX init) */
70	uint64_t hostCR4;
71
72	/** VMX MSR values */
73	struct
74	{
75	uint64_t feature_ctrl;
76	uint64_t vmx_basic_info;
77	uint64_t vmx_pin_ctls;
78	uint64_t vmx_proc_ctls;
79	uint64_t vmx_exit;
80	uint64_t vmx_entry;
81	uint64_t vmx_misc;
82	uint64_t vmx_cr0_fixed0;
83	uint64_t vmx_cr0_fixed1;
84	uint64_t vmx_cr4_fixed0;
85	uint64_t vmx_cr4_fixed1;
86	uint64_t vmx_vmcs_enum;
87	} msr;
88	/* Last instruction error */
89	uint32_t ulLastInstrError;
90	} vmx;
91	struct
92	{
93	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
94	bool fSupported;
95
96	/** SVM revision. */
97	uint32_t u32Rev;
98
99	/** Maximum ASID allowed. */
100	uint32_t u32MaxASID;
101	} svm;
102	/** Saved error from detection */
103	int32_t lLastError;
104
105	struct
106	{
107	uint32_t u32AMDFeatureECX;
108	uint32_t u32AMDFeatureEDX;
109	} cpuid;
110
111	HWACCMSTATE enmHwAccmState;
112	} HWACCMR0Globals;
113
114
115
116	/**
117	* Does global Ring-0 HWACCM initialization.
118	*
119	* @returns VBox status code.
120	*/
121	HWACCMR0DECL(int) HWACCMR0Init()
122	{
123	int rc;
124
125	memset(&HWACCMR0Globals, 0, sizeof(HWACCMR0Globals));
126	HWACCMR0Globals.enmHwAccmState = HWACCMSTATE_UNINITIALIZED;
127
128	#ifdef RT_OS_WINDOWS /* kernel panics on Linux; disabled for now */
129	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL /* paranoia */
130
131	/*
132	* Check for VT-x and AMD-V capabilities
133	*/
134	if (ASMHasCpuId())
135	{
136	uint32_t u32FeaturesECX;
137	uint32_t u32Dummy;
138	uint32_t u32FeaturesEDX;
139	uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
140
141	ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
142	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
143	/* Query AMD features. */
144	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy, &HWACCMR0Globals.cpuid.u32AMDFeatureECX, &HWACCMR0Globals.cpuid.u32AMDFeatureEDX);
145
146	if ( u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
147	&& u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
148	&& u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX
149	)
150	{
151	/*
152	* Read all VMX MSRs if VMX is available. (same goes for RDMSR/WRMSR)
153	* We also assume all VMX-enabled CPUs support fxsave/fxrstor.
154	*/
155	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
156	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
157	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
158	)
159	{
160	int aRc[RTCPUSET_MAX_CPUS];
161	RTCPUID idCpu = 0;
162
163	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
164
165	/* We need to check if VT-x has been properly initialized on all CPUs. Some BIOSes do a lousy job. */
166	memset(aRc, 0, sizeof(aRc));
167	HWACCMR0Globals.lLastError = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
168
169	/* Check the return code of all invocations. */
170	if (VBOX_SUCCESS(HWACCMR0Globals.lLastError))
171	HWACCMR0Globals.lLastError = hwaccmr0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
172
173	AssertMsg(VBOX_SUCCESS(HWACCMR0Globals.lLastError), ("HWACCMR0InitCPU failed for cpu %d with rc=%d\n", idCpu, HWACCMR0Globals.lLastError));
174	if (VBOX_SUCCESS(HWACCMR0Globals.lLastError))
175	{
176	/* Reread in case we've changed it. */
177	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
178
179	if ( (HWACCMR0Globals.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
180	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
181	{
182	HWACCMR0Globals.vmx.fSupported = true;
183	HWACCMR0Globals.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
184	HWACCMR0Globals.vmx.msr.vmx_pin_ctls = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
185	HWACCMR0Globals.vmx.msr.vmx_proc_ctls = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
186	HWACCMR0Globals.vmx.msr.vmx_exit = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
187	HWACCMR0Globals.vmx.msr.vmx_entry = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
188	HWACCMR0Globals.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
189	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
190	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
191	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
192	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
193	HWACCMR0Globals.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
194	HWACCMR0Globals.vmx.hostCR4 = ASMGetCR4();
195
196	#if HC_ARCH_BITS == 64
197	RTR0MEMOBJ pScatchMemObj;
198	void *pvScatchPage;
199	RTHCPHYS pScatchPagePhys;
200
201	rc = RTR0MemObjAllocCont(&pScatchMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
202	if (RT_FAILURE(rc))
203	return rc;
204
205	pvScatchPage = RTR0MemObjAddress(pScatchMemObj);
206	pScatchPagePhys = RTR0MemObjGetPagePhysAddr(pScatchMemObj, 0);
207	memset(pvScatchPage, 0, PAGE_SIZE);
208
209	/* Set revision dword at the beginning of the structure. */
210	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(HWACCMR0Globals.vmx.msr.vmx_basic_info);
211
212	/* Make sure we don't get rescheduled to another cpu during this probe. */
213	RTCCUINTREG fFlags = ASMIntDisableFlags();
214
215	/*
216	* Check CR4.VMXE
217	*/
218	if (!(HWACCMR0Globals.vmx.hostCR4 & X86_CR4_VMXE))
219	{
220	/* In theory this bit could be cleared behind our back. Which would cause #UD faults when we
221	* try to execute the VMX instructions...
222	*/
223	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4 \| X86_CR4_VMXE);
224	}
225
226	/* Enter VMX Root Mode */
227	rc = VMXEnable(pScatchPagePhys);
228	if (VBOX_FAILURE(rc))
229	{
230	/* KVM leaves the CPU in VMX root mode. Not only is this not allowed, it will crash the host when we enter raw mode, because
231	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify this bit)
232	* (b) turning off paging causes a #GP (unavoidable when switching from long to 32 bits mode)
233	*
234	* They should fix their code, but until they do we simply refuse to run.
235	*/
236	HWACCMR0Globals.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
237	HWACCMR0Globals.vmx.fSupported = false;
238	}
239	else
240	VMXDisable();
241
242	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it wasn't so before (some software could incorrectly think it's in VMX mode) */
243	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4);
244	ASMSetFlags(fFlags);
245
246	RTR0MemObjFree(pScatchMemObj, false);
247	#endif
248	}
249	else
250	{
251	AssertFailed(); /* can't hit this case anymore */
252	HWACCMR0Globals.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
253	}
254	}
255	}
256	else
257	HWACCMR0Globals.lLastError = VERR_VMX_NO_VMX;
258	}
259	else
260	if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
261	&& u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
262	&& u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX
263	)
264	{
265	/*
266	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
267	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
268	*/
269	if ( (HWACCMR0Globals.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
270	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
271	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
272	)
273	{
274	int aRc[RTCPUSET_MAX_CPUS];
275	RTCPUID idCpu = 0;
276
277	/* We need to check if AMD-V has been properly initialized on all CPUs. Some BIOSes might do a poor job. */
278	memset(aRc, 0, sizeof(aRc));
279	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
280	AssertRC(rc);
281
282	/* Check the return code of all invocations. */
283	if (VBOX_SUCCESS(rc))
284	rc = hwaccmr0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
285
286	AssertMsg(VBOX_SUCCESS(rc), ("HWACCMR0InitCPU failed for cpu %d with rc=%d\n", idCpu, rc));
287
288	if (VBOX_SUCCESS(rc))
289	{
290	/* Query AMD features. */
291	ASMCpuId(0x8000000A, &HWACCMR0Globals.svm.u32Rev, &HWACCMR0Globals.svm.u32MaxASID, &u32Dummy, &u32Dummy);
292
293	HWACCMR0Globals.svm.fSupported = true;
294	}
295	else
296	HWACCMR0Globals.lLastError = rc;
297	}
298	else
299	HWACCMR0Globals.lLastError = VERR_SVM_NO_SVM;
300	}
301	else
302	HWACCMR0Globals.lLastError = VERR_HWACCM_UNKNOWN_CPU;
303	}
304	else
305	HWACCMR0Globals.lLastError = VERR_HWACCM_NO_CPUID;
306
307	#endif /* !VBOX_WITH_HYBIRD_32BIT_KERNEL */
308	#endif /* RT_OS_WINDOWS */
309
310	return VINF_SUCCESS;
311	}
312
313
314	/**
315	* Checks the error code array filled in for each cpu in the system.
316	*
317	* @returns VBox status code.
318	* @param paRc Error code array
319	* @param cErrorCodes Array size
320	* @param pidCpu Value of the first cpu that set an error (out)
321	*/
322	static int hwaccmr0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu)
323	{
324	int rc = VINF_SUCCESS;
325
326	Assert(cErrorCodes == RTCPUSET_MAX_CPUS);
327
328	for (unsigned i=0;i<cErrorCodes;i++)
329	{
330	if (RTMpIsCpuOnline(i))
331	{
332	if (VBOX_FAILURE(paRc[i]))
333	{
334	rc = paRc[i];
335	*pidCpu = i;
336	break;
337	}
338	}
339	}
340	return rc;
341	}
342
343	/**
344	* Does global Ring-0 HWACCM termination.
345	*
346	* @returns VBox status code.
347	*/
348	HWACCMR0DECL(int) HWACCMR0Term()
349	{
350	int aRc[RTCPUSET_MAX_CPUS];
351
352	memset(aRc, 0, sizeof(aRc));
353	int rc = RTMpOnAll(HWACCMR0DisableCPU, aRc, NULL);
354	AssertRC(rc);
355
356	/* Free the per-cpu pages used for VT-x and AMD-V */
357	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
358	{
359	AssertMsg(VBOX_SUCCESS(aRc[i]), ("HWACCMR0DisableCPU failed for cpu %d with rc=%d\n", i, aRc[i]));
360	if (HWACCMR0Globals.aCpuInfo[i].pMemObj)
361	{
362	RTR0MemObjFree(HWACCMR0Globals.aCpuInfo[i].pMemObj, false);
363	HWACCMR0Globals.aCpuInfo[i].pMemObj = NULL;
364	}
365	}
366	return rc;
367	}
368
369
370	/**
371	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
372	* is to be called on the target cpus.
373	*
374	* @param idCpu The identifier for the CPU the function is called on.
375	* @param pvUser1 The 1st user argument.
376	* @param pvUser2 The 2nd user argument.
377	*/
378	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
379	{
380	unsigned u32VendorEBX = (uintptr_t)pvUser1;
381	int paRc = (int )pvUser2;
382	uint64_t val;
383
384	#ifdef LOG_ENABLED
385	SUPR0Printf("HWACCMR0InitCPU cpu %d\n", idCpu);
386	#endif
387
388	if (u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX)
389	{
390	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
391
392	/*
393	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
394	* Once the lock bit is set, this MSR can no longer be modified.
395	*/
396	if (!(val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK)))
397	{
398	/* MSR is not yet locked; we can change it ourselves here */
399	ASMWrMsr(MSR_IA32_FEATURE_CONTROL, HWACCMR0Globals.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
400	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
401	}
402	if ( (val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
403	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
404	paRc[idCpu] = VINF_SUCCESS;
405	else
406	paRc[idCpu] = VERR_VMX_MSR_LOCKED_OR_DISABLED;
407	}
408	else
409	if (u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX)
410	{
411	/* Check if SVM is disabled */
412	val = ASMRdMsr(MSR_K8_VM_CR);
413	if (!(val & MSR_K8_VM_CR_SVM_DISABLE))
414	{
415	/* Turn on SVM in the EFER MSR. */
416	val = ASMRdMsr(MSR_K6_EFER);
417	if (!(val & MSR_K6_EFER_SVME))
418	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
419
420	/* Paranoia. */
421	val = ASMRdMsr(MSR_K6_EFER);
422	if (val & MSR_K6_EFER_SVME)
423	paRc[idCpu] = VINF_SUCCESS;
424	else
425	paRc[idCpu] = VERR_SVM_ILLEGAL_EFER_MSR;
426	}
427	else
428	paRc[idCpu] = HWACCMR0Globals.lLastError = VERR_SVM_DISABLED;
429	}
430	else
431	AssertFailed(); /* can't happen */
432	return;
433	}
434
435
436	/**
437	* Sets up HWACCM on all cpus.
438	*
439	* @returns VBox status code.
440	* @param pVM The VM to operate on.
441	* @param enmNewHwAccmState New hwaccm state
442	*
443	*/
444	HWACCMR0DECL(int) HWACCMR0EnableAllCpus(PVM pVM, HWACCMSTATE enmNewHwAccmState)
445	{
446	Assert(sizeof(HWACCMR0Globals.enmHwAccmState) == sizeof(uint32_t));
447	if (ASMAtomicCmpXchgU32((volatile uint32_t *)&HWACCMR0Globals.enmHwAccmState, enmNewHwAccmState, HWACCMSTATE_UNINITIALIZED))
448	{
449	int aRc[RTCPUSET_MAX_CPUS];
450	RTCPUID idCpu = 0;
451
452	/* Don't setup hwaccm as that might not work (vt-x & 64 bits raw mode) */
453	if (enmNewHwAccmState == HWACCMSTATE_DISABLED)
454	return VINF_SUCCESS;
455
456	memset(aRc, 0, sizeof(aRc));
457
458	/* Allocate one page per cpu for the global vt-x and amd-v pages */
459	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
460	{
461	Assert(!HWACCMR0Globals.aCpuInfo[i].pMemObj);
462
463	/** @todo this is rather dangerous if cpus can be taken offline; we don't care for now */
464	if (RTMpIsCpuOnline(i))
465	{
466	int rc = RTR0MemObjAllocCont(&HWACCMR0Globals.aCpuInfo[i].pMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
467	if (RT_FAILURE(rc))
468	return rc;
469
470	void *pvR0 = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[i].pMemObj);
471	memset(pvR0, 0, PAGE_SIZE);
472
473	#ifdef LOG_ENABLED
474	SUPR0Printf("address %x phys %x\n", pvR0, (uint32_t)RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[i].pMemObj, 0));
475	#endif
476	}
477	}
478	/* First time, so initialize each cpu/core */
479	int rc = RTMpOnAll(HWACCMR0EnableCPU, (void *)pVM, aRc);
480
481	/* Check the return code of all invocations. */
482	if (VBOX_SUCCESS(rc))
483	rc = hwaccmr0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
484
485	AssertMsg(VBOX_SUCCESS(rc), ("HWACCMR0EnableAllCpus failed for cpu %d with rc=%d\n", idCpu, rc));
486	return rc;
487	}
488
489	if (HWACCMR0Globals.enmHwAccmState == enmNewHwAccmState)
490	return VINF_SUCCESS;
491
492	/* Request to change the mode is not allowed */
493	return VERR_ACCESS_DENIED;
494	}
495
496	/**
497	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
498	* is to be called on the target cpus.
499	*
500	* @param idCpu The identifier for the CPU the function is called on.
501	* @param pvUser1 The 1st user argument.
502	* @param pvUser2 The 2nd user argument.
503	*/
504	static DECLCALLBACK(void) HWACCMR0EnableCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
505	{
506	PVM pVM = (PVM)pvUser1;
507	int paRc = (int )pvUser2;
508	void *pvPageCpu;
509	RTHCPHYS pPageCpuPhys;
510
511	Assert(pVM);
512	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
513
514	/* Should never happen */
515	if (!HWACCMR0Globals.aCpuInfo[idCpu].pMemObj)
516	{
517	AssertFailed();
518	return;
519	}
520
521	pvPageCpu = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[idCpu].pMemObj);
522	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[idCpu].pMemObj, 0);
523
524	if (pVM->hwaccm.s.vmx.fSupported)
525	{
526	paRc[idCpu] = VMXR0EnableCpu(idCpu, pVM, pvPageCpu, pPageCpuPhys);
527	if (VBOX_SUCCESS(paRc[idCpu]))
528	HWACCMR0Globals.aCpuInfo[idCpu].fVMXConfigured = true;
529	}
530	else
531	if (pVM->hwaccm.s.svm.fSupported)
532	{
533	paRc[idCpu] = SVMR0EnableCpu(idCpu, pVM, pvPageCpu, pPageCpuPhys);
534	if (VBOX_SUCCESS(paRc[idCpu]))
535	HWACCMR0Globals.aCpuInfo[idCpu].fSVMConfigured = true;
536	}
537	return;
538	}
539
540	/**
541	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
542	* is to be called on the target cpus.
543	*
544	* @param idCpu The identifier for the CPU the function is called on.
545	* @param pvUser1 The 1st user argument.
546	* @param pvUser2 The 2nd user argument.
547	*/
548	static DECLCALLBACK(void) HWACCMR0DisableCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
549	{
550	void *pvPageCpu;
551	RTHCPHYS pPageCpuPhys;
552	int paRc = (int )pvUser1;
553
554	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
555
556	if (!HWACCMR0Globals.aCpuInfo[idCpu].pMemObj)
557	return;
558
559	pvPageCpu = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[idCpu].pMemObj);
560	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[idCpu].pMemObj, 0);
561
562	if (HWACCMR0Globals.aCpuInfo[idCpu].fVMXConfigured)
563	{
564	paRc[idCpu] = VMXR0DisableCpu(idCpu, pvPageCpu, pPageCpuPhys);
565	AssertRC(paRc[idCpu]);
566	HWACCMR0Globals.aCpuInfo[idCpu].fVMXConfigured = false;
567	}
568	else
569	if (HWACCMR0Globals.aCpuInfo[idCpu].fSVMConfigured)
570	{
571	paRc[idCpu] = SVMR0DisableCpu(idCpu, pvPageCpu, pPageCpuPhys);
572	AssertRC(paRc[idCpu]);
573	HWACCMR0Globals.aCpuInfo[idCpu].fSVMConfigured = false;
574	}
575	return;
576	}
577
578
579	/**
580	* Does Ring-0 per VM HWACCM initialization.
581	*
582	* This is mainly to check that the Host CPU mode is compatible
583	* with VMX.
584	*
585	* @returns VBox status code.
586	* @param pVM The VM to operate on.
587	*/
588	HWACCMR0DECL(int) HWACCMR0InitVM(PVM pVM)
589	{
590	int rc = VINF_SUCCESS;
591
592	AssertReturn(pVM, VERR_INVALID_PARAMETER);
593
594	#ifdef LOG_ENABLED
595	SUPR0Printf("HWACCMR0InitVM: %p\n", pVM);
596	#endif
597
598	pVM->hwaccm.s.vmx.fSupported = HWACCMR0Globals.vmx.fSupported;
599	pVM->hwaccm.s.svm.fSupported = HWACCMR0Globals.svm.fSupported;
600
601	pVM->hwaccm.s.vmx.msr.feature_ctrl = HWACCMR0Globals.vmx.msr.feature_ctrl;
602	pVM->hwaccm.s.vmx.hostCR4 = HWACCMR0Globals.vmx.hostCR4;
603	pVM->hwaccm.s.vmx.msr.vmx_basic_info = HWACCMR0Globals.vmx.msr.vmx_basic_info;
604	pVM->hwaccm.s.vmx.msr.vmx_pin_ctls = HWACCMR0Globals.vmx.msr.vmx_pin_ctls;
605	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls = HWACCMR0Globals.vmx.msr.vmx_proc_ctls;
606	pVM->hwaccm.s.vmx.msr.vmx_exit = HWACCMR0Globals.vmx.msr.vmx_exit;
607	pVM->hwaccm.s.vmx.msr.vmx_entry = HWACCMR0Globals.vmx.msr.vmx_entry;
608	pVM->hwaccm.s.vmx.msr.vmx_misc = HWACCMR0Globals.vmx.msr.vmx_misc;
609	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0;
610	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1;
611	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0;
612	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1;
613	pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum = HWACCMR0Globals.vmx.msr.vmx_vmcs_enum;
614	pVM->hwaccm.s.svm.u32Rev = HWACCMR0Globals.svm.u32Rev;
615	pVM->hwaccm.s.svm.u32MaxASID = HWACCMR0Globals.svm.u32MaxASID;
616	pVM->hwaccm.s.cpuid.u32AMDFeatureECX = HWACCMR0Globals.cpuid.u32AMDFeatureECX;
617	pVM->hwaccm.s.cpuid.u32AMDFeatureEDX = HWACCMR0Globals.cpuid.u32AMDFeatureEDX;
618	pVM->hwaccm.s.lLastError = HWACCMR0Globals.lLastError;
619
620	/* Init a VT-x or AMD-V VM. */
621	if (pVM->hwaccm.s.vmx.fSupported)
622	rc = VMXR0InitVM(pVM);
623	else
624	if (pVM->hwaccm.s.svm.fSupported)
625	rc = SVMR0InitVM(pVM);
626
627	return rc;
628	}
629
630
631	/**
632	* Does Ring-0 per VM HWACCM termination.
633	*
634	* @returns VBox status code.
635	* @param pVM The VM to operate on.
636	*/
637	HWACCMR0DECL(int) HWACCMR0TermVM(PVM pVM)
638	{
639	int rc = VINF_SUCCESS;
640
641	AssertReturn(pVM, VERR_INVALID_PARAMETER);
642
643	#ifdef LOG_ENABLED
644	SUPR0Printf("HWACCMR0TermVM: %p\n", pVM);
645	#endif
646
647	/* Terminate a VT-x or AMD-V VM. */
648	if (pVM->hwaccm.s.vmx.fSupported)
649	rc = VMXR0TermVM(pVM);
650	else
651	if (pVM->hwaccm.s.svm.fSupported)
652	rc = SVMR0TermVM(pVM);
653
654	return rc;
655	}
656
657
658	/**
659	* Sets up a VT-x or AMD-V session
660	*
661	* @returns VBox status code.
662	* @param pVM The VM to operate on.
663	*/
664	HWACCMR0DECL(int) HWACCMR0SetupVM(PVM pVM)
665	{
666	int rc = VINF_SUCCESS;
667
668	AssertReturn(pVM, VERR_INVALID_PARAMETER);
669
670	#ifdef LOG_ENABLED
671	SUPR0Printf("HWACCMR0SetupVM: %p\n", pVM);
672	#endif
673
674	/* Setup VT-x or AMD-V. */
675	if (pVM->hwaccm.s.vmx.fSupported)
676	rc = VMXR0SetupVM(pVM);
677	else
678	if (pVM->hwaccm.s.svm.fSupported)
679	rc = SVMR0SetupVM(pVM);
680
681	return rc;
682	}
683
684
685	/**
686	* Enters the VT-x or AMD-V session
687	*
688	* @returns VBox status code.
689	* @param pVM The VM to operate on.
690	*/
691	HWACCMR0DECL(int) HWACCMR0Enter(PVM pVM)
692	{
693	CPUMCTX *pCtx;
694	int rc;
695
696	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
697	if (VBOX_FAILURE(rc))
698	return rc;
699
700	/* Always load the guest's FPU/XMM state on-demand. */
701	CPUMDeactivateGuestFPUState(pVM);
702
703	/* Always reload the host context and the guest's CR0 register. (!!!!) */
704	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0 \| HWACCM_CHANGED_HOST_CONTEXT;
705
706	if (pVM->hwaccm.s.vmx.fSupported)
707	{
708	rc = VMXR0Enter(pVM);
709	AssertRC(rc);
710	rc \|= VMXR0SaveHostState(pVM);
711	AssertRC(rc);
712	rc \|= VMXR0LoadGuestState(pVM, pCtx);
713	AssertRC(rc);
714	if (rc != VINF_SUCCESS)
715	return rc;
716	}
717	else
718	{
719	Assert(pVM->hwaccm.s.svm.fSupported);
720	rc = SVMR0Enter(pVM);
721	AssertRC(rc);
722	rc \|= SVMR0LoadGuestState(pVM, pCtx);
723	AssertRC(rc);
724	if (rc != VINF_SUCCESS)
725	return rc;
726
727	}
728	return VINF_SUCCESS;
729	}
730
731
732	/**
733	* Leaves the VT-x or AMD-V session
734	*
735	* @returns VBox status code.
736	* @param pVM The VM to operate on.
737	*/
738	HWACCMR0DECL(int) HWACCMR0Leave(PVM pVM)
739	{
740	CPUMCTX *pCtx;
741	int rc;
742
743	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
744	if (VBOX_FAILURE(rc))
745	return rc;
746
747	/** @note It's rather tricky with longjmps done by e.g. Log statements or the page fault handler. */
748	/* We must restore the host FPU here to make absolutely sure we don't leave the guest FPU state active
749	* or trash somebody else's FPU state.
750	*/
751
752	/* Restore host FPU and XMM state if necessary. */
753	if (CPUMIsGuestFPUStateActive(pVM))
754	{
755	Log2(("CPUMRestoreHostFPUState\n"));
756	/** @note CPUMRestoreHostFPUState keeps the current CR0 intact. */
757	CPUMRestoreHostFPUState(pVM);
758
759	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
760	}
761
762	if (pVM->hwaccm.s.vmx.fSupported)
763	{
764	return VMXR0Leave(pVM);
765	}
766	else
767	{
768	Assert(pVM->hwaccm.s.svm.fSupported);
769	return SVMR0Leave(pVM);
770	}
771	}
772
773	/**
774	* Runs guest code in a hardware accelerated VM.
775	*
776	* @returns VBox status code.
777	* @param pVM The VM to operate on.
778	*/
779	HWACCMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM)
780	{
781	CPUMCTX *pCtx;
782	int rc;
783
784	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
785	if (VBOX_FAILURE(rc))
786	return rc;
787
788	if (pVM->hwaccm.s.vmx.fSupported)
789	{
790	return VMXR0RunGuestCode(pVM, pCtx);
791	}
792	else
793	{
794	Assert(pVM->hwaccm.s.svm.fSupported);
795	return SVMR0RunGuestCode(pVM, pCtx);
796	}
797	}
798
799
800	#ifdef VBOX_STRICT
801	#include <iprt/string.h>
802	/**
803	* Dumps a descriptor.
804	*
805	* @param Desc Descriptor to dump.
806	* @param Sel Selector number.
807	* @param pszMsg Message to prepend the log entry with.
808	*/
809	HWACCMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg)
810	{
811	/*
812	* Make variable description string.
813	*/
814	static struct
815	{
816	unsigned cch;
817	const char *psz;
818	} const aTypes[32] =
819	{
820	#define STRENTRY(str) { sizeof(str) - 1, str }
821
822	/* system */
823	#if HC_ARCH_BITS == 64
824	STRENTRY("Reserved0 "), /* 0x00 */
825	STRENTRY("Reserved1 "), /* 0x01 */
826	STRENTRY("LDT "), /* 0x02 */
827	STRENTRY("Reserved3 "), /* 0x03 */
828	STRENTRY("Reserved4 "), /* 0x04 */
829	STRENTRY("Reserved5 "), /* 0x05 */
830	STRENTRY("Reserved6 "), /* 0x06 */
831	STRENTRY("Reserved7 "), /* 0x07 */
832	STRENTRY("Reserved8 "), /* 0x08 */
833	STRENTRY("TSS64Avail "), /* 0x09 */
834	STRENTRY("ReservedA "), /* 0x0a */
835	STRENTRY("TSS64Busy "), /* 0x0b */
836	STRENTRY("Call64 "), /* 0x0c */
837	STRENTRY("ReservedD "), /* 0x0d */
838	STRENTRY("Int64 "), /* 0x0e */
839	STRENTRY("Trap64 "), /* 0x0f */
840	#else
841	STRENTRY("Reserved0 "), /* 0x00 */
842	STRENTRY("TSS16Avail "), /* 0x01 */
843	STRENTRY("LDT "), /* 0x02 */
844	STRENTRY("TSS16Busy "), /* 0x03 */
845	STRENTRY("Call16 "), /* 0x04 */
846	STRENTRY("Task "), /* 0x05 */
847	STRENTRY("Int16 "), /* 0x06 */
848	STRENTRY("Trap16 "), /* 0x07 */
849	STRENTRY("Reserved8 "), /* 0x08 */
850	STRENTRY("TSS32Avail "), /* 0x09 */
851	STRENTRY("ReservedA "), /* 0x0a */
852	STRENTRY("TSS32Busy "), /* 0x0b */
853	STRENTRY("Call32 "), /* 0x0c */
854	STRENTRY("ReservedD "), /* 0x0d */
855	STRENTRY("Int32 "), /* 0x0e */
856	STRENTRY("Trap32 "), /* 0x0f */
857	#endif
858	/* non system */
859	STRENTRY("DataRO "), /* 0x10 */
860	STRENTRY("DataRO Accessed "), /* 0x11 */
861	STRENTRY("DataRW "), /* 0x12 */
862	STRENTRY("DataRW Accessed "), /* 0x13 */
863	STRENTRY("DataDownRO "), /* 0x14 */
864	STRENTRY("DataDownRO Accessed "), /* 0x15 */
865	STRENTRY("DataDownRW "), /* 0x16 */
866	STRENTRY("DataDownRW Accessed "), /* 0x17 */
867	STRENTRY("CodeEO "), /* 0x18 */
868	STRENTRY("CodeEO Accessed "), /* 0x19 */
869	STRENTRY("CodeER "), /* 0x1a */
870	STRENTRY("CodeER Accessed "), /* 0x1b */
871	STRENTRY("CodeConfEO "), /* 0x1c */
872	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
873	STRENTRY("CodeConfER "), /* 0x1e */
874	STRENTRY("CodeConfER Accessed ") /* 0x1f */
875	#undef SYSENTRY
876	};
877	#define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
878	char szMsg[128];
879	char *psz = &szMsg[0];
880	unsigned i = Desc->Gen.u1DescType << 4 \| Desc->Gen.u4Type;
881	memcpy(psz, aTypes[i].psz, aTypes[i].cch);
882	psz += aTypes[i].cch;
883
884	if (Desc->Gen.u1Present)
885	ADD_STR(psz, "Present ");
886	else
887	ADD_STR(psz, "Not-Present ");
888	#if HC_ARCH_BITS == 64
889	if (Desc->Gen.u1Long)
890	ADD_STR(psz, "64-bit ");
891	else
892	ADD_STR(psz, "Comp ");
893	#else
894	if (Desc->Gen.u1Granularity)
895	ADD_STR(psz, "Page ");
896	if (Desc->Gen.u1DefBig)
897	ADD_STR(psz, "32-bit ");
898	else
899	ADD_STR(psz, "16-bit ");
900	#endif
901	#undef ADD_STR
902	*psz = '\0';
903
904	/*
905	* Limit and Base and format the output.
906	*/
907	uint32_t u32Limit = Desc->Gen.u4LimitHigh << 16 \| Desc->Gen.u16LimitLow;
908	if (Desc->Gen.u1Granularity)
909	u32Limit = u32Limit << PAGE_SHIFT \| PAGE_OFFSET_MASK;
910
911	#if HC_ARCH_BITS == 64
912	uint64_t u32Base = ((uintptr_t)Desc->Gen.u32BaseHigh3 << 32ULL) \| Desc->Gen.u8BaseHigh2 << 24ULL \| Desc->Gen.u8BaseHigh1 << 16ULL \| Desc->Gen.u16BaseLow;
913
914	Log(("%s %04x - %VX64 %VX64 - base=%VX64 limit=%08x dpl=%d %s\n", pszMsg,
915	Sel, Desc->au64[0], Desc->au64[1], u32Base, u32Limit, Desc->Gen.u2Dpl, szMsg));
916	#else
917	uint32_t u32Base = Desc->Gen.u8BaseHigh2 << 24 \| Desc->Gen.u8BaseHigh1 << 16 \| Desc->Gen.u16BaseLow;
918
919	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
920	Sel, Desc->au32[0], Desc->au32[1], u32Base, u32Limit, Desc->Gen.u2Dpl, szMsg));
921	#endif
922	}
923
924	/**
925	* Formats a full register dump.
926	*
927	* @param pCtx The context to format.
928	*/
929	HWACCMR0DECL(void) HWACCMDumpRegs(PCPUMCTX pCtx)
930	{
931	/*
932	* Format the flags.
933	*/
934	static struct
935	{
936	const char pszSet; const char pszClear; uint32_t fFlag;
937	} aFlags[] =
938	{
939	{ "vip",NULL, X86_EFL_VIP },
940	{ "vif",NULL, X86_EFL_VIF },
941	{ "ac", NULL, X86_EFL_AC },
942	{ "vm", NULL, X86_EFL_VM },
943	{ "rf", NULL, X86_EFL_RF },
944	{ "nt", NULL, X86_EFL_NT },
945	{ "ov", "nv", X86_EFL_OF },
946	{ "dn", "up", X86_EFL_DF },
947	{ "ei", "di", X86_EFL_IF },
948	{ "tf", NULL, X86_EFL_TF },
949	{ "nt", "pl", X86_EFL_SF },
950	{ "nz", "zr", X86_EFL_ZF },
951	{ "ac", "na", X86_EFL_AF },
952	{ "po", "pe", X86_EFL_PF },
953	{ "cy", "nc", X86_EFL_CF },
954	};
955	char szEFlags[80];
956	char *psz = szEFlags;
957	uint32_t efl = pCtx->eflags.u32;
958	for (unsigned i = 0; i < ELEMENTS(aFlags); i++)
959	{
960	const char *pszAdd = aFlags[i].fFlag & efl ? aFlags[i].pszSet : aFlags[i].pszClear;
961	if (pszAdd)
962	{
963	strcpy(psz, pszAdd);
964	psz += strlen(pszAdd);
965	*psz++ = ' ';
966	}
967	}
968	psz[-1] = '\0';
969
970
971	/*
972	* Format the registers.
973	*/
974	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
975	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
976	"cs={%04x base=%08x limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
977	"ds={%04x base=%08x limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
978	"es={%04x base=%08x limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
979	"fs={%04x base=%08x limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
980	,
981	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
982	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
983	(RTSEL)pCtx->cs, pCtx->csHid.u32Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr0, pCtx->dr1,
984	(RTSEL)pCtx->ds, pCtx->dsHid.u32Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr2, pCtx->dr3,
985	(RTSEL)pCtx->es, pCtx->esHid.u32Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr4, pCtx->dr5,
986	(RTSEL)pCtx->fs, pCtx->fsHid.u32Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr6, pCtx->dr7));
987
988	Log(("gs={%04x base=%08x limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
989	"ss={%04x base=%08x limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
990	"gdtr=%08x:%04x idtr=%08x:%04x eflags=%08x\n"
991	"ldtr={%04x base=%08x limit=%08x flags=%08x}\n"
992	"tr ={%04x base=%08x limit=%08x flags=%08x}\n"
993	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
994	"FCW=%04x FSW=%04x FTW=%04x\n",
995	(RTSEL)pCtx->gs, pCtx->gsHid.u32Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0, pCtx->cr2,
996	(RTSEL)pCtx->ss, pCtx->ssHid.u32Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3, pCtx->cr4,
997	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
998	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u32Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
999	(RTSEL)pCtx->tr, pCtx->trHid.u32Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1000	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1001	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW));
1002
1003
1004	}
1005	#endif

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp@ 7503

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