HWACCMR0A.asm@ 13182

Last change on this file since 13182 was 13093, checked in by vboxsync, 16 years ago
Compile fixes
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File size: 29.7 KB

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1	; $Id: HWACCMR0A.asm 13093 2008-10-08 16:01:56Z vboxsync $
2	;; @file
3	; VMXM - R0 vmx helpers
4	;
5
6	;
7	; Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	;
9	; This file is part of VirtualBox Open Source Edition (OSE), as
10	; available from http://www.virtualbox.org. This file is free software;
11	; you can redistribute it and/or modify it under the terms of the GNU
12	; General Public License (GPL) as published by the Free Software
13	; Foundation, in version 2 as it comes in the "COPYING" file of the
14	; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	;
17	; Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	; Clara, CA 95054 USA or visit http://www.sun.com if you need
19	; additional information or have any questions.
20	;
21
22	;*******************************************************************************
23	;* Header Files *
24	;*******************************************************************************
25	%include "VBox/asmdefs.mac"
26	%include "VBox/err.mac"
27	%include "VBox/hwacc_vmx.mac"
28	%include "VBox/cpum.mac"
29	%include "VBox/x86.mac"
30
31	%ifdef RT_OS_OS2 ;; @todo fix OMF support in yasm and kick nasm out completely.
32	%macro vmwrite 2,
33	int3
34	%endmacro
35	%define vmlaunch int3
36	%define vmresume int3
37	%define vmsave int3
38	%define vmload int3
39	%define vmrun int3
40	%define clgi int3
41	%define stgi int3
42	%macro invlpga 2,
43	int3
44	%endmacro
45	%endif
46
47	;; This is too risky wrt. stability, performance and correctness.
48	;%define VBOX_WITH_DR6_EXPERIMENT 1
49
50	;; @def MYPUSHAD
51	; Macro generating an equivalent to pushad
52
53	;; @def MYPOPAD
54	; Macro generating an equivalent to popad
55
56	;; @def MYPUSHSEGS
57	; Macro saving all segment registers on the stack.
58	; @param 1 full width register name
59	; @param 2 16-bit regsiter name for \a 1.
60
61	;; @def MYPOPSEGS
62	; Macro restoring all segment registers on the stack
63	; @param 1 full width register name
64	; @param 2 16-bit regsiter name for \a 1.
65
66	%ifdef RT_ARCH_AMD64
67	; Save a host and load the corresponding guest MSR (trashes rdx & rcx)
68	%macro LOADGUESTMSR 2
69	mov rcx, %1
70	rdmsr
71	push rdx
72	push rax
73	mov edx, dword [xSI + %2 + 4]
74	mov eax, dword [xSI + %2]
75	wrmsr
76	%endmacro
77
78	; Save a guest and load the corresponding host MSR (trashes rdx & rcx)
79	; Only really useful for gs kernel base as that one can be changed behind our back (swapgs)
80	%macro LOADHOSTMSREX 2
81	mov rcx, %1
82	rdmsr
83	mov dword [xSI + %2], eax
84	mov dword [xSI + %2 + 4], edx
85	pop rax
86	pop rdx
87	wrmsr
88	%endmacro
89
90	; Load the corresponding host MSR (trashes rdx & rcx)
91	%macro LOADHOSTMSR 1
92	mov rcx, %1
93	pop rax
94	pop rdx
95	wrmsr
96	%endmacro
97
98	%ifdef ASM_CALL64_GCC
99	%macro MYPUSHAD 0
100	push r15
101	push r14
102	push r13
103	push r12
104	push rbx
105	%endmacro
106	%macro MYPOPAD 0
107	pop rbx
108	pop r12
109	pop r13
110	pop r14
111	pop r15
112	%endmacro
113
114	%else ; ASM_CALL64_MSC
115	%macro MYPUSHAD 0
116	push r15
117	push r14
118	push r13
119	push r12
120	push rbx
121	push rsi
122	push rdi
123	%endmacro
124	%macro MYPOPAD 0
125	pop rdi
126	pop rsi
127	pop rbx
128	pop r12
129	pop r13
130	pop r14
131	pop r15
132	%endmacro
133	%endif
134
135	; trashes, rax, rdx & rcx
136	%macro MYPUSHSEGS 2
137	mov %2, es
138	push %1
139	mov %2, ds
140	push %1
141
142	; Special case for FS; Windows and Linux either don't use it or restore it when leaving kernel mode, Solaris OTOH doesn't and we must save it.
143	mov ecx, MSR_K8_FS_BASE
144	rdmsr
145	push rdx
146	push rax
147	push fs
148
149	; Special case for GS; OSes typically use swapgs to reset the hidden base register for GS on entry into the kernel. The same happens on exit
150	mov ecx, MSR_K8_GS_BASE
151	rdmsr
152	push rdx
153	push rax
154	push gs
155	%endmacro
156
157	; trashes, rax, rdx & rcx
158	%macro MYPOPSEGS 2
159	; Note: do not step through this code with a debugger!
160	pop gs
161	pop rax
162	pop rdx
163	mov ecx, MSR_K8_GS_BASE
164	wrmsr
165
166	pop fs
167	pop rax
168	pop rdx
169	mov ecx, MSR_K8_FS_BASE
170	wrmsr
171	; Now it's safe to step again
172
173	pop %1
174	mov ds, %2
175	pop %1
176	mov es, %2
177	%endmacro
178
179	%else ; RT_ARCH_X86
180	%macro MYPUSHAD 0
181	pushad
182	%endmacro
183	%macro MYPOPAD 0
184	popad
185	%endmacro
186
187	%macro MYPUSHSEGS 2
188	push ds
189	push es
190	push fs
191	push gs
192	%endmacro
193	%macro MYPOPSEGS 2
194	pop gs
195	pop fs
196	pop es
197	pop ds
198	%endmacro
199	%endif
200
201
202	BEGINCODE
203
204	;/**
205	; * Prepares for and executes VMLAUNCH/VMRESUME (32 bits guest mode)
206	; *
207	; * @returns VBox status code
208	; * @param fResume vmlauch/vmresume
209	; * @param pCtx Guest context
210	; */
211	BEGINPROC VMXR0StartVM32
212	push xBP
213	mov xBP, xSP
214
215	pushf
216	cli
217
218	;/* First we have to save some final CPU context registers. */
219	%ifdef RT_ARCH_AMD64
220	mov rax, qword .vmlaunch_done
221	push rax
222	%else
223	push .vmlaunch_done
224	%endif
225	mov eax, VMX_VMCS_HOST_RIP ;/* return address (too difficult to continue after VMLAUNCH?) */
226	vmwrite xAX, [xSP]
227	;/* Note: assumes success... */
228	add xSP, xS
229
230	;/* Manual save and restore:
231	; * - General purpose registers except RIP, RSP
232	; *
233	; * Trashed:
234	; * - CR2 (we don't care)
235	; * - LDTR (reset to 0)
236	; * - DRx (presumably not changed at all)
237	; * - DR7 (reset to 0x400)
238	; * - EFLAGS (reset to RT_BIT(1); not relevant)
239	; *
240	; */
241
242	;/* Save all general purpose host registers. */
243	MYPUSHAD
244
245	;/* Save the Guest CPU context pointer. */
246	%ifdef RT_ARCH_AMD64
247	%ifdef ASM_CALL64_GCC
248	; fResume already in rdi
249	; pCtx already in rsi
250	%else
251	mov rdi, rcx ; fResume
252	mov rsi, rdx ; pCtx
253	%endif
254	%else
255	mov edi, [ebp + 8] ; fResume
256	mov esi, [ebp + 12] ; pCtx
257	%endif
258
259	;/* Save segment registers */
260	; Note: MYPUSHSEGS trashes rdx & rcx, so we moved it here (msvc amd64 case)
261	MYPUSHSEGS xAX, ax
262
263	; Save the pCtx pointer
264	push xSI
265
266	; Save LDTR
267	xor eax, eax
268	sldt ax
269	push xAX
270
271	; VMX only saves the base of the GDTR & IDTR and resets the limit to 0xffff; we must restore the limit correctly!
272	sub xSP, xS*2
273	sgdt [xSP]
274
275	sub xSP, xS*2
276	sidt [xSP]
277
278	%ifdef VBOX_WITH_DR6_EXPERIMENT
279	; Restore DR6 - experiment, not safe!
280	mov xBX, [xSI + CPUMCTX.dr6]
281	mov dr6, xBX
282	%endif
283
284	; Restore CR2
285	mov ebx, [xSI + CPUMCTX.cr2]
286	mov cr2, xBX
287
288	mov eax, VMX_VMCS_HOST_RSP
289	vmwrite xAX, xSP
290	;/* Note: assumes success... */
291	;/* Don't mess with ESP anymore!! */
292
293	;/* Restore Guest's general purpose registers. */
294	mov eax, [xSI + CPUMCTX.eax]
295	mov ebx, [xSI + CPUMCTX.ebx]
296	mov ecx, [xSI + CPUMCTX.ecx]
297	mov edx, [xSI + CPUMCTX.edx]
298	mov ebp, [xSI + CPUMCTX.ebp]
299
300	; resume or start?
301	cmp xDI, 0 ; fResume
302	je .vmlauch_lauch
303
304	;/* Restore edi & esi. */
305	mov edi, [xSI + CPUMCTX.edi]
306	mov esi, [xSI + CPUMCTX.esi]
307
308	vmresume
309	jmp .vmlaunch_done; ;/* here if vmresume detected a failure. */
310
311	.vmlauch_lauch:
312	;/* Restore edi & esi. */
313	mov edi, [xSI + CPUMCTX.edi]
314	mov esi, [xSI + CPUMCTX.esi]
315
316	vmlaunch
317	jmp .vmlaunch_done; ;/* here if vmlaunch detected a failure. */
318
319	ALIGNCODE(16)
320	.vmlaunch_done:
321	jc near .vmxstart_invalid_vmxon_ptr
322	jz near .vmxstart_start_failed
323
324	; Restore base and limit of the IDTR & GDTR
325	lidt [xSP]
326	add xSP, xS*2
327	lgdt [xSP]
328	add xSP, xS*2
329
330	push xDI
331	mov xDI, [xSP + xS * 2] ; pCtx
332
333	mov [ss:xDI + CPUMCTX.eax], eax
334	mov [ss:xDI + CPUMCTX.ebx], ebx
335	mov [ss:xDI + CPUMCTX.ecx], ecx
336	mov [ss:xDI + CPUMCTX.edx], edx
337	mov [ss:xDI + CPUMCTX.esi], esi
338	mov [ss:xDI + CPUMCTX.ebp], ebp
339	%ifdef RT_ARCH_AMD64
340	pop xAX ; the guest edi we pushed above
341	mov dword [ss:xDI + CPUMCTX.edi], eax
342	%else
343	pop dword [ss:xDI + CPUMCTX.edi] ; the guest edi we pushed above
344	%endif
345
346	%ifdef VBOX_WITH_DR6_EXPERIMENT
347	; Save DR6 - experiment, not safe!
348	mov xAX, dr6
349	mov [ss:xDI + CPUMCTX.dr6], xAX
350	%endif
351
352	pop xAX ; saved LDTR
353	lldt ax
354
355	add xSP, xS ; pCtx
356
357	; Restore segment registers
358	MYPOPSEGS xAX, ax
359
360	; Restore general purpose registers
361	MYPOPAD
362
363	mov eax, VINF_SUCCESS
364
365	.vmstart_end:
366	popf
367	pop xBP
368	ret
369
370
371	.vmxstart_invalid_vmxon_ptr:
372	; Restore base and limit of the IDTR & GDTR
373	lidt [xSP]
374	add xSP, xS*2
375	lgdt [xSP]
376	add xSP, xS*2
377
378	pop xAX ; saved LDTR
379	lldt ax
380
381	add xSP, xS ; pCtx
382
383	; Restore segment registers
384	MYPOPSEGS xAX, ax
385
386	; Restore all general purpose host registers.
387	MYPOPAD
388	mov eax, VERR_VMX_INVALID_VMXON_PTR
389	jmp .vmstart_end
390
391	.vmxstart_start_failed:
392	; Restore base and limit of the IDTR & GDTR
393	lidt [xSP]
394	add xSP, xS*2
395	lgdt [xSP]
396	add xSP, xS*2
397
398	pop xAX ; saved LDTR
399	lldt ax
400
401	add xSP, xS ; pCtx
402
403	; Restore segment registers
404	MYPOPSEGS xAX, ax
405
406	; Restore all general purpose host registers.
407	MYPOPAD
408	mov eax, VERR_VMX_UNABLE_TO_START_VM
409	jmp .vmstart_end
410
411	ENDPROC VMXR0StartVM32
412
413	%ifdef RT_ARCH_AMD64
414	;/**
415	; * Prepares for and executes VMLAUNCH/VMRESUME (64 bits guest mode)
416	; *
417	; * @returns VBox status code
418	; * @param fResume vmlauch/vmresume
419	; * @param pCtx Guest context
420	; */
421	BEGINPROC VMXR0StartVM64
422	push xBP
423	mov xBP, xSP
424
425	pushf
426	cli
427
428	;/* First we have to save some final CPU context registers. */
429	mov rax, qword .vmlaunch64_done
430	push rax
431	mov rax, VMX_VMCS_HOST_RIP ;/* return address (too difficult to continue after VMLAUNCH?) */
432	vmwrite rax, [xSP]
433	;/* Note: assumes success... */
434	add xSP, xS
435
436	;/* Manual save and restore:
437	; * - General purpose registers except RIP, RSP
438	; *
439	; * Trashed:
440	; * - CR2 (we don't care)
441	; * - LDTR (reset to 0)
442	; * - DRx (presumably not changed at all)
443	; * - DR7 (reset to 0x400)
444	; * - EFLAGS (reset to RT_BIT(1); not relevant)
445	; *
446	; */
447
448	;/* Save all general purpose host registers. */
449	MYPUSHAD
450
451	;/* Save the Guest CPU context pointer. */
452	%ifdef ASM_CALL64_GCC
453	; fResume already in rdi
454	; pCtx already in rsi
455	%else
456	mov rdi, rcx ; fResume
457	mov rsi, rdx ; pCtx
458	%endif
459
460	;/* Save segment registers */
461	; Note: MYPUSHSEGS trashes rdx & rcx, so we moved it here (msvc amd64 case)
462	MYPUSHSEGS xAX, ax
463
464	; Save the host LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs and restore the guest MSRs
465	;; @todo use the automatic load feature for MSRs
466	LOADGUESTMSR MSR_K8_LSTAR, CPUMCTX.msrLSTAR
467	%if 0 ; not supported on Intel CPUs
468	LOADGUESTMSR MSR_K8_CSTAR, CPUMCTX.msrCSTAR
469	%endif
470	LOADGUESTMSR MSR_K6_STAR, CPUMCTX.msrSTAR
471	LOADGUESTMSR MSR_K8_SF_MASK, CPUMCTX.msrSFMASK
472	LOADGUESTMSR MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
473
474	; Save the pCtx pointer
475	push xSI
476
477	; Save LDTR
478	xor eax, eax
479	sldt ax
480	push xAX
481
482	; VMX only saves the base of the GDTR & IDTR and resets the limit to 0xffff; we must restore the limit correctly!
483	sub xSP, xS*2
484	sgdt [xSP]
485
486	sub xSP, xS*2
487	sidt [xSP]
488
489	%ifdef VBOX_WITH_DR6_EXPERIMENT
490	; Restore DR6 - experiment, not safe!
491	mov xBX, [xSI + CPUMCTX.dr6]
492	mov dr6, xBX
493	%endif
494
495	; Restore CR2
496	mov rbx, qword [xSI + CPUMCTX.cr2]
497	mov cr2, rbx
498
499	mov eax, VMX_VMCS_HOST_RSP
500	vmwrite xAX, xSP
501	;/* Note: assumes success... */
502	;/* Don't mess with ESP anymore!! */
503
504	;/* Restore Guest's general purpose registers. */
505	mov rax, qword [xSI + CPUMCTX.eax]
506	mov rbx, qword [xSI + CPUMCTX.ebx]
507	mov rcx, qword [xSI + CPUMCTX.ecx]
508	mov rdx, qword [xSI + CPUMCTX.edx]
509	mov rbp, qword [xSI + CPUMCTX.ebp]
510	mov r8, qword [xSI + CPUMCTX.r8]
511	mov r9, qword [xSI + CPUMCTX.r9]
512	mov r10, qword [xSI + CPUMCTX.r10]
513	mov r11, qword [xSI + CPUMCTX.r11]
514	mov r12, qword [xSI + CPUMCTX.r12]
515	mov r13, qword [xSI + CPUMCTX.r13]
516	mov r14, qword [xSI + CPUMCTX.r14]
517	mov r15, qword [xSI + CPUMCTX.r15]
518
519	; resume or start?
520	cmp xDI, 0 ; fResume
521	je .vmlauch64_lauch
522
523	;/* Restore edi & esi. */
524	mov rdi, qword [xSI + CPUMCTX.edi]
525	mov rsi, qword [xSI + CPUMCTX.esi]
526
527	vmresume
528	jmp .vmlaunch64_done; ;/* here if vmresume detected a failure. */
529
530	.vmlauch64_lauch:
531	;/* Restore rdi & rsi. */
532	mov rdi, qword [xSI + CPUMCTX.edi]
533	mov rsi, qword [xSI + CPUMCTX.esi]
534
535	vmlaunch
536	jmp .vmlaunch64_done; ;/* here if vmlaunch detected a failure. */
537
538	ALIGNCODE(16)
539	.vmlaunch64_done:
540	jc near .vmxstart64_invalid_vmxon_ptr
541	jz near .vmxstart64_start_failed
542
543	; Restore base and limit of the IDTR & GDTR
544	lidt [xSP]
545	add xSP, xS*2
546	lgdt [xSP]
547	add xSP, xS*2
548
549	push xDI
550	mov xDI, [xSP + xS * 2] ; pCtx
551
552	mov qword [xDI + CPUMCTX.eax], rax
553	mov qword [xDI + CPUMCTX.ebx], rbx
554	mov qword [xDI + CPUMCTX.ecx], rcx
555	mov qword [xDI + CPUMCTX.edx], rdx
556	mov qword [xDI + CPUMCTX.esi], rsi
557	mov qword [xDI + CPUMCTX.ebp], rbp
558	mov qword [xDI + CPUMCTX.r8], r8
559	mov qword [xDI + CPUMCTX.r9], r9
560	mov qword [xDI + CPUMCTX.r10], r10
561	mov qword [xDI + CPUMCTX.r11], r11
562	mov qword [xDI + CPUMCTX.r12], r12
563	mov qword [xDI + CPUMCTX.r13], r13
564	mov qword [xDI + CPUMCTX.r14], r14
565	mov qword [xDI + CPUMCTX.r15], r15
566
567	pop xAX ; the guest edi we pushed above
568	mov qword [xDI + CPUMCTX.edi], rax
569
570	%ifdef VBOX_WITH_DR6_EXPERIMENT
571	; Save DR6 - experiment, not safe!
572	mov xAX, dr6
573	mov [xDI + CPUMCTX.dr6], xAX
574	%endif
575
576	pop xAX ; saved LDTR
577	lldt ax
578
579	pop xSI ; pCtx (needed in rsi by the macros below)
580
581	; Restore the host LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs
582	;; @todo use the automatic load feature for MSRs
583	LOADHOSTMSREX MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
584	LOADHOSTMSR MSR_K8_SF_MASK
585	LOADHOSTMSR MSR_K6_STAR
586	%if 0 ; not supported on Intel CPUs
587	LOADHOSTMSR MSR_K8_CSTAR
588	%endif
589	LOADHOSTMSR MSR_K8_LSTAR
590
591	; Restore segment registers
592	MYPOPSEGS xAX, ax
593
594	; Restore general purpose registers
595	MYPOPAD
596
597	mov eax, VINF_SUCCESS
598
599	.vmstart64_end:
600	popf
601	pop xBP
602	ret
603
604
605	.vmxstart64_invalid_vmxon_ptr:
606	; Restore base and limit of the IDTR & GDTR
607	lidt [xSP]
608	add xSP, xS*2
609	lgdt [xSP]
610	add xSP, xS*2
611
612	pop xAX ; saved LDTR
613	lldt ax
614
615	pop xSI ; pCtx (needed in rsi by the macros below)
616
617	; Restore the host LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs
618	;; @todo use the automatic load feature for MSRs
619	LOADHOSTMSREX MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
620	LOADHOSTMSR MSR_K8_SF_MASK
621	%if 0 ; not supported on Intel CPUs
622	LOADHOSTMSR MSR_K8_CSTAR
623	%endif
624	LOADHOSTMSR MSR_K8_LSTAR
625
626	; Restore segment registers
627	MYPOPSEGS xAX, ax
628
629	; Restore all general purpose host registers.
630	MYPOPAD
631	mov eax, VERR_VMX_INVALID_VMXON_PTR
632	jmp .vmstart64_end
633
634	.vmxstart64_start_failed:
635	; Restore base and limit of the IDTR & GDTR
636	lidt [xSP]
637	add xSP, xS*2
638	lgdt [xSP]
639	add xSP, xS*2
640
641	pop xAX ; saved LDTR
642	lldt ax
643
644	pop xSI ; pCtx (needed in rsi by the macros below)
645
646	; Restore the host LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs
647	;; @todo use the automatic load feature for MSRs
648	LOADHOSTMSREX MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
649	LOADHOSTMSR MSR_K8_SF_MASK
650	%if 0 ; not supported on Intel CPUs
651	LOADHOSTMSR MSR_K8_CSTAR
652	%endif
653	LOADHOSTMSR MSR_K8_LSTAR
654
655	; Restore segment registers
656	MYPOPSEGS xAX, ax
657
658	; Restore all general purpose host registers.
659	MYPOPAD
660	mov eax, VERR_VMX_UNABLE_TO_START_VM
661	jmp .vmstart64_end
662	ENDPROC VMXR0StartVM64
663
664	;/**
665	; * Executes VMWRITE
666	; *
667	; * @returns VBox status code
668	; * @param idxField x86: [ebp + 08h] msc: rcx gcc: rdi VMCS index
669	; * @param pData x86: [ebp + 0ch] msc: rdx gcc: rsi VM field value
670	; */
671	BEGINPROC VMXWriteVMCS64
672	%ifdef ASM_CALL64_GCC
673	mov eax, 0ffffffffh
674	and rdi, rax
675	xor rax, rax
676	vmwrite rdi, rsi
677	%else
678	mov eax, 0ffffffffh
679	and rcx, rax
680	xor rax, rax
681	vmwrite rcx, rdx
682	%endif
683	jnc .valid_vmcs
684	mov eax, VERR_VMX_INVALID_VMCS_PTR
685	ret
686	.valid_vmcs:
687	jnz .the_end
688	mov eax, VERR_VMX_INVALID_VMCS_FIELD
689	.the_end:
690	ret
691	ENDPROC VMXWriteVMCS64
692
693	;/**
694	; * Executes VMREAD
695	; *
696	; * @returns VBox status code
697	; * @param idxField VMCS index
698	; * @param pData Ptr to store VM field value
699	; */
700	;DECLASM(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData);
701	BEGINPROC VMXReadVMCS64
702	%ifdef ASM_CALL64_GCC
703	mov eax, 0ffffffffh
704	and rdi, rax
705	xor rax, rax
706	vmread [rsi], rdi
707	%else
708	mov eax, 0ffffffffh
709	and rcx, rax
710	xor rax, rax
711	vmread [rdx], rcx
712	%endif
713	jnc .valid_vmcs
714	mov eax, VERR_VMX_INVALID_VMCS_PTR
715	ret
716	.valid_vmcs:
717	jnz .the_end
718	mov eax, VERR_VMX_INVALID_VMCS_FIELD
719	.the_end:
720	ret
721	ENDPROC VMXReadVMCS64
722
723
724	;/**
725	; * Executes VMXON
726	; *
727	; * @returns VBox status code
728	; * @param HCPhysVMXOn Physical address of VMXON structure
729	; */
730	;DECLASM(int) VMXEnable(RTHCPHYS HCPhysVMXOn);
731	BEGINPROC VMXEnable
732	%ifdef RT_ARCH_AMD64
733	xor rax, rax
734	%ifdef ASM_CALL64_GCC
735	push rdi
736	%else
737	push rcx
738	%endif
739	vmxon [rsp]
740	%else
741	xor eax, eax
742	vmxon [esp + 4]
743	%endif
744	jnc .good
745	mov eax, VERR_VMX_INVALID_VMXON_PTR
746	jmp .the_end
747
748	.good:
749	jnz .the_end
750	mov eax, VERR_VMX_GENERIC
751
752	.the_end:
753	%ifdef RT_ARCH_AMD64
754	add rsp, 8
755	%endif
756	ret
757	ENDPROC VMXEnable
758
759	;/**
760	; * Executes VMXOFF
761	; */
762	;DECLASM(void) VMXDisable(void);
763	BEGINPROC VMXDisable
764	vmxoff
765	ret
766	ENDPROC VMXDisable
767
768
769	;/**
770	; * Executes VMCLEAR
771	; *
772	; * @returns VBox status code
773	; * @param HCPhysVMCS Physical address of VM control structure
774	; */
775	;DECLASM(int) VMXClearVMCS(RTHCPHYS HCPhysVMCS);
776	BEGINPROC VMXClearVMCS
777	%ifdef RT_ARCH_AMD64
778	xor rax, rax
779	%ifdef ASM_CALL64_GCC
780	push rdi
781	%else
782	push rcx
783	%endif
784	vmclear [rsp]
785	%else
786	xor eax, eax
787	vmclear [esp + 4]
788	%endif
789	jnc .the_end
790	mov eax, VERR_VMX_INVALID_VMCS_PTR
791	.the_end:
792	%ifdef RT_ARCH_AMD64
793	add rsp, 8
794	%endif
795	ret
796	ENDPROC VMXClearVMCS
797
798
799	;/**
800	; * Executes VMPTRLD
801	; *
802	; * @returns VBox status code
803	; * @param HCPhysVMCS Physical address of VMCS structure
804	; */
805	;DECLASM(int) VMXActivateVMCS(RTHCPHYS HCPhysVMCS);
806	BEGINPROC VMXActivateVMCS
807	%ifdef RT_ARCH_AMD64
808	xor rax, rax
809	%ifdef ASM_CALL64_GCC
810	push rdi
811	%else
812	push rcx
813	%endif
814	vmptrld [rsp]
815	%else
816	xor eax, eax
817	vmptrld [esp + 4]
818	%endif
819	jnc .the_end
820	mov eax, VERR_VMX_INVALID_VMCS_PTR
821	.the_end:
822	%ifdef RT_ARCH_AMD64
823	add rsp, 8
824	%endif
825	ret
826	ENDPROC VMXActivateVMCS
827
828	%endif ; RT_ARCH_AMD64
829
830	;/**
831	; * Executes VMPTRST
832	; *
833	; * @returns VBox status code
834	; * @param [esp + 04h] gcc:rdi msc:rcx Param 1 - First parameter - Address that will receive the current pointer
835	; */
836	;DECLASM(int) VMXGetActivateVMCS(RTHCPHYS *pVMCS);
837	BEGINPROC VMXGetActivateVMCS
838	%ifdef RT_ARCH_AMD64
839	%ifdef ASM_CALL64_GCC
840	vmptrst qword [rdi]
841	%else
842	vmptrst qword [rcx]
843	%endif
844	%else
845	vmptrst qword [esp+04h]
846	%endif
847	xor eax, eax
848	ret
849	ENDPROC VMXGetActivateVMCS
850
851	;/**
852	; * Invalidate a page using invept
853	; @param enmFlush msc:ecx gcc:edi x86:[esp+04] Type of flush
854	; @param pDescriptor msc:edx gcc:esi x86:[esp+08] Descriptor pointer
855	; */
856	;DECLASM(int) VMXR0InvEPT(VMX_FLUSH enmFlush, uint64_t *pDescriptor);
857	BEGINPROC VMXR0InvEPT
858	%ifdef RT_ARCH_AMD64
859	%ifdef ASM_CALL64_GCC
860	mov eax, 0ffffffffh
861	and rdi, rax
862	xor rax, rax
863	; invept rdi, qword [rsi]
864	DB 0x66, 0x0F, 0x38, 0x80, 0x3E
865	%else
866	mov eax, 0ffffffffh
867	and rcx, rax
868	xor rax, rax
869	; invept rcx, qword [rdx]
870	DB 0x66, 0x0F, 0x38, 0x80, 0xA
871	%endif
872	%else
873	mov eax, [esp + 4]
874	mov ecx, [esp + 8]
875	; invept eax, qword [ecx]
876	DB 0x66, 0x0F, 0x38, 0x80, 0x1
877	%endif
878	jnc .valid_vmcs
879	mov eax, VERR_VMX_INVALID_VMCS_PTR
880	ret
881	.valid_vmcs:
882	jnz .the_end
883	mov eax, VERR_INVALID_PARAMETER
884	.the_end:
885	ret
886	ENDPROC VMXR0InvEPT
887
888	;/**
889	; * Invalidate a page using invvpid
890	; @param enmFlush msc:ecx gcc:edi x86:[esp+04] Type of flush
891	; @param pDescriptor msc:edx gcc:esi x86:[esp+08] Descriptor pointer
892	; */
893	;DECLASM(int) VMXR0InvVPID(VMX_FLUSH enmFlush, uint64_t *pDescriptor);
894	BEGINPROC VMXR0InvVPID
895	%ifdef RT_ARCH_AMD64
896	%ifdef ASM_CALL64_GCC
897	mov eax, 0ffffffffh
898	and rdi, rax
899	xor rax, rax
900	;invvpid rdi, qword [rsi]
901	DB 0x66, 0x0F, 0x38, 0x81, 0x3E
902	%else
903	mov eax, 0ffffffffh
904	and rcx, rax
905	xor rax, rax
906	; invvpid rcx, qword [rdx]
907	DB 0x66, 0x0F, 0x38, 0x81, 0xA
908	%endif
909	%else
910	mov eax, [esp + 4]
911	mov ecx, [esp + 8]
912	; invept eax, qword [ecx]
913	DB 0x66, 0x0F, 0x38, 0x81, 0x1
914	%endif
915	jnc .valid_vmcs
916	mov eax, VERR_VMX_INVALID_VMCS_PTR
917	ret
918	.valid_vmcs:
919	jnz .the_end
920	mov eax, VERR_INVALID_PARAMETER
921	.the_end:
922	ret
923	ENDPROC VMXR0InvVPID
924
925
926	;/**
927	; * Prepares for and executes VMRUN (32 bits guests)
928	; *
929	; * @returns VBox status code
930	; * @param HCPhysVMCB Physical address of host VMCB
931	; * @param HCPhysVMCB Physical address of guest VMCB
932	; * @param pCtx Guest context
933	; */
934	BEGINPROC SVMVMRun
935	%ifdef RT_ARCH_AMD64 ; fake a cdecl stack frame
936	%ifdef ASM_CALL64_GCC
937	push rdx
938	push rsi
939	push rdi
940	%else
941	push r8
942	push rdx
943	push rcx
944	%endif
945	push 0
946	%endif
947	push xBP
948	mov xBP, xSP
949	pushf
950
951	;/* Manual save and restore:
952	; * - General purpose registers except RIP, RSP, RAX
953	; *
954	; * Trashed:
955	; * - CR2 (we don't care)
956	; * - LDTR (reset to 0)
957	; * - DRx (presumably not changed at all)
958	; * - DR7 (reset to 0x400)
959	; */
960
961	;/* Save all general purpose host registers. */
962	MYPUSHAD
963
964	;/* Save the Guest CPU context pointer. */
965	mov xSI, [xBP + xS2 + RTHCPHYS_CB2] ; pCtx
966	push xSI ; push for saving the state at the end
967
968	; Restore CR2
969	mov ebx, [xSI + CPUMCTX.cr2]
970	mov cr2, xBX
971
972	; save host fs, gs, sysenter msr etc
973	mov xAX, [xBP + xS*2] ; pVMCBHostPhys (64 bits physical address; x86: take low dword only)
974	push xAX ; save for the vmload after vmrun
975	vmsave
976
977	; setup eax for VMLOAD
978	mov xAX, [xBP + xS*2 + RTHCPHYS_CB] ; pVMCBPhys (64 bits physical address; take low dword only)
979
980	;/* Restore Guest's general purpose registers. */
981	;/* EAX is loaded from the VMCB by VMRUN */
982	mov ebx, [xSI + CPUMCTX.ebx]
983	mov ecx, [xSI + CPUMCTX.ecx]
984	mov edx, [xSI + CPUMCTX.edx]
985	mov edi, [xSI + CPUMCTX.edi]
986	mov ebp, [xSI + CPUMCTX.ebp]
987	mov esi, [xSI + CPUMCTX.esi]
988
989	; Clear the global interrupt flag & execute sti to make sure external interrupts cause a world switch
990	clgi
991	sti
992
993	; load guest fs, gs, sysenter msr etc
994	vmload
995	; run the VM
996	vmrun
997
998	;/* EAX is in the VMCB already; we can use it here. */
999
1000	; save guest fs, gs, sysenter msr etc
1001	vmsave
1002
1003	; load host fs, gs, sysenter msr etc
1004	pop xAX ; pushed above
1005	vmload
1006
1007	; Set the global interrupt flag again, but execute cli to make sure IF=0.
1008	cli
1009	stgi
1010
1011	pop xAX ; pCtx
1012
1013	mov [ss:xAX + CPUMCTX.ebx], ebx
1014	mov [ss:xAX + CPUMCTX.ecx], ecx
1015	mov [ss:xAX + CPUMCTX.edx], edx
1016	mov [ss:xAX + CPUMCTX.esi], esi
1017	mov [ss:xAX + CPUMCTX.edi], edi
1018	mov [ss:xAX + CPUMCTX.ebp], ebp
1019
1020	; Restore general purpose registers
1021	MYPOPAD
1022
1023	mov eax, VINF_SUCCESS
1024
1025	popf
1026	pop xBP
1027	%ifdef RT_ARCH_AMD64
1028	add xSP, 4*xS
1029	%endif
1030	ret
1031	ENDPROC SVMVMRun
1032
1033	%ifdef RT_ARCH_AMD64
1034	;/**
1035	; * Prepares for and executes VMRUN (64 bits guests)
1036	; *
1037	; * @returns VBox status code
1038	; * @param HCPhysVMCB Physical address of host VMCB
1039	; * @param HCPhysVMCB Physical address of guest VMCB
1040	; * @param pCtx Guest context
1041	; */
1042	BEGINPROC SVMVMRun64
1043	; fake a cdecl stack frame
1044	%ifdef ASM_CALL64_GCC
1045	push rdx
1046	push rsi
1047	push rdi
1048	%else
1049	push r8
1050	push rdx
1051	push rcx
1052	%endif
1053	push 0
1054	push rbp
1055	mov rbp, rsp
1056	pushf
1057
1058	;/* Manual save and restore:
1059	; * - General purpose registers except RIP, RSP, RAX
1060	; *
1061	; * Trashed:
1062	; * - CR2 (we don't care)
1063	; * - LDTR (reset to 0)
1064	; * - DRx (presumably not changed at all)
1065	; * - DR7 (reset to 0x400)
1066	; */
1067
1068	;/* Save all general purpose host registers. */
1069	MYPUSHAD
1070
1071	;/* Save the Guest CPU context pointer. */
1072	mov rsi, [rbp + xS2 + RTHCPHYS_CB2] ; pCtx
1073	push rsi ; push for saving the state at the end
1074
1075	; Restore CR2
1076	mov rbx, [rsi + CPUMCTX.cr2]
1077	mov cr2, rbx
1078
1079	; save host fs, gs, sysenter msr etc
1080	mov rax, [rbp + xS*2] ; pVMCBHostPhys (64 bits physical address; x86: take low dword only)
1081	push rax ; save for the vmload after vmrun
1082	vmsave
1083
1084	; setup eax for VMLOAD
1085	mov rax, [rbp + xS*2 + RTHCPHYS_CB] ; pVMCBPhys (64 bits physical address; take low dword only)
1086
1087	;/* Restore Guest's general purpose registers. */
1088	;/* RAX is loaded from the VMCB by VMRUN */
1089	mov rbx, qword [xSI + CPUMCTX.ebx]
1090	mov rcx, qword [xSI + CPUMCTX.ecx]
1091	mov rdx, qword [xSI + CPUMCTX.edx]
1092	mov rdi, qword [xSI + CPUMCTX.edi]
1093	mov rbp, qword [xSI + CPUMCTX.ebp]
1094	mov r8, qword [xSI + CPUMCTX.r8]
1095	mov r9, qword [xSI + CPUMCTX.r9]
1096	mov r10, qword [xSI + CPUMCTX.r10]
1097	mov r11, qword [xSI + CPUMCTX.r11]
1098	mov r12, qword [xSI + CPUMCTX.r12]
1099	mov r13, qword [xSI + CPUMCTX.r13]
1100	mov r14, qword [xSI + CPUMCTX.r14]
1101	mov r15, qword [xSI + CPUMCTX.r15]
1102	mov rsi, qword [xSI + CPUMCTX.esi]
1103
1104	; Clear the global interrupt flag & execute sti to make sure external interrupts cause a world switch
1105	clgi
1106	sti
1107
1108	; load guest fs, gs, sysenter msr etc
1109	vmload
1110	; run the VM
1111	vmrun
1112
1113	;/* RAX is in the VMCB already; we can use it here. */
1114
1115	; save guest fs, gs, sysenter msr etc
1116	vmsave
1117
1118	; load host fs, gs, sysenter msr etc
1119	pop rax ; pushed above
1120	vmload
1121
1122	; Set the global interrupt flag again, but execute cli to make sure IF=0.
1123	cli
1124	stgi
1125
1126	pop rax ; pCtx
1127
1128	mov qword [rax + CPUMCTX.ebx], rbx
1129	mov qword [rax + CPUMCTX.ecx], rcx
1130	mov qword [rax + CPUMCTX.edx], rdx
1131	mov qword [rax + CPUMCTX.esi], rsi
1132	mov qword [rax + CPUMCTX.edi], rdi
1133	mov qword [rax + CPUMCTX.ebp], rbp
1134	mov qword [rax + CPUMCTX.r8], r8
1135	mov qword [rax + CPUMCTX.r9], r9
1136	mov qword [rax + CPUMCTX.r10], r10
1137	mov qword [rax + CPUMCTX.r11], r11
1138	mov qword [rax + CPUMCTX.r12], r12
1139	mov qword [rax + CPUMCTX.r13], r13
1140	mov qword [rax + CPUMCTX.r14], r14
1141	mov qword [rax + CPUMCTX.r15], r15
1142
1143	; Restore general purpose registers
1144	MYPOPAD
1145
1146	mov eax, VINF_SUCCESS
1147
1148	popf
1149	pop rbp
1150	add rsp, 4*xS
1151	ret
1152	ENDPROC SVMVMRun64
1153	%endif ; RT_ARCH_AMD64
1154
1155
1156	%if GC_ARCH_BITS == 64
1157	;;
1158	; Executes INVLPGA
1159	;
1160	; @param pPageGC msc:rcx gcc:rdi x86:[esp+04] Virtual page to invalidate
1161	; @param uASID msc:rdx gcc:rsi x86:[esp+0C] Tagged TLB id
1162	;
1163	;DECLASM(void) SVMInvlpgA(RTGCPTR pPageGC, uint32_t uASID);
1164	BEGINPROC SVMInvlpgA
1165	%ifdef RT_ARCH_AMD64
1166	%ifdef ASM_CALL64_GCC
1167	mov rax, rdi
1168	mov rcx, rsi
1169	%else
1170	; from http://www.cs.cmu.edu/~fp/courses/15213-s06/misc/asm64-handout.pdf:
1171	; ``Perhaps unexpectedly, instructions that move or generate 32-bit register
1172	; values also set the upper 32 bits of the register to zero. Consequently
1173	; there is no need for an instruction movzlq.''
1174	mov eax, ecx
1175	mov rcx, rdx
1176	%endif
1177	%else
1178	mov eax, [esp + 4]
1179	mov ecx, [esp + 0Ch]
1180	%endif
1181	invlpga [xAX], ecx
1182	ret
1183	ENDPROC SVMInvlpgA
1184
1185	%else
1186	;;
1187	; Executes INVLPGA
1188	;
1189	; @param pPageGC msc:ecx gcc:edi x86:[esp+04] Virtual page to invalidate
1190	; @param uASID msc:edx gcc:esi x86:[esp+08] Tagged TLB id
1191	;
1192	;DECLASM(void) SVMInvlpgA(RTGCPTR pPageGC, uint32_t uASID);
1193	BEGINPROC SVMInvlpgA
1194	%ifdef RT_ARCH_AMD64
1195	%ifdef ASM_CALL64_GCC
1196	movzx rax, edi
1197	mov ecx, esi
1198	%else
1199	; from http://www.cs.cmu.edu/~fp/courses/15213-s06/misc/asm64-handout.pdf:
1200	; ``Perhaps unexpectedly, instructions that move or generate 32-bit register
1201	; values also set the upper 32 bits of the register to zero. Consequently
1202	; there is no need for an instruction movzlq.''
1203	mov eax, ecx
1204	mov ecx, edx
1205	%endif
1206	%else
1207	mov eax, [esp + 4]
1208	mov ecx, [esp + 8]
1209	%endif
1210	invlpga [xAX], ecx
1211	ret
1212	ENDPROC SVMInvlpgA
1213
1214	%endif ; GC_ARCH_BITS != 64
1215

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWACCMR0A.asm@ 13182

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