VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWACCMR0A.asm@ 5106

Last change on this file since 5106 was 5072, checked in by vboxsync, 17 years ago

Run vmx guest code with interrupts disabled.
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1; $Id: HWACCMR0A.asm 5072 2007-09-27 09:20:23Z vboxsync $
2;; @file
3; VMXM - R0 vmx helpers
4;
5
6;
7; Copyright (C) 2006-2007 innotek GmbH
8;
9; This file is part of VirtualBox Open Source Edition (OSE), as
10; available from http://www.virtualbox.org. This file is free software;
11; you can redistribute it and/or modify it under the terms of the GNU
12; General Public License as published by the Free Software Foundation,
13; in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14; distribution. VirtualBox OSE is distributed in the hope that it will
15; be useful, but WITHOUT ANY WARRANTY of any kind.
16
17;*******************************************************************************
18;* Header Files *
19;*******************************************************************************
20%include "VBox/asmdefs.mac"
21%include "VBox/err.mac"
22%include "VBox/hwacc_vmx.mac"
23%include "VBox/cpum.mac"
24%include "VBox/x86.mac"
25
26%ifdef RT_OS_OS2 ;; @todo build cvs nasm like on OS X.
27 %macro vmwrite 2,
28 int3
29 %endmacro
30 %define vmlaunch int3
31 %define vmresume int3
32%endif
33
34
35;; @def MYPUSHAD
36; Macro generating an equivalent to pushad
37
38;; @def MYPOPAD
39; Macro generating an equivalent to popad
40
41;; @def MYPUSHSEGS
42; Macro saving all segment registers on the stack.
43; @param 1 full width register name
44; @param 2 16-bit regsiter name for \a 1.
45
46;; @def MYPOPSEGS
47; Macro restoring all segment registers on the stack
48; @param 1 full width register name
49; @param 2 16-bit regsiter name for \a 1.
50
51%ifdef RT_ARCH_AMD64
52 %ifdef ASM_CALL64_GCC
53 %macro MYPUSHAD 0
54 push r15
55 push r14
56 push r13
57 push r12
58 push rbx
59 %endmacro
60 %macro MYPOPAD 0
61 pop rbx
62 pop r12
63 pop r13
64 pop r14
65 pop r15
66 %endmacro
67
68 %else ; ASM_CALL64_MSC
69 %macro MYPUSHAD 0
70 push r15
71 push r14
72 push r13
73 push r12
74 push rbx
75 push rsi
76 push rdi
77 %endmacro
78 %macro MYPOPAD 0
79 pop rdi
80 pop rsi
81 pop rbx
82 pop r12
83 pop r13
84 pop r14
85 pop r15
86 %endmacro
87 %endif
88
89 %macro MYPUSHSEGS 2
90 mov %2, es
91 push %1
92 mov %2, ds
93 push %1
94 push fs
95 ; Special case for GS; OSes typically use swapgs to reset the hidden base register for GS on entry into the kernel. The same happens on exit
96 push rcx
97 mov ecx, MSR_K8_GS_BASE
98 rdmsr
99 pop rcx
100 push rdx
101 push rax
102 push gs
103 %endmacro
104
105 %macro MYPOPSEGS 2
106 ; Note: do not step through this code with a debugger!
107 pop gs
108 pop rax
109 pop rdx
110 push rcx
111 mov ecx, MSR_K8_GS_BASE
112 wrmsr
113 pop rcx
114 ; Now it's safe to step again
115
116 pop fs
117 pop %1
118 mov ds, %2
119 pop %1
120 mov es, %2
121 %endmacro
122
123%else ; RT_ARCH_X86
124 %macro MYPUSHAD 0
125 pushad
126 %endmacro
127 %macro MYPOPAD 0
128 popad
129 %endmacro
130
131 %macro MYPUSHSEGS 2
132 push ds
133 push es
134 push fs
135 push gs
136 %endmacro
137 %macro MYPOPSEGS 2
138 pop gs
139 pop fs
140 pop es
141 pop ds
142 %endmacro
143%endif
144
145
146BEGINCODE
147
148;/**
149; * Prepares for and executes VMLAUNCH
150; *
151; * @note identical to VMXResumeVM, except for the vmlaunch/vmresume opcode
152; *
153; * @returns VBox status code
154; * @param pCtx Guest context
155; */
156BEGINPROC VMXStartVM
157 push xBP
158 mov xBP, xSP
159
160 pushf
161 cli
162
163 ;/* First we have to save some final CPU context registers. */
164%ifdef RT_ARCH_AMD64
165 mov rax, qword .vmlaunch_done
166 push rax
167%else
168 push .vmlaunch_done
169%endif
170 mov eax, VMX_VMCS_HOST_RIP ;/* return address (too difficult to continue after VMLAUNCH?) */
171 vmwrite xAX, [xSP]
172 ;/* @todo assumes success... */
173 add xSP, xS
174
175 ;/* Manual save and restore:
176 ; * - General purpose registers except RIP, RSP
177 ; *
178 ; * Trashed:
179 ; * - CR2 (we don't care)
180 ; * - LDTR (reset to 0)
181 ; * - DRx (presumably not changed at all)
182 ; * - DR7 (reset to 0x400)
183 ; * - EFLAGS (reset to BIT(1); not relevant)
184 ; *
185 ; */
186
187 ;/* Save all general purpose host registers. */
188 MYPUSHAD
189
190 ;/* Save segment registers */
191 MYPUSHSEGS xAX, ax
192
193 ;/* Save the Guest CPU context pointer. */
194%ifdef RT_ARCH_AMD64
195 %ifdef ASM_CALL64_GCC
196 mov rsi, rdi ; pCtx
197 %else
198 mov rsi, rcx ; pCtx
199 %endif
200%else
201 mov esi, [ebp + 8] ; pCtx
202%endif
203 push xSI
204
205 ; Save LDTR
206 xor eax, eax
207 sldt ax
208 push xAX
209
210 ; VMX only saves the base of the GDTR & IDTR and resets the limit to 0xffff; we must restore the limit correctly!
211 sub xSP, xS*2
212 sgdt [xSP]
213
214 sub xSP, xS*2
215 sidt [xSP]
216
217 ; Restore CR2
218 mov ebx, [xSI + CPUMCTX.cr2]
219 mov cr2, xBX
220
221 mov eax, VMX_VMCS_HOST_RSP
222 vmwrite xAX, xSP
223 ;/* @todo assumes success... */
224 ;/* Don't mess with ESP anymore!! */
225
226 ;/* Restore Guest's general purpose registers. */
227 mov eax, [xSI + CPUMCTX.eax]
228 mov ebx, [xSI + CPUMCTX.ebx]
229 mov ecx, [xSI + CPUMCTX.ecx]
230 mov edx, [xSI + CPUMCTX.edx]
231 mov edi, [xSI + CPUMCTX.edi]
232 mov ebp, [xSI + CPUMCTX.ebp]
233 mov esi, [xSI + CPUMCTX.esi]
234
235 vmlaunch
236 jmp .vmlaunch_done; ;/* here if vmlaunch detected a failure. */
237
238ALIGNCODE(16)
239.vmlaunch_done:
240 jc near .vmxstart_invalid_vmxon_ptr
241 jz near .vmxstart_start_failed
242
243 ; Restore base and limit of the IDTR & GDTR
244 lidt [xSP]
245 add xSP, xS*2
246 lgdt [xSP]
247 add xSP, xS*2
248
249 push xDI
250 mov xDI, [xSP + xS * 2] ; pCtx
251
252 mov [ss:xDI + CPUMCTX.eax], eax
253 mov [ss:xDI + CPUMCTX.ebx], ebx
254 mov [ss:xDI + CPUMCTX.ecx], ecx
255 mov [ss:xDI + CPUMCTX.edx], edx
256 mov [ss:xDI + CPUMCTX.esi], esi
257 mov [ss:xDI + CPUMCTX.ebp], ebp
258%ifdef RT_ARCH_AMD64
259 pop xAX ; the guest edi we pushed above
260 mov dword [ss:xDI + CPUMCTX.edi], eax
261%else
262 pop dword [ss:xDI + CPUMCTX.edi] ; the guest edi we pushed above
263%endif
264
265 pop xAX ; saved LDTR
266 lldt ax
267
268 add xSP, xS ; pCtx
269
270 ; Restore segment registers
271 MYPOPSEGS xAX, ax
272
273 ; Restore general purpose registers
274 MYPOPAD
275
276 mov eax, VINF_SUCCESS
277
278.vmstart_end:
279 popf
280 pop xBP
281 ret
282
283
284.vmxstart_invalid_vmxon_ptr:
285 ; Restore base and limit of the IDTR & GDTR
286 lidt [xSP]
287 add xSP, xS*2
288 lgdt [xSP]
289 add xSP, xS*2
290
291 pop xAX ; saved LDTR
292 lldt ax
293
294 add xSP, xS ; pCtx
295
296 ; Restore segment registers
297 MYPOPSEGS xAX, ax
298
299 ; Restore all general purpose host registers.
300 MYPOPAD
301 mov eax, VERR_VMX_INVALID_VMXON_PTR
302 jmp .vmstart_end
303
304.vmxstart_start_failed:
305 ; Restore base and limit of the IDTR & GDTR
306 lidt [xSP]
307 add xSP, xS*2
308 lgdt [xSP]
309 add xSP, xS*2
310
311 pop xAX ; saved LDTR
312 lldt ax
313
314 add xSP, xS ; pCtx
315
316 ; Restore segment registers
317 MYPOPSEGS xAX, ax
318
319 ; Restore all general purpose host registers.
320 MYPOPAD
321 mov eax, VERR_VMX_UNABLE_TO_START_VM
322 jmp .vmstart_end
323
324ENDPROC VMXStartVM
325
326
327;/**
328; * Prepares for and executes VMRESUME
329; *
330; * @note identical to VMXStartVM, except for the vmlaunch/vmresume opcode
331; *
332; * @returns VBox status code
333; * @param pCtx Guest context
334; */
335BEGINPROC VMXResumeVM
336 push xBP
337 mov xBP, xSP
338
339 pushf
340 cli
341
342 ;/* First we have to save some final CPU context registers. */
343%ifdef RT_ARCH_AMD64
344 mov rax, qword .vmresume_done
345 push rax
346%else
347 push .vmresume_done
348%endif
349 mov eax, VMX_VMCS_HOST_RIP ;/* return address (too difficult to continue after VMLAUNCH?) */
350 vmwrite xAX, [xSP]
351 ;/* @todo assumes success... */
352 add xSP, xS
353
354 ;/* Manual save and restore:
355 ; * - General purpose registers except RIP, RSP
356 ; *
357 ; * Trashed:
358 ; * - CR2 (we don't care)
359 ; * - LDTR (reset to 0)
360 ; * - DRx (presumably not changed at all)
361 ; * - DR7 (reset to 0x400)
362 ; * - EFLAGS (reset to BIT(1); not relevant)
363 ; *
364 ; */
365
366 ;/* Save all general purpose host registers. */
367 MYPUSHAD
368
369 ;/* Save segment registers */
370 MYPUSHSEGS xAX, ax
371
372 ;/* Save the Guest CPU context pointer. */
373%ifdef RT_ARCH_AMD64
374 %ifdef ASM_CALL64_GCC
375 mov rsi, rdi ; pCtx
376 %else
377 mov rsi, rcx ; pCtx
378 %endif
379%else
380 mov esi, [ebp + 8] ; pCtx
381%endif
382 push xSI
383
384 ; Save LDTR
385 xor eax, eax
386 sldt ax
387 push xAX
388
389 ; VMX only saves the base of the GDTR & IDTR and resets the limit to 0xffff; we must restore the limit correctly!
390 sub xSP, xS*2
391 sgdt [xSP]
392
393 sub xSP, xS*2
394 sidt [xSP]
395
396 ; Restore CR2
397 mov xBX, [xSI + CPUMCTX.cr2]
398 mov cr2, xBX
399
400 mov eax, VMX_VMCS_HOST_RSP
401 vmwrite xAX, xSP
402 ;/* @todo assumes success... */
403 ;/* Don't mess with ESP anymore!! */
404
405 ;/* Restore Guest's general purpose registers. */
406 mov eax, [xSI + CPUMCTX.eax]
407 mov ebx, [xSI + CPUMCTX.ebx]
408 mov ecx, [xSI + CPUMCTX.ecx]
409 mov edx, [xSI + CPUMCTX.edx]
410 mov edi, [xSI + CPUMCTX.edi]
411 mov ebp, [xSI + CPUMCTX.ebp]
412 mov esi, [xSI + CPUMCTX.esi]
413
414 vmresume
415 jmp .vmresume_done; ;/* here if vmresume detected a failure. */
416
417ALIGNCODE(16)
418.vmresume_done:
419 jc near .vmxresume_invalid_vmxon_ptr
420 jz near .vmxresume_start_failed
421
422 ; Restore base and limit of the IDTR & GDTR
423 lidt [xSP]
424 add xSP, xS*2
425 lgdt [xSP]
426 add xSP, xS*2
427
428 push xDI
429 mov xDI, [xSP + xS * 2] ; pCtx
430
431 mov [ss:xDI + CPUMCTX.eax], eax
432 mov [ss:xDI + CPUMCTX.ebx], ebx
433 mov [ss:xDI + CPUMCTX.ecx], ecx
434 mov [ss:xDI + CPUMCTX.edx], edx
435 mov [ss:xDI + CPUMCTX.esi], esi
436 mov [ss:xDI + CPUMCTX.ebp], ebp
437%ifdef RT_ARCH_AMD64
438 pop xAX ; the guest edi we pushed above
439 mov dword [ss:xDI + CPUMCTX.edi], eax
440%else
441 pop dword [ss:xDI + CPUMCTX.edi] ; the guest edi we pushed above
442%endif
443
444 pop xAX ; saved LDTR
445 lldt ax
446
447 add xSP, xS ; pCtx
448
449 ; Restore segment registers
450 MYPOPSEGS xAX, ax
451
452 ; Restore general purpose registers
453 MYPOPAD
454
455 mov eax, VINF_SUCCESS
456
457.vmresume_end:
458 popf
459 pop xBP
460 ret
461
462.vmxresume_invalid_vmxon_ptr:
463 ; Restore base and limit of the IDTR & GDTR
464 lidt [xSP]
465 add xSP, xS*2
466 lgdt [xSP]
467 add xSP, xS*2
468
469 pop xAX ; saved LDTR
470 lldt ax
471
472 add xSP, xS ; pCtx
473
474 ; Restore segment registers
475 MYPOPSEGS xAX, ax
476
477 ; Restore all general purpose host registers.
478 MYPOPAD
479 mov eax, VERR_VMX_INVALID_VMXON_PTR
480 jmp .vmresume_end
481
482.vmxresume_start_failed:
483 ; Restore base and limit of the IDTR & GDTR
484 lidt [xSP]
485 add xSP, xS*2
486 lgdt [xSP]
487 add xSP, xS*2
488
489 pop xAX ; saved LDTR
490 lldt ax
491
492 add xSP, xS ; pCtx
493
494 ; Restore segment registers
495 MYPOPSEGS xAX, ax
496
497 ; Restore all general purpose host registers.
498 MYPOPAD
499 mov eax, VERR_VMX_UNABLE_TO_RESUME_VM
500 jmp .vmresume_end
501
502ENDPROC VMXResumeVM
503
504
505%ifdef RT_ARCH_AMD64
506;/**
507; * Executes VMWRITE
508; *
509; * @returns VBox status code
510; * @param idxField x86: [ebp + 08h] msc: rcx gcc: edi VMCS index
511; * @param pData x86: [ebp + 0ch] msc: rdx gcc: rsi VM field value
512; */
513BEGINPROC VMXWriteVMCS64
514%ifdef ASM_CALL64_GCC
515 mov eax, 0ffffffffh
516 and rdi, rax
517 xor rax, rax
518 vmwrite rdi, rsi
519%else
520 mov eax, 0ffffffffh
521 and rcx, rax
522 xor rax, rax
523 vmwrite rcx, rdx
524%endif
525 jnc .valid_vmcs
526 mov eax, VERR_VMX_INVALID_VMCS_PTR
527 ret
528.valid_vmcs:
529 jnz .the_end
530 mov eax, VERR_VMX_INVALID_VMCS_FIELD
531.the_end:
532 ret
533ENDPROC VMXWriteVMCS64
534
535;/**
536; * Executes VMREAD
537; *
538; * @returns VBox status code
539; * @param idxField VMCS index
540; * @param pData Ptr to store VM field value
541; */
542;DECLASM(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData);
543BEGINPROC VMXReadVMCS64
544%ifdef ASM_CALL64_GCC
545 mov eax, 0ffffffffh
546 and rdi, rax
547 xor rax, rax
548 vmread [rsi], rdi
549%else
550 mov eax, 0ffffffffh
551 and rcx, rax
552 xor rax, rax
553 vmread [rdx], rcx
554%endif
555 jnc .valid_vmcs
556 mov eax, VERR_VMX_INVALID_VMCS_PTR
557 ret
558.valid_vmcs:
559 jnz .the_end
560 mov eax, VERR_VMX_INVALID_VMCS_FIELD
561.the_end:
562 ret
563ENDPROC VMXReadVMCS64
564
565
566;/**
567; * Executes VMXON
568; *
569; * @returns VBox status code
570; * @param HCPhysVMXOn Physical address of VMXON structure
571; */
572;DECLASM(int) VMXEnable(RTHCPHYS HCPhysVMXOn);
573BEGINPROC VMXEnable
574%ifdef RT_ARCH_AMD64
575 xor rax, rax
576 %ifdef ASM_CALL64_GCC
577 push rdi
578 %else
579 push rcx
580 %endif
581 vmxon [rsp]
582%else
583 xor eax, eax
584 vmxon [esp + 4]
585%endif
586 jnc .good
587 mov eax, VERR_VMX_INVALID_VMXON_PTR
588 jmp .the_end
589
590.good:
591 jnz .the_end
592 mov eax, VERR_VMX_GENERIC
593
594.the_end:
595%ifdef RT_ARCH_AMD64
596 add rsp, 8
597%endif
598 ret
599ENDPROC VMXEnable
600
601
602;/**
603; * Executes VMXOFF
604; */
605;DECLASM(void) VMXDisable(void);
606BEGINPROC VMXDisable
607 vmxoff
608 ret
609ENDPROC VMXDisable
610
611
612;/**
613; * Executes VMCLEAR
614; *
615; * @returns VBox status code
616; * @param HCPhysVMCS Physical address of VM control structure
617; */
618;DECLASM(int) VMXClearVMCS(RTHCPHYS HCPhysVMCS);
619BEGINPROC VMXClearVMCS
620%ifdef RT_ARCH_AMD64
621 xor rax, rax
622 %ifdef ASM_CALL64_GCC
623 push rdi
624 %else
625 push rcx
626 %endif
627 vmclear [rsp]
628%else
629 xor eax, eax
630 vmclear [esp + 4]
631%endif
632 jnc .the_end
633 mov eax, VERR_VMX_INVALID_VMCS_PTR
634.the_end:
635%ifdef RT_ARCH_AMD64
636 add rsp, 8
637%endif
638 ret
639ENDPROC VMXClearVMCS
640
641
642;/**
643; * Executes VMPTRLD
644; *
645; * @returns VBox status code
646; * @param HCPhysVMCS Physical address of VMCS structure
647; */
648;DECLASM(int) VMXActivateVMCS(RTHCPHYS HCPhysVMCS);
649BEGINPROC VMXActivateVMCS
650%ifdef RT_ARCH_AMD64
651 xor rax, rax
652 %ifdef ASM_CALL64_GCC
653 push rdi
654 %else
655 push rcx
656 %endif
657 vmptrld [rsp]
658%else
659 xor eax, eax
660 vmptrld [esp + 4]
661%endif
662 jnc .the_end
663 mov eax, VERR_VMX_INVALID_VMCS_PTR
664.the_end:
665%ifdef RT_ARCH_AMD64
666 add rsp, 8
667%endif
668 ret
669ENDPROC VMXActivateVMCS
670
671%endif ; RT_ARCH_AMD64
672
673
674;/**
675; * Prepares for and executes VMRUN
676; *
677; * @returns VBox status code
678; * @param HCPhysVMCB Physical address of host VMCB
679; * @param HCPhysVMCB Physical address of guest VMCB
680; * @param pCtx Guest context
681; */
682BEGINPROC SVMVMRun
683%ifdef RT_ARCH_AMD64 ; fake a cdecl stack frame - I'm lazy, sosume.
684 %ifdef ASM_CALL64_GCC
685 push rdx
686 push rsi
687 push rdi
688 %else
689 push r8
690 push rdx
691 push rcx
692 %endif
693 push 0
694%endif
695 push xBP
696 mov xBP, xSP
697
698 ;/* Manual save and restore:
699 ; * - General purpose registers except RIP, RSP, RAX
700 ; *
701 ; * Trashed:
702 ; * - CR2 (we don't care)
703 ; * - LDTR (reset to 0)
704 ; * - DRx (presumably not changed at all)
705 ; * - DR7 (reset to 0x400)
706 ; */
707
708 ;/* Save all general purpose host registers. */
709 MYPUSHAD
710
711 ;/* Save the Guest CPU context pointer. */
712 mov xSI, [xBP + xS*2 + RTHCPHYS_CB*2] ; pCtx
713 push xSI ; push for saving the state at the end
714
715 ; Restore CR2
716 mov ebx, [xSI + CPUMCTX.cr2]
717 mov cr2, xBX
718
719 ; save host fs, gs, sysenter msr etc
720 mov xAX, [xBP + xS*2] ; pVMCBHostPhys (64 bits physical address; x86: take low dword only)
721 push xAX ; save for the vmload after vmrun
722 DB 0x0F, 0x01, 0xDB ; VMSAVE
723
724 ; setup eax for VMLOAD
725 mov xAX, [xBP + xS*2 + RTHCPHYS_CB] ; pVMCBPhys (64 bits physical address; take low dword only)
726
727 ;/* Restore Guest's general purpose registers. */
728 ;/* EAX is loaded from the VMCB by VMRUN */
729 mov ebx, [xSI + CPUMCTX.ebx]
730 mov ecx, [xSI + CPUMCTX.ecx]
731 mov edx, [xSI + CPUMCTX.edx]
732 mov edi, [xSI + CPUMCTX.edi]
733 mov ebp, [xSI + CPUMCTX.ebp]
734 mov esi, [xSI + CPUMCTX.esi]
735
736 ; Clear the global interrupt flag & execute sti to make sure external interrupts cause a world switch
737 DB 0x0f, 0x01, 0xDD ; CLGI
738 sti
739
740 ; load guest fs, gs, sysenter msr etc
741 DB 0x0f, 0x01, 0xDA ; VMLOAD
742 ; run the VM
743 DB 0x0F, 0x01, 0xD8 ; VMRUN
744
745 ;/* EAX is in the VMCB already; we can use it here. */
746
747 ; save guest fs, gs, sysenter msr etc
748 DB 0x0F, 0x01, 0xDB ; VMSAVE
749
750 ; load host fs, gs, sysenter msr etc
751 pop xAX ; pushed above
752 DB 0x0F, 0x01, 0xDA ; VMLOAD
753
754 ; Set the global interrupt flag again, but execute cli to make sure IF=0.
755 cli
756 DB 0x0f, 0x01, 0xDC ; STGI
757
758 pop xAX ; pCtx
759
760 mov [ss:xAX + CPUMCTX.ebx], ebx
761 mov [ss:xAX + CPUMCTX.ecx], ecx
762 mov [ss:xAX + CPUMCTX.edx], edx
763 mov [ss:xAX + CPUMCTX.esi], esi
764 mov [ss:xAX + CPUMCTX.edi], edi
765 mov [ss:xAX + CPUMCTX.ebp], ebp
766
767 ; Restore general purpose registers
768 MYPOPAD
769
770 mov eax, VINF_SUCCESS
771
772 pop xBP
773%ifdef RT_ARCH_AMD64
774 add xSP, 4*xS
775%endif
776 ret
777ENDPROC SVMVMRun
778
779%ifdef RT_ARCH_AMD64
780%ifdef RT_OS_WINDOWS
781
782;;
783; Executes INVLPGA
784;
785; @param pPageGC msc:ecx gcc:edi x86:[esp+04] Virtual page to invalidate
786; @param uASID msc:edx gcc:esi x86:[esp+08] Tagged TLB id
787;
788;DECLASM(void) SVMInvlpgA(RTGCPTR pPageGC, uint32_t uASID);
789BEGINPROC SVMInvlpgA
790%ifdef RT_ARCH_AMD64
791 %ifdef ASM_CALL64_GCC
792 mov eax, edi ;; @todo 64-bit guest.
793 mov ecx, esi
794 %else
795 mov eax, ecx ;; @todo 64-bit guest.
796 mov ecx, edx
797 %endif
798 invlpga rax, ecx
799%else
800 mov eax, [esp + 4]
801 mov ecx, [esp + 8]
802 invlpga eax, ecx
803%endif
804 ret
805ENDPROC SVMInvlpgA
806%endif
807%endif
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