| 1 | ; $Id: HWACCMR0Mixed.mac 15360 2008-12-12 12:25:21Z vboxsync $
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| 2 | ;; @file
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| 3 | ; HWACCMR0Mixed.mac - Stuff that darwin needs to build two versions of.
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| 4 | ;
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| 5 | ; Included by HWACCMR0A.asm with RT_ARCH_AMD64 defined or or undefined.
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| 6 | ;
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| 7 |
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| 8 | ;
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| 9 | ; Copyright (C) 2006-2007 Sun Microsystems, Inc.
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| 10 | ;
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| 11 | ; This file is part of VirtualBox Open Source Edition (OSE), as
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| 12 | ; available from http://www.virtualbox.org. This file is free software;
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| 13 | ; you can redistribute it and/or modify it under the terms of the GNU
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| 14 | ; General Public License (GPL) as published by the Free Software
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| 15 | ; Foundation, in version 2 as it comes in the "COPYING" file of the
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| 16 | ; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 17 | ; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 18 | ;
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| 19 | ; Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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| 20 | ; Clara, CA 95054 USA or visit http://www.sun.com if you need
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| 21 | ; additional information or have any questions.
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| 22 | ;
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| 23 |
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| 24 |
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| 25 | ;/**
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| 26 | ; * Prepares for and executes VMLAUNCH/VMRESUME (32 bits guest mode)
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| 27 | ; *
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| 28 | ; * @returns VBox status code
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| 29 | ; * @param fResume x86:[ebp+8], msc:rcx,gcc:rdi vmlauch/vmresume
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| 30 | ; * @param pCtx x86:[ebp+c], msc:rdx,gcc:rsi Guest context
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| 31 | ; * @param pCache x86:[esp+10],msc:r8, gcc:rdx VMCS cache
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| 32 | ; */
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| 33 | ALIGNCODE(16)
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| 34 | BEGINPROC MY_NAME(VMXR0StartVM32)
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| 35 | push xBP
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| 36 | mov xBP, xSP
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| 37 |
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| 38 | pushf
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| 39 | cli
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| 40 |
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| 41 | ;/* Save all general purpose host registers. */
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| 42 | MYPUSHAD
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| 43 |
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| 44 | ;/* First we have to save some final CPU context registers. */
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| 45 | mov eax, VMX_VMCS_HOST_RIP
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| 46 | %ifdef RT_ARCH_AMD64
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| 47 | lea r10, [.vmlaunch_done wrt rip]
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| 48 | vmwrite rax, r10
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| 49 | %else
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| 50 | mov ecx, .vmlaunch_done
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| 51 | vmwrite eax, ecx
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| 52 | %endif
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| 53 | ;/* Note: assumes success... */
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| 54 |
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| 55 | ;/* Manual save and restore:
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| 56 | ; * - General purpose registers except RIP, RSP
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| 57 | ; *
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| 58 | ; * Trashed:
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| 59 | ; * - CR2 (we don't care)
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| 60 | ; * - LDTR (reset to 0)
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| 61 | ; * - DRx (presumably not changed at all)
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| 62 | ; * - DR7 (reset to 0x400)
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| 63 | ; * - EFLAGS (reset to RT_BIT(1); not relevant)
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| 64 | ; *
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| 65 | ; */
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| 66 |
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| 67 | ;/* Save the Guest CPU context pointer. */
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| 68 | %ifdef RT_ARCH_AMD64
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| 69 | %ifdef ASM_CALL64_GCC
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| 70 | ; fResume already in rdi
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| 71 | ; pCtx already in rsi
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| 72 | mov rbx, rdx ; pCache
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| 73 | %else
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| 74 | mov rdi, rcx ; fResume
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| 75 | mov rsi, rdx ; pCtx
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| 76 | mov rbx, r8 ; pCache
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| 77 | %endif
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| 78 | %else
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| 79 | mov edi, [ebp + 8] ; fResume
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| 80 | mov esi, [ebp + 12] ; pCtx
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| 81 | mov ebx, [ebp + 16] ; pCache
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| 82 | %endif
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| 83 |
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| 84 | ;/* Save segment registers */
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| 85 | ; Note: MYPUSHSEGS trashes rdx & rcx, so we moved it here (msvc amd64 case)
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| 86 | MYPUSHSEGS xAX, ax
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| 87 |
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| 88 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
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| 89 | mov ecx, [xBX + VMCSCACHE.Write.cValidEntries]
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| 90 | cmp ecx, 0
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| 91 | je .no_cached_writes
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| 92 | mov edx, ecx
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| 93 | mov ecx, 0
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| 94 | jmp .cached_write
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| 95 |
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| 96 | ALIGN(16)
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| 97 | .cached_write:
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| 98 | mov eax, [xBX + VMCSCACHE.Write.aField + xCX*4]
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| 99 | vmwrite xAX, [xBX + VMCSCACHE.Write.aFieldVal + xCX*8]
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| 100 | inc xCX
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| 101 | cmp xCX, xDX
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| 102 | jl .cached_write
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| 103 |
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| 104 | mov dword [xBX + VMCSCACHE.Write.cValidEntries], 0
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| 105 | .no_cached_writes:
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| 106 |
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| 107 | ; Save the pCache pointer
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| 108 | push xBX
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| 109 | %endif
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| 110 |
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| 111 | ; Save the pCtx pointer
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| 112 | push xSI
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| 113 |
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| 114 | ; Save LDTR
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| 115 | xor eax, eax
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| 116 | sldt ax
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| 117 | push xAX
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| 118 |
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| 119 | ; VMX only saves the base of the GDTR & IDTR and resets the limit to 0xffff; we must restore the limit correctly!
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| 120 | sub xSP, xS*2
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| 121 | sgdt [xSP]
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| 122 |
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| 123 | sub xSP, xS*2
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| 124 | sidt [xSP]
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| 125 |
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| 126 | %ifdef VBOX_WITH_DR6_EXPERIMENT
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| 127 | ; Restore DR6 - experiment, not safe!
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| 128 | mov xBX, [xSI + CPUMCTX.dr6]
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| 129 | mov dr6, xBX
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| 130 | %endif
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| 131 |
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| 132 | ; Restore CR2
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| 133 | mov ebx, [xSI + CPUMCTX.cr2]
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| 134 | mov cr2, xBX
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| 135 |
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| 136 | mov eax, VMX_VMCS_HOST_RSP
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| 137 | vmwrite xAX, xSP
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| 138 | ;/* Note: assumes success... */
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| 139 | ;/* Don't mess with ESP anymore!! */
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| 140 |
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| 141 | ;/* Restore Guest's general purpose registers. */
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| 142 | mov eax, [xSI + CPUMCTX.eax]
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| 143 | mov ebx, [xSI + CPUMCTX.ebx]
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| 144 | mov ecx, [xSI + CPUMCTX.ecx]
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| 145 | mov edx, [xSI + CPUMCTX.edx]
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| 146 | mov ebp, [xSI + CPUMCTX.ebp]
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| 147 |
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| 148 | ; resume or start?
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| 149 | cmp xDI, 0 ; fResume
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| 150 | je .vmlauch_lauch
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| 151 |
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| 152 | ;/* Restore edi & esi. */
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| 153 | mov edi, [xSI + CPUMCTX.edi]
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| 154 | mov esi, [xSI + CPUMCTX.esi]
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| 155 |
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| 156 | vmresume
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| 157 | jmp .vmlaunch_done; ;/* here if vmresume detected a failure. */
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| 158 |
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| 159 | .vmlauch_lauch:
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| 160 | ;/* Restore edi & esi. */
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| 161 | mov edi, [xSI + CPUMCTX.edi]
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| 162 | mov esi, [xSI + CPUMCTX.esi]
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| 163 |
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| 164 | vmlaunch
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| 165 | jmp .vmlaunch_done; ;/* here if vmlaunch detected a failure. */
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| 166 |
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| 167 | ALIGNCODE(16) ;; @todo YASM BUG - this alignment is wrong on darwin, it's 1 byte off.
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| 168 | .vmlaunch_done:
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| 169 | jc near .vmxstart_invalid_vmxon_ptr
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| 170 | jz near .vmxstart_start_failed
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| 171 |
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| 172 | ; Restore base and limit of the IDTR & GDTR
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| 173 | lidt [xSP]
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| 174 | add xSP, xS*2
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| 175 | lgdt [xSP]
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| 176 | add xSP, xS*2
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| 177 |
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| 178 | push xDI
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| 179 | mov xDI, [xSP + xS * 2] ; pCtx (*2 to skip the saved LDTR)
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| 180 |
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| 181 | mov [ss:xDI + CPUMCTX.eax], eax
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| 182 | mov [ss:xDI + CPUMCTX.ebx], ebx
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| 183 | mov [ss:xDI + CPUMCTX.ecx], ecx
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| 184 | mov [ss:xDI + CPUMCTX.edx], edx
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| 185 | mov [ss:xDI + CPUMCTX.esi], esi
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| 186 | mov [ss:xDI + CPUMCTX.ebp], ebp
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| 187 | %ifdef RT_ARCH_AMD64
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| 188 | pop xAX ; the guest edi we pushed above
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| 189 | mov dword [ss:xDI + CPUMCTX.edi], eax
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| 190 | %else
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| 191 | pop dword [ss:xDI + CPUMCTX.edi] ; the guest edi we pushed above
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| 192 | %endif
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| 193 |
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| 194 | %ifdef VBOX_WITH_DR6_EXPERIMENT
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| 195 | ; Save DR6 - experiment, not safe!
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| 196 | mov xAX, dr6
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| 197 | mov [ss:xDI + CPUMCTX.dr6], xAX
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| 198 | %endif
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| 199 |
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| 200 | pop xAX ; saved LDTR
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| 201 | lldt ax
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| 202 |
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| 203 | add xSP, xS ; pCtx
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| 204 |
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| 205 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
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| 206 | pop xDX ; saved pCache
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| 207 |
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| 208 | mov ecx, [ss:xDX + VMCSCACHE.Read.cValidEntries]
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| 209 | cmp ecx, 0 ; can't happen
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| 210 | je .no_cached_reads
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| 211 | jmp .cached_read
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| 212 |
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| 213 | ALIGN(16)
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| 214 | .cached_read:
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| 215 | dec xCX
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| 216 | mov eax, [ss:xDX + VMCSCACHE.Read.aField + xCX*4]
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| 217 | vmread [ss:xDX + VMCSCACHE.Read.aFieldVal + xCX*8], xAX
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| 218 | cmp xCX, 0
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| 219 | jnz .cached_read
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| 220 | .no_cached_reads:
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| 221 | %endif
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| 222 |
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| 223 | ; Restore segment registers
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| 224 | MYPOPSEGS xAX, ax
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| 225 |
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| 226 | ; Restore general purpose registers
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| 227 | MYPOPAD
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| 228 |
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| 229 | mov eax, VINF_SUCCESS
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| 230 |
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| 231 | .vmstart_end:
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| 232 | popf
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| 233 | pop xBP
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| 234 | ret
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| 235 |
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| 236 |
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| 237 | .vmxstart_invalid_vmxon_ptr:
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| 238 | ; Restore base and limit of the IDTR & GDTR
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| 239 | lidt [xSP]
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| 240 | add xSP, xS*2
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| 241 | lgdt [xSP]
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| 242 | add xSP, xS*2
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| 243 |
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| 244 | pop xAX ; saved LDTR
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| 245 | lldt ax
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| 246 |
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| 247 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
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| 248 | add xSP, xS*2 ; pCtx + pCache
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| 249 | %else
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| 250 | add xSP, xS ; pCtx
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| 251 | %endif
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| 252 |
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| 253 | ; Restore segment registers
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| 254 | MYPOPSEGS xAX, ax
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| 255 |
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| 256 | ; Restore all general purpose host registers.
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| 257 | MYPOPAD
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| 258 | mov eax, VERR_VMX_INVALID_VMXON_PTR
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| 259 | jmp .vmstart_end
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| 260 |
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| 261 | .vmxstart_start_failed:
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| 262 | ; Restore base and limit of the IDTR & GDTR
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| 263 | lidt [xSP]
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| 264 | add xSP, xS*2
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| 265 | lgdt [xSP]
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| 266 | add xSP, xS*2
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| 267 |
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| 268 | pop xAX ; saved LDTR
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| 269 | lldt ax
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| 270 |
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| 271 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
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| 272 | add xSP, xS*2 ; pCtx + pCache
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| 273 | %else
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| 274 | add xSP, xS ; pCtx
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| 275 | %endif
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| 276 |
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| 277 | ; Restore segment registers
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| 278 | MYPOPSEGS xAX, ax
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| 279 |
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| 280 | ; Restore all general purpose host registers.
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| 281 | MYPOPAD
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| 282 | mov eax, VERR_VMX_UNABLE_TO_START_VM
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| 283 | jmp .vmstart_end
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| 284 |
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| 285 | ENDPROC MY_NAME(VMXR0StartVM32)
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| 286 |
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| 287 | %ifdef RT_ARCH_AMD64
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| 288 | ;/**
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| 289 | ; * Prepares for and executes VMLAUNCH/VMRESUME (64 bits guest mode)
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| 290 | ; *
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| 291 | ; * @returns VBox status code
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| 292 | ; * @param fResume msc:rcx, gcc:rdi vmlauch/vmresume
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| 293 | ; * @param pCtx msc:rdx, gcc:rsi Guest context
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| 294 | ; * @param pCache msc:r8, gcc:rdx VMCS cache
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| 295 | ; */
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| 296 | ALIGNCODE(16)
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| 297 | BEGINPROC MY_NAME(VMXR0StartVM64)
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| 298 | push xBP
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| 299 | mov xBP, xSP
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| 300 |
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| 301 | pushf
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| 302 | cli
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| 303 |
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| 304 | ;/* Save all general purpose host registers. */
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| 305 | MYPUSHAD
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| 306 |
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| 307 | ;/* First we have to save some final CPU context registers. */
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| 308 | lea r10, [.vmlaunch64_done wrt rip]
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| 309 | mov rax, VMX_VMCS_HOST_RIP ;/* return address (too difficult to continue after VMLAUNCH?) */
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| 310 | vmwrite rax, r10
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| 311 | ;/* Note: assumes success... */
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| 312 |
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| 313 | ;/* Manual save and restore:
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| 314 | ; * - General purpose registers except RIP, RSP
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| 315 | ; *
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| 316 | ; * Trashed:
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| 317 | ; * - CR2 (we don't care)
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| 318 | ; * - LDTR (reset to 0)
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| 319 | ; * - DRx (presumably not changed at all)
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| 320 | ; * - DR7 (reset to 0x400)
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| 321 | ; * - EFLAGS (reset to RT_BIT(1); not relevant)
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| 322 | ; *
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| 323 | ; */
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| 324 |
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| 325 | ;/* Save the Guest CPU context pointer. */
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| 326 | %ifdef ASM_CALL64_GCC
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| 327 | ; fResume already in rdi
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| 328 | ; pCtx already in rsi
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| 329 | mov rbx, rdx ; pCache
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| 330 | %else
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| 331 | mov rdi, rcx ; fResume
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| 332 | mov rsi, rdx ; pCtx
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| 333 | mov rbx, r8 ; pCache
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| 334 | %endif
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| 335 |
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| 336 | ;/* Save segment registers */
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| 337 | ; Note: MYPUSHSEGS trashes rdx & rcx, so we moved it here (msvc amd64 case)
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| 338 | MYPUSHSEGS xAX, ax
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| 339 |
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| 340 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
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| 341 | mov ecx, [xBX + VMCSCACHE.Write.cValidEntries]
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| 342 | cmp ecx, 0
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| 343 | je .no_cached_writes
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| 344 | mov edx, ecx
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| 345 | mov ecx, 0
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| 346 | jmp .cached_write
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| 347 |
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| 348 | ALIGN(16)
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| 349 | .cached_write:
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| 350 | mov eax, [xBX + VMCSCACHE.Write.aField + xCX*4]
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| 351 | vmwrite xAX, [xBX + VMCSCACHE.Write.aFieldVal + xCX*8]
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| 352 | inc xCX
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| 353 | cmp xCX, xDX
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| 354 | jl .cached_write
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| 355 |
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| 356 | mov dword [xBX + VMCSCACHE.Write.cValidEntries], 0
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| 357 | .no_cached_writes:
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| 358 |
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| 359 | ; Save the pCache pointer
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| 360 | push xBX
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| 361 | %endif
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| 362 |
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| 363 | ; Save the host LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs and restore the guest MSRs
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| 364 | ;; @todo use the automatic load feature for MSRs
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| 365 | LOADGUESTMSR MSR_K8_LSTAR, CPUMCTX.msrLSTAR
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| 366 | %if 0 ; not supported on Intel CPUs
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| 367 | LOADGUESTMSR MSR_K8_CSTAR, CPUMCTX.msrCSTAR
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| 368 | %endif
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| 369 | LOADGUESTMSR MSR_K6_STAR, CPUMCTX.msrSTAR
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| 370 | LOADGUESTMSR MSR_K8_SF_MASK, CPUMCTX.msrSFMASK
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| 371 | LOADGUESTMSR MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
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| 372 |
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| 373 | ; Save the pCtx pointer
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| 374 | push xSI
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| 375 |
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| 376 | ; Save LDTR
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| 377 | xor eax, eax
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| 378 | sldt ax
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| 379 | push xAX
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| 380 |
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| 381 | ; VMX only saves the base of the GDTR & IDTR and resets the limit to 0xffff; we must restore the limit correctly!
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| 382 | sub xSP, xS*2
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| 383 | sgdt [xSP]
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| 384 |
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| 385 | sub xSP, xS*2
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| 386 | sidt [xSP]
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| 387 |
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| 388 | %ifdef VBOX_WITH_DR6_EXPERIMENT
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| 389 | ; Restore DR6 - experiment, not safe!
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| 390 | mov xBX, [xSI + CPUMCTX.dr6]
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| 391 | mov dr6, xBX
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| 392 | %endif
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| 393 |
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| 394 | ; Restore CR2
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| 395 | mov rbx, qword [xSI + CPUMCTX.cr2]
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| 396 | mov cr2, rbx
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| 397 |
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| 398 | mov eax, VMX_VMCS_HOST_RSP
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| 399 | vmwrite xAX, xSP
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| 400 | ;/* Note: assumes success... */
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| 401 | ;/* Don't mess with ESP anymore!! */
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| 402 |
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| 403 | ;/* Restore Guest's general purpose registers. */
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| 404 | mov rax, qword [xSI + CPUMCTX.eax]
|
|---|
| 405 | mov rbx, qword [xSI + CPUMCTX.ebx]
|
|---|
| 406 | mov rcx, qword [xSI + CPUMCTX.ecx]
|
|---|
| 407 | mov rdx, qword [xSI + CPUMCTX.edx]
|
|---|
| 408 | mov rbp, qword [xSI + CPUMCTX.ebp]
|
|---|
| 409 | mov r8, qword [xSI + CPUMCTX.r8]
|
|---|
| 410 | mov r9, qword [xSI + CPUMCTX.r9]
|
|---|
| 411 | mov r10, qword [xSI + CPUMCTX.r10]
|
|---|
| 412 | mov r11, qword [xSI + CPUMCTX.r11]
|
|---|
| 413 | mov r12, qword [xSI + CPUMCTX.r12]
|
|---|
| 414 | mov r13, qword [xSI + CPUMCTX.r13]
|
|---|
| 415 | mov r14, qword [xSI + CPUMCTX.r14]
|
|---|
| 416 | mov r15, qword [xSI + CPUMCTX.r15]
|
|---|
| 417 |
|
|---|
| 418 | ; resume or start?
|
|---|
| 419 | cmp xDI, 0 ; fResume
|
|---|
| 420 | je .vmlauch64_lauch
|
|---|
| 421 |
|
|---|
| 422 | ;/* Restore edi & esi. */
|
|---|
| 423 | mov rdi, qword [xSI + CPUMCTX.edi]
|
|---|
| 424 | mov rsi, qword [xSI + CPUMCTX.esi]
|
|---|
| 425 |
|
|---|
| 426 | vmresume
|
|---|
| 427 | jmp .vmlaunch64_done; ;/* here if vmresume detected a failure. */
|
|---|
| 428 |
|
|---|
| 429 | .vmlauch64_lauch:
|
|---|
| 430 | ;/* Restore rdi & rsi. */
|
|---|
| 431 | mov rdi, qword [xSI + CPUMCTX.edi]
|
|---|
| 432 | mov rsi, qword [xSI + CPUMCTX.esi]
|
|---|
| 433 |
|
|---|
| 434 | vmlaunch
|
|---|
| 435 | jmp .vmlaunch64_done; ;/* here if vmlaunch detected a failure. */
|
|---|
| 436 |
|
|---|
| 437 | ALIGNCODE(16)
|
|---|
| 438 | .vmlaunch64_done:
|
|---|
| 439 | jc near .vmxstart64_invalid_vmxon_ptr
|
|---|
| 440 | jz near .vmxstart64_start_failed
|
|---|
| 441 |
|
|---|
| 442 | ; Restore base and limit of the IDTR & GDTR
|
|---|
| 443 | lidt [xSP]
|
|---|
| 444 | add xSP, xS*2
|
|---|
| 445 | lgdt [xSP]
|
|---|
| 446 | add xSP, xS*2
|
|---|
| 447 |
|
|---|
| 448 | push xDI
|
|---|
| 449 | mov xDI, [xSP + xS * 2] ; pCtx (*2 to skip the saved LDTR)
|
|---|
| 450 |
|
|---|
| 451 | mov qword [xDI + CPUMCTX.eax], rax
|
|---|
| 452 | mov qword [xDI + CPUMCTX.ebx], rbx
|
|---|
| 453 | mov qword [xDI + CPUMCTX.ecx], rcx
|
|---|
| 454 | mov qword [xDI + CPUMCTX.edx], rdx
|
|---|
| 455 | mov qword [xDI + CPUMCTX.esi], rsi
|
|---|
| 456 | mov qword [xDI + CPUMCTX.ebp], rbp
|
|---|
| 457 | mov qword [xDI + CPUMCTX.r8], r8
|
|---|
| 458 | mov qword [xDI + CPUMCTX.r9], r9
|
|---|
| 459 | mov qword [xDI + CPUMCTX.r10], r10
|
|---|
| 460 | mov qword [xDI + CPUMCTX.r11], r11
|
|---|
| 461 | mov qword [xDI + CPUMCTX.r12], r12
|
|---|
| 462 | mov qword [xDI + CPUMCTX.r13], r13
|
|---|
| 463 | mov qword [xDI + CPUMCTX.r14], r14
|
|---|
| 464 | mov qword [xDI + CPUMCTX.r15], r15
|
|---|
| 465 |
|
|---|
| 466 | pop xAX ; the guest edi we pushed above
|
|---|
| 467 | mov qword [xDI + CPUMCTX.edi], rax
|
|---|
| 468 |
|
|---|
| 469 | %ifdef VBOX_WITH_DR6_EXPERIMENT
|
|---|
| 470 | ; Save DR6 - experiment, not safe!
|
|---|
| 471 | mov xAX, dr6
|
|---|
| 472 | mov [xDI + CPUMCTX.dr6], xAX
|
|---|
| 473 | %endif
|
|---|
| 474 |
|
|---|
| 475 | pop xAX ; saved LDTR
|
|---|
| 476 | lldt ax
|
|---|
| 477 |
|
|---|
| 478 | pop xSI ; pCtx (needed in rsi by the macros below)
|
|---|
| 479 |
|
|---|
| 480 | ; Restore the host LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs
|
|---|
| 481 | ;; @todo use the automatic load feature for MSRs
|
|---|
| 482 | LOADHOSTMSREX MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
|
|---|
| 483 | LOADHOSTMSR MSR_K8_SF_MASK
|
|---|
| 484 | LOADHOSTMSR MSR_K6_STAR
|
|---|
| 485 | %if 0 ; not supported on Intel CPUs
|
|---|
| 486 | LOADHOSTMSR MSR_K8_CSTAR
|
|---|
| 487 | %endif
|
|---|
| 488 | LOADHOSTMSR MSR_K8_LSTAR
|
|---|
| 489 |
|
|---|
| 490 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
|
|---|
| 491 | pop xDX ; saved pCache
|
|---|
| 492 |
|
|---|
| 493 | mov ecx, [xDX + VMCSCACHE.Read.cValidEntries]
|
|---|
| 494 | cmp ecx, 0 ; can't happen
|
|---|
| 495 | je .no_cached_reads
|
|---|
| 496 | jmp .cached_read
|
|---|
| 497 |
|
|---|
| 498 | ALIGN(16)
|
|---|
| 499 | .cached_read:
|
|---|
| 500 | dec xCX
|
|---|
| 501 | mov eax, [xDX + VMCSCACHE.Read.aField + xCX*4]
|
|---|
| 502 | vmread [xDX + VMCSCACHE.Read.aFieldVal + xCX*8], xAX
|
|---|
| 503 | cmp xCX, 0
|
|---|
| 504 | jnz .cached_read
|
|---|
| 505 | .no_cached_reads:
|
|---|
| 506 | %endif
|
|---|
| 507 |
|
|---|
| 508 | ; Restore segment registers
|
|---|
| 509 | MYPOPSEGS xAX, ax
|
|---|
| 510 |
|
|---|
| 511 | ; Restore general purpose registers
|
|---|
| 512 | MYPOPAD
|
|---|
| 513 |
|
|---|
| 514 | mov eax, VINF_SUCCESS
|
|---|
| 515 |
|
|---|
| 516 | .vmstart64_end:
|
|---|
| 517 | popf
|
|---|
| 518 | pop xBP
|
|---|
| 519 | ret
|
|---|
| 520 |
|
|---|
| 521 |
|
|---|
| 522 | .vmxstart64_invalid_vmxon_ptr:
|
|---|
| 523 | ; Restore base and limit of the IDTR & GDTR
|
|---|
| 524 | lidt [xSP]
|
|---|
| 525 | add xSP, xS*2
|
|---|
| 526 | lgdt [xSP]
|
|---|
| 527 | add xSP, xS*2
|
|---|
| 528 |
|
|---|
| 529 | pop xAX ; saved LDTR
|
|---|
| 530 | lldt ax
|
|---|
| 531 |
|
|---|
| 532 | pop xSI ; pCtx (needed in rsi by the macros below)
|
|---|
| 533 |
|
|---|
| 534 | ; Restore the host LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs
|
|---|
| 535 | ;; @todo use the automatic load feature for MSRs
|
|---|
| 536 | LOADHOSTMSREX MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
|
|---|
| 537 | LOADHOSTMSR MSR_K8_SF_MASK
|
|---|
| 538 | LOADHOSTMSR MSR_K6_STAR
|
|---|
| 539 | %if 0 ; not supported on Intel CPUs
|
|---|
| 540 | LOADHOSTMSR MSR_K8_CSTAR
|
|---|
| 541 | %endif
|
|---|
| 542 | LOADHOSTMSR MSR_K8_LSTAR
|
|---|
| 543 |
|
|---|
| 544 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
|
|---|
| 545 | add xSP, xS ; pCache
|
|---|
| 546 | %endif
|
|---|
| 547 |
|
|---|
| 548 | ; Restore segment registers
|
|---|
| 549 | MYPOPSEGS xAX, ax
|
|---|
| 550 |
|
|---|
| 551 | ; Restore all general purpose host registers.
|
|---|
| 552 | MYPOPAD
|
|---|
| 553 | mov eax, VERR_VMX_INVALID_VMXON_PTR
|
|---|
| 554 | jmp .vmstart64_end
|
|---|
| 555 |
|
|---|
| 556 | .vmxstart64_start_failed:
|
|---|
| 557 | ; Restore base and limit of the IDTR & GDTR
|
|---|
| 558 | lidt [xSP]
|
|---|
| 559 | add xSP, xS*2
|
|---|
| 560 | lgdt [xSP]
|
|---|
| 561 | add xSP, xS*2
|
|---|
| 562 |
|
|---|
| 563 | pop xAX ; saved LDTR
|
|---|
| 564 | lldt ax
|
|---|
| 565 |
|
|---|
| 566 | pop xSI ; pCtx (needed in rsi by the macros below)
|
|---|
| 567 |
|
|---|
| 568 | ; Restore the host LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs
|
|---|
| 569 | ;; @todo use the automatic load feature for MSRs
|
|---|
| 570 | LOADHOSTMSREX MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
|
|---|
| 571 | LOADHOSTMSR MSR_K8_SF_MASK
|
|---|
| 572 | LOADHOSTMSR MSR_K6_STAR
|
|---|
| 573 | %if 0 ; not supported on Intel CPUs
|
|---|
| 574 | LOADHOSTMSR MSR_K8_CSTAR
|
|---|
| 575 | %endif
|
|---|
| 576 | LOADHOSTMSR MSR_K8_LSTAR
|
|---|
| 577 |
|
|---|
| 578 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
|
|---|
| 579 | add xSP, xS ; pCache
|
|---|
| 580 | %endif
|
|---|
| 581 |
|
|---|
| 582 | ; Restore segment registers
|
|---|
| 583 | MYPOPSEGS xAX, ax
|
|---|
| 584 |
|
|---|
| 585 | ; Restore all general purpose host registers.
|
|---|
| 586 | MYPOPAD
|
|---|
| 587 | mov eax, VERR_VMX_UNABLE_TO_START_VM
|
|---|
| 588 | jmp .vmstart64_end
|
|---|
| 589 | ENDPROC MY_NAME(VMXR0StartVM64)
|
|---|
| 590 | %endif ; RT_ARCH_AMD64
|
|---|
| 591 |
|
|---|
| 592 |
|
|---|
| 593 | ;/**
|
|---|
| 594 | ; * Prepares for and executes VMRUN (32 bits guests)
|
|---|
| 595 | ; *
|
|---|
| 596 | ; * @returns VBox status code
|
|---|
| 597 | ; * @param HCPhysVMCB Physical address of host VMCB
|
|---|
| 598 | ; * @param HCPhysVMCB Physical address of guest VMCB
|
|---|
| 599 | ; * @param pCtx Guest context
|
|---|
| 600 | ; */
|
|---|
| 601 | ALIGNCODE(16)
|
|---|
| 602 | BEGINPROC MY_NAME(SVMR0VMRun)
|
|---|
| 603 | %ifdef RT_ARCH_AMD64 ; fake a cdecl stack frame
|
|---|
| 604 | %ifdef ASM_CALL64_GCC
|
|---|
| 605 | push rdx
|
|---|
| 606 | push rsi
|
|---|
| 607 | push rdi
|
|---|
| 608 | %else
|
|---|
| 609 | push r8
|
|---|
| 610 | push rdx
|
|---|
| 611 | push rcx
|
|---|
| 612 | %endif
|
|---|
| 613 | push 0
|
|---|
| 614 | %endif
|
|---|
| 615 | push xBP
|
|---|
| 616 | mov xBP, xSP
|
|---|
| 617 | pushf
|
|---|
| 618 |
|
|---|
| 619 | ;/* Manual save and restore:
|
|---|
| 620 | ; * - General purpose registers except RIP, RSP, RAX
|
|---|
| 621 | ; *
|
|---|
| 622 | ; * Trashed:
|
|---|
| 623 | ; * - CR2 (we don't care)
|
|---|
| 624 | ; * - LDTR (reset to 0)
|
|---|
| 625 | ; * - DRx (presumably not changed at all)
|
|---|
| 626 | ; * - DR7 (reset to 0x400)
|
|---|
| 627 | ; */
|
|---|
| 628 |
|
|---|
| 629 | ;/* Save all general purpose host registers. */
|
|---|
| 630 | MYPUSHAD
|
|---|
| 631 |
|
|---|
| 632 | ;/* Save the Guest CPU context pointer. */
|
|---|
| 633 | mov xSI, [xBP + xS*2 + RTHCPHYS_CB*2] ; pCtx
|
|---|
| 634 | push xSI ; push for saving the state at the end
|
|---|
| 635 |
|
|---|
| 636 | ; save host fs, gs, sysenter msr etc
|
|---|
| 637 | mov xAX, [xBP + xS*2] ; pVMCBHostPhys (64 bits physical address; x86: take low dword only)
|
|---|
| 638 | push xAX ; save for the vmload after vmrun
|
|---|
| 639 | vmsave
|
|---|
| 640 |
|
|---|
| 641 | ; setup eax for VMLOAD
|
|---|
| 642 | mov xAX, [xBP + xS*2 + RTHCPHYS_CB] ; pVMCBPhys (64 bits physical address; take low dword only)
|
|---|
| 643 |
|
|---|
| 644 | ;/* Restore Guest's general purpose registers. */
|
|---|
| 645 | ;/* EAX is loaded from the VMCB by VMRUN */
|
|---|
| 646 | mov ebx, [xSI + CPUMCTX.ebx]
|
|---|
| 647 | mov ecx, [xSI + CPUMCTX.ecx]
|
|---|
| 648 | mov edx, [xSI + CPUMCTX.edx]
|
|---|
| 649 | mov edi, [xSI + CPUMCTX.edi]
|
|---|
| 650 | mov ebp, [xSI + CPUMCTX.ebp]
|
|---|
| 651 | mov esi, [xSI + CPUMCTX.esi]
|
|---|
| 652 |
|
|---|
| 653 | ; Clear the global interrupt flag & execute sti to make sure external interrupts cause a world switch
|
|---|
| 654 | clgi
|
|---|
| 655 | sti
|
|---|
| 656 |
|
|---|
| 657 | ; load guest fs, gs, sysenter msr etc
|
|---|
| 658 | vmload
|
|---|
| 659 | ; run the VM
|
|---|
| 660 | vmrun
|
|---|
| 661 |
|
|---|
| 662 | ;/* EAX is in the VMCB already; we can use it here. */
|
|---|
| 663 |
|
|---|
| 664 | ; save guest fs, gs, sysenter msr etc
|
|---|
| 665 | vmsave
|
|---|
| 666 |
|
|---|
| 667 | ; load host fs, gs, sysenter msr etc
|
|---|
| 668 | pop xAX ; pushed above
|
|---|
| 669 | vmload
|
|---|
| 670 |
|
|---|
| 671 | ; Set the global interrupt flag again, but execute cli to make sure IF=0.
|
|---|
| 672 | cli
|
|---|
| 673 | stgi
|
|---|
| 674 |
|
|---|
| 675 | pop xAX ; pCtx
|
|---|
| 676 |
|
|---|
| 677 | mov [ss:xAX + CPUMCTX.ebx], ebx
|
|---|
| 678 | mov [ss:xAX + CPUMCTX.ecx], ecx
|
|---|
| 679 | mov [ss:xAX + CPUMCTX.edx], edx
|
|---|
| 680 | mov [ss:xAX + CPUMCTX.esi], esi
|
|---|
| 681 | mov [ss:xAX + CPUMCTX.edi], edi
|
|---|
| 682 | mov [ss:xAX + CPUMCTX.ebp], ebp
|
|---|
| 683 |
|
|---|
| 684 | ; Restore general purpose registers
|
|---|
| 685 | MYPOPAD
|
|---|
| 686 |
|
|---|
| 687 | mov eax, VINF_SUCCESS
|
|---|
| 688 |
|
|---|
| 689 | popf
|
|---|
| 690 | pop xBP
|
|---|
| 691 | %ifdef RT_ARCH_AMD64
|
|---|
| 692 | add xSP, 4*xS
|
|---|
| 693 | %endif
|
|---|
| 694 | ret
|
|---|
| 695 | ENDPROC MY_NAME(SVMR0VMRun)
|
|---|
| 696 |
|
|---|
| 697 | %ifdef RT_ARCH_AMD64
|
|---|
| 698 | ;/**
|
|---|
| 699 | ; * Prepares for and executes VMRUN (64 bits guests)
|
|---|
| 700 | ; *
|
|---|
| 701 | ; * @returns VBox status code
|
|---|
| 702 | ; * @param HCPhysVMCB Physical address of host VMCB
|
|---|
| 703 | ; * @param HCPhysVMCB Physical address of guest VMCB
|
|---|
| 704 | ; * @param pCtx Guest context
|
|---|
| 705 | ; */
|
|---|
| 706 | ALIGNCODE(16)
|
|---|
| 707 | BEGINPROC MY_NAME(SVMR0VMRun64)
|
|---|
| 708 | ; fake a cdecl stack frame
|
|---|
| 709 | %ifdef ASM_CALL64_GCC
|
|---|
| 710 | push rdx
|
|---|
| 711 | push rsi
|
|---|
| 712 | push rdi
|
|---|
| 713 | %else
|
|---|
| 714 | push r8
|
|---|
| 715 | push rdx
|
|---|
| 716 | push rcx
|
|---|
| 717 | %endif
|
|---|
| 718 | push 0
|
|---|
| 719 | push rbp
|
|---|
| 720 | mov rbp, rsp
|
|---|
| 721 | pushf
|
|---|
| 722 |
|
|---|
| 723 | ;/* Manual save and restore:
|
|---|
| 724 | ; * - General purpose registers except RIP, RSP, RAX
|
|---|
| 725 | ; *
|
|---|
| 726 | ; * Trashed:
|
|---|
| 727 | ; * - CR2 (we don't care)
|
|---|
| 728 | ; * - LDTR (reset to 0)
|
|---|
| 729 | ; * - DRx (presumably not changed at all)
|
|---|
| 730 | ; * - DR7 (reset to 0x400)
|
|---|
| 731 | ; */
|
|---|
| 732 |
|
|---|
| 733 | ;/* Save all general purpose host registers. */
|
|---|
| 734 | MYPUSHAD
|
|---|
| 735 |
|
|---|
| 736 | ;/* Save the Guest CPU context pointer. */
|
|---|
| 737 | mov rsi, [rbp + xS*2 + RTHCPHYS_CB*2] ; pCtx
|
|---|
| 738 | push rsi ; push for saving the state at the end
|
|---|
| 739 |
|
|---|
| 740 | ; save host fs, gs, sysenter msr etc
|
|---|
| 741 | mov rax, [rbp + xS*2] ; pVMCBHostPhys (64 bits physical address; x86: take low dword only)
|
|---|
| 742 | push rax ; save for the vmload after vmrun
|
|---|
| 743 | vmsave
|
|---|
| 744 |
|
|---|
| 745 | ; setup eax for VMLOAD
|
|---|
| 746 | mov rax, [rbp + xS*2 + RTHCPHYS_CB] ; pVMCBPhys (64 bits physical address; take low dword only)
|
|---|
| 747 |
|
|---|
| 748 | ;/* Restore Guest's general purpose registers. */
|
|---|
| 749 | ;/* RAX is loaded from the VMCB by VMRUN */
|
|---|
| 750 | mov rbx, qword [xSI + CPUMCTX.ebx]
|
|---|
| 751 | mov rcx, qword [xSI + CPUMCTX.ecx]
|
|---|
| 752 | mov rdx, qword [xSI + CPUMCTX.edx]
|
|---|
| 753 | mov rdi, qword [xSI + CPUMCTX.edi]
|
|---|
| 754 | mov rbp, qword [xSI + CPUMCTX.ebp]
|
|---|
| 755 | mov r8, qword [xSI + CPUMCTX.r8]
|
|---|
| 756 | mov r9, qword [xSI + CPUMCTX.r9]
|
|---|
| 757 | mov r10, qword [xSI + CPUMCTX.r10]
|
|---|
| 758 | mov r11, qword [xSI + CPUMCTX.r11]
|
|---|
| 759 | mov r12, qword [xSI + CPUMCTX.r12]
|
|---|
| 760 | mov r13, qword [xSI + CPUMCTX.r13]
|
|---|
| 761 | mov r14, qword [xSI + CPUMCTX.r14]
|
|---|
| 762 | mov r15, qword [xSI + CPUMCTX.r15]
|
|---|
| 763 | mov rsi, qword [xSI + CPUMCTX.esi]
|
|---|
| 764 |
|
|---|
| 765 | ; Clear the global interrupt flag & execute sti to make sure external interrupts cause a world switch
|
|---|
| 766 | clgi
|
|---|
| 767 | sti
|
|---|
| 768 |
|
|---|
| 769 | ; load guest fs, gs, sysenter msr etc
|
|---|
| 770 | vmload
|
|---|
| 771 | ; run the VM
|
|---|
| 772 | vmrun
|
|---|
| 773 |
|
|---|
| 774 | ;/* RAX is in the VMCB already; we can use it here. */
|
|---|
| 775 |
|
|---|
| 776 | ; save guest fs, gs, sysenter msr etc
|
|---|
| 777 | vmsave
|
|---|
| 778 |
|
|---|
| 779 | ; load host fs, gs, sysenter msr etc
|
|---|
| 780 | pop rax ; pushed above
|
|---|
| 781 | vmload
|
|---|
| 782 |
|
|---|
| 783 | ; Set the global interrupt flag again, but execute cli to make sure IF=0.
|
|---|
| 784 | cli
|
|---|
| 785 | stgi
|
|---|
| 786 |
|
|---|
| 787 | pop rax ; pCtx
|
|---|
| 788 |
|
|---|
| 789 | mov qword [rax + CPUMCTX.ebx], rbx
|
|---|
| 790 | mov qword [rax + CPUMCTX.ecx], rcx
|
|---|
| 791 | mov qword [rax + CPUMCTX.edx], rdx
|
|---|
| 792 | mov qword [rax + CPUMCTX.esi], rsi
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| 793 | mov qword [rax + CPUMCTX.edi], rdi
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| 794 | mov qword [rax + CPUMCTX.ebp], rbp
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| 795 | mov qword [rax + CPUMCTX.r8], r8
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| 796 | mov qword [rax + CPUMCTX.r9], r9
|
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| 797 | mov qword [rax + CPUMCTX.r10], r10
|
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| 798 | mov qword [rax + CPUMCTX.r11], r11
|
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| 799 | mov qword [rax + CPUMCTX.r12], r12
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| 800 | mov qword [rax + CPUMCTX.r13], r13
|
|---|
| 801 | mov qword [rax + CPUMCTX.r14], r14
|
|---|
| 802 | mov qword [rax + CPUMCTX.r15], r15
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| 803 |
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| 804 | ; Restore general purpose registers
|
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| 805 | MYPOPAD
|
|---|
| 806 |
|
|---|
| 807 | mov eax, VINF_SUCCESS
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|---|
| 808 |
|
|---|
| 809 | popf
|
|---|
| 810 | pop rbp
|
|---|
| 811 | add rsp, 4*xS
|
|---|
| 812 | ret
|
|---|
| 813 | ENDPROC MY_NAME(SVMR0VMRun64)
|
|---|
| 814 | %endif ; RT_ARCH_AMD64
|
|---|
| 815 |
|
|---|
