| 1 | ; $Id: HWACCMR0Mixed.mac 15440 2008-12-13 13:09:30Z vboxsync $
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| 2 | ;; @file
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| 3 | ; HWACCMR0Mixed.mac - Stuff that darwin needs to build two versions of.
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| 4 | ;
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| 5 | ; Included by HWACCMR0A.asm with RT_ARCH_AMD64 defined or or undefined.
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| 6 | ;
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| 7 |
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| 8 | ;
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| 9 | ; Copyright (C) 2006-2007 Sun Microsystems, Inc.
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| 10 | ;
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| 11 | ; This file is part of VirtualBox Open Source Edition (OSE), as
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| 12 | ; available from http://www.virtualbox.org. This file is free software;
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| 13 | ; you can redistribute it and/or modify it under the terms of the GNU
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| 14 | ; General Public License (GPL) as published by the Free Software
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| 15 | ; Foundation, in version 2 as it comes in the "COPYING" file of the
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| 16 | ; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 17 | ; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 18 | ;
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| 19 | ; Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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| 20 | ; Clara, CA 95054 USA or visit http://www.sun.com if you need
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| 21 | ; additional information or have any questions.
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| 22 | ;
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| 23 |
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| 24 |
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| 25 | ;/**
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| 26 | ; * Prepares for and executes VMLAUNCH/VMRESUME (32 bits guest mode)
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| 27 | ; *
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| 28 | ; * @returns VBox status code
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| 29 | ; * @param fResume x86:[ebp+8], msc:rcx,gcc:rdi vmlauch/vmresume
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| 30 | ; * @param pCtx x86:[ebp+c], msc:rdx,gcc:rsi Guest context
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| 31 | ; * @param pCache x86:[esp+10],msc:r8, gcc:rdx VMCS cache
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| 32 | ; */
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| 33 | ALIGNCODE(16)
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| 34 | BEGINPROC MY_NAME(VMXR0StartVM32)
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| 35 | push xBP
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| 36 | mov xBP, xSP
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| 37 |
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| 38 | pushf
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| 39 | cli
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| 40 |
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| 41 | ;/* Save all general purpose host registers. */
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| 42 | MYPUSHAD
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| 43 |
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| 44 | ;/* First we have to save some final CPU context registers. */
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| 45 | mov eax, VMX_VMCS_HOST_RIP
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| 46 | %ifdef RT_ARCH_AMD64
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| 47 | lea r10, [.vmlaunch_done wrt rip]
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| 48 | vmwrite rax, r10
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| 49 | %else
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| 50 | mov ecx, .vmlaunch_done
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| 51 | vmwrite eax, ecx
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| 52 | %endif
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| 53 | ;/* Note: assumes success... */
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| 54 |
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| 55 | ;/* Manual save and restore:
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| 56 | ; * - General purpose registers except RIP, RSP
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| 57 | ; *
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| 58 | ; * Trashed:
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| 59 | ; * - CR2 (we don't care)
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| 60 | ; * - LDTR (reset to 0)
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| 61 | ; * - DRx (presumably not changed at all)
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| 62 | ; * - DR7 (reset to 0x400)
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| 63 | ; * - EFLAGS (reset to RT_BIT(1); not relevant)
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| 64 | ; *
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| 65 | ; */
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| 66 |
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| 67 | ;/* Save the Guest CPU context pointer. */
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| 68 | %ifdef RT_ARCH_AMD64
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| 69 | %ifdef ASM_CALL64_GCC
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| 70 | ; fResume already in rdi
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| 71 | ; pCtx already in rsi
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| 72 | mov rbx, rdx ; pCache
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| 73 | %else
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| 74 | mov rdi, rcx ; fResume
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| 75 | mov rsi, rdx ; pCtx
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| 76 | mov rbx, r8 ; pCache
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| 77 | %endif
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| 78 | %else
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| 79 | mov edi, [ebp + 8] ; fResume
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| 80 | mov esi, [ebp + 12] ; pCtx
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| 81 | mov ebx, [ebp + 16] ; pCache
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| 82 | %endif
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| 83 |
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| 84 | ;/* Save segment registers */
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| 85 | ; Note: MYPUSHSEGS trashes rdx & rcx, so we moved it here (msvc amd64 case)
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| 86 | MYPUSHSEGS xAX, ax
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| 87 |
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| 88 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
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| 89 | mov ecx, [xBX + VMCSCACHE.Write.cValidEntries]
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| 90 | cmp ecx, 0
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| 91 | je .no_cached_writes
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| 92 | mov edx, ecx
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| 93 | mov ecx, 0
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| 94 | jmp .cached_write
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| 95 |
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| 96 | ALIGN(16)
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| 97 | .cached_write:
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| 98 | mov eax, [xBX + VMCSCACHE.Write.aField + xCX*4]
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| 99 | vmwrite xAX, [xBX + VMCSCACHE.Write.aFieldVal + xCX*8]
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| 100 | inc xCX
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| 101 | cmp xCX, xDX
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| 102 | jl .cached_write
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| 103 |
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| 104 | mov dword [xBX + VMCSCACHE.Write.cValidEntries], 0
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| 105 | .no_cached_writes:
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| 106 |
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| 107 | ; Save the pCache pointer
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| 108 | push xBX
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| 109 | %endif
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| 110 |
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| 111 | ; Save the pCtx pointer
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| 112 | push xSI
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| 113 |
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| 114 | ; Save LDTR
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| 115 | xor eax, eax
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| 116 | sldt ax
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| 117 | push xAX
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| 118 |
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| 119 | ; VMX only saves the base of the GDTR & IDTR and resets the limit to 0xffff; we must restore the limit correctly!
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| 120 | sub xSP, xS*2
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| 121 | sgdt [xSP]
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| 122 |
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| 123 | sub xSP, xS*2
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| 124 | sidt [xSP]
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| 125 |
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| 126 | %ifdef VBOX_WITH_DR6_EXPERIMENT
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| 127 | ; Restore DR6 - experiment, not safe!
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| 128 | mov xBX, [xSI + CPUMCTX.dr6]
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| 129 | mov dr6, xBX
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| 130 | %endif
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| 131 |
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| 132 | ; Restore CR2
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| 133 | mov ebx, [xSI + CPUMCTX.cr2]
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| 134 | mov cr2, xBX
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| 135 |
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| 136 | mov eax, VMX_VMCS_HOST_RSP
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| 137 | vmwrite xAX, xSP
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| 138 | ;/* Note: assumes success... */
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| 139 | ;/* Don't mess with ESP anymore!! */
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| 140 |
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| 141 | ;/* Restore Guest's general purpose registers. */
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| 142 | mov eax, [xSI + CPUMCTX.eax]
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| 143 | mov ebx, [xSI + CPUMCTX.ebx]
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| 144 | mov ecx, [xSI + CPUMCTX.ecx]
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| 145 | mov edx, [xSI + CPUMCTX.edx]
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| 146 | mov ebp, [xSI + CPUMCTX.ebp]
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| 147 |
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| 148 | ; resume or start?
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| 149 | cmp xDI, 0 ; fResume
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| 150 | je .vmlauch_lauch
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| 151 |
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| 152 | ;/* Restore edi & esi. */
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| 153 | mov edi, [xSI + CPUMCTX.edi]
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| 154 | mov esi, [xSI + CPUMCTX.esi]
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| 155 |
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| 156 | vmresume
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| 157 | jmp .vmlaunch_done; ;/* here if vmresume detected a failure. */
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| 158 |
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| 159 | .vmlauch_lauch:
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| 160 | ;/* Restore edi & esi. */
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| 161 | mov edi, [xSI + CPUMCTX.edi]
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| 162 | mov esi, [xSI + CPUMCTX.esi]
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| 163 |
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| 164 | vmlaunch
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| 165 | jmp .vmlaunch_done; ;/* here if vmlaunch detected a failure. */
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| 166 |
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| 167 | ALIGNCODE(16) ;; @todo YASM BUG - this alignment is wrong on darwin, it's 1 byte off.
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| 168 | .vmlaunch_done:
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| 169 | jc near .vmxstart_invalid_vmxon_ptr
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| 170 | jz near .vmxstart_start_failed
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| 171 |
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| 172 | ; Restore base and limit of the IDTR & GDTR
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| 173 | lidt [xSP]
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| 174 | add xSP, xS*2
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| 175 | lgdt [xSP]
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| 176 | add xSP, xS*2
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| 177 |
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| 178 | push xDI
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| 179 | mov xDI, [xSP + xS * 2] ; pCtx (*2 to skip the saved LDTR)
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| 180 |
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| 181 | mov [ss:xDI + CPUMCTX.eax], eax
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| 182 | mov [ss:xDI + CPUMCTX.ebx], ebx
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| 183 | mov [ss:xDI + CPUMCTX.ecx], ecx
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| 184 | mov [ss:xDI + CPUMCTX.edx], edx
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| 185 | mov [ss:xDI + CPUMCTX.esi], esi
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| 186 | mov [ss:xDI + CPUMCTX.ebp], ebp
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| 187 | %ifdef RT_ARCH_AMD64
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| 188 | pop xAX ; the guest edi we pushed above
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| 189 | mov dword [ss:xDI + CPUMCTX.edi], eax
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| 190 | %else
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| 191 | pop dword [ss:xDI + CPUMCTX.edi] ; the guest edi we pushed above
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| 192 | %endif
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| 193 |
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| 194 | %ifdef VBOX_WITH_DR6_EXPERIMENT
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| 195 | ; Save DR6 - experiment, not safe!
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| 196 | mov xAX, dr6
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| 197 | mov [ss:xDI + CPUMCTX.dr6], xAX
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| 198 | %endif
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| 199 |
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| 200 | pop xAX ; saved LDTR
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| 201 | lldt ax
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| 202 |
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| 203 | add xSP, xS ; pCtx
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| 204 |
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| 205 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
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| 206 | pop xDX ; saved pCache
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| 207 |
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| 208 | mov ecx, [ss:xDX + VMCSCACHE.Read.cValidEntries]
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| 209 | cmp ecx, 0 ; can't happen
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| 210 | je .no_cached_reads
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| 211 | jmp .cached_read
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| 212 |
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| 213 | ALIGN(16)
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| 214 | .cached_read:
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| 215 | dec xCX
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| 216 | mov eax, [ss:xDX + VMCSCACHE.Read.aField + xCX*4]
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| 217 | vmread [ss:xDX + VMCSCACHE.Read.aFieldVal + xCX*8], xAX
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| 218 | cmp xCX, 0
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| 219 | jnz .cached_read
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| 220 | .no_cached_reads:
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| 221 |
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| 222 | ; Save CR2 for EPT
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| 223 | mov xAX, cr2
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| 224 | mov [ss:xDX + VMCSCACHE.cr2], xAX
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| 225 | %endif
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| 226 |
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| 227 | ; Restore segment registers
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| 228 | MYPOPSEGS xAX, ax
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| 229 |
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| 230 | ; Restore general purpose registers
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| 231 | MYPOPAD
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| 232 |
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| 233 | mov eax, VINF_SUCCESS
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| 234 |
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| 235 | .vmstart_end:
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| 236 | popf
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| 237 | pop xBP
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| 238 | ret
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| 239 |
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| 240 |
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| 241 | .vmxstart_invalid_vmxon_ptr:
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| 242 | ; Restore base and limit of the IDTR & GDTR
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| 243 | lidt [xSP]
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| 244 | add xSP, xS*2
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| 245 | lgdt [xSP]
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| 246 | add xSP, xS*2
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| 247 |
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| 248 | pop xAX ; saved LDTR
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| 249 | lldt ax
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| 250 |
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| 251 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
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| 252 | add xSP, xS*2 ; pCtx + pCache
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| 253 | %else
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| 254 | add xSP, xS ; pCtx
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| 255 | %endif
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| 256 |
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| 257 | ; Restore segment registers
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| 258 | MYPOPSEGS xAX, ax
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| 259 |
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| 260 | ; Restore all general purpose host registers.
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| 261 | MYPOPAD
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| 262 | mov eax, VERR_VMX_INVALID_VMXON_PTR
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| 263 | jmp .vmstart_end
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| 264 |
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| 265 | .vmxstart_start_failed:
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| 266 | ; Restore base and limit of the IDTR & GDTR
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| 267 | lidt [xSP]
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| 268 | add xSP, xS*2
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| 269 | lgdt [xSP]
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| 270 | add xSP, xS*2
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| 271 |
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| 272 | pop xAX ; saved LDTR
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| 273 | lldt ax
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| 274 |
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| 275 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
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| 276 | add xSP, xS*2 ; pCtx + pCache
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| 277 | %else
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| 278 | add xSP, xS ; pCtx
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| 279 | %endif
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| 280 |
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| 281 | ; Restore segment registers
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| 282 | MYPOPSEGS xAX, ax
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| 283 |
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| 284 | ; Restore all general purpose host registers.
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| 285 | MYPOPAD
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| 286 | mov eax, VERR_VMX_UNABLE_TO_START_VM
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| 287 | jmp .vmstart_end
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| 288 |
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| 289 | ENDPROC MY_NAME(VMXR0StartVM32)
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| 290 |
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| 291 | %ifdef RT_ARCH_AMD64
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| 292 | ;/**
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| 293 | ; * Prepares for and executes VMLAUNCH/VMRESUME (64 bits guest mode)
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| 294 | ; *
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| 295 | ; * @returns VBox status code
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| 296 | ; * @param fResume msc:rcx, gcc:rdi vmlauch/vmresume
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| 297 | ; * @param pCtx msc:rdx, gcc:rsi Guest context
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| 298 | ; * @param pCache msc:r8, gcc:rdx VMCS cache
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| 299 | ; */
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| 300 | ALIGNCODE(16)
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| 301 | BEGINPROC MY_NAME(VMXR0StartVM64)
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| 302 | push xBP
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| 303 | mov xBP, xSP
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| 304 |
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| 305 | pushf
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| 306 | cli
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| 307 |
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| 308 | ;/* Save all general purpose host registers. */
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| 309 | MYPUSHAD
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| 310 |
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| 311 | ;/* First we have to save some final CPU context registers. */
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| 312 | lea r10, [.vmlaunch64_done wrt rip]
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| 313 | mov rax, VMX_VMCS_HOST_RIP ;/* return address (too difficult to continue after VMLAUNCH?) */
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| 314 | vmwrite rax, r10
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| 315 | ;/* Note: assumes success... */
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| 316 |
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| 317 | ;/* Manual save and restore:
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| 318 | ; * - General purpose registers except RIP, RSP
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| 319 | ; *
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| 320 | ; * Trashed:
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| 321 | ; * - CR2 (we don't care)
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| 322 | ; * - LDTR (reset to 0)
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| 323 | ; * - DRx (presumably not changed at all)
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| 324 | ; * - DR7 (reset to 0x400)
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| 325 | ; * - EFLAGS (reset to RT_BIT(1); not relevant)
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| 326 | ; *
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| 327 | ; */
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| 328 |
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| 329 | ;/* Save the Guest CPU context pointer. */
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| 330 | %ifdef ASM_CALL64_GCC
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| 331 | ; fResume already in rdi
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| 332 | ; pCtx already in rsi
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| 333 | mov rbx, rdx ; pCache
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| 334 | %else
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| 335 | mov rdi, rcx ; fResume
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| 336 | mov rsi, rdx ; pCtx
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| 337 | mov rbx, r8 ; pCache
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| 338 | %endif
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| 339 |
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| 340 | ;/* Save segment registers */
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| 341 | ; Note: MYPUSHSEGS trashes rdx & rcx, so we moved it here (msvc amd64 case)
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| 342 | MYPUSHSEGS xAX, ax
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| 343 |
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| 344 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
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| 345 | mov ecx, [xBX + VMCSCACHE.Write.cValidEntries]
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| 346 | cmp ecx, 0
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| 347 | je .no_cached_writes
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| 348 | mov edx, ecx
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| 349 | mov ecx, 0
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| 350 | jmp .cached_write
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| 351 |
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| 352 | ALIGN(16)
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| 353 | .cached_write:
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| 354 | mov eax, [xBX + VMCSCACHE.Write.aField + xCX*4]
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| 355 | vmwrite xAX, [xBX + VMCSCACHE.Write.aFieldVal + xCX*8]
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| 356 | inc xCX
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| 357 | cmp xCX, xDX
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| 358 | jl .cached_write
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| 359 |
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| 360 | mov dword [xBX + VMCSCACHE.Write.cValidEntries], 0
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| 361 | .no_cached_writes:
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| 362 |
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| 363 | ; Save the pCache pointer
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| 364 | push xBX
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| 365 | %endif
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| 366 |
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| 367 | ; Save the host LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs and restore the guest MSRs
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| 368 | ;; @todo use the automatic load feature for MSRs
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| 369 | LOADGUESTMSR MSR_K8_LSTAR, CPUMCTX.msrLSTAR
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| 370 | %if 0 ; not supported on Intel CPUs
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| 371 | LOADGUESTMSR MSR_K8_CSTAR, CPUMCTX.msrCSTAR
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| 372 | %endif
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| 373 | LOADGUESTMSR MSR_K6_STAR, CPUMCTX.msrSTAR
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| 374 | LOADGUESTMSR MSR_K8_SF_MASK, CPUMCTX.msrSFMASK
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| 375 | LOADGUESTMSR MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
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| 376 |
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| 377 | ; Save the pCtx pointer
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| 378 | push xSI
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| 379 |
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| 380 | ; Save LDTR
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| 381 | xor eax, eax
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| 382 | sldt ax
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| 383 | push xAX
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| 384 |
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| 385 | ; VMX only saves the base of the GDTR & IDTR and resets the limit to 0xffff; we must restore the limit correctly!
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| 386 | sub xSP, xS*2
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| 387 | sgdt [xSP]
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| 388 |
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| 389 | sub xSP, xS*2
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| 390 | sidt [xSP]
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| 391 |
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| 392 | %ifdef VBOX_WITH_DR6_EXPERIMENT
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| 393 | ; Restore DR6 - experiment, not safe!
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| 394 | mov xBX, [xSI + CPUMCTX.dr6]
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| 395 | mov dr6, xBX
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| 396 | %endif
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| 397 |
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| 398 | ; Restore CR2
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| 399 | mov rbx, qword [xSI + CPUMCTX.cr2]
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| 400 | mov cr2, rbx
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| 401 |
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| 402 | mov eax, VMX_VMCS_HOST_RSP
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| 403 | vmwrite xAX, xSP
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| 404 | ;/* Note: assumes success... */
|
|---|
| 405 | ;/* Don't mess with ESP anymore!! */
|
|---|
| 406 |
|
|---|
| 407 | ;/* Restore Guest's general purpose registers. */
|
|---|
| 408 | mov rax, qword [xSI + CPUMCTX.eax]
|
|---|
| 409 | mov rbx, qword [xSI + CPUMCTX.ebx]
|
|---|
| 410 | mov rcx, qword [xSI + CPUMCTX.ecx]
|
|---|
| 411 | mov rdx, qword [xSI + CPUMCTX.edx]
|
|---|
| 412 | mov rbp, qword [xSI + CPUMCTX.ebp]
|
|---|
| 413 | mov r8, qword [xSI + CPUMCTX.r8]
|
|---|
| 414 | mov r9, qword [xSI + CPUMCTX.r9]
|
|---|
| 415 | mov r10, qword [xSI + CPUMCTX.r10]
|
|---|
| 416 | mov r11, qword [xSI + CPUMCTX.r11]
|
|---|
| 417 | mov r12, qword [xSI + CPUMCTX.r12]
|
|---|
| 418 | mov r13, qword [xSI + CPUMCTX.r13]
|
|---|
| 419 | mov r14, qword [xSI + CPUMCTX.r14]
|
|---|
| 420 | mov r15, qword [xSI + CPUMCTX.r15]
|
|---|
| 421 |
|
|---|
| 422 | ; resume or start?
|
|---|
| 423 | cmp xDI, 0 ; fResume
|
|---|
| 424 | je .vmlauch64_lauch
|
|---|
| 425 |
|
|---|
| 426 | ;/* Restore edi & esi. */
|
|---|
| 427 | mov rdi, qword [xSI + CPUMCTX.edi]
|
|---|
| 428 | mov rsi, qword [xSI + CPUMCTX.esi]
|
|---|
| 429 |
|
|---|
| 430 | vmresume
|
|---|
| 431 | jmp .vmlaunch64_done; ;/* here if vmresume detected a failure. */
|
|---|
| 432 |
|
|---|
| 433 | .vmlauch64_lauch:
|
|---|
| 434 | ;/* Restore rdi & rsi. */
|
|---|
| 435 | mov rdi, qword [xSI + CPUMCTX.edi]
|
|---|
| 436 | mov rsi, qword [xSI + CPUMCTX.esi]
|
|---|
| 437 |
|
|---|
| 438 | vmlaunch
|
|---|
| 439 | jmp .vmlaunch64_done; ;/* here if vmlaunch detected a failure. */
|
|---|
| 440 |
|
|---|
| 441 | ALIGNCODE(16)
|
|---|
| 442 | .vmlaunch64_done:
|
|---|
| 443 | jc near .vmxstart64_invalid_vmxon_ptr
|
|---|
| 444 | jz near .vmxstart64_start_failed
|
|---|
| 445 |
|
|---|
| 446 | ; Restore base and limit of the IDTR & GDTR
|
|---|
| 447 | lidt [xSP]
|
|---|
| 448 | add xSP, xS*2
|
|---|
| 449 | lgdt [xSP]
|
|---|
| 450 | add xSP, xS*2
|
|---|
| 451 |
|
|---|
| 452 | push xDI
|
|---|
| 453 | mov xDI, [xSP + xS * 2] ; pCtx (*2 to skip the saved LDTR)
|
|---|
| 454 |
|
|---|
| 455 | mov qword [xDI + CPUMCTX.eax], rax
|
|---|
| 456 | mov qword [xDI + CPUMCTX.ebx], rbx
|
|---|
| 457 | mov qword [xDI + CPUMCTX.ecx], rcx
|
|---|
| 458 | mov qword [xDI + CPUMCTX.edx], rdx
|
|---|
| 459 | mov qword [xDI + CPUMCTX.esi], rsi
|
|---|
| 460 | mov qword [xDI + CPUMCTX.ebp], rbp
|
|---|
| 461 | mov qword [xDI + CPUMCTX.r8], r8
|
|---|
| 462 | mov qword [xDI + CPUMCTX.r9], r9
|
|---|
| 463 | mov qword [xDI + CPUMCTX.r10], r10
|
|---|
| 464 | mov qword [xDI + CPUMCTX.r11], r11
|
|---|
| 465 | mov qword [xDI + CPUMCTX.r12], r12
|
|---|
| 466 | mov qword [xDI + CPUMCTX.r13], r13
|
|---|
| 467 | mov qword [xDI + CPUMCTX.r14], r14
|
|---|
| 468 | mov qword [xDI + CPUMCTX.r15], r15
|
|---|
| 469 |
|
|---|
| 470 | pop xAX ; the guest edi we pushed above
|
|---|
| 471 | mov qword [xDI + CPUMCTX.edi], rax
|
|---|
| 472 |
|
|---|
| 473 | %ifdef VBOX_WITH_DR6_EXPERIMENT
|
|---|
| 474 | ; Save DR6 - experiment, not safe!
|
|---|
| 475 | mov xAX, dr6
|
|---|
| 476 | mov [xDI + CPUMCTX.dr6], xAX
|
|---|
| 477 | %endif
|
|---|
| 478 |
|
|---|
| 479 | pop xAX ; saved LDTR
|
|---|
| 480 | lldt ax
|
|---|
| 481 |
|
|---|
| 482 | pop xSI ; pCtx (needed in rsi by the macros below)
|
|---|
| 483 |
|
|---|
| 484 | ; Restore the host LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs
|
|---|
| 485 | ;; @todo use the automatic load feature for MSRs
|
|---|
| 486 | LOADHOSTMSREX MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
|
|---|
| 487 | LOADHOSTMSR MSR_K8_SF_MASK
|
|---|
| 488 | LOADHOSTMSR MSR_K6_STAR
|
|---|
| 489 | %if 0 ; not supported on Intel CPUs
|
|---|
| 490 | LOADHOSTMSR MSR_K8_CSTAR
|
|---|
| 491 | %endif
|
|---|
| 492 | LOADHOSTMSR MSR_K8_LSTAR
|
|---|
| 493 |
|
|---|
| 494 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
|
|---|
| 495 | pop xDX ; saved pCache
|
|---|
| 496 |
|
|---|
| 497 | mov ecx, [xDX + VMCSCACHE.Read.cValidEntries]
|
|---|
| 498 | cmp ecx, 0 ; can't happen
|
|---|
| 499 | je .no_cached_reads
|
|---|
| 500 | jmp .cached_read
|
|---|
| 501 |
|
|---|
| 502 | ALIGN(16)
|
|---|
| 503 | .cached_read:
|
|---|
| 504 | dec xCX
|
|---|
| 505 | mov eax, [xDX + VMCSCACHE.Read.aField + xCX*4]
|
|---|
| 506 | vmread [xDX + VMCSCACHE.Read.aFieldVal + xCX*8], xAX
|
|---|
| 507 | cmp xCX, 0
|
|---|
| 508 | jnz .cached_read
|
|---|
| 509 | .no_cached_reads:
|
|---|
| 510 |
|
|---|
| 511 | ; Save CR2 for EPT
|
|---|
| 512 | mov xAX, cr2
|
|---|
| 513 | mov [xDX + VMCSCACHE.cr2], xAX
|
|---|
| 514 | %endif
|
|---|
| 515 |
|
|---|
| 516 | ; Restore segment registers
|
|---|
| 517 | MYPOPSEGS xAX, ax
|
|---|
| 518 |
|
|---|
| 519 | ; Restore general purpose registers
|
|---|
| 520 | MYPOPAD
|
|---|
| 521 |
|
|---|
| 522 | mov eax, VINF_SUCCESS
|
|---|
| 523 |
|
|---|
| 524 | .vmstart64_end:
|
|---|
| 525 | popf
|
|---|
| 526 | pop xBP
|
|---|
| 527 | ret
|
|---|
| 528 |
|
|---|
| 529 |
|
|---|
| 530 | .vmxstart64_invalid_vmxon_ptr:
|
|---|
| 531 | ; Restore base and limit of the IDTR & GDTR
|
|---|
| 532 | lidt [xSP]
|
|---|
| 533 | add xSP, xS*2
|
|---|
| 534 | lgdt [xSP]
|
|---|
| 535 | add xSP, xS*2
|
|---|
| 536 |
|
|---|
| 537 | pop xAX ; saved LDTR
|
|---|
| 538 | lldt ax
|
|---|
| 539 |
|
|---|
| 540 | pop xSI ; pCtx (needed in rsi by the macros below)
|
|---|
| 541 |
|
|---|
| 542 | ; Restore the host LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs
|
|---|
| 543 | ;; @todo use the automatic load feature for MSRs
|
|---|
| 544 | LOADHOSTMSREX MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
|
|---|
| 545 | LOADHOSTMSR MSR_K8_SF_MASK
|
|---|
| 546 | LOADHOSTMSR MSR_K6_STAR
|
|---|
| 547 | %if 0 ; not supported on Intel CPUs
|
|---|
| 548 | LOADHOSTMSR MSR_K8_CSTAR
|
|---|
| 549 | %endif
|
|---|
| 550 | LOADHOSTMSR MSR_K8_LSTAR
|
|---|
| 551 |
|
|---|
| 552 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
|
|---|
| 553 | add xSP, xS ; pCache
|
|---|
| 554 | %endif
|
|---|
| 555 |
|
|---|
| 556 | ; Restore segment registers
|
|---|
| 557 | MYPOPSEGS xAX, ax
|
|---|
| 558 |
|
|---|
| 559 | ; Restore all general purpose host registers.
|
|---|
| 560 | MYPOPAD
|
|---|
| 561 | mov eax, VERR_VMX_INVALID_VMXON_PTR
|
|---|
| 562 | jmp .vmstart64_end
|
|---|
| 563 |
|
|---|
| 564 | .vmxstart64_start_failed:
|
|---|
| 565 | ; Restore base and limit of the IDTR & GDTR
|
|---|
| 566 | lidt [xSP]
|
|---|
| 567 | add xSP, xS*2
|
|---|
| 568 | lgdt [xSP]
|
|---|
| 569 | add xSP, xS*2
|
|---|
| 570 |
|
|---|
| 571 | pop xAX ; saved LDTR
|
|---|
| 572 | lldt ax
|
|---|
| 573 |
|
|---|
| 574 | pop xSI ; pCtx (needed in rsi by the macros below)
|
|---|
| 575 |
|
|---|
| 576 | ; Restore the host LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs
|
|---|
| 577 | ;; @todo use the automatic load feature for MSRs
|
|---|
| 578 | LOADHOSTMSREX MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
|
|---|
| 579 | LOADHOSTMSR MSR_K8_SF_MASK
|
|---|
| 580 | LOADHOSTMSR MSR_K6_STAR
|
|---|
| 581 | %if 0 ; not supported on Intel CPUs
|
|---|
| 582 | LOADHOSTMSR MSR_K8_CSTAR
|
|---|
| 583 | %endif
|
|---|
| 584 | LOADHOSTMSR MSR_K8_LSTAR
|
|---|
| 585 |
|
|---|
| 586 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
|
|---|
| 587 | add xSP, xS ; pCache
|
|---|
| 588 | %endif
|
|---|
| 589 |
|
|---|
| 590 | ; Restore segment registers
|
|---|
| 591 | MYPOPSEGS xAX, ax
|
|---|
| 592 |
|
|---|
| 593 | ; Restore all general purpose host registers.
|
|---|
| 594 | MYPOPAD
|
|---|
| 595 | mov eax, VERR_VMX_UNABLE_TO_START_VM
|
|---|
| 596 | jmp .vmstart64_end
|
|---|
| 597 | ENDPROC MY_NAME(VMXR0StartVM64)
|
|---|
| 598 | %endif ; RT_ARCH_AMD64
|
|---|
| 599 |
|
|---|
| 600 |
|
|---|
| 601 | ;/**
|
|---|
| 602 | ; * Prepares for and executes VMRUN (32 bits guests)
|
|---|
| 603 | ; *
|
|---|
| 604 | ; * @returns VBox status code
|
|---|
| 605 | ; * @param HCPhysVMCB Physical address of host VMCB
|
|---|
| 606 | ; * @param HCPhysVMCB Physical address of guest VMCB
|
|---|
| 607 | ; * @param pCtx Guest context
|
|---|
| 608 | ; */
|
|---|
| 609 | ALIGNCODE(16)
|
|---|
| 610 | BEGINPROC MY_NAME(SVMR0VMRun)
|
|---|
| 611 | %ifdef RT_ARCH_AMD64 ; fake a cdecl stack frame
|
|---|
| 612 | %ifdef ASM_CALL64_GCC
|
|---|
| 613 | push rdx
|
|---|
| 614 | push rsi
|
|---|
| 615 | push rdi
|
|---|
| 616 | %else
|
|---|
| 617 | push r8
|
|---|
| 618 | push rdx
|
|---|
| 619 | push rcx
|
|---|
| 620 | %endif
|
|---|
| 621 | push 0
|
|---|
| 622 | %endif
|
|---|
| 623 | push xBP
|
|---|
| 624 | mov xBP, xSP
|
|---|
| 625 | pushf
|
|---|
| 626 |
|
|---|
| 627 | ;/* Manual save and restore:
|
|---|
| 628 | ; * - General purpose registers except RIP, RSP, RAX
|
|---|
| 629 | ; *
|
|---|
| 630 | ; * Trashed:
|
|---|
| 631 | ; * - CR2 (we don't care)
|
|---|
| 632 | ; * - LDTR (reset to 0)
|
|---|
| 633 | ; * - DRx (presumably not changed at all)
|
|---|
| 634 | ; * - DR7 (reset to 0x400)
|
|---|
| 635 | ; */
|
|---|
| 636 |
|
|---|
| 637 | ;/* Save all general purpose host registers. */
|
|---|
| 638 | MYPUSHAD
|
|---|
| 639 |
|
|---|
| 640 | ;/* Save the Guest CPU context pointer. */
|
|---|
| 641 | mov xSI, [xBP + xS*2 + RTHCPHYS_CB*2] ; pCtx
|
|---|
| 642 | push xSI ; push for saving the state at the end
|
|---|
| 643 |
|
|---|
| 644 | ; save host fs, gs, sysenter msr etc
|
|---|
| 645 | mov xAX, [xBP + xS*2] ; pVMCBHostPhys (64 bits physical address; x86: take low dword only)
|
|---|
| 646 | push xAX ; save for the vmload after vmrun
|
|---|
| 647 | vmsave
|
|---|
| 648 |
|
|---|
| 649 | ; setup eax for VMLOAD
|
|---|
| 650 | mov xAX, [xBP + xS*2 + RTHCPHYS_CB] ; pVMCBPhys (64 bits physical address; take low dword only)
|
|---|
| 651 |
|
|---|
| 652 | ;/* Restore Guest's general purpose registers. */
|
|---|
| 653 | ;/* EAX is loaded from the VMCB by VMRUN */
|
|---|
| 654 | mov ebx, [xSI + CPUMCTX.ebx]
|
|---|
| 655 | mov ecx, [xSI + CPUMCTX.ecx]
|
|---|
| 656 | mov edx, [xSI + CPUMCTX.edx]
|
|---|
| 657 | mov edi, [xSI + CPUMCTX.edi]
|
|---|
| 658 | mov ebp, [xSI + CPUMCTX.ebp]
|
|---|
| 659 | mov esi, [xSI + CPUMCTX.esi]
|
|---|
| 660 |
|
|---|
| 661 | ; Clear the global interrupt flag & execute sti to make sure external interrupts cause a world switch
|
|---|
| 662 | clgi
|
|---|
| 663 | sti
|
|---|
| 664 |
|
|---|
| 665 | ; load guest fs, gs, sysenter msr etc
|
|---|
| 666 | vmload
|
|---|
| 667 | ; run the VM
|
|---|
| 668 | vmrun
|
|---|
| 669 |
|
|---|
| 670 | ;/* EAX is in the VMCB already; we can use it here. */
|
|---|
| 671 |
|
|---|
| 672 | ; save guest fs, gs, sysenter msr etc
|
|---|
| 673 | vmsave
|
|---|
| 674 |
|
|---|
| 675 | ; load host fs, gs, sysenter msr etc
|
|---|
| 676 | pop xAX ; pushed above
|
|---|
| 677 | vmload
|
|---|
| 678 |
|
|---|
| 679 | ; Set the global interrupt flag again, but execute cli to make sure IF=0.
|
|---|
| 680 | cli
|
|---|
| 681 | stgi
|
|---|
| 682 |
|
|---|
| 683 | pop xAX ; pCtx
|
|---|
| 684 |
|
|---|
| 685 | mov [ss:xAX + CPUMCTX.ebx], ebx
|
|---|
| 686 | mov [ss:xAX + CPUMCTX.ecx], ecx
|
|---|
| 687 | mov [ss:xAX + CPUMCTX.edx], edx
|
|---|
| 688 | mov [ss:xAX + CPUMCTX.esi], esi
|
|---|
| 689 | mov [ss:xAX + CPUMCTX.edi], edi
|
|---|
| 690 | mov [ss:xAX + CPUMCTX.ebp], ebp
|
|---|
| 691 |
|
|---|
| 692 | ; Restore general purpose registers
|
|---|
| 693 | MYPOPAD
|
|---|
| 694 |
|
|---|
| 695 | mov eax, VINF_SUCCESS
|
|---|
| 696 |
|
|---|
| 697 | popf
|
|---|
| 698 | pop xBP
|
|---|
| 699 | %ifdef RT_ARCH_AMD64
|
|---|
| 700 | add xSP, 4*xS
|
|---|
| 701 | %endif
|
|---|
| 702 | ret
|
|---|
| 703 | ENDPROC MY_NAME(SVMR0VMRun)
|
|---|
| 704 |
|
|---|
| 705 | %ifdef RT_ARCH_AMD64
|
|---|
| 706 | ;/**
|
|---|
| 707 | ; * Prepares for and executes VMRUN (64 bits guests)
|
|---|
| 708 | ; *
|
|---|
| 709 | ; * @returns VBox status code
|
|---|
| 710 | ; * @param HCPhysVMCB Physical address of host VMCB
|
|---|
| 711 | ; * @param HCPhysVMCB Physical address of guest VMCB
|
|---|
| 712 | ; * @param pCtx Guest context
|
|---|
| 713 | ; */
|
|---|
| 714 | ALIGNCODE(16)
|
|---|
| 715 | BEGINPROC MY_NAME(SVMR0VMRun64)
|
|---|
| 716 | ; fake a cdecl stack frame
|
|---|
| 717 | %ifdef ASM_CALL64_GCC
|
|---|
| 718 | push rdx
|
|---|
| 719 | push rsi
|
|---|
| 720 | push rdi
|
|---|
| 721 | %else
|
|---|
| 722 | push r8
|
|---|
| 723 | push rdx
|
|---|
| 724 | push rcx
|
|---|
| 725 | %endif
|
|---|
| 726 | push 0
|
|---|
| 727 | push rbp
|
|---|
| 728 | mov rbp, rsp
|
|---|
| 729 | pushf
|
|---|
| 730 |
|
|---|
| 731 | ;/* Manual save and restore:
|
|---|
| 732 | ; * - General purpose registers except RIP, RSP, RAX
|
|---|
| 733 | ; *
|
|---|
| 734 | ; * Trashed:
|
|---|
| 735 | ; * - CR2 (we don't care)
|
|---|
| 736 | ; * - LDTR (reset to 0)
|
|---|
| 737 | ; * - DRx (presumably not changed at all)
|
|---|
| 738 | ; * - DR7 (reset to 0x400)
|
|---|
| 739 | ; */
|
|---|
| 740 |
|
|---|
| 741 | ;/* Save all general purpose host registers. */
|
|---|
| 742 | MYPUSHAD
|
|---|
| 743 |
|
|---|
| 744 | ;/* Save the Guest CPU context pointer. */
|
|---|
| 745 | mov rsi, [rbp + xS*2 + RTHCPHYS_CB*2] ; pCtx
|
|---|
| 746 | push rsi ; push for saving the state at the end
|
|---|
| 747 |
|
|---|
| 748 | ; save host fs, gs, sysenter msr etc
|
|---|
| 749 | mov rax, [rbp + xS*2] ; pVMCBHostPhys (64 bits physical address; x86: take low dword only)
|
|---|
| 750 | push rax ; save for the vmload after vmrun
|
|---|
| 751 | vmsave
|
|---|
| 752 |
|
|---|
| 753 | ; setup eax for VMLOAD
|
|---|
| 754 | mov rax, [rbp + xS*2 + RTHCPHYS_CB] ; pVMCBPhys (64 bits physical address; take low dword only)
|
|---|
| 755 |
|
|---|
| 756 | ;/* Restore Guest's general purpose registers. */
|
|---|
| 757 | ;/* RAX is loaded from the VMCB by VMRUN */
|
|---|
| 758 | mov rbx, qword [xSI + CPUMCTX.ebx]
|
|---|
| 759 | mov rcx, qword [xSI + CPUMCTX.ecx]
|
|---|
| 760 | mov rdx, qword [xSI + CPUMCTX.edx]
|
|---|
| 761 | mov rdi, qword [xSI + CPUMCTX.edi]
|
|---|
| 762 | mov rbp, qword [xSI + CPUMCTX.ebp]
|
|---|
| 763 | mov r8, qword [xSI + CPUMCTX.r8]
|
|---|
| 764 | mov r9, qword [xSI + CPUMCTX.r9]
|
|---|
| 765 | mov r10, qword [xSI + CPUMCTX.r10]
|
|---|
| 766 | mov r11, qword [xSI + CPUMCTX.r11]
|
|---|
| 767 | mov r12, qword [xSI + CPUMCTX.r12]
|
|---|
| 768 | mov r13, qword [xSI + CPUMCTX.r13]
|
|---|
| 769 | mov r14, qword [xSI + CPUMCTX.r14]
|
|---|
| 770 | mov r15, qword [xSI + CPUMCTX.r15]
|
|---|
| 771 | mov rsi, qword [xSI + CPUMCTX.esi]
|
|---|
| 772 |
|
|---|
| 773 | ; Clear the global interrupt flag & execute sti to make sure external interrupts cause a world switch
|
|---|
| 774 | clgi
|
|---|
| 775 | sti
|
|---|
| 776 |
|
|---|
| 777 | ; load guest fs, gs, sysenter msr etc
|
|---|
| 778 | vmload
|
|---|
| 779 | ; run the VM
|
|---|
| 780 | vmrun
|
|---|
| 781 |
|
|---|
| 782 | ;/* RAX is in the VMCB already; we can use it here. */
|
|---|
| 783 |
|
|---|
| 784 | ; save guest fs, gs, sysenter msr etc
|
|---|
| 785 | vmsave
|
|---|
| 786 |
|
|---|
| 787 | ; load host fs, gs, sysenter msr etc
|
|---|
| 788 | pop rax ; pushed above
|
|---|
| 789 | vmload
|
|---|
| 790 |
|
|---|
| 791 | ; Set the global interrupt flag again, but execute cli to make sure IF=0.
|
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| 792 | cli
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| 793 | stgi
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| 794 |
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| 795 | pop rax ; pCtx
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| 796 |
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| 797 | mov qword [rax + CPUMCTX.ebx], rbx
|
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| 798 | mov qword [rax + CPUMCTX.ecx], rcx
|
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| 799 | mov qword [rax + CPUMCTX.edx], rdx
|
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| 800 | mov qword [rax + CPUMCTX.esi], rsi
|
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| 801 | mov qword [rax + CPUMCTX.edi], rdi
|
|---|
| 802 | mov qword [rax + CPUMCTX.ebp], rbp
|
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| 803 | mov qword [rax + CPUMCTX.r8], r8
|
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| 804 | mov qword [rax + CPUMCTX.r9], r9
|
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| 805 | mov qword [rax + CPUMCTX.r10], r10
|
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| 806 | mov qword [rax + CPUMCTX.r11], r11
|
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| 807 | mov qword [rax + CPUMCTX.r12], r12
|
|---|
| 808 | mov qword [rax + CPUMCTX.r13], r13
|
|---|
| 809 | mov qword [rax + CPUMCTX.r14], r14
|
|---|
| 810 | mov qword [rax + CPUMCTX.r15], r15
|
|---|
| 811 |
|
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| 812 | ; Restore general purpose registers
|
|---|
| 813 | MYPOPAD
|
|---|
| 814 |
|
|---|
| 815 | mov eax, VINF_SUCCESS
|
|---|
| 816 |
|
|---|
| 817 | popf
|
|---|
| 818 | pop rbp
|
|---|
| 819 | add rsp, 4*xS
|
|---|
| 820 | ret
|
|---|
| 821 | ENDPROC MY_NAME(SVMR0VMRun64)
|
|---|
| 822 | %endif ; RT_ARCH_AMD64
|
|---|
| 823 |
|
|---|
