| 1 | ; $Id: HWACCMR0Mixed.mac 22079 2009-08-07 16:26:25Z vboxsync $
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| 2 | ;; @file
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| 3 | ; HWACCMR0Mixed.mac - Stuff that darwin needs to build two versions of.
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| 4 | ;
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| 5 | ; Included by HWACCMR0A.asm with RT_ARCH_AMD64 defined or or undefined.
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| 6 | ;
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| 7 |
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| 8 | ;
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| 9 | ; Copyright (C) 2006-2007 Sun Microsystems, Inc.
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| 10 | ;
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| 11 | ; This file is part of VirtualBox Open Source Edition (OSE), as
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| 12 | ; available from http://www.virtualbox.org. This file is free software;
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| 13 | ; you can redistribute it and/or modify it under the terms of the GNU
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| 14 | ; General Public License (GPL) as published by the Free Software
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| 15 | ; Foundation, in version 2 as it comes in the "COPYING" file of the
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| 16 | ; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 17 | ; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 18 | ;
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| 19 | ; Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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| 20 | ; Clara, CA 95054 USA or visit http://www.sun.com if you need
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| 21 | ; additional information or have any questions.
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| 22 | ;
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| 23 |
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| 24 |
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| 25 | ;/**
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| 26 | ; * Prepares for and executes VMLAUNCH/VMRESUME (32 bits guest mode)
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| 27 | ; *
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| 28 | ; * @returns VBox status code
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| 29 | ; * @param fResume x86:[ebp+8], msc:rcx,gcc:rdi vmlauch/vmresume
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| 30 | ; * @param pCtx x86:[ebp+c], msc:rdx,gcc:rsi Guest context
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| 31 | ; * @param pCache x86:[esp+10],msc:r8, gcc:rdx VMCS cache
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| 32 | ; */
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| 33 | ALIGNCODE(16)
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| 34 | BEGINPROC MY_NAME(VMXR0StartVM32)
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| 35 | push xBP
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| 36 | mov xBP, xSP
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| 37 |
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| 38 | pushf
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| 39 | cli
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| 40 |
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| 41 | ;/* Save all general purpose host registers. */
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| 42 | MYPUSHAD
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| 43 |
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| 44 | ;/* First we have to save some final CPU context registers. */
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| 45 | mov eax, VMX_VMCS_HOST_RIP
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| 46 | %ifdef RT_ARCH_AMD64
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| 47 | lea r10, [.vmlaunch_done wrt rip]
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| 48 | vmwrite rax, r10
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| 49 | %else
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| 50 | mov ecx, .vmlaunch_done
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| 51 | vmwrite eax, ecx
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| 52 | %endif
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| 53 | ;/* Note: assumes success... */
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| 54 |
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| 55 | ;/* Manual save and restore:
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| 56 | ; * - General purpose registers except RIP, RSP
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| 57 | ; *
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| 58 | ; * Trashed:
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| 59 | ; * - CR2 (we don't care)
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| 60 | ; * - LDTR (reset to 0)
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| 61 | ; * - DRx (presumably not changed at all)
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| 62 | ; * - DR7 (reset to 0x400)
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| 63 | ; * - EFLAGS (reset to RT_BIT(1); not relevant)
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| 64 | ; *
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| 65 | ; */
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| 66 |
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| 67 | ;/* Save the Guest CPU context pointer. */
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| 68 | %ifdef RT_ARCH_AMD64
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| 69 | %ifdef ASM_CALL64_GCC
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| 70 | ; fResume already in rdi
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| 71 | ; pCtx already in rsi
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| 72 | mov rbx, rdx ; pCache
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| 73 | %else
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| 74 | mov rdi, rcx ; fResume
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| 75 | mov rsi, rdx ; pCtx
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| 76 | mov rbx, r8 ; pCache
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| 77 | %endif
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| 78 | %else
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| 79 | mov edi, [ebp + 8] ; fResume
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| 80 | mov esi, [ebp + 12] ; pCtx
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| 81 | mov ebx, [ebp + 16] ; pCache
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| 82 | %endif
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| 83 |
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| 84 | ;/* Save segment registers */
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| 85 | ; Note: MYPUSHSEGS trashes rdx & rcx, so we moved it here (msvc amd64 case)
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| 86 | MYPUSHSEGS xAX, ax
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| 87 |
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| 88 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
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| 89 | mov ecx, [xBX + VMCSCACHE.Write.cValidEntries]
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| 90 | cmp ecx, 0
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| 91 | je .no_cached_writes
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| 92 | mov edx, ecx
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| 93 | mov ecx, 0
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| 94 | jmp .cached_write
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| 95 |
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| 96 | ALIGN(16)
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| 97 | .cached_write:
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| 98 | mov eax, [xBX + VMCSCACHE.Write.aField + xCX*4]
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| 99 | vmwrite xAX, [xBX + VMCSCACHE.Write.aFieldVal + xCX*8]
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| 100 | inc xCX
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| 101 | cmp xCX, xDX
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| 102 | jl .cached_write
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| 103 |
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| 104 | mov dword [xBX + VMCSCACHE.Write.cValidEntries], 0
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| 105 | .no_cached_writes:
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| 106 |
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| 107 | ; Save the pCache pointer
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| 108 | push xBX
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| 109 | %endif
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| 110 |
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| 111 | ; Save the pCtx pointer
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| 112 | push xSI
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| 113 |
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| 114 | ; Save LDTR
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| 115 | xor eax, eax
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| 116 | sldt ax
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| 117 | push xAX
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| 118 |
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| 119 | ; The TR limit is reset to 0x67; restore it manually
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| 120 | str eax
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| 121 | push xAX
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| 122 |
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| 123 | ; VMX only saves the base of the GDTR & IDTR and resets the limit to 0xffff; we must restore the limit correctly!
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| 124 | sub xSP, xS*2
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| 125 | sgdt [xSP]
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| 126 |
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| 127 | sub xSP, xS*2
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| 128 | sidt [xSP]
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| 129 |
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| 130 | %ifdef VBOX_WITH_DR6_EXPERIMENT
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| 131 | ; Restore DR6 - experiment, not safe!
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| 132 | mov xBX, [xSI + CPUMCTX.dr6]
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| 133 | mov dr6, xBX
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| 134 | %endif
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| 135 |
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| 136 | ; Restore CR2
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| 137 | mov ebx, [xSI + CPUMCTX.cr2]
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| 138 | mov cr2, xBX
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| 139 |
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| 140 | mov eax, VMX_VMCS_HOST_RSP
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| 141 | vmwrite xAX, xSP
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| 142 | ;/* Note: assumes success... */
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| 143 | ;/* Don't mess with ESP anymore!! */
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| 144 |
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| 145 | ;/* Restore Guest's general purpose registers. */
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| 146 | mov eax, [xSI + CPUMCTX.eax]
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| 147 | mov ebx, [xSI + CPUMCTX.ebx]
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| 148 | mov ecx, [xSI + CPUMCTX.ecx]
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| 149 | mov edx, [xSI + CPUMCTX.edx]
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| 150 | mov ebp, [xSI + CPUMCTX.ebp]
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| 151 |
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| 152 | ; resume or start?
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| 153 | cmp xDI, 0 ; fResume
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| 154 | je .vmlauch_lauch
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| 155 |
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| 156 | ;/* Restore edi & esi. */
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| 157 | mov edi, [xSI + CPUMCTX.edi]
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| 158 | mov esi, [xSI + CPUMCTX.esi]
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| 159 |
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| 160 | vmresume
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| 161 | jmp .vmlaunch_done; ;/* here if vmresume detected a failure. */
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| 162 |
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| 163 | .vmlauch_lauch:
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| 164 | ;/* Restore edi & esi. */
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| 165 | mov edi, [xSI + CPUMCTX.edi]
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| 166 | mov esi, [xSI + CPUMCTX.esi]
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| 167 |
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| 168 | vmlaunch
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| 169 | jmp .vmlaunch_done; ;/* here if vmlaunch detected a failure. */
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| 170 |
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| 171 | ALIGNCODE(16) ;; @todo YASM BUG - this alignment is wrong on darwin, it's 1 byte off.
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| 172 | .vmlaunch_done:
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| 173 | jc near .vmxstart_invalid_vmxon_ptr
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| 174 | jz near .vmxstart_start_failed
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| 175 |
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| 176 | ; Restore base and limit of the IDTR & GDTR
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| 177 | lidt [xSP]
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| 178 | add xSP, xS*2
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| 179 | lgdt [xSP]
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| 180 | add xSP, xS*2
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| 181 |
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| 182 | push xDI
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| 183 | mov xDI, [xSP + xS * 3] ; pCtx (*3 to skip the saved LDTR + TR)
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| 184 |
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| 185 | mov [ss:xDI + CPUMCTX.eax], eax
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| 186 | mov [ss:xDI + CPUMCTX.ebx], ebx
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| 187 | mov [ss:xDI + CPUMCTX.ecx], ecx
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| 188 | mov [ss:xDI + CPUMCTX.edx], edx
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| 189 | mov [ss:xDI + CPUMCTX.esi], esi
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| 190 | mov [ss:xDI + CPUMCTX.ebp], ebp
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| 191 | %ifdef RT_ARCH_AMD64
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| 192 | pop xAX ; the guest edi we pushed above
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| 193 | mov dword [ss:xDI + CPUMCTX.edi], eax
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| 194 | %else
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| 195 | pop dword [ss:xDI + CPUMCTX.edi] ; the guest edi we pushed above
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| 196 | %endif
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| 197 |
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| 198 | %ifdef VBOX_WITH_DR6_EXPERIMENT
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| 199 | ; Save DR6 - experiment, not safe!
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| 200 | mov xAX, dr6
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| 201 | mov [ss:xDI + CPUMCTX.dr6], xAX
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| 202 | %endif
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| 203 |
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| 204 | ; Restore TSS selector; must mark it as not busy before using ltr (!)
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| 205 | ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p)
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| 206 | ; @todo get rid of sgdt
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| 207 | pop xBX ; saved TR
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| 208 | %ifndef RT_ARCH_AMD64
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| 209 | sub xSP, xS*2
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| 210 | sgdt [xSP]
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| 211 | mov eax, ebx
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| 212 | and al, 0F8h ; mask away TI and RPL bits, get descriptor offset.
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| 213 | add xAX, [xSP + 2] ; eax <- GDTR.address + descriptor offset.
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| 214 | and dword [ss:xAX + 4], ~0200h ; clear busy flag (2nd type2 bit)
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| 215 | ltr bx
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| 216 | add xSP, xS*2
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| 217 | %endif
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| 218 |
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| 219 | pop xAX ; saved LDTR
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| 220 | lldt ax
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| 221 |
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| 222 | add xSP, xS ; pCtx
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| 223 |
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| 224 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
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| 225 | pop xDX ; saved pCache
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| 226 |
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| 227 | mov ecx, [ss:xDX + VMCSCACHE.Read.cValidEntries]
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| 228 | cmp ecx, 0 ; can't happen
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| 229 | je .no_cached_reads
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| 230 | jmp .cached_read
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| 231 |
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| 232 | ALIGN(16)
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| 233 | .cached_read:
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| 234 | dec xCX
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| 235 | mov eax, [ss:xDX + VMCSCACHE.Read.aField + xCX*4]
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| 236 | vmread [ss:xDX + VMCSCACHE.Read.aFieldVal + xCX*8], xAX
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| 237 | cmp xCX, 0
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| 238 | jnz .cached_read
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| 239 | .no_cached_reads:
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| 240 |
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| 241 | ; Save CR2 for EPT
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| 242 | mov xAX, cr2
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| 243 | mov [ss:xDX + VMCSCACHE.cr2], xAX
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| 244 | %endif
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| 245 |
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| 246 | ; Restore segment registers
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| 247 | MYPOPSEGS xAX, ax
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| 248 |
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| 249 | ; Restore general purpose registers
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| 250 | MYPOPAD
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| 251 |
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| 252 | mov eax, VINF_SUCCESS
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| 253 |
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| 254 | .vmstart_end:
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| 255 | popf
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| 256 | pop xBP
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| 257 | ret
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| 258 |
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| 259 |
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| 260 | .vmxstart_invalid_vmxon_ptr:
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| 261 | ; Restore base and limit of the IDTR & GDTR
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| 262 | lidt [xSP]
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| 263 | add xSP, xS*2
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| 264 | lgdt [xSP]
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| 265 | add xSP, xS*2
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| 266 |
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| 267 | ; Restore TSS selector; must mark it as not busy before using ltr (!)
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| 268 | ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p)
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| 269 | ; @todo get rid of sgdt
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| 270 | pop xBX ; saved TR
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| 271 | %ifndef RT_ARCH_AMD64
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| 272 | sub xSP, xS*2
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| 273 | sgdt [xSP]
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| 274 | mov eax, ebx
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| 275 | and al, 0F8h ; mask away TI and RPL bits, get descriptor offset.
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| 276 | add eax, [xSP + 2] ; eax <- GDTR.address + descriptor offset.
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| 277 | and dword [ss:eax + 4], ~0200h ; clear busy flag (2nd type2 bit)
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| 278 | ltr bx
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| 279 | add xSP, xS*2
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| 280 | %endif
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| 281 |
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| 282 | pop xAX ; saved LDTR
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| 283 | lldt ax
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| 284 |
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| 285 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
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| 286 | add xSP, xS*2 ; pCtx + pCache
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| 287 | %else
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| 288 | add xSP, xS ; pCtx
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| 289 | %endif
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| 290 |
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| 291 | ; Restore segment registers
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| 292 | MYPOPSEGS xAX, ax
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| 293 |
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| 294 | ; Restore all general purpose host registers.
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| 295 | MYPOPAD
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| 296 | mov eax, VERR_VMX_INVALID_VMXON_PTR
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| 297 | jmp .vmstart_end
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| 298 |
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| 299 | .vmxstart_start_failed:
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| 300 | ; Restore base and limit of the IDTR & GDTR
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| 301 | lidt [xSP]
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| 302 | add xSP, xS*2
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| 303 | lgdt [xSP]
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| 304 | add xSP, xS*2
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| 305 |
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| 306 | ; Restore TSS selector; must mark it as not busy before using ltr (!)
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| 307 | ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p)
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| 308 | ; @todo get rid of sgdt
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| 309 | pop xBX ; saved TR
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| 310 | %ifndef RT_ARCH_AMD64
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| 311 | sub xSP, xS*2
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| 312 | sgdt [xSP]
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| 313 | mov eax, ebx
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| 314 | and al, 0F8h ; mask away TI and RPL bits, get descriptor offset.
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| 315 | add eax, [xSP + 2] ; eax <- GDTR.address + descriptor offset.
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| 316 | and dword [ss:eax + 4], ~0200h ; clear busy flag (2nd type2 bit)
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| 317 | ltr bx
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| 318 | add xSP, xS*2
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| 319 | %endif
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| 320 |
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| 321 | pop xAX ; saved LDTR
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| 322 | lldt ax
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| 323 |
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| 324 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
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| 325 | add xSP, xS*2 ; pCtx + pCache
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| 326 | %else
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| 327 | add xSP, xS ; pCtx
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| 328 | %endif
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| 329 |
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| 330 | ; Restore segment registers
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| 331 | MYPOPSEGS xAX, ax
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| 332 |
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| 333 | ; Restore all general purpose host registers.
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| 334 | MYPOPAD
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| 335 | mov eax, VERR_VMX_UNABLE_TO_START_VM
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| 336 | jmp .vmstart_end
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| 337 |
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| 338 | ENDPROC MY_NAME(VMXR0StartVM32)
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| 339 |
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| 340 | %ifdef RT_ARCH_AMD64
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| 341 | ;/**
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| 342 | ; * Prepares for and executes VMLAUNCH/VMRESUME (64 bits guest mode)
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| 343 | ; *
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| 344 | ; * @returns VBox status code
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| 345 | ; * @param fResume msc:rcx, gcc:rdi vmlauch/vmresume
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| 346 | ; * @param pCtx msc:rdx, gcc:rsi Guest context
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| 347 | ; * @param pCache msc:r8, gcc:rdx VMCS cache
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| 348 | ; */
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| 349 | ALIGNCODE(16)
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| 350 | BEGINPROC MY_NAME(VMXR0StartVM64)
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| 351 | push xBP
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| 352 | mov xBP, xSP
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| 353 |
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| 354 | pushf
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| 355 | cli
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| 356 |
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| 357 | ;/* Save all general purpose host registers. */
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| 358 | MYPUSHAD
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| 359 |
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| 360 | ;/* First we have to save some final CPU context registers. */
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| 361 | lea r10, [.vmlaunch64_done wrt rip]
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| 362 | mov rax, VMX_VMCS_HOST_RIP ;/* return address (too difficult to continue after VMLAUNCH?) */
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| 363 | vmwrite rax, r10
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| 364 | ;/* Note: assumes success... */
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| 365 |
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| 366 | ;/* Manual save and restore:
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| 367 | ; * - General purpose registers except RIP, RSP
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| 368 | ; *
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| 369 | ; * Trashed:
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| 370 | ; * - CR2 (we don't care)
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| 371 | ; * - LDTR (reset to 0)
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| 372 | ; * - DRx (presumably not changed at all)
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| 373 | ; * - DR7 (reset to 0x400)
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| 374 | ; * - EFLAGS (reset to RT_BIT(1); not relevant)
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| 375 | ; *
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| 376 | ; */
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| 377 |
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| 378 | ;/* Save the Guest CPU context pointer. */
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| 379 | %ifdef ASM_CALL64_GCC
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| 380 | ; fResume already in rdi
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| 381 | ; pCtx already in rsi
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| 382 | mov rbx, rdx ; pCache
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| 383 | %else
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| 384 | mov rdi, rcx ; fResume
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| 385 | mov rsi, rdx ; pCtx
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| 386 | mov rbx, r8 ; pCache
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| 387 | %endif
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| 388 |
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| 389 | ;/* Save segment registers */
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| 390 | ; Note: MYPUSHSEGS trashes rdx & rcx, so we moved it here (msvc amd64 case)
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| 391 | MYPUSHSEGS xAX, ax
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| 392 |
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| 393 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
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| 394 | mov ecx, [xBX + VMCSCACHE.Write.cValidEntries]
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| 395 | cmp ecx, 0
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| 396 | je .no_cached_writes
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| 397 | mov edx, ecx
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| 398 | mov ecx, 0
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| 399 | jmp .cached_write
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| 400 |
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|---|
| 401 | ALIGN(16)
|
|---|
| 402 | .cached_write:
|
|---|
| 403 | mov eax, [xBX + VMCSCACHE.Write.aField + xCX*4]
|
|---|
| 404 | vmwrite xAX, [xBX + VMCSCACHE.Write.aFieldVal + xCX*8]
|
|---|
| 405 | inc xCX
|
|---|
| 406 | cmp xCX, xDX
|
|---|
| 407 | jl .cached_write
|
|---|
| 408 |
|
|---|
| 409 | mov dword [xBX + VMCSCACHE.Write.cValidEntries], 0
|
|---|
| 410 | .no_cached_writes:
|
|---|
| 411 |
|
|---|
| 412 | ; Save the pCache pointer
|
|---|
| 413 | push xBX
|
|---|
| 414 | %endif
|
|---|
| 415 |
|
|---|
| 416 | ; Save the host LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs and restore the guest MSRs
|
|---|
| 417 | ;; @todo use the automatic load feature for MSRs
|
|---|
| 418 | LOADGUESTMSR MSR_K8_LSTAR, CPUMCTX.msrLSTAR
|
|---|
| 419 | %if 0 ; not supported on Intel CPUs
|
|---|
| 420 | LOADGUESTMSR MSR_K8_CSTAR, CPUMCTX.msrCSTAR
|
|---|
| 421 | %endif
|
|---|
| 422 | LOADGUESTMSR MSR_K6_STAR, CPUMCTX.msrSTAR
|
|---|
| 423 | LOADGUESTMSR MSR_K8_SF_MASK, CPUMCTX.msrSFMASK
|
|---|
| 424 | LOADGUESTMSR MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
|
|---|
| 425 |
|
|---|
| 426 | ; Save the pCtx pointer
|
|---|
| 427 | push xSI
|
|---|
| 428 |
|
|---|
| 429 | ; Save LDTR
|
|---|
| 430 | xor eax, eax
|
|---|
| 431 | sldt ax
|
|---|
| 432 | push xAX
|
|---|
| 433 |
|
|---|
| 434 | ; VMX only saves the base of the GDTR & IDTR and resets the limit to 0xffff; we must restore the limit correctly!
|
|---|
| 435 | sub xSP, xS*2
|
|---|
| 436 | sgdt [xSP]
|
|---|
| 437 |
|
|---|
| 438 | sub xSP, xS*2
|
|---|
| 439 | sidt [xSP]
|
|---|
| 440 |
|
|---|
| 441 | %ifdef VBOX_WITH_DR6_EXPERIMENT
|
|---|
| 442 | ; Restore DR6 - experiment, not safe!
|
|---|
| 443 | mov xBX, [xSI + CPUMCTX.dr6]
|
|---|
| 444 | mov dr6, xBX
|
|---|
| 445 | %endif
|
|---|
| 446 |
|
|---|
| 447 | ; Restore CR2
|
|---|
| 448 | mov rbx, qword [xSI + CPUMCTX.cr2]
|
|---|
| 449 | mov cr2, rbx
|
|---|
| 450 |
|
|---|
| 451 | mov eax, VMX_VMCS_HOST_RSP
|
|---|
| 452 | vmwrite xAX, xSP
|
|---|
| 453 | ;/* Note: assumes success... */
|
|---|
| 454 | ;/* Don't mess with ESP anymore!! */
|
|---|
| 455 |
|
|---|
| 456 | ;/* Restore Guest's general purpose registers. */
|
|---|
| 457 | mov rax, qword [xSI + CPUMCTX.eax]
|
|---|
| 458 | mov rbx, qword [xSI + CPUMCTX.ebx]
|
|---|
| 459 | mov rcx, qword [xSI + CPUMCTX.ecx]
|
|---|
| 460 | mov rdx, qword [xSI + CPUMCTX.edx]
|
|---|
| 461 | mov rbp, qword [xSI + CPUMCTX.ebp]
|
|---|
| 462 | mov r8, qword [xSI + CPUMCTX.r8]
|
|---|
| 463 | mov r9, qword [xSI + CPUMCTX.r9]
|
|---|
| 464 | mov r10, qword [xSI + CPUMCTX.r10]
|
|---|
| 465 | mov r11, qword [xSI + CPUMCTX.r11]
|
|---|
| 466 | mov r12, qword [xSI + CPUMCTX.r12]
|
|---|
| 467 | mov r13, qword [xSI + CPUMCTX.r13]
|
|---|
| 468 | mov r14, qword [xSI + CPUMCTX.r14]
|
|---|
| 469 | mov r15, qword [xSI + CPUMCTX.r15]
|
|---|
| 470 |
|
|---|
| 471 | ; resume or start?
|
|---|
| 472 | cmp xDI, 0 ; fResume
|
|---|
| 473 | je .vmlauch64_lauch
|
|---|
| 474 |
|
|---|
| 475 | ;/* Restore edi & esi. */
|
|---|
| 476 | mov rdi, qword [xSI + CPUMCTX.edi]
|
|---|
| 477 | mov rsi, qword [xSI + CPUMCTX.esi]
|
|---|
| 478 |
|
|---|
| 479 | vmresume
|
|---|
| 480 | jmp .vmlaunch64_done; ;/* here if vmresume detected a failure. */
|
|---|
| 481 |
|
|---|
| 482 | .vmlauch64_lauch:
|
|---|
| 483 | ;/* Restore rdi & rsi. */
|
|---|
| 484 | mov rdi, qword [xSI + CPUMCTX.edi]
|
|---|
| 485 | mov rsi, qword [xSI + CPUMCTX.esi]
|
|---|
| 486 |
|
|---|
| 487 | vmlaunch
|
|---|
| 488 | jmp .vmlaunch64_done; ;/* here if vmlaunch detected a failure. */
|
|---|
| 489 |
|
|---|
| 490 | ALIGNCODE(16)
|
|---|
| 491 | .vmlaunch64_done:
|
|---|
| 492 | jc near .vmxstart64_invalid_vmxon_ptr
|
|---|
| 493 | jz near .vmxstart64_start_failed
|
|---|
| 494 |
|
|---|
| 495 | ; Restore base and limit of the IDTR & GDTR
|
|---|
| 496 | lidt [xSP]
|
|---|
| 497 | add xSP, xS*2
|
|---|
| 498 | lgdt [xSP]
|
|---|
| 499 | add xSP, xS*2
|
|---|
| 500 |
|
|---|
| 501 | push xDI
|
|---|
| 502 | mov xDI, [xSP + xS * 2] ; pCtx (*2 to skip the saved LDTR)
|
|---|
| 503 |
|
|---|
| 504 | mov qword [xDI + CPUMCTX.eax], rax
|
|---|
| 505 | mov qword [xDI + CPUMCTX.ebx], rbx
|
|---|
| 506 | mov qword [xDI + CPUMCTX.ecx], rcx
|
|---|
| 507 | mov qword [xDI + CPUMCTX.edx], rdx
|
|---|
| 508 | mov qword [xDI + CPUMCTX.esi], rsi
|
|---|
| 509 | mov qword [xDI + CPUMCTX.ebp], rbp
|
|---|
| 510 | mov qword [xDI + CPUMCTX.r8], r8
|
|---|
| 511 | mov qword [xDI + CPUMCTX.r9], r9
|
|---|
| 512 | mov qword [xDI + CPUMCTX.r10], r10
|
|---|
| 513 | mov qword [xDI + CPUMCTX.r11], r11
|
|---|
| 514 | mov qword [xDI + CPUMCTX.r12], r12
|
|---|
| 515 | mov qword [xDI + CPUMCTX.r13], r13
|
|---|
| 516 | mov qword [xDI + CPUMCTX.r14], r14
|
|---|
| 517 | mov qword [xDI + CPUMCTX.r15], r15
|
|---|
| 518 |
|
|---|
| 519 | pop xAX ; the guest edi we pushed above
|
|---|
| 520 | mov qword [xDI + CPUMCTX.edi], rax
|
|---|
| 521 |
|
|---|
| 522 | %ifdef VBOX_WITH_DR6_EXPERIMENT
|
|---|
| 523 | ; Save DR6 - experiment, not safe!
|
|---|
| 524 | mov xAX, dr6
|
|---|
| 525 | mov [xDI + CPUMCTX.dr6], xAX
|
|---|
| 526 | %endif
|
|---|
| 527 |
|
|---|
| 528 | pop xAX ; saved LDTR
|
|---|
| 529 | lldt ax
|
|---|
| 530 |
|
|---|
| 531 | pop xSI ; pCtx (needed in rsi by the macros below)
|
|---|
| 532 |
|
|---|
| 533 | ; Restore the host LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs
|
|---|
| 534 | ;; @todo use the automatic load feature for MSRs
|
|---|
| 535 | LOADHOSTMSREX MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
|
|---|
| 536 | LOADHOSTMSREX MSR_K8_SF_MASK, CPUMCTX.msrSFMASK
|
|---|
| 537 | LOADHOSTMSREX MSR_K6_STAR, CPUMCTX.msrSTAR
|
|---|
| 538 | %if 0 ; not supported on Intel CPUs
|
|---|
| 539 | LOADHOSTMSREX MSR_K8_CSTAR, CPUMCTX.msrCSTAR
|
|---|
| 540 | %endif
|
|---|
| 541 | LOADHOSTMSREX MSR_K8_LSTAR, CPUMCTX.msrLSTAR
|
|---|
| 542 |
|
|---|
| 543 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
|
|---|
| 544 | pop xDX ; saved pCache
|
|---|
| 545 |
|
|---|
| 546 | mov ecx, [xDX + VMCSCACHE.Read.cValidEntries]
|
|---|
| 547 | cmp ecx, 0 ; can't happen
|
|---|
| 548 | je .no_cached_reads
|
|---|
| 549 | jmp .cached_read
|
|---|
| 550 |
|
|---|
| 551 | ALIGN(16)
|
|---|
| 552 | .cached_read:
|
|---|
| 553 | dec xCX
|
|---|
| 554 | mov eax, [xDX + VMCSCACHE.Read.aField + xCX*4]
|
|---|
| 555 | vmread [xDX + VMCSCACHE.Read.aFieldVal + xCX*8], xAX
|
|---|
| 556 | cmp xCX, 0
|
|---|
| 557 | jnz .cached_read
|
|---|
| 558 | .no_cached_reads:
|
|---|
| 559 |
|
|---|
| 560 | ; Save CR2 for EPT
|
|---|
| 561 | mov xAX, cr2
|
|---|
| 562 | mov [xDX + VMCSCACHE.cr2], xAX
|
|---|
| 563 | %endif
|
|---|
| 564 |
|
|---|
| 565 | ; Restore segment registers
|
|---|
| 566 | MYPOPSEGS xAX, ax
|
|---|
| 567 |
|
|---|
| 568 | ; Restore general purpose registers
|
|---|
| 569 | MYPOPAD
|
|---|
| 570 |
|
|---|
| 571 | mov eax, VINF_SUCCESS
|
|---|
| 572 |
|
|---|
| 573 | .vmstart64_end:
|
|---|
| 574 | popf
|
|---|
| 575 | pop xBP
|
|---|
| 576 | ret
|
|---|
| 577 |
|
|---|
| 578 |
|
|---|
| 579 | .vmxstart64_invalid_vmxon_ptr:
|
|---|
| 580 | ; Restore base and limit of the IDTR & GDTR
|
|---|
| 581 | lidt [xSP]
|
|---|
| 582 | add xSP, xS*2
|
|---|
| 583 | lgdt [xSP]
|
|---|
| 584 | add xSP, xS*2
|
|---|
| 585 |
|
|---|
| 586 | pop xAX ; saved LDTR
|
|---|
| 587 | lldt ax
|
|---|
| 588 |
|
|---|
| 589 | pop xSI ; pCtx (needed in rsi by the macros below)
|
|---|
| 590 |
|
|---|
| 591 | ; Restore the host LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs
|
|---|
| 592 | ;; @todo use the automatic load feature for MSRs
|
|---|
| 593 | LOADHOSTMSREX MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
|
|---|
| 594 | LOADHOSTMSR MSR_K8_SF_MASK
|
|---|
| 595 | LOADHOSTMSR MSR_K6_STAR
|
|---|
| 596 | %if 0 ; not supported on Intel CPUs
|
|---|
| 597 | LOADHOSTMSR MSR_K8_CSTAR
|
|---|
| 598 | %endif
|
|---|
| 599 | LOADHOSTMSR MSR_K8_LSTAR
|
|---|
| 600 |
|
|---|
| 601 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
|
|---|
| 602 | add xSP, xS ; pCache
|
|---|
| 603 | %endif
|
|---|
| 604 |
|
|---|
| 605 | ; Restore segment registers
|
|---|
| 606 | MYPOPSEGS xAX, ax
|
|---|
| 607 |
|
|---|
| 608 | ; Restore all general purpose host registers.
|
|---|
| 609 | MYPOPAD
|
|---|
| 610 | mov eax, VERR_VMX_INVALID_VMXON_PTR
|
|---|
| 611 | jmp .vmstart64_end
|
|---|
| 612 |
|
|---|
| 613 | .vmxstart64_start_failed:
|
|---|
| 614 | ; Restore base and limit of the IDTR & GDTR
|
|---|
| 615 | lidt [xSP]
|
|---|
| 616 | add xSP, xS*2
|
|---|
| 617 | lgdt [xSP]
|
|---|
| 618 | add xSP, xS*2
|
|---|
| 619 |
|
|---|
| 620 | pop xAX ; saved LDTR
|
|---|
| 621 | lldt ax
|
|---|
| 622 |
|
|---|
| 623 | pop xSI ; pCtx (needed in rsi by the macros below)
|
|---|
| 624 |
|
|---|
| 625 | ; Restore the host LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs
|
|---|
| 626 | ;; @todo use the automatic load feature for MSRs
|
|---|
| 627 | LOADHOSTMSREX MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
|
|---|
| 628 | LOADHOSTMSR MSR_K8_SF_MASK
|
|---|
| 629 | LOADHOSTMSR MSR_K6_STAR
|
|---|
| 630 | %if 0 ; not supported on Intel CPUs
|
|---|
| 631 | LOADHOSTMSR MSR_K8_CSTAR
|
|---|
| 632 | %endif
|
|---|
| 633 | LOADHOSTMSR MSR_K8_LSTAR
|
|---|
| 634 |
|
|---|
| 635 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
|
|---|
| 636 | add xSP, xS ; pCache
|
|---|
| 637 | %endif
|
|---|
| 638 |
|
|---|
| 639 | ; Restore segment registers
|
|---|
| 640 | MYPOPSEGS xAX, ax
|
|---|
| 641 |
|
|---|
| 642 | ; Restore all general purpose host registers.
|
|---|
| 643 | MYPOPAD
|
|---|
| 644 | mov eax, VERR_VMX_UNABLE_TO_START_VM
|
|---|
| 645 | jmp .vmstart64_end
|
|---|
| 646 | ENDPROC MY_NAME(VMXR0StartVM64)
|
|---|
| 647 | %endif ; RT_ARCH_AMD64
|
|---|
| 648 |
|
|---|
| 649 |
|
|---|
| 650 | ;/**
|
|---|
| 651 | ; * Prepares for and executes VMRUN (32 bits guests)
|
|---|
| 652 | ; *
|
|---|
| 653 | ; * @returns VBox status code
|
|---|
| 654 | ; * @param HCPhysVMCB Physical address of host VMCB
|
|---|
| 655 | ; * @param HCPhysVMCB Physical address of guest VMCB
|
|---|
| 656 | ; * @param pCtx Guest context
|
|---|
| 657 | ; */
|
|---|
| 658 | ALIGNCODE(16)
|
|---|
| 659 | BEGINPROC MY_NAME(SVMR0VMRun)
|
|---|
| 660 | %ifdef RT_ARCH_AMD64 ; fake a cdecl stack frame
|
|---|
| 661 | %ifdef ASM_CALL64_GCC
|
|---|
| 662 | push rdx
|
|---|
| 663 | push rsi
|
|---|
| 664 | push rdi
|
|---|
| 665 | %else
|
|---|
| 666 | push r8
|
|---|
| 667 | push rdx
|
|---|
| 668 | push rcx
|
|---|
| 669 | %endif
|
|---|
| 670 | push 0
|
|---|
| 671 | %endif
|
|---|
| 672 | push xBP
|
|---|
| 673 | mov xBP, xSP
|
|---|
| 674 | pushf
|
|---|
| 675 |
|
|---|
| 676 | ;/* Manual save and restore:
|
|---|
| 677 | ; * - General purpose registers except RIP, RSP, RAX
|
|---|
| 678 | ; *
|
|---|
| 679 | ; * Trashed:
|
|---|
| 680 | ; * - CR2 (we don't care)
|
|---|
| 681 | ; * - LDTR (reset to 0)
|
|---|
| 682 | ; * - DRx (presumably not changed at all)
|
|---|
| 683 | ; * - DR7 (reset to 0x400)
|
|---|
| 684 | ; */
|
|---|
| 685 |
|
|---|
| 686 | ;/* Save all general purpose host registers. */
|
|---|
| 687 | MYPUSHAD
|
|---|
| 688 |
|
|---|
| 689 | ;/* Save the Guest CPU context pointer. */
|
|---|
| 690 | mov xSI, [xBP + xS*2 + RTHCPHYS_CB*2] ; pCtx
|
|---|
| 691 | push xSI ; push for saving the state at the end
|
|---|
| 692 |
|
|---|
| 693 | ; save host fs, gs, sysenter msr etc
|
|---|
| 694 | mov xAX, [xBP + xS*2] ; pVMCBHostPhys (64 bits physical address; x86: take low dword only)
|
|---|
| 695 | push xAX ; save for the vmload after vmrun
|
|---|
| 696 | vmsave
|
|---|
| 697 |
|
|---|
| 698 | ; setup eax for VMLOAD
|
|---|
| 699 | mov xAX, [xBP + xS*2 + RTHCPHYS_CB] ; pVMCBPhys (64 bits physical address; take low dword only)
|
|---|
| 700 |
|
|---|
| 701 | ;/* Restore Guest's general purpose registers. */
|
|---|
| 702 | ;/* EAX is loaded from the VMCB by VMRUN */
|
|---|
| 703 | mov ebx, [xSI + CPUMCTX.ebx]
|
|---|
| 704 | mov ecx, [xSI + CPUMCTX.ecx]
|
|---|
| 705 | mov edx, [xSI + CPUMCTX.edx]
|
|---|
| 706 | mov edi, [xSI + CPUMCTX.edi]
|
|---|
| 707 | mov ebp, [xSI + CPUMCTX.ebp]
|
|---|
| 708 | mov esi, [xSI + CPUMCTX.esi]
|
|---|
| 709 |
|
|---|
| 710 | ; Clear the global interrupt flag & execute sti to make sure external interrupts cause a world switch
|
|---|
| 711 | clgi
|
|---|
| 712 | sti
|
|---|
| 713 |
|
|---|
| 714 | ; load guest fs, gs, sysenter msr etc
|
|---|
| 715 | vmload
|
|---|
| 716 | ; run the VM
|
|---|
| 717 | vmrun
|
|---|
| 718 |
|
|---|
| 719 | ;/* EAX is in the VMCB already; we can use it here. */
|
|---|
| 720 |
|
|---|
| 721 | ; save guest fs, gs, sysenter msr etc
|
|---|
| 722 | vmsave
|
|---|
| 723 |
|
|---|
| 724 | ; load host fs, gs, sysenter msr etc
|
|---|
| 725 | pop xAX ; pushed above
|
|---|
| 726 | vmload
|
|---|
| 727 |
|
|---|
| 728 | ; Set the global interrupt flag again, but execute cli to make sure IF=0.
|
|---|
| 729 | cli
|
|---|
| 730 | stgi
|
|---|
| 731 |
|
|---|
| 732 | pop xAX ; pCtx
|
|---|
| 733 |
|
|---|
| 734 | mov [ss:xAX + CPUMCTX.ebx], ebx
|
|---|
| 735 | mov [ss:xAX + CPUMCTX.ecx], ecx
|
|---|
| 736 | mov [ss:xAX + CPUMCTX.edx], edx
|
|---|
| 737 | mov [ss:xAX + CPUMCTX.esi], esi
|
|---|
| 738 | mov [ss:xAX + CPUMCTX.edi], edi
|
|---|
| 739 | mov [ss:xAX + CPUMCTX.ebp], ebp
|
|---|
| 740 |
|
|---|
| 741 | ; Restore general purpose registers
|
|---|
| 742 | MYPOPAD
|
|---|
| 743 |
|
|---|
| 744 | mov eax, VINF_SUCCESS
|
|---|
| 745 |
|
|---|
| 746 | popf
|
|---|
| 747 | pop xBP
|
|---|
| 748 | %ifdef RT_ARCH_AMD64
|
|---|
| 749 | add xSP, 4*xS
|
|---|
| 750 | %endif
|
|---|
| 751 | ret
|
|---|
| 752 | ENDPROC MY_NAME(SVMR0VMRun)
|
|---|
| 753 |
|
|---|
| 754 | %ifdef RT_ARCH_AMD64
|
|---|
| 755 | ;/**
|
|---|
| 756 | ; * Prepares for and executes VMRUN (64 bits guests)
|
|---|
| 757 | ; *
|
|---|
| 758 | ; * @returns VBox status code
|
|---|
| 759 | ; * @param HCPhysVMCB Physical address of host VMCB
|
|---|
| 760 | ; * @param HCPhysVMCB Physical address of guest VMCB
|
|---|
| 761 | ; * @param pCtx Guest context
|
|---|
| 762 | ; */
|
|---|
| 763 | ALIGNCODE(16)
|
|---|
| 764 | BEGINPROC MY_NAME(SVMR0VMRun64)
|
|---|
| 765 | ; fake a cdecl stack frame
|
|---|
| 766 | %ifdef ASM_CALL64_GCC
|
|---|
| 767 | push rdx
|
|---|
| 768 | push rsi
|
|---|
| 769 | push rdi
|
|---|
| 770 | %else
|
|---|
| 771 | push r8
|
|---|
| 772 | push rdx
|
|---|
| 773 | push rcx
|
|---|
| 774 | %endif
|
|---|
| 775 | push 0
|
|---|
| 776 | push rbp
|
|---|
| 777 | mov rbp, rsp
|
|---|
| 778 | pushf
|
|---|
| 779 |
|
|---|
| 780 | ;/* Manual save and restore:
|
|---|
| 781 | ; * - General purpose registers except RIP, RSP, RAX
|
|---|
| 782 | ; *
|
|---|
| 783 | ; * Trashed:
|
|---|
| 784 | ; * - CR2 (we don't care)
|
|---|
| 785 | ; * - LDTR (reset to 0)
|
|---|
| 786 | ; * - DRx (presumably not changed at all)
|
|---|
| 787 | ; * - DR7 (reset to 0x400)
|
|---|
| 788 | ; */
|
|---|
| 789 |
|
|---|
| 790 | ;/* Save all general purpose host registers. */
|
|---|
| 791 | MYPUSHAD
|
|---|
| 792 |
|
|---|
| 793 | ;/* Save the Guest CPU context pointer. */
|
|---|
| 794 | mov rsi, [rbp + xS*2 + RTHCPHYS_CB*2] ; pCtx
|
|---|
| 795 | push rsi ; push for saving the state at the end
|
|---|
| 796 |
|
|---|
| 797 | ; save host fs, gs, sysenter msr etc
|
|---|
| 798 | mov rax, [rbp + xS*2] ; pVMCBHostPhys (64 bits physical address; x86: take low dword only)
|
|---|
| 799 | push rax ; save for the vmload after vmrun
|
|---|
| 800 | vmsave
|
|---|
| 801 |
|
|---|
| 802 | ; setup eax for VMLOAD
|
|---|
| 803 | mov rax, [rbp + xS*2 + RTHCPHYS_CB] ; pVMCBPhys (64 bits physical address; take low dword only)
|
|---|
| 804 |
|
|---|
| 805 | ;/* Restore Guest's general purpose registers. */
|
|---|
| 806 | ;/* RAX is loaded from the VMCB by VMRUN */
|
|---|
| 807 | mov rbx, qword [xSI + CPUMCTX.ebx]
|
|---|
| 808 | mov rcx, qword [xSI + CPUMCTX.ecx]
|
|---|
| 809 | mov rdx, qword [xSI + CPUMCTX.edx]
|
|---|
| 810 | mov rdi, qword [xSI + CPUMCTX.edi]
|
|---|
| 811 | mov rbp, qword [xSI + CPUMCTX.ebp]
|
|---|
| 812 | mov r8, qword [xSI + CPUMCTX.r8]
|
|---|
| 813 | mov r9, qword [xSI + CPUMCTX.r9]
|
|---|
| 814 | mov r10, qword [xSI + CPUMCTX.r10]
|
|---|
| 815 | mov r11, qword [xSI + CPUMCTX.r11]
|
|---|
| 816 | mov r12, qword [xSI + CPUMCTX.r12]
|
|---|
| 817 | mov r13, qword [xSI + CPUMCTX.r13]
|
|---|
| 818 | mov r14, qword [xSI + CPUMCTX.r14]
|
|---|
| 819 | mov r15, qword [xSI + CPUMCTX.r15]
|
|---|
| 820 | mov rsi, qword [xSI + CPUMCTX.esi]
|
|---|
| 821 |
|
|---|
| 822 | ; Clear the global interrupt flag & execute sti to make sure external interrupts cause a world switch
|
|---|
| 823 | clgi
|
|---|
| 824 | sti
|
|---|
| 825 |
|
|---|
| 826 | ; load guest fs, gs, sysenter msr etc
|
|---|
| 827 | vmload
|
|---|
| 828 | ; run the VM
|
|---|
| 829 | vmrun
|
|---|
| 830 |
|
|---|
| 831 | ;/* RAX is in the VMCB already; we can use it here. */
|
|---|
| 832 |
|
|---|
| 833 | ; save guest fs, gs, sysenter msr etc
|
|---|
| 834 | vmsave
|
|---|
| 835 |
|
|---|
| 836 | ; load host fs, gs, sysenter msr etc
|
|---|
| 837 | pop rax ; pushed above
|
|---|
| 838 | vmload
|
|---|
| 839 |
|
|---|
| 840 | ; Set the global interrupt flag again, but execute cli to make sure IF=0.
|
|---|
| 841 | cli
|
|---|
| 842 | stgi
|
|---|
| 843 |
|
|---|
| 844 | pop rax ; pCtx
|
|---|
| 845 |
|
|---|
| 846 | mov qword [rax + CPUMCTX.ebx], rbx
|
|---|
| 847 | mov qword [rax + CPUMCTX.ecx], rcx
|
|---|
| 848 | mov qword [rax + CPUMCTX.edx], rdx
|
|---|
| 849 | mov qword [rax + CPUMCTX.esi], rsi
|
|---|
| 850 | mov qword [rax + CPUMCTX.edi], rdi
|
|---|
| 851 | mov qword [rax + CPUMCTX.ebp], rbp
|
|---|
| 852 | mov qword [rax + CPUMCTX.r8], r8
|
|---|
| 853 | mov qword [rax + CPUMCTX.r9], r9
|
|---|
| 854 | mov qword [rax + CPUMCTX.r10], r10
|
|---|
| 855 | mov qword [rax + CPUMCTX.r11], r11
|
|---|
| 856 | mov qword [rax + CPUMCTX.r12], r12
|
|---|
| 857 | mov qword [rax + CPUMCTX.r13], r13
|
|---|
| 858 | mov qword [rax + CPUMCTX.r14], r14
|
|---|
| 859 | mov qword [rax + CPUMCTX.r15], r15
|
|---|
| 860 |
|
|---|
| 861 | ; Restore general purpose registers
|
|---|
| 862 | MYPOPAD
|
|---|
| 863 |
|
|---|
| 864 | mov eax, VINF_SUCCESS
|
|---|
| 865 |
|
|---|
| 866 | popf
|
|---|
| 867 | pop rbp
|
|---|
| 868 | add rsp, 4*xS
|
|---|
| 869 | ret
|
|---|
| 870 | ENDPROC MY_NAME(SVMR0VMRun64)
|
|---|
| 871 | %endif ; RT_ARCH_AMD64
|
|---|
| 872 |
|
|---|
