HWACCMR0Mixed.mac@ 43054

Last change on this file since 43054 was 42815, checked in by vboxsync, 12 years ago
VMM/VMMR0: Remove commented code, no CSTARs on Intels.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 25.1 KB

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1	; $Id: HWACCMR0Mixed.mac 42815 2012-08-15 04:11:49Z vboxsync $
2	;; @file
3	; HWACCMR0Mixed.mac - Stuff that darwin needs to build two versions of.
4	;
5	; Included by HWACCMR0A.asm with RT_ARCH_AMD64 defined or or undefined.
6	;
7
8	;
9	; Copyright (C) 2006-2012 Oracle Corporation
10	;
11	; This file is part of VirtualBox Open Source Edition (OSE), as
12	; available from http://www.virtualbox.org. This file is free software;
13	; you can redistribute it and/or modify it under the terms of the GNU
14	; General Public License (GPL) as published by the Free Software
15	; Foundation, in version 2 as it comes in the "COPYING" file of the
16	; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	;
19
20
21	;/**
22	; * Prepares for and executes VMLAUNCH/VMRESUME (32 bits guest mode)
23	; *
24	; * @returns VBox status code
25	; * @param fResume x86:[ebp+8], msc:rcx,gcc:rdi vmlauch/vmresume
26	; * @param pCtx x86:[ebp+c], msc:rdx,gcc:rsi Guest context
27	; * @param pCache x86:[esp+10],msc:r8, gcc:rdx VMCS cache
28	; */
29	ALIGNCODE(16)
30	BEGINPROC MY_NAME(VMXR0StartVM32)
31	push xBP
32	mov xBP, xSP
33
34	pushf
35	cli
36
37	;/* Save all general purpose host registers. */
38	MYPUSHAD
39
40	;/* First we have to save some final CPU context registers. */
41	mov eax, VMX_VMCS_HOST_RIP
42	%ifdef RT_ARCH_AMD64
43	lea r10, [.vmlaunch_done wrt rip]
44	vmwrite rax, r10
45	%else
46	mov ecx, .vmlaunch_done
47	vmwrite eax, ecx
48	%endif
49	;/* Note: assumes success... */
50
51	;/* Manual save and restore:
52	; * - General purpose registers except RIP, RSP
53	; *
54	; * Trashed:
55	; * - CR2 (we don't care)
56	; * - LDTR (reset to 0)
57	; * - DRx (presumably not changed at all)
58	; * - DR7 (reset to 0x400)
59	; * - EFLAGS (reset to RT_BIT(1); not relevant)
60	; *
61	; */
62
63	;/* Save the Guest CPU context pointer. */
64	%ifdef RT_ARCH_AMD64
65	%ifdef ASM_CALL64_GCC
66	; fResume already in rdi
67	; pCtx already in rsi
68	mov rbx, rdx ; pCache
69	%else
70	mov rdi, rcx ; fResume
71	mov rsi, rdx ; pCtx
72	mov rbx, r8 ; pCache
73	%endif
74	%else
75	mov edi, [ebp + 8] ; fResume
76	mov esi, [ebp + 12] ; pCtx
77	mov ebx, [ebp + 16] ; pCache
78	%endif
79
80	;/* Save segment registers */
81	; Note: MYPUSHSEGS trashes rdx & rcx, so we moved it here (msvc amd64 case)
82	MYPUSHSEGS xAX, ax
83
84	%ifdef VMX_USE_CACHED_VMCS_ACCESSES
85	mov ecx, [xBX + VMCSCACHE.Write.cValidEntries]
86	cmp ecx, 0
87	je .no_cached_writes
88	mov edx, ecx
89	mov ecx, 0
90	jmp .cached_write
91
92	ALIGN(16)
93	.cached_write:
94	mov eax, [xBX + VMCSCACHE.Write.aField + xCX*4]
95	vmwrite xAX, [xBX + VMCSCACHE.Write.aFieldVal + xCX*8]
96	inc xCX
97	cmp xCX, xDX
98	jl .cached_write
99
100	mov dword [xBX + VMCSCACHE.Write.cValidEntries], 0
101	.no_cached_writes:
102
103	; Save the pCache pointer
104	push xBX
105	%endif
106
107	; Save the pCtx pointer
108	push xSI
109
110	; Save LDTR
111	xor eax, eax
112	sldt ax
113	push xAX
114
115	; The TR limit is reset to 0x67; restore it manually
116	str eax
117	push xAX
118
119	; VMX only saves the base of the GDTR & IDTR and resets the limit to 0xffff; we must restore the limit correctly!
120	sub xSP, xS*2
121	sgdt [xSP]
122
123	sub xSP, xS*2
124	sidt [xSP]
125
126	%ifdef VBOX_WITH_DR6_EXPERIMENT
127	; Restore DR6 - experiment, not safe!
128	mov xBX, [xSI + CPUMCTX.dr6]
129	mov dr6, xBX
130	%endif
131
132	; Restore CR2
133	mov ebx, [xSI + CPUMCTX.cr2]
134	mov cr2, xBX
135
136	mov eax, VMX_VMCS_HOST_RSP
137	vmwrite xAX, xSP
138	;/* Note: assumes success... */
139	;/* Don't mess with ESP anymore!! */
140
141	;/* Restore Guest's general purpose registers. */
142	mov eax, [xSI + CPUMCTX.eax]
143	mov ebx, [xSI + CPUMCTX.ebx]
144	mov ecx, [xSI + CPUMCTX.ecx]
145	mov edx, [xSI + CPUMCTX.edx]
146	mov ebp, [xSI + CPUMCTX.ebp]
147
148	; resume or start?
149	cmp xDI, 0 ; fResume
150	je .vmlauch_lauch
151
152	;/* Restore edi & esi. */
153	mov edi, [xSI + CPUMCTX.edi]
154	mov esi, [xSI + CPUMCTX.esi]
155
156	vmresume
157	jmp .vmlaunch_done; ;/* here if vmresume detected a failure. */
158
159	.vmlauch_lauch:
160	;/* Restore edi & esi. */
161	mov edi, [xSI + CPUMCTX.edi]
162	mov esi, [xSI + CPUMCTX.esi]
163
164	vmlaunch
165	jmp .vmlaunch_done; ;/* here if vmlaunch detected a failure. */
166
167	ALIGNCODE(16) ;; @todo YASM BUG - this alignment is wrong on darwin, it's 1 byte off.
168	.vmlaunch_done:
169	jc near .vmxstart_invalid_vmxon_ptr
170	jz near .vmxstart_start_failed
171
172	; Restore base and limit of the IDTR & GDTR
173	lidt [xSP]
174	add xSP, xS*2
175	lgdt [xSP]
176	add xSP, xS*2
177
178	push xDI
179	mov xDI, [xSP + xS * 3] ; pCtx (*3 to skip the saved LDTR + TR)
180
181	mov [ss:xDI + CPUMCTX.eax], eax
182	mov [ss:xDI + CPUMCTX.ebx], ebx
183	mov [ss:xDI + CPUMCTX.ecx], ecx
184	mov [ss:xDI + CPUMCTX.edx], edx
185	mov [ss:xDI + CPUMCTX.esi], esi
186	mov [ss:xDI + CPUMCTX.ebp], ebp
187	%ifdef RT_ARCH_AMD64
188	pop xAX ; the guest edi we pushed above
189	mov dword [ss:xDI + CPUMCTX.edi], eax
190	%else
191	pop dword [ss:xDI + CPUMCTX.edi] ; the guest edi we pushed above
192	%endif
193
194	%ifdef VBOX_WITH_DR6_EXPERIMENT
195	; Save DR6 - experiment, not safe!
196	mov xAX, dr6
197	mov [ss:xDI + CPUMCTX.dr6], xAX
198	%endif
199
200	; Restore TSS selector; must mark it as not busy before using ltr (!)
201	; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p)
202	; @todo get rid of sgdt
203	pop xBX ; saved TR
204	sub xSP, xS*2
205	sgdt [xSP]
206	mov xAX, xBX
207	and al, 0F8h ; mask away TI and RPL bits, get descriptor offset.
208	add xAX, [xSP + 2] ; eax <- GDTR.address + descriptor offset.
209	and dword [ss:xAX + 4], ~0200h ; clear busy flag (2nd type2 bit)
210	ltr bx
211	add xSP, xS*2
212
213	pop xAX ; saved LDTR
214	lldt ax
215
216	add xSP, xS ; pCtx
217
218	%ifdef VMX_USE_CACHED_VMCS_ACCESSES
219	pop xDX ; saved pCache
220
221	mov ecx, [ss:xDX + VMCSCACHE.Read.cValidEntries]
222	cmp ecx, 0 ; can't happen
223	je .no_cached_reads
224	jmp .cached_read
225
226	ALIGN(16)
227	.cached_read:
228	dec xCX
229	mov eax, [ss:xDX + VMCSCACHE.Read.aField + xCX*4]
230	vmread [ss:xDX + VMCSCACHE.Read.aFieldVal + xCX*8], xAX
231	cmp xCX, 0
232	jnz .cached_read
233	.no_cached_reads:
234
235	; Save CR2 for EPT
236	mov xAX, cr2
237	mov [ss:xDX + VMCSCACHE.cr2], xAX
238	%endif
239
240	; Restore segment registers
241	MYPOPSEGS xAX, ax
242
243	; Restore general purpose registers
244	MYPOPAD
245
246	mov eax, VINF_SUCCESS
247
248	.vmstart_end:
249	popf
250	pop xBP
251	ret
252
253
254	.vmxstart_invalid_vmxon_ptr:
255	; Restore base and limit of the IDTR & GDTR
256	lidt [xSP]
257	add xSP, xS*2
258	lgdt [xSP]
259	add xSP, xS*2
260
261	; Restore TSS selector; must mark it as not busy before using ltr (!)
262	; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p)
263	; @todo get rid of sgdt
264	pop xBX ; saved TR
265	sub xSP, xS*2
266	sgdt [xSP]
267	mov xAX, xBX
268	and al, 0F8h ; mask away TI and RPL bits, get descriptor offset.
269	add xAX, [xSP + 2] ; eax <- GDTR.address + descriptor offset.
270	and dword [ss:xAX + 4], ~0200h ; clear busy flag (2nd type2 bit)
271	ltr bx
272	add xSP, xS*2
273
274	pop xAX ; saved LDTR
275	lldt ax
276
277	%ifdef VMX_USE_CACHED_VMCS_ACCESSES
278	add xSP, xS*2 ; pCtx + pCache
279	%else
280	add xSP, xS ; pCtx
281	%endif
282
283	; Restore segment registers
284	MYPOPSEGS xAX, ax
285
286	; Restore all general purpose host registers.
287	MYPOPAD
288	mov eax, VERR_VMX_INVALID_VMXON_PTR
289	jmp .vmstart_end
290
291	.vmxstart_start_failed:
292	; Restore base and limit of the IDTR & GDTR
293	lidt [xSP]
294	add xSP, xS*2
295	lgdt [xSP]
296	add xSP, xS*2
297
298	; Restore TSS selector; must mark it as not busy before using ltr (!)
299	; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p)
300	; @todo get rid of sgdt
301	pop xBX ; saved TR
302	sub xSP, xS*2
303	sgdt [xSP]
304	mov xAX, xBX
305	and al, 0F8h ; mask away TI and RPL bits, get descriptor offset.
306	add xAX, [xSP + 2] ; eax <- GDTR.address + descriptor offset.
307	and dword [ss:xAX + 4], ~0200h ; clear busy flag (2nd type2 bit)
308	ltr bx
309	add xSP, xS*2
310
311	pop xAX ; saved LDTR
312	lldt ax
313
314	%ifdef VMX_USE_CACHED_VMCS_ACCESSES
315	add xSP, xS*2 ; pCtx + pCache
316	%else
317	add xSP, xS ; pCtx
318	%endif
319
320	; Restore segment registers
321	MYPOPSEGS xAX, ax
322
323	; Restore all general purpose host registers.
324	MYPOPAD
325	mov eax, VERR_VMX_UNABLE_TO_START_VM
326	jmp .vmstart_end
327
328	ENDPROC MY_NAME(VMXR0StartVM32)
329
330	%ifdef RT_ARCH_AMD64
331	;/**
332	; * Prepares for and executes VMLAUNCH/VMRESUME (64 bits guest mode)
333	; *
334	; * @returns VBox status code
335	; * @param fResume msc:rcx, gcc:rdi vmlauch/vmresume
336	; * @param pCtx msc:rdx, gcc:rsi Guest context
337	; * @param pCache msc:r8, gcc:rdx VMCS cache
338	; */
339	ALIGNCODE(16)
340	BEGINPROC MY_NAME(VMXR0StartVM64)
341	push xBP
342	mov xBP, xSP
343
344	pushf
345	cli
346
347	;/* Save all general purpose host registers. */
348	MYPUSHAD
349
350	;/* First we have to save some final CPU context registers. */
351	lea r10, [.vmlaunch64_done wrt rip]
352	mov rax, VMX_VMCS_HOST_RIP ;/* return address (too difficult to continue after VMLAUNCH?) */
353	vmwrite rax, r10
354	;/* Note: assumes success... */
355
356	;/* Manual save and restore:
357	; * - General purpose registers except RIP, RSP
358	; *
359	; * Trashed:
360	; * - CR2 (we don't care)
361	; * - LDTR (reset to 0)
362	; * - DRx (presumably not changed at all)
363	; * - DR7 (reset to 0x400)
364	; * - EFLAGS (reset to RT_BIT(1); not relevant)
365	; *
366	; */
367
368	;/* Save the Guest CPU context pointer. */
369	%ifdef ASM_CALL64_GCC
370	; fResume already in rdi
371	; pCtx already in rsi
372	mov rbx, rdx ; pCache
373	%else
374	mov rdi, rcx ; fResume
375	mov rsi, rdx ; pCtx
376	mov rbx, r8 ; pCache
377	%endif
378
379	;/* Save segment registers */
380	; Note: MYPUSHSEGS trashes rdx & rcx, so we moved it here (msvc amd64 case)
381	MYPUSHSEGS xAX, ax
382
383	%ifdef VMX_USE_CACHED_VMCS_ACCESSES
384	mov ecx, [xBX + VMCSCACHE.Write.cValidEntries]
385	cmp ecx, 0
386	je .no_cached_writes
387	mov edx, ecx
388	mov ecx, 0
389	jmp .cached_write
390
391	ALIGN(16)
392	.cached_write:
393	mov eax, [xBX + VMCSCACHE.Write.aField + xCX*4]
394	vmwrite xAX, [xBX + VMCSCACHE.Write.aFieldVal + xCX*8]
395	inc xCX
396	cmp xCX, xDX
397	jl .cached_write
398
399	mov dword [xBX + VMCSCACHE.Write.cValidEntries], 0
400	.no_cached_writes:
401
402	; Save the pCache pointer
403	push xBX
404	%endif
405
406	%ifndef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
407	; Save the host MSRs and load the guest MSRs
408	LOADGUESTMSR MSR_K8_LSTAR, CPUMCTX.msrLSTAR
409	LOADGUESTMSR MSR_K6_STAR, CPUMCTX.msrSTAR
410	LOADGUESTMSR MSR_K8_SF_MASK, CPUMCTX.msrSFMASK
411	%endif
412	; Kernel GS Base is special, we need to manually load/store it, see @bugref{6208}
413	LOADGUESTMSR MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
414
415	; Save the pCtx pointer
416	push xSI
417
418	; Save LDTR
419	xor eax, eax
420	sldt ax
421	push xAX
422
423	; The TR limit is reset to 0x67; restore it manually
424	str eax
425	push xAX
426
427	; VMX only saves the base of the GDTR & IDTR and resets the limit to 0xffff; we must restore the limit correctly!
428	sub xSP, xS*2
429	sgdt [xSP]
430
431	sub xSP, xS*2
432	sidt [xSP]
433
434	%ifdef VBOX_WITH_DR6_EXPERIMENT
435	; Restore DR6 - experiment, not safe!
436	mov xBX, [xSI + CPUMCTX.dr6]
437	mov dr6, xBX
438	%endif
439
440	; Restore CR2
441	mov rbx, qword [xSI + CPUMCTX.cr2]
442	mov cr2, rbx
443
444	mov eax, VMX_VMCS_HOST_RSP
445	vmwrite xAX, xSP
446	;/* Note: assumes success... */
447	;/* Don't mess with ESP anymore!! */
448
449	;/* Restore Guest's general purpose registers. */
450	mov rax, qword [xSI + CPUMCTX.eax]
451	mov rbx, qword [xSI + CPUMCTX.ebx]
452	mov rcx, qword [xSI + CPUMCTX.ecx]
453	mov rdx, qword [xSI + CPUMCTX.edx]
454	mov rbp, qword [xSI + CPUMCTX.ebp]
455	mov r8, qword [xSI + CPUMCTX.r8]
456	mov r9, qword [xSI + CPUMCTX.r9]
457	mov r10, qword [xSI + CPUMCTX.r10]
458	mov r11, qword [xSI + CPUMCTX.r11]
459	mov r12, qword [xSI + CPUMCTX.r12]
460	mov r13, qword [xSI + CPUMCTX.r13]
461	mov r14, qword [xSI + CPUMCTX.r14]
462	mov r15, qword [xSI + CPUMCTX.r15]
463
464	; resume or start?
465	cmp xDI, 0 ; fResume
466	je .vmlauch64_lauch
467
468	;/* Restore edi & esi. */
469	mov rdi, qword [xSI + CPUMCTX.edi]
470	mov rsi, qword [xSI + CPUMCTX.esi]
471
472	vmresume
473	jmp .vmlaunch64_done; ;/* here if vmresume detected a failure. */
474
475	.vmlauch64_lauch:
476	;/* Restore rdi & rsi. */
477	mov rdi, qword [xSI + CPUMCTX.edi]
478	mov rsi, qword [xSI + CPUMCTX.esi]
479
480	vmlaunch
481	jmp .vmlaunch64_done; ;/* here if vmlaunch detected a failure. */
482
483	ALIGNCODE(16)
484	.vmlaunch64_done:
485	jc near .vmxstart64_invalid_vmxon_ptr
486	jz near .vmxstart64_start_failed
487
488	; Restore base and limit of the IDTR & GDTR
489	lidt [xSP]
490	add xSP, xS*2
491	lgdt [xSP]
492	add xSP, xS*2
493
494	push xDI
495	mov xDI, [xSP + xS * 3] ; pCtx (*3 to skip the saved LDTR + TR)
496
497	mov qword [xDI + CPUMCTX.eax], rax
498	mov qword [xDI + CPUMCTX.ebx], rbx
499	mov qword [xDI + CPUMCTX.ecx], rcx
500	mov qword [xDI + CPUMCTX.edx], rdx
501	mov qword [xDI + CPUMCTX.esi], rsi
502	mov qword [xDI + CPUMCTX.ebp], rbp
503	mov qword [xDI + CPUMCTX.r8], r8
504	mov qword [xDI + CPUMCTX.r9], r9
505	mov qword [xDI + CPUMCTX.r10], r10
506	mov qword [xDI + CPUMCTX.r11], r11
507	mov qword [xDI + CPUMCTX.r12], r12
508	mov qword [xDI + CPUMCTX.r13], r13
509	mov qword [xDI + CPUMCTX.r14], r14
510	mov qword [xDI + CPUMCTX.r15], r15
511
512	pop xAX ; the guest edi we pushed above
513	mov qword [xDI + CPUMCTX.edi], rax
514
515	%ifdef VBOX_WITH_DR6_EXPERIMENT
516	; Save DR6 - experiment, not safe!
517	mov xAX, dr6
518	mov [xDI + CPUMCTX.dr6], xAX
519	%endif
520
521	; Restore TSS selector; must mark it as not busy before using ltr (!)
522	; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p)
523	; @todo get rid of sgdt
524	pop xBX ; saved TR
525	sub xSP, xS*2
526	sgdt [xSP]
527	mov xAX, xBX
528	and al, 0F8h ; mask away TI and RPL bits, get descriptor offset.
529	add xAX, [xSP + 2] ; eax <- GDTR.address + descriptor offset.
530	and dword [xAX + 4], ~0200h ; clear busy flag (2nd type2 bit)
531	ltr bx
532	add xSP, xS*2
533
534	pop xAX ; saved LDTR
535	lldt ax
536
537	pop xSI ; pCtx (needed in rsi by the macros below)
538
539	; Kernel GS Base is special, we need to manually load/store it, see @bugref{6208}.
540	LOADHOSTMSREX MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
541	%ifndef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
542	; Save the guest MSRs and load the host MSRs
543	LOADHOSTMSREX MSR_K8_SF_MASK, CPUMCTX.msrSFMASK
544	LOADHOSTMSREX MSR_K6_STAR, CPUMCTX.msrSTAR
545	LOADHOSTMSREX MSR_K8_LSTAR, CPUMCTX.msrLSTAR
546	%endif
547
548	%ifdef VMX_USE_CACHED_VMCS_ACCESSES
549	pop xDX ; saved pCache
550
551	mov ecx, [xDX + VMCSCACHE.Read.cValidEntries]
552	cmp ecx, 0 ; can't happen
553	je .no_cached_reads
554	jmp .cached_read
555
556	ALIGN(16)
557	.cached_read:
558	dec xCX
559	mov eax, [xDX + VMCSCACHE.Read.aField + xCX*4]
560	vmread [xDX + VMCSCACHE.Read.aFieldVal + xCX*8], xAX
561	cmp xCX, 0
562	jnz .cached_read
563	.no_cached_reads:
564
565	; Save CR2 for EPT
566	mov xAX, cr2
567	mov [xDX + VMCSCACHE.cr2], xAX
568	%endif
569
570	; Restore segment registers
571	MYPOPSEGS xAX, ax
572
573	; Restore general purpose registers
574	MYPOPAD
575
576	mov eax, VINF_SUCCESS
577
578	.vmstart64_end:
579	popf
580	pop xBP
581	ret
582
583
584	.vmxstart64_invalid_vmxon_ptr:
585	; Restore base and limit of the IDTR & GDTR
586	lidt [xSP]
587	add xSP, xS*2
588	lgdt [xSP]
589	add xSP, xS*2
590
591	; Restore TSS selector; must mark it as not busy before using ltr (!)
592	; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p)
593	; @todo get rid of sgdt
594	pop xBX ; saved TR
595	sub xSP, xS*2
596	sgdt [xSP]
597	mov xAX, xBX
598	and al, 0F8h ; mask away TI and RPL bits, get descriptor offset.
599	add xAX, [xSP + 2] ; eax <- GDTR.address + descriptor offset.
600	and dword [xAX + 4], ~0200h ; clear busy flag (2nd type2 bit)
601	ltr bx
602	add xSP, xS*2
603
604	pop xAX ; saved LDTR
605	lldt ax
606
607	pop xSI ; pCtx (needed in rsi by the macros below)
608
609	; Kernel GS base is special, we need to manually load/store it See @bugref{6208}.
610	LOADHOSTMSREX MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
611	%ifndef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
612	; Load the host MSRs
613	LOADHOSTMSR MSR_K8_SF_MASK
614	LOADHOSTMSR MSR_K6_STAR
615	LOADHOSTMSR MSR_K8_LSTAR
616	%endif
617
618	%ifdef VMX_USE_CACHED_VMCS_ACCESSES
619	add xSP, xS ; pCache
620	%endif
621
622	; Restore segment registers
623	MYPOPSEGS xAX, ax
624
625	; Restore all general purpose host registers.
626	MYPOPAD
627	mov eax, VERR_VMX_INVALID_VMXON_PTR
628	jmp .vmstart64_end
629
630	.vmxstart64_start_failed:
631	; Restore base and limit of the IDTR & GDTR
632	lidt [xSP]
633	add xSP, xS*2
634	lgdt [xSP]
635	add xSP, xS*2
636
637	; Restore TSS selector; must mark it as not busy before using ltr (!)
638	; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p)
639	; @todo get rid of sgdt
640	pop xBX ; saved TR
641	sub xSP, xS*2
642	sgdt [xSP]
643	mov xAX, xBX
644	and al, 0F8h ; mask away TI and RPL bits, get descriptor offset.
645	add xAX, [xSP + 2] ; eax <- GDTR.address + descriptor offset.
646	and dword [xAX + 4], ~0200h ; clear busy flag (2nd type2 bit)
647	ltr bx
648	add xSP, xS*2
649
650	pop xAX ; saved LDTR
651	lldt ax
652
653	pop xSI ; pCtx (needed in rsi by the macros below)
654
655	; Kernel GS base is special, load it manually. See @bugref{6208}.
656	LOADHOSTMSREX MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
657	%ifndef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
658	; Load the host MSRs
659	LOADHOSTMSR MSR_K8_SF_MASK
660	LOADHOSTMSR MSR_K6_STAR
661	LOADHOSTMSR MSR_K8_LSTAR
662	%endif
663
664	%ifdef VMX_USE_CACHED_VMCS_ACCESSES
665	add xSP, xS ; pCache
666	%endif
667
668	; Restore segment registers
669	MYPOPSEGS xAX, ax
670
671	; Restore all general purpose host registers.
672	MYPOPAD
673	mov eax, VERR_VMX_UNABLE_TO_START_VM
674	jmp .vmstart64_end
675	ENDPROC MY_NAME(VMXR0StartVM64)
676	%endif ; RT_ARCH_AMD64
677
678
679	;/**
680	; * Prepares for and executes VMRUN (32 bits guests)
681	; *
682	; * @returns VBox status code
683	; * @param HCPhysVMCB Physical address of host VMCB
684	; * @param HCPhysVMCB Physical address of guest VMCB
685	; * @param pCtx Guest context
686	; */
687	ALIGNCODE(16)
688	BEGINPROC MY_NAME(SVMR0VMRun)
689	%ifdef RT_ARCH_AMD64 ; fake a cdecl stack frame
690	%ifdef ASM_CALL64_GCC
691	push rdx
692	push rsi
693	push rdi
694	%else
695	push r8
696	push rdx
697	push rcx
698	%endif
699	push 0
700	%endif
701	push xBP
702	mov xBP, xSP
703	pushf
704
705	;/* Manual save and restore:
706	; * - General purpose registers except RIP, RSP, RAX
707	; *
708	; * Trashed:
709	; * - CR2 (we don't care)
710	; * - LDTR (reset to 0)
711	; * - DRx (presumably not changed at all)
712	; * - DR7 (reset to 0x400)
713	; */
714
715	;/* Save all general purpose host registers. */
716	MYPUSHAD
717
718	;/* Save the Guest CPU context pointer. */
719	mov xSI, [xBP + xS2 + RTHCPHYS_CB2] ; pCtx
720	push xSI ; push for saving the state at the end
721
722	; save host fs, gs, sysenter msr etc
723	mov xAX, [xBP + xS*2] ; pVMCBHostPhys (64 bits physical address; x86: take low dword only)
724	push xAX ; save for the vmload after vmrun
725	vmsave
726
727	; setup eax for VMLOAD
728	mov xAX, [xBP + xS*2 + RTHCPHYS_CB] ; pVMCBPhys (64 bits physical address; take low dword only)
729
730	;/* Restore Guest's general purpose registers. */
731	;/* EAX is loaded from the VMCB by VMRUN */
732	mov ebx, [xSI + CPUMCTX.ebx]
733	mov ecx, [xSI + CPUMCTX.ecx]
734	mov edx, [xSI + CPUMCTX.edx]
735	mov edi, [xSI + CPUMCTX.edi]
736	mov ebp, [xSI + CPUMCTX.ebp]
737	mov esi, [xSI + CPUMCTX.esi]
738
739	; Clear the global interrupt flag & execute sti to make sure external interrupts cause a world switch
740	clgi
741	sti
742
743	; load guest fs, gs, sysenter msr etc
744	vmload
745	; run the VM
746	vmrun
747
748	;/* EAX is in the VMCB already; we can use it here. */
749
750	; save guest fs, gs, sysenter msr etc
751	vmsave
752
753	; load host fs, gs, sysenter msr etc
754	pop xAX ; pushed above
755	vmload
756
757	; Set the global interrupt flag again, but execute cli to make sure IF=0.
758	cli
759	stgi
760
761	pop xAX ; pCtx
762
763	mov [ss:xAX + CPUMCTX.ebx], ebx
764	mov [ss:xAX + CPUMCTX.ecx], ecx
765	mov [ss:xAX + CPUMCTX.edx], edx
766	mov [ss:xAX + CPUMCTX.esi], esi
767	mov [ss:xAX + CPUMCTX.edi], edi
768	mov [ss:xAX + CPUMCTX.ebp], ebp
769
770	; Restore general purpose registers
771	MYPOPAD
772
773	mov eax, VINF_SUCCESS
774
775	popf
776	pop xBP
777	%ifdef RT_ARCH_AMD64
778	add xSP, 4*xS
779	%endif
780	ret
781	ENDPROC MY_NAME(SVMR0VMRun)
782
783	%ifdef RT_ARCH_AMD64
784	;/**
785	; * Prepares for and executes VMRUN (64 bits guests)
786	; *
787	; * @returns VBox status code
788	; * @param HCPhysVMCB Physical address of host VMCB
789	; * @param HCPhysVMCB Physical address of guest VMCB
790	; * @param pCtx Guest context
791	; */
792	ALIGNCODE(16)
793	BEGINPROC MY_NAME(SVMR0VMRun64)
794	; fake a cdecl stack frame
795	%ifdef ASM_CALL64_GCC
796	push rdx
797	push rsi
798	push rdi
799	%else
800	push r8
801	push rdx
802	push rcx
803	%endif
804	push 0
805	push rbp
806	mov rbp, rsp
807	pushf
808
809	;/* Manual save and restore:
810	; * - General purpose registers except RIP, RSP, RAX
811	; *
812	; * Trashed:
813	; * - CR2 (we don't care)
814	; * - LDTR (reset to 0)
815	; * - DRx (presumably not changed at all)
816	; * - DR7 (reset to 0x400)
817	; */
818
819	;/* Save all general purpose host registers. */
820	MYPUSHAD
821
822	;/* Save the Guest CPU context pointer. */
823	mov rsi, [rbp + xS2 + RTHCPHYS_CB2] ; pCtx
824	push rsi ; push for saving the state at the end
825
826	; save host fs, gs, sysenter msr etc
827	mov rax, [rbp + xS*2] ; pVMCBHostPhys (64 bits physical address; x86: take low dword only)
828	push rax ; save for the vmload after vmrun
829	vmsave
830
831	; setup eax for VMLOAD
832	mov rax, [rbp + xS*2 + RTHCPHYS_CB] ; pVMCBPhys (64 bits physical address; take low dword only)
833
834	;/* Restore Guest's general purpose registers. */
835	;/* RAX is loaded from the VMCB by VMRUN */
836	mov rbx, qword [xSI + CPUMCTX.ebx]
837	mov rcx, qword [xSI + CPUMCTX.ecx]
838	mov rdx, qword [xSI + CPUMCTX.edx]
839	mov rdi, qword [xSI + CPUMCTX.edi]
840	mov rbp, qword [xSI + CPUMCTX.ebp]
841	mov r8, qword [xSI + CPUMCTX.r8]
842	mov r9, qword [xSI + CPUMCTX.r9]
843	mov r10, qword [xSI + CPUMCTX.r10]
844	mov r11, qword [xSI + CPUMCTX.r11]
845	mov r12, qword [xSI + CPUMCTX.r12]
846	mov r13, qword [xSI + CPUMCTX.r13]
847	mov r14, qword [xSI + CPUMCTX.r14]
848	mov r15, qword [xSI + CPUMCTX.r15]
849	mov rsi, qword [xSI + CPUMCTX.esi]
850
851	; Clear the global interrupt flag & execute sti to make sure external interrupts cause a world switch
852	clgi
853	sti
854
855	; load guest fs, gs, sysenter msr etc
856	vmload
857	; run the VM
858	vmrun
859
860	;/* RAX is in the VMCB already; we can use it here. */
861
862	; save guest fs, gs, sysenter msr etc
863	vmsave
864
865	; load host fs, gs, sysenter msr etc
866	pop rax ; pushed above
867	vmload
868
869	; Set the global interrupt flag again, but execute cli to make sure IF=0.
870	cli
871	stgi
872
873	pop rax ; pCtx
874
875	mov qword [rax + CPUMCTX.ebx], rbx
876	mov qword [rax + CPUMCTX.ecx], rcx
877	mov qword [rax + CPUMCTX.edx], rdx
878	mov qword [rax + CPUMCTX.esi], rsi
879	mov qword [rax + CPUMCTX.edi], rdi
880	mov qword [rax + CPUMCTX.ebp], rbp
881	mov qword [rax + CPUMCTX.r8], r8
882	mov qword [rax + CPUMCTX.r9], r9
883	mov qword [rax + CPUMCTX.r10], r10
884	mov qword [rax + CPUMCTX.r11], r11
885	mov qword [rax + CPUMCTX.r12], r12
886	mov qword [rax + CPUMCTX.r13], r13
887	mov qword [rax + CPUMCTX.r14], r14
888	mov qword [rax + CPUMCTX.r15], r15
889
890	; Restore general purpose registers
891	MYPOPAD
892
893	mov eax, VINF_SUCCESS
894
895	popf
896	pop rbp
897	add rsp, 4*xS
898	ret
899	ENDPROC MY_NAME(SVMR0VMRun64)
900	%endif ; RT_ARCH_AMD64
901

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