HWSVMR0.cpp@ 10645

Last change on this file since 10645 was 10609, checked in by vboxsync, 17 years ago
Check for unexpected rescheduling.
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1	/* $Id: HWSVMR0.cpp 10609 2008-07-14 16:28:23Z vboxsync $ */
2	/** @file
3	* HWACCM SVM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_svm.h>
32	#include <VBox/pgm.h>
33	#include <VBox/pdm.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <VBox/selm.h>
37	#include <VBox/iom.h>
38	#include <VBox/dis.h>
39	#include <VBox/dbgf.h>
40	#include <VBox/disopcode.h>
41	#include <iprt/param.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm.h>
44	#include <iprt/cpuset.h>
45	#include <iprt/mp.h>
46	#include "HWSVMR0.h"
47
48	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
49
50	/**
51	* Sets up and activates AMD-V on the current CPU
52	*
53	* @returns VBox status code.
54	* @param pCpu CPU info struct
55	* @param pVM The VM to operate on.
56	* @param pvPageCpu Pointer to the global cpu page
57	* @param pPageCpuPhys Physical address of the global cpu page
58	*/
59	HWACCMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
60	{
61	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
62	AssertReturn(pVM, VERR_INVALID_PARAMETER);
63	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
64
65	/* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
66
67	#ifdef LOG_ENABLED
68	SUPR0Printf("SVMR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
69	#endif
70
71	/* Turn on AMD-V in the EFER MSR. */
72	uint64_t val = ASMRdMsr(MSR_K6_EFER);
73	if (!(val & MSR_K6_EFER_SVME))
74	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
75
76	/* Write the physical page address where the CPU will store the host state while executing the VM. */
77	ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
78
79	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
80	pCpu->cTLBFlushes = 0;
81	return VINF_SUCCESS;
82	}
83
84	/**
85	* Deactivates AMD-V on the current CPU
86	*
87	* @returns VBox status code.
88	* @param pCpu CPU info struct
89	* @param pvPageCpu Pointer to the global cpu page
90	* @param pPageCpuPhys Physical address of the global cpu page
91	*/
92	HWACCMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
93	{
94	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
95	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
96
97	#ifdef LOG_ENABLED
98	SUPR0Printf("SVMR0DisableCpu cpu %d\n", pCpu->idCpu);
99	#endif
100
101	/* Turn off AMD-V in the EFER MSR. */
102	uint64_t val = ASMRdMsr(MSR_K6_EFER);
103	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
104
105	/* Invalidate host state physical address. */
106	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
107	pCpu->uCurrentASID = 0;
108
109	return VINF_SUCCESS;
110	}
111
112	/**
113	* Does Ring-0 per VM AMD-V init.
114	*
115	* @returns VBox status code.
116	* @param pVM The VM to operate on.
117	*/
118	HWACCMR0DECL(int) SVMR0InitVM(PVM pVM)
119	{
120	int rc;
121
122	pVM->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
123	pVM->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
124	pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
125	pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
126
127
128	/* Allocate one page for the VM control block (VMCB). */
129	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
130	if (RT_FAILURE(rc))
131	return rc;
132
133	pVM->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCB);
134	pVM->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCB, 0);
135	ASMMemZeroPage(pVM->hwaccm.s.svm.pVMCB);
136
137	/* Allocate one page for the host context */
138	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
139	if (RT_FAILURE(rc))
140	return rc;
141
142	pVM->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCBHost);
143	pVM->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCBHost, 0);
144	ASMMemZeroPage(pVM->hwaccm.s.svm.pVMCBHost);
145
146	/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
147	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
148	if (RT_FAILURE(rc))
149	return rc;
150
151	pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
152	pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
153	/* Set all bits to intercept all IO accesses. */
154	ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
155
156	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
157	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
158	if (RT_FAILURE(rc))
159	return rc;
160
161	pVM->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
162	pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
163	/* Set all bits to intercept all MSR accesses. */
164	ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
165
166	/* Erratum 170 which requires a forced TLB flush for each world switch:
167	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
168	*
169	* All BH-G1/2 and DH-G1/2 models include a fix:
170	* Athlon X2: 0x6b 1/2
171	* 0x68 1/2
172	* Athlon 64: 0x7f 1
173	* 0x6f 2
174	* Sempron: 0x7f 1/2
175	* 0x6f 2
176	* 0x6c 2
177	* 0x7c 2
178	* Turion 64: 0x68 2
179	*
180	*/
181	uint32_t u32Dummy;
182	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
183	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
184	u32BaseFamily= (u32Version >> 8) & 0xf;
185	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
186	u32Model = ((u32Version >> 4) & 0xf);
187	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
188	u32Stepping = u32Version & 0xf;
189	if ( u32Family == 0xf
190	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
191	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
192	{
193	Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
194	pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
195	}
196
197	/* Invalidate the last cpu we were running on. */
198	pVM->hwaccm.s.svm.idLastCpu = NIL_RTCPUID;
199	return VINF_SUCCESS;
200	}
201
202	/**
203	* Does Ring-0 per VM AMD-V termination.
204	*
205	* @returns VBox status code.
206	* @param pVM The VM to operate on.
207	*/
208	HWACCMR0DECL(int) SVMR0TermVM(PVM pVM)
209	{
210	if (pVM->hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)
211	{
212	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCB, false);
213	pVM->hwaccm.s.svm.pVMCB = 0;
214	pVM->hwaccm.s.svm.pVMCBPhys = 0;
215	pVM->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
216	}
217	if (pVM->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ)
218	{
219	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCBHost, false);
220	pVM->hwaccm.s.svm.pVMCBHost = 0;
221	pVM->hwaccm.s.svm.pVMCBHostPhys = 0;
222	pVM->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
223	}
224	if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)
225	{
226	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
227	pVM->hwaccm.s.svm.pIOBitmap = 0;
228	pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
229	pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
230	}
231	if (pVM->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
232	{
233	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
234	pVM->hwaccm.s.svm.pMSRBitmap = 0;
235	pVM->hwaccm.s.svm.pMSRBitmapPhys = 0;
236	pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
237	}
238	return VINF_SUCCESS;
239	}
240
241	/**
242	* Sets up AMD-V for the specified VM
243	*
244	* @returns VBox status code.
245	* @param pVM The VM to operate on.
246	*/
247	HWACCMR0DECL(int) SVMR0SetupVM(PVM pVM)
248	{
249	int rc = VINF_SUCCESS;
250	SVM_VMCB *pVMCB;
251
252	AssertReturn(pVM, VERR_INVALID_PARAMETER);
253
254	Assert(pVM->hwaccm.s.svm.fSupported);
255
256	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
257	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
258
259	/* Program the control fields. Most of them never have to be changed again. */
260	/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
261	/** @note CR0 & CR4 can be safely read when guest and shadow copies are identical. */
262	if (!pVM->hwaccm.s.fNestedPaging)
263	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
264	else
265	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
266
267	/*
268	* CR0/3/4 writes must be intercepted for obvious reasons.
269	*/
270	if (!pVM->hwaccm.s.fNestedPaging)
271	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(8);
272	else
273	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4) \| RT_BIT(8);
274
275	/* Intercept all DRx reads and writes. */
276	pVMCB->ctrl.u16InterceptRdDRx = RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7);
277	pVMCB->ctrl.u16InterceptWrDRx = RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7);
278
279	/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
280	* All breakpoints are automatically cleared when the VM exits.
281	*/
282
283	pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
284	#ifndef DEBUG
285	if (pVM->hwaccm.s.fNestedPaging)
286	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(14); /* no longer need to intercept #PF. */
287	#endif
288
289	pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
290	\| SVM_CTRL1_INTERCEPT_VINTR
291	\| SVM_CTRL1_INTERCEPT_NMI
292	\| SVM_CTRL1_INTERCEPT_SMI
293	\| SVM_CTRL1_INTERCEPT_INIT
294	\| SVM_CTRL1_INTERCEPT_RDPMC
295	\| SVM_CTRL1_INTERCEPT_CPUID
296	\| SVM_CTRL1_INTERCEPT_RSM
297	\| SVM_CTRL1_INTERCEPT_HLT
298	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
299	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
300	\| SVM_CTRL1_INTERCEPT_INVLPG
301	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
302	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH
303	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
304	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
305	;
306	/* With nested paging we don't care about invlpg anymore. */
307	if (pVM->hwaccm.s.fNestedPaging)
308	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
309
310	pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
311	\| SVM_CTRL2_INTERCEPT_VMMCALL
312	\| SVM_CTRL2_INTERCEPT_VMLOAD
313	\| SVM_CTRL2_INTERCEPT_VMSAVE
314	\| SVM_CTRL2_INTERCEPT_STGI
315	\| SVM_CTRL2_INTERCEPT_CLGI
316	\| SVM_CTRL2_INTERCEPT_SKINIT
317	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
318	\| SVM_CTRL2_INTERCEPT_WBINVD
319	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
320	;
321	Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
322	Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
323	Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
324
325	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
326	pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
327	/* Ignore the priority in the TPR; just deliver it when we tell it to. */
328	pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
329
330	/* Set IO and MSR bitmap addresses. */
331	pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
332	pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
333
334	/* No LBR virtualization. */
335	pVMCB->ctrl.u64LBRVirt = 0;
336
337	/** The ASID must start at 1; the host uses 0. */
338	pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
339
340	/** Setup the PAT msr (nested paging only) */
341	pVMCB->guest.u64GPAT = 0x0007040600070406ULL;
342	return rc;
343	}
344
345
346	/**
347	* Injects an event (trap or external interrupt)
348	*
349	* @param pVM The VM to operate on.
350	* @param pVMCB SVM control block
351	* @param pCtx CPU Context
352	* @param pIntInfo SVM interrupt info
353	*/
354	inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx, SVM_EVENT* pEvent)
355	{
356	#ifdef VBOX_STRICT
357	if (pEvent->n.u8Vector == 0xE)
358	Log(("SVM: Inject int %d at %VGv error code=%02x CR2=%VGv intInfo=%08x\n", pEvent->n.u8Vector, pCtx->rip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
359	else
360	if (pEvent->n.u8Vector < 0x20)
361	Log(("SVM: Inject int %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->rip, pEvent->n.u32ErrorCode));
362	else
363	{
364	Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->rip));
365	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
366	Assert(pCtx->eflags.u32 & X86_EFL_IF);
367	}
368	#endif
369
370	/* Set event injection state. */
371	pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
372	}
373
374
375	/**
376	* Checks for pending guest interrupts and injects them
377	*
378	* @returns VBox status code.
379	* @param pVM The VM to operate on.
380	* @param pVMCB SVM control block
381	* @param pCtx CPU Context
382	*/
383	static int SVMR0CheckPendingInterrupt(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx)
384	{
385	int rc;
386
387	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
388	if (pVM->hwaccm.s.Event.fPending)
389	{
390	SVM_EVENT Event;
391
392	Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip));
393	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
394	Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
395	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
396
397	pVM->hwaccm.s.Event.fPending = false;
398	return VINF_SUCCESS;
399	}
400
401	/* When external interrupts are pending, we should exit the VM when IF is set. */
402	if ( !TRPMHasTrap(pVM)
403	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
404	{
405	if ( !(pCtx->eflags.u32 & X86_EFL_IF)
406	\|\| VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
407	{
408	if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
409	{
410	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
411	LogFlow(("Enable irq window exit!\n"));
412	else
413	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", pCtx->rip));
414
415	/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
416	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
417	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
418	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
419	}
420	}
421	else
422	{
423	uint8_t u8Interrupt;
424
425	rc = PDMGetInterrupt(pVM, &u8Interrupt);
426	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
427	if (VBOX_SUCCESS(rc))
428	{
429	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
430	AssertRC(rc);
431	}
432	else
433	{
434	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
435	Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)));
436	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
437	/* Just continue */
438	}
439	}
440	}
441
442	#ifdef VBOX_STRICT
443	if (TRPMHasTrap(pVM))
444	{
445	uint8_t u8Vector;
446	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
447	AssertRC(rc);
448	}
449	#endif
450
451	if ( pCtx->eflags.u32 & X86_EFL_IF
452	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
453	&& TRPMHasTrap(pVM)
454	)
455	{
456	uint8_t u8Vector;
457	int rc;
458	TRPMEVENT enmType;
459	SVM_EVENT Event;
460	RTGCUINT u32ErrorCode;
461
462	Event.au64[0] = 0;
463
464	/* If a new event is pending, then dispatch it now. */
465	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &u32ErrorCode, 0);
466	AssertRC(rc);
467	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
468	Assert(enmType != TRPM_SOFTWARE_INT);
469
470	/* Clear the pending trap. */
471	rc = TRPMResetTrap(pVM);
472	AssertRC(rc);
473
474	Event.n.u8Vector = u8Vector;
475	Event.n.u1Valid = 1;
476	Event.n.u32ErrorCode = u32ErrorCode;
477
478	if (enmType == TRPM_TRAP)
479	{
480	switch (u8Vector) {
481	case 8:
482	case 10:
483	case 11:
484	case 12:
485	case 13:
486	case 14:
487	case 17:
488	/* Valid error codes. */
489	Event.n.u1ErrorCodeValid = 1;
490	break;
491	default:
492	break;
493	}
494	if (u8Vector == X86_XCPT_NMI)
495	Event.n.u3Type = SVM_EVENT_NMI;
496	else
497	Event.n.u3Type = SVM_EVENT_EXCEPTION;
498	}
499	else
500	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
501
502	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
503	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
504	} /* if (interrupts can be dispatched) */
505
506	return VINF_SUCCESS;
507	}
508
509	/**
510	* Save the host state
511	*
512	* @returns VBox status code.
513	* @param pVM The VM to operate on.
514	*/
515	HWACCMR0DECL(int) SVMR0SaveHostState(PVM pVM)
516	{
517	/* Nothing to do here. */
518	return VINF_SUCCESS;
519	}
520
521	/**
522	* Loads the guest state
523	*
524	* NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
525	*
526	* @returns VBox status code.
527	* @param pVM The VM to operate on.
528	* @param pCtx Guest context
529	*/
530	HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
531	{
532	RTGCUINTPTR val;
533	SVM_VMCB *pVMCB;
534
535	if (pVM == NULL)
536	return VERR_INVALID_PARAMETER;
537
538	/* Setup AMD SVM. */
539	Assert(pVM->hwaccm.s.svm.fSupported);
540
541	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
542	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
543
544	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
545	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
546	{
547	SVM_WRITE_SELREG(CS, cs);
548	SVM_WRITE_SELREG(SS, ss);
549	SVM_WRITE_SELREG(DS, ds);
550	SVM_WRITE_SELREG(ES, es);
551	SVM_WRITE_SELREG(FS, fs);
552	SVM_WRITE_SELREG(GS, gs);
553	}
554
555	/* Guest CPU context: LDTR. */
556	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
557	{
558	SVM_WRITE_SELREG(LDTR, ldtr);
559	}
560
561	/* Guest CPU context: TR. */
562	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
563	{
564	SVM_WRITE_SELREG(TR, tr);
565	}
566
567	/* Guest CPU context: GDTR. */
568	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
569	{
570	pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
571	pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
572	}
573
574	/* Guest CPU context: IDTR. */
575	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
576	{
577	pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
578	pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
579	}
580
581	/*
582	* Sysenter MSRs (unconditional)
583	*/
584	pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
585	pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
586	pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
587
588	/* Control registers */
589	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
590	{
591	val = pCtx->cr0;
592	if (!CPUMIsGuestFPUStateActive(pVM))
593	{
594	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
595	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
596	}
597	else
598	{
599	/** @todo check if we support the old style mess correctly. */
600	if (!(val & X86_CR0_NE))
601	{
602	Log(("Forcing X86_CR0_NE!!!\n"));
603
604	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
605	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
606	{
607	pVMCB->ctrl.u32InterceptException \|= RT_BIT(16);
608	pVM->hwaccm.s.fFPUOldStyleOverride = true;
609	}
610	}
611	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
612	}
613	/* Always enable caching. */
614	val &= ~(X86_CR0_CD\|X86_CR0_NW);
615
616	/* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
617	/* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
618	if (!pVM->hwaccm.s.fNestedPaging)
619	{
620	val \|= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
621	val \|= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
622	}
623	pVMCB->guest.u64CR0 = val;
624	}
625	/* CR2 as well */
626	pVMCB->guest.u64CR2 = pCtx->cr2;
627
628	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
629	{
630	/* Save our shadow CR3 register. */
631	if (pVM->hwaccm.s.fNestedPaging)
632	{
633	pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVM, PGMGetHostMode(pVM));
634	Assert(pVMCB->ctrl.u64NestedPagingCR3);
635	pVMCB->guest.u64CR3 = pCtx->cr3;
636	}
637	else
638	{
639	pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
640	Assert(pVMCB->guest.u64CR3);
641	}
642	}
643
644	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
645	{
646	val = pCtx->cr4;
647	if (!pVM->hwaccm.s.fNestedPaging)
648	{
649	switch(pVM->hwaccm.s.enmShadowMode)
650	{
651	case PGMMODE_REAL:
652	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
653	AssertFailed();
654	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
655
656	case PGMMODE_32_BIT: /* 32-bit paging. */
657	break;
658
659	case PGMMODE_PAE: /* PAE paging. */
660	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
661	/** @todo use normal 32 bits paging */
662	val \|= X86_CR4_PAE;
663	break;
664
665	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
666	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
667	#ifdef VBOX_ENABLE_64_BITS_GUESTS
668	break;
669	#else
670	AssertFailed();
671	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
672	#endif
673
674	default: /* shut up gcc */
675	AssertFailed();
676	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
677	}
678	}
679	pVMCB->guest.u64CR4 = val;
680	}
681
682	/* Debug registers. */
683	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
684	{
685	/** @todo DR0-6 */
686	val = pCtx->dr7;
687	val &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
688	val \|= 0x400; /* must be one */
689	#ifdef VBOX_STRICT
690	val = 0x400;
691	#endif
692	pVMCB->guest.u64DR7 = val;
693
694	pVMCB->guest.u64DR6 = pCtx->dr6;
695	}
696
697	/* EIP, ESP and EFLAGS */
698	pVMCB->guest.u64RIP = pCtx->rip;
699	pVMCB->guest.u64RSP = pCtx->rsp;
700	pVMCB->guest.u64RFlags = pCtx->eflags.u32;
701
702	/* Set CPL */
703	pVMCB->guest.u8CPL = pCtx->csHid.Attr.n.u2Dpl;
704
705	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
706	pVMCB->guest.u64RAX = pCtx->rax;
707
708	/* vmrun will fail without MSR_K6_EFER_SVME. */
709	pVMCB->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
710
711	/* 64 bits guest mode? */
712	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
713	{
714	#if !defined(VBOX_WITH_64_BITS_GUESTS) \|\| HC_ARCH_BITS != 64
715	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
716	#else
717	pVM->hwaccm.s.svm.pfnVMRun = SVMVMRun64;
718	#endif
719	/* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
720	pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
721	pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
722	}
723	else
724	{
725	/* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
726	pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
727
728	pVM->hwaccm.s.svm.pfnVMRun = SVMVMRun;
729	}
730
731	/** TSC offset. */
732	if (TMCpuTickCanUseRealTSC(pVM, &pVMCB->ctrl.u64TSCOffset))
733	{
734	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
735	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
736	}
737	else
738	{
739	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
740	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
741	}
742
743	/* Sync the various msrs for 64 bits mode. */
744	pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
745	pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
746	pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
747	pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
748	pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
749
750	#ifdef DEBUG
751	/* Intercept X86_XCPT_DB if stepping is enabled */
752	if (DBGFIsStepping(pVM))
753	pVMCB->ctrl.u32InterceptException \|= RT_BIT(1);
754	else
755	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(1);
756	#endif
757
758	/* Done. */
759	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
760
761	return VINF_SUCCESS;
762	}
763
764
765	/**
766	* Runs guest code in an SVM VM.
767	*
768	* @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
769	*
770	* @returns VBox status code.
771	* @param pVM The VM to operate on.
772	* @param pCtx Guest context
773	*/
774	HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
775	{
776	int rc = VINF_SUCCESS;
777	uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
778	SVM_VMCB *pVMCB;
779	bool fGuestStateSynced = false;
780	unsigned cResume = 0;
781	uint8_t u8LastVTPR;
782	PHWACCM_CPUINFO pCpu = 0;
783	#ifdef VBOX_STRICT
784	RTCPUID idCpuCheck;
785	#endif
786
787	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
788
789	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
790	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
791
792	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
793	*/
794	ResumeExecution:
795	/* Safety precaution; looping for too long here can have a very bad effect on the host */
796	if (++cResume > HWACCM_MAX_RESUME_LOOPS)
797	{
798	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
799	rc = VINF_EM_RAW_INTERRUPT;
800	goto end;
801	}
802
803	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
804	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
805	{
806	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
807	if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
808	{
809	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
810	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
811	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
812	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
813	*/
814	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
815	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
816	pVMCB->ctrl.u64IntShadow = 0;
817	}
818	}
819	else
820	{
821	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
822	pVMCB->ctrl.u64IntShadow = 0;
823	}
824
825	/* Check for pending actions that force us to go back to ring 3. */
826	#ifdef DEBUG
827	/* Intercept X86_XCPT_DB if stepping is enabled */
828	if (!DBGFIsStepping(pVM))
829	#endif
830	{
831	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
832	{
833	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
834	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
835	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
836	rc = VINF_EM_RAW_TO_R3;
837	goto end;
838	}
839	}
840
841	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
842	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
843	{
844	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
845	rc = VINF_EM_PENDING_REQUEST;
846	goto end;
847	}
848
849	/* When external interrupts are pending, we should exit the VM when IF is set. */
850	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
851	rc = SVMR0CheckPendingInterrupt(pVM, pVMCB, pCtx);
852	if (VBOX_FAILURE(rc))
853	{
854	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
855	goto end;
856	}
857
858	/* TPR caching using CR8 is only available in 64 bits mode */
859	/* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
860	/* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! */
861	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
862	{
863	/* TPR caching in CR8 */
864	int rc = PDMApicGetTPR(pVM, &u8LastVTPR);
865	AssertRC(rc);
866	pVMCB->ctrl.IntCtrl.n.u8VTPR = u8LastVTPR;
867	}
868
869	/* All done! Let's start VM execution. */
870	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
871
872	/* Enable nested paging if necessary (disabled each time after #VMEXIT). */
873	pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
874
875	#ifdef LOG_ENABLED
876	pCpu = HWACCMR0GetCurrentCpu();
877	if ( pVM->hwaccm.s.svm.idLastCpu != pCpu->idCpu
878	\|\| pVM->hwaccm.s.svm.cTLBFlushes != pCpu->cTLBFlushes)
879	{
880	if (pVM->hwaccm.s.svm.idLastCpu != pCpu->idCpu)
881	Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVM->hwaccm.s.svm.idLastCpu, pCpu->idCpu));
882	else
883	Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVM->hwaccm.s.svm.cTLBFlushes, pCpu->cTLBFlushes));
884	}
885	if (pCpu->fFlushTLB)
886	Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
887	#endif
888
889	/*
890	* NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
891	* (until the actual world switch)
892	*/
893
894	#ifdef VBOX_STRICT
895	idCpuCheck = RTMpCpuId();
896	#endif
897
898	/* Load the guest state; must be here as it sets up the shadow cr0 for lazy fpu syncing! */
899	rc = SVMR0LoadGuestState(pVM, pCtx);
900	if (rc != VINF_SUCCESS)
901	{
902	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
903	goto end;
904	}
905	fGuestStateSynced = true;
906
907	pCpu = HWACCMR0GetCurrentCpu();
908	/* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
909	/* Note that this can happen both for start and resume due to long jumps back to ring 3. */
910	if ( pVM->hwaccm.s.svm.idLastCpu != pCpu->idCpu
911	/* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
912	\|\| pVM->hwaccm.s.svm.cTLBFlushes != pCpu->cTLBFlushes)
913	{
914	/* Force a TLB flush on VM entry. */
915	pVM->hwaccm.s.svm.fForceTLBFlush = true;
916	}
917	else
918	Assert(!pCpu->fFlushTLB);
919
920	pVM->hwaccm.s.svm.idLastCpu = pCpu->idCpu;
921
922	/* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
923	if ( pVM->hwaccm.s.svm.fForceTLBFlush
924	&& !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
925	{
926	if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.svm.u32MaxASID
927	\|\| pCpu->fFlushTLB)
928	{
929	pCpu->fFlushTLB = false;
930	pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
931	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
932	pCpu->cTLBFlushes++;
933	}
934	else
935	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushASID);
936
937	pVM->hwaccm.s.svm.cTLBFlushes = pCpu->cTLBFlushes;
938	}
939	else
940	{
941	Assert(!pCpu->fFlushTLB \|\| pVM->hwaccm.s.svm.fAlwaysFlushTLB);
942
943	/* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
944	if (!pCpu->uCurrentASID)
945	pCpu->uCurrentASID = 1;
946
947	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVM->hwaccm.s.svm.fForceTLBFlush;
948	}
949	AssertMsg(pVM->hwaccm.s.svm.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVM->hwaccm.s.svm.cTLBFlushes, pCpu->cTLBFlushes));
950	AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.svm.u32MaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
951	pVMCB->ctrl.TLBCtrl.n.u32ASID = pCpu->uCurrentASID;
952
953	#ifdef VBOX_WITH_STATISTICS
954	if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
955	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBWorldSwitch);
956	else
957	STAM_COUNTER_INC(&pVM->hwaccm.s.StatNoFlushTLBWorldSwitch);
958	#endif
959
960	/* In case we execute a goto ResumeExecution later on. */
961	pVM->hwaccm.s.svm.fResumeVM = true;
962	pVM->hwaccm.s.svm.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
963
964	Assert(sizeof(pVM->hwaccm.s.svm.pVMCBPhys) == 8);
965	Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
966	\| SVM_CTRL2_INTERCEPT_VMMCALL
967	\| SVM_CTRL2_INTERCEPT_VMLOAD
968	\| SVM_CTRL2_INTERCEPT_VMSAVE
969	\| SVM_CTRL2_INTERCEPT_STGI
970	\| SVM_CTRL2_INTERCEPT_CLGI
971	\| SVM_CTRL2_INTERCEPT_SKINIT
972	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
973	\| SVM_CTRL2_INTERCEPT_WBINVD
974	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
975	));
976	Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
977	Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
978	Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
979	Assert(pVMCB->ctrl.u64LBRVirt == 0);
980
981	#ifdef VBOX_STRICT
982	Assert(idCpuCheck == RTMpCpuId());
983	#endif
984	pVM->hwaccm.s.svm.pfnVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);
985	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
986
987	/**
988	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
989	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
990	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
991	*/
992
993	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
994
995	/* Reason for the VM exit */
996	exitCode = pVMCB->ctrl.u64ExitCode;
997
998	if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
999	{
1000	HWACCMDumpRegs(pVM, pCtx);
1001	#ifdef DEBUG
1002	Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
1003	Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
1004	Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
1005	Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
1006	Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
1007	Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
1008	Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
1009	Log(("ctrl.u64IOPMPhysAddr %VX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
1010	Log(("ctrl.u64MSRPMPhysAddr %VX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
1011	Log(("ctrl.u64TSCOffset %VX64\n", pVMCB->ctrl.u64TSCOffset));
1012
1013	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
1014	Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
1015	Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
1016	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
1017
1018	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
1019	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
1020	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
1021	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
1022	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
1023	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
1024	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
1025	Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
1026	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
1027	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
1028
1029	Log(("ctrl.u64IntShadow %VX64\n", pVMCB->ctrl.u64IntShadow));
1030	Log(("ctrl.u64ExitCode %VX64\n", pVMCB->ctrl.u64ExitCode));
1031	Log(("ctrl.u64ExitInfo1 %VX64\n", pVMCB->ctrl.u64ExitInfo1));
1032	Log(("ctrl.u64ExitInfo2 %VX64\n", pVMCB->ctrl.u64ExitInfo2));
1033	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
1034	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
1035	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
1036	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
1037	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
1038	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
1039	Log(("ctrl.NestedPaging %VX64\n", pVMCB->ctrl.NestedPaging.au64));
1040	Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
1041	Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
1042	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
1043	Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
1044	Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
1045	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
1046
1047	Log(("ctrl.u64NestedPagingCR3 %VX64\n", pVMCB->ctrl.u64NestedPagingCR3));
1048	Log(("ctrl.u64LBRVirt %VX64\n", pVMCB->ctrl.u64LBRVirt));
1049
1050	Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
1051	Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1052	Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1053	Log(("guest.CS.u64Base %VX64\n", pVMCB->guest.CS.u64Base));
1054	Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1055	Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1056	Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1057	Log(("guest.DS.u64Base %VX64\n", pVMCB->guest.DS.u64Base));
1058	Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1059	Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1060	Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1061	Log(("guest.ES.u64Base %VX64\n", pVMCB->guest.ES.u64Base));
1062	Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1063	Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1064	Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1065	Log(("guest.FS.u64Base %VX64\n", pVMCB->guest.FS.u64Base));
1066	Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1067	Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1068	Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1069	Log(("guest.GS.u64Base %VX64\n", pVMCB->guest.GS.u64Base));
1070
1071	Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1072	Log(("guest.GDTR.u64Base %VX64\n", pVMCB->guest.GDTR.u64Base));
1073
1074	Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1075	Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1076	Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1077	Log(("guest.LDTR.u64Base %VX64\n", pVMCB->guest.LDTR.u64Base));
1078
1079	Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1080	Log(("guest.IDTR.u64Base %VX64\n", pVMCB->guest.IDTR.u64Base));
1081
1082	Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1083	Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1084	Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1085	Log(("guest.TR.u64Base %VX64\n", pVMCB->guest.TR.u64Base));
1086
1087	Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1088	Log(("guest.u64CR0 %VX64\n", pVMCB->guest.u64CR0));
1089	Log(("guest.u64CR2 %VX64\n", pVMCB->guest.u64CR2));
1090	Log(("guest.u64CR3 %VX64\n", pVMCB->guest.u64CR3));
1091	Log(("guest.u64CR4 %VX64\n", pVMCB->guest.u64CR4));
1092	Log(("guest.u64DR6 %VX64\n", pVMCB->guest.u64DR6));
1093	Log(("guest.u64DR7 %VX64\n", pVMCB->guest.u64DR7));
1094
1095	Log(("guest.u64RIP %VX64\n", pVMCB->guest.u64RIP));
1096	Log(("guest.u64RSP %VX64\n", pVMCB->guest.u64RSP));
1097	Log(("guest.u64RAX %VX64\n", pVMCB->guest.u64RAX));
1098	Log(("guest.u64RFlags %VX64\n", pVMCB->guest.u64RFlags));
1099
1100	Log(("guest.u64SysEnterCS %VX64\n", pVMCB->guest.u64SysEnterCS));
1101	Log(("guest.u64SysEnterEIP %VX64\n", pVMCB->guest.u64SysEnterEIP));
1102	Log(("guest.u64SysEnterESP %VX64\n", pVMCB->guest.u64SysEnterESP));
1103
1104	Log(("guest.u64EFER %VX64\n", pVMCB->guest.u64EFER));
1105	Log(("guest.u64STAR %VX64\n", pVMCB->guest.u64STAR));
1106	Log(("guest.u64LSTAR %VX64\n", pVMCB->guest.u64LSTAR));
1107	Log(("guest.u64CSTAR %VX64\n", pVMCB->guest.u64CSTAR));
1108	Log(("guest.u64SFMASK %VX64\n", pVMCB->guest.u64SFMASK));
1109	Log(("guest.u64KernelGSBase %VX64\n", pVMCB->guest.u64KernelGSBase));
1110	Log(("guest.u64GPAT %VX64\n", pVMCB->guest.u64GPAT));
1111	Log(("guest.u64DBGCTL %VX64\n", pVMCB->guest.u64DBGCTL));
1112	Log(("guest.u64BR_FROM %VX64\n", pVMCB->guest.u64BR_FROM));
1113	Log(("guest.u64BR_TO %VX64\n", pVMCB->guest.u64BR_TO));
1114	Log(("guest.u64LASTEXCPFROM %VX64\n", pVMCB->guest.u64LASTEXCPFROM));
1115	Log(("guest.u64LASTEXCPTO %VX64\n", pVMCB->guest.u64LASTEXCPTO));
1116
1117	#endif
1118	rc = VERR_SVM_UNABLE_TO_START_VM;
1119	goto end;
1120	}
1121
1122	/* Let's first sync back eip, esp, and eflags. */
1123	pCtx->rip = pVMCB->guest.u64RIP;
1124	pCtx->rsp = pVMCB->guest.u64RSP;
1125	pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1126	/* eax is saved/restore across the vmrun instruction */
1127	pCtx->rax = pVMCB->guest.u64RAX;
1128
1129	pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
1130
1131	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1132	SVM_READ_SELREG(SS, ss);
1133	SVM_READ_SELREG(CS, cs);
1134	SVM_READ_SELREG(DS, ds);
1135	SVM_READ_SELREG(ES, es);
1136	SVM_READ_SELREG(FS, fs);
1137	SVM_READ_SELREG(GS, gs);
1138
1139	/* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1140	/* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1141	if ( pVM->hwaccm.s.fNestedPaging
1142	&& pCtx->cr3 != pVMCB->guest.u64CR3)
1143	{
1144	CPUMSetGuestCR3(pVM, pVMCB->guest.u64CR3);
1145	PGMUpdateCR3(pVM, pVMCB->guest.u64CR3);
1146	}
1147
1148	/** @note NOW IT'S SAFE FOR LOGGING! */
1149
1150	/* Take care of instruction fusing (sti, mov ss) (see 15.20.5 Interrupt Shadows) */
1151	if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1152	{
1153	Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->rip));
1154	EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1155	}
1156	else
1157	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1158
1159	Log2(("exitCode = %x\n", exitCode));
1160
1161	/* Sync back the debug registers. */
1162	/** @todo Implement debug registers correctly. */
1163	pCtx->dr6 = pVMCB->guest.u64DR6;
1164	pCtx->dr7 = pVMCB->guest.u64DR7;
1165
1166	/* Check if an injected event was interrupted prematurely. */
1167	pVM->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1168	if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1169	&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1170	{
1171	Log(("Pending inject %VX64 at %VGv exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitCode));
1172
1173	#ifdef LOG_ENABLED
1174	SVM_EVENT Event;
1175	Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
1176
1177	if ( exitCode == SVM_EXIT_EXCEPTION_E
1178	&& Event.n.u8Vector == 0xE)
1179	{
1180	Log(("Double fault!\n"));
1181	}
1182	#endif
1183
1184	pVM->hwaccm.s.Event.fPending = true;
1185	/* Error code present? (redundant) */
1186	if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1187	{
1188	pVM->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1189	}
1190	else
1191	pVM->hwaccm.s.Event.errCode = 0;
1192	}
1193	#ifdef VBOX_WITH_STATISTICS
1194	if (exitCode == SVM_EXIT_NPF)
1195	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitReasonNPF);
1196	else
1197	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1198	#endif
1199
1200	/* Deal with the reason of the VM-exit. */
1201	switch (exitCode)
1202	{
1203	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1204	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1205	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1206	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1207	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1208	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1209	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1210	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1211	{
1212	/* Pending trap. */
1213	SVM_EVENT Event;
1214	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1215
1216	Log2(("Hardware/software interrupt %d\n", vector));
1217	switch (vector)
1218	{
1219	#ifdef DEBUG
1220	case X86_XCPT_DB:
1221	rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), pVMCB->guest.u64DR6);
1222	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
1223	break;
1224	#endif
1225
1226	case X86_XCPT_NM:
1227	{
1228	uint32_t oldCR0;
1229
1230	Log(("#NM fault at %VGv\n", pCtx->rip));
1231
1232	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1233	oldCR0 = ASMGetCR0();
1234	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1235	rc = CPUMHandleLazyFPU(pVM);
1236	if (rc == VINF_SUCCESS)
1237	{
1238	Assert(CPUMIsGuestFPUStateActive(pVM));
1239
1240	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
1241	ASMSetCR0(oldCR0);
1242
1243	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1244
1245	/* Continue execution. */
1246	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1247	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1248
1249	goto ResumeExecution;
1250	}
1251
1252	Log(("Forward #NM fault to the guest\n"));
1253	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1254
1255	Event.au64[0] = 0;
1256	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1257	Event.n.u1Valid = 1;
1258	Event.n.u8Vector = X86_XCPT_NM;
1259
1260	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1261	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1262	goto ResumeExecution;
1263	}
1264
1265	case X86_XCPT_PF: /* Page fault */
1266	{
1267	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1268	RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1269
1270	#ifdef DEBUG
1271	if (pVM->hwaccm.s.fNestedPaging)
1272	{ /* A genuine pagefault.
1273	* Forward the trap to the guest by injecting the exception and resuming execution.
1274	*/
1275	Log(("Guest page fault at %VGv cr2=%VGv error code %x rsp=%VGv\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
1276	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1277
1278	/* Now we must update CR2. */
1279	pCtx->cr2 = uFaultAddress;
1280
1281	Event.au64[0] = 0;
1282	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1283	Event.n.u1Valid = 1;
1284	Event.n.u8Vector = X86_XCPT_PF;
1285	Event.n.u1ErrorCodeValid = 1;
1286	Event.n.u32ErrorCode = errCode;
1287
1288	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1289
1290	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1291	goto ResumeExecution;
1292	}
1293	#endif
1294	Assert(!pVM->hwaccm.s.fNestedPaging);
1295
1296	Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, uFaultAddress, errCode));
1297	/* Exit qualification contains the linear address of the page fault. */
1298	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1299	TRPMSetErrorCode(pVM, errCode);
1300	TRPMSetFaultAddress(pVM, uFaultAddress);
1301
1302	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1303	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1304	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
1305	if (rc == VINF_SUCCESS)
1306	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1307	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, uFaultAddress, errCode));
1308	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1309
1310	TRPMResetTrap(pVM);
1311
1312	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1313	goto ResumeExecution;
1314	}
1315	else
1316	if (rc == VINF_EM_RAW_GUEST_TRAP)
1317	{ /* A genuine pagefault.
1318	* Forward the trap to the guest by injecting the exception and resuming execution.
1319	*/
1320	Log2(("Forward page fault to the guest\n"));
1321	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1322	/* The error code might have been changed. */
1323	errCode = TRPMGetErrorCode(pVM);
1324
1325	TRPMResetTrap(pVM);
1326
1327	/* Now we must update CR2. */
1328	pCtx->cr2 = uFaultAddress;
1329
1330	Event.au64[0] = 0;
1331	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1332	Event.n.u1Valid = 1;
1333	Event.n.u8Vector = X86_XCPT_PF;
1334	Event.n.u1ErrorCodeValid = 1;
1335	Event.n.u32ErrorCode = errCode;
1336
1337	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1338
1339	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1340	goto ResumeExecution;
1341	}
1342	#ifdef VBOX_STRICT
1343	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1344	LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
1345	#endif
1346	/* Need to go back to the recompiler to emulate the instruction. */
1347	TRPMResetTrap(pVM);
1348	break;
1349	}
1350
1351	case X86_XCPT_MF: /* Floating point exception. */
1352	{
1353	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1354	if (!(pCtx->cr0 & X86_CR0_NE))
1355	{
1356	/* old style FPU error reporting needs some extra work. */
1357	/** @todo don't fall back to the recompiler, but do it manually. */
1358	rc = VINF_EM_RAW_EMULATE_INSTR;
1359	break;
1360	}
1361	Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1362
1363	Event.au64[0] = 0;
1364	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1365	Event.n.u1Valid = 1;
1366	Event.n.u8Vector = X86_XCPT_MF;
1367
1368	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1369
1370	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1371	goto ResumeExecution;
1372	}
1373
1374	#ifdef VBOX_STRICT
1375	case X86_XCPT_GP: /* General protection failure exception.*/
1376	case X86_XCPT_UD: /* Unknown opcode exception. */
1377	case X86_XCPT_DE: /* Debug exception. */
1378	case X86_XCPT_SS: /* Stack segment exception. */
1379	case X86_XCPT_NP: /* Segment not present exception. */
1380	{
1381	Event.au64[0] = 0;
1382	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1383	Event.n.u1Valid = 1;
1384	Event.n.u8Vector = vector;
1385
1386	switch(vector)
1387	{
1388	case X86_XCPT_GP:
1389	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1390	Event.n.u1ErrorCodeValid = 1;
1391	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1392	break;
1393	case X86_XCPT_DE:
1394	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1395	break;
1396	case X86_XCPT_UD:
1397	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1398	break;
1399	case X86_XCPT_SS:
1400	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1401	Event.n.u1ErrorCodeValid = 1;
1402	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1403	break;
1404	case X86_XCPT_NP:
1405	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1406	Event.n.u1ErrorCodeValid = 1;
1407	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1408	break;
1409	}
1410	Log(("Trap %x at %VGv esi=%x\n", vector, pCtx->rip, pCtx->esi));
1411	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1412
1413	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1414	goto ResumeExecution;
1415	}
1416	#endif
1417	default:
1418	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1419	rc = VERR_EM_INTERNAL_ERROR;
1420	break;
1421
1422	} /* switch (vector) */
1423	break;
1424	}
1425
1426	case SVM_EXIT_NPF:
1427	{
1428	/* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1429	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1430	RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1431
1432	Assert(pVM->hwaccm.s.fNestedPaging);
1433	Log(("Nested page fault at %VGv cr2=%VGp error code %x\n", pCtx->rip, uFaultAddress, errCode));
1434	/* Exit qualification contains the linear address of the page fault. */
1435	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1436	TRPMSetErrorCode(pVM, errCode);
1437	TRPMSetFaultAddress(pVM, uFaultAddress);
1438
1439	/* Handle the pagefault trap for the nested shadow table. */
1440	rc = PGMR0Trap0eHandlerNestedPaging(pVM, PGMGetHostMode(pVM), errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1441	Log2(("PGMR0Trap0eHandlerNestedPaging %VGv returned %Vrc\n", pCtx->rip, rc));
1442	if (rc == VINF_SUCCESS)
1443	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1444	Log2(("Shadow page fault at %VGv cr2=%VGp error code %x\n", pCtx->rip, uFaultAddress, errCode));
1445	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1446
1447	TRPMResetTrap(pVM);
1448
1449	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1450	goto ResumeExecution;
1451	}
1452
1453	#ifdef VBOX_STRICT
1454	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1455	LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
1456	#endif
1457	/* Need to go back to the recompiler to emulate the instruction. */
1458	TRPMResetTrap(pVM);
1459	break;
1460	}
1461
1462	case SVM_EXIT_VINTR:
1463	/* A virtual interrupt is about to be delivered, which means IF=1. */
1464	Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1465	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1466	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1467	goto ResumeExecution;
1468
1469	case SVM_EXIT_FERR_FREEZE:
1470	case SVM_EXIT_INTR:
1471	case SVM_EXIT_NMI:
1472	case SVM_EXIT_SMI:
1473	case SVM_EXIT_INIT:
1474	/* External interrupt; leave to allow it to be dispatched again. */
1475	rc = VINF_EM_RAW_INTERRUPT;
1476	break;
1477
1478	case SVM_EXIT_WBINVD:
1479	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1480	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1481	/* Skip instruction and continue directly. */
1482	pCtx->rip += 2; /** @note hardcoded opcode size! */
1483	/* Continue execution.*/
1484	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1485	goto ResumeExecution;
1486
1487	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1488	{
1489	Log2(("SVM: Cpuid at %VGv for %x\n", pCtx->rip, pCtx->eax));
1490	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1491	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1492	if (rc == VINF_SUCCESS)
1493	{
1494	/* Update EIP and continue execution. */
1495	pCtx->rip += 2; /** @note hardcoded opcode size! */
1496	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1497	goto ResumeExecution;
1498	}
1499	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1500	rc = VINF_EM_RAW_EMULATE_INSTR;
1501	break;
1502	}
1503
1504	case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1505	{
1506	Log2(("SVM: Rdtsc\n"));
1507	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1508	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1509	if (rc == VINF_SUCCESS)
1510	{
1511	/* Update EIP and continue execution. */
1512	pCtx->rip += 2; /** @note hardcoded opcode size! */
1513	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1514	goto ResumeExecution;
1515	}
1516	AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1517	rc = VINF_EM_RAW_EMULATE_INSTR;
1518	break;
1519	}
1520
1521	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1522	{
1523	Log2(("SVM: invlpg\n"));
1524	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1525
1526	Assert(!pVM->hwaccm.s.fNestedPaging);
1527
1528	/* Truly a pita. Why can't SVM give the same information as VT-x? */
1529	rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1530	if (rc == VINF_SUCCESS)
1531	{
1532	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageInvlpg);
1533	goto ResumeExecution; /* eip already updated */
1534	}
1535	break;
1536	}
1537
1538	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1539	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1540	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1541	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1542	{
1543	uint32_t cbSize;
1544
1545	Log2(("SVM: %VGv mov cr%d, \n", pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
1546	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1547	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1548
1549	switch (exitCode - SVM_EXIT_WRITE_CR0)
1550	{
1551	case 0:
1552	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1553	break;
1554	case 2:
1555	break;
1556	case 3:
1557	Assert(!pVM->hwaccm.s.fNestedPaging);
1558	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1559	break;
1560	case 4:
1561	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1562	break;
1563	case 8:
1564	break;
1565	default:
1566	AssertFailed();
1567	}
1568	/* Check if a sync operation is pending. */
1569	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1570	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1571	{
1572	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1573	AssertRC(rc);
1574
1575	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBCRxChange);
1576
1577	/* Must be set by PGMSyncCR3 */
1578	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PROTECTED \|\| pVM->hwaccm.s.svm.fForceTLBFlush);
1579	}
1580	if (rc == VINF_SUCCESS)
1581	{
1582	/* EIP has been updated already. */
1583
1584	/* Only resume if successful. */
1585	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1586	goto ResumeExecution;
1587	}
1588	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1589	break;
1590	}
1591
1592	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1593	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1594	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1595	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1596	{
1597	uint32_t cbSize;
1598
1599	Log2(("SVM: %VGv mov x, cr%d\n", pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
1600	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1601	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1602	if (rc == VINF_SUCCESS)
1603	{
1604	/* EIP has been updated already. */
1605
1606	/* Only resume if successful. */
1607	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1608	goto ResumeExecution;
1609	}
1610	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1611	break;
1612	}
1613
1614	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1615	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1616	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1617	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1618	{
1619	uint32_t cbSize;
1620
1621	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
1622	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1623	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1624	if (rc == VINF_SUCCESS)
1625	{
1626	/* EIP has been updated already. */
1627
1628	/* Only resume if successful. */
1629	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1630	goto ResumeExecution;
1631	}
1632	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1633	break;
1634	}
1635
1636	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1637	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1638	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1639	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1640	{
1641	uint32_t cbSize;
1642
1643	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
1644	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1645	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1646	if (rc == VINF_SUCCESS)
1647	{
1648	/* EIP has been updated already. */
1649
1650	/* Only resume if successful. */
1651	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1652	goto ResumeExecution;
1653	}
1654	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1655	break;
1656	}
1657
1658	/* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1659	case SVM_EXIT_IOIO: /* I/O instruction. */
1660	{
1661	SVM_IOIO_EXIT IoExitInfo;
1662	uint32_t uIOSize, uAndVal;
1663
1664	IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1665
1666	/** @todo could use a lookup table here */
1667	if (IoExitInfo.n.u1OP8)
1668	{
1669	uIOSize = 1;
1670	uAndVal = 0xff;
1671	}
1672	else
1673	if (IoExitInfo.n.u1OP16)
1674	{
1675	uIOSize = 2;
1676	uAndVal = 0xffff;
1677	}
1678	else
1679	if (IoExitInfo.n.u1OP32)
1680	{
1681	uIOSize = 4;
1682	uAndVal = 0xffffffff;
1683	}
1684	else
1685	{
1686	AssertFailed(); /* should be fatal. */
1687	rc = VINF_EM_RAW_EMULATE_INSTR;
1688	break;
1689	}
1690
1691	if (IoExitInfo.n.u1STR)
1692	{
1693	/* ins/outs */
1694	uint32_t prefix = 0;
1695	if (IoExitInfo.n.u1REP)
1696	prefix \|= PREFIX_REP;
1697
1698	if (IoExitInfo.n.u1Type == 0)
1699	{
1700	Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1701	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1702	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1703	}
1704	else
1705	{
1706	Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1707	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1708	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1709	}
1710	}
1711	else
1712	{
1713	/* normal in/out */
1714	Assert(!IoExitInfo.n.u1REP);
1715
1716	if (IoExitInfo.n.u1Type == 0)
1717	{
1718	Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1719	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1720	rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1721	}
1722	else
1723	{
1724	uint32_t u32Val = 0;
1725
1726	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1727	rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1728	if (IOM_SUCCESS(rc))
1729	{
1730	/* Write back to the EAX register. */
1731	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1732	Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1733	}
1734	}
1735	}
1736	/*
1737	* Handled the I/O return codes.
1738	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1739	*/
1740	if (IOM_SUCCESS(rc))
1741	{
1742	/* Update EIP and continue execution. */
1743	pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1744	if (RT_LIKELY(rc == VINF_SUCCESS))
1745	{
1746	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1747	goto ResumeExecution;
1748	}
1749	Log2(("EM status from IO at %VGv %x size %d: %Vrc\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
1750	break;
1751	}
1752
1753	#ifdef VBOX_STRICT
1754	if (rc == VINF_IOM_HC_IOPORT_READ)
1755	Assert(IoExitInfo.n.u1Type != 0);
1756	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1757	Assert(IoExitInfo.n.u1Type == 0);
1758	else
1759	AssertMsg(VBOX_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1760	#endif
1761	Log2(("Failed IO at %VGv %x size %d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1762	break;
1763	}
1764
1765	case SVM_EXIT_HLT:
1766	/** Check if external interrupts are pending; if so, don't switch back. */
1767	pCtx->rip++; /* skip hlt */
1768	if ( pCtx->eflags.Bits.u1IF
1769	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1770	goto ResumeExecution;
1771
1772	rc = VINF_EM_HALT;
1773	break;
1774
1775	case SVM_EXIT_RSM:
1776	case SVM_EXIT_INVLPGA:
1777	case SVM_EXIT_VMRUN:
1778	case SVM_EXIT_VMMCALL:
1779	case SVM_EXIT_VMLOAD:
1780	case SVM_EXIT_VMSAVE:
1781	case SVM_EXIT_STGI:
1782	case SVM_EXIT_CLGI:
1783	case SVM_EXIT_SKINIT:
1784	case SVM_EXIT_RDTSCP:
1785	{
1786	/* Unsupported instructions. */
1787	SVM_EVENT Event;
1788
1789	Event.au64[0] = 0;
1790	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1791	Event.n.u1Valid = 1;
1792	Event.n.u8Vector = X86_XCPT_UD;
1793
1794	Log(("Forced #UD trap at %VGv\n", pCtx->rip));
1795	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1796
1797	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1798	goto ResumeExecution;
1799	}
1800
1801	/* Emulate in ring 3. */
1802	case SVM_EXIT_MSR:
1803	{
1804	uint32_t cbSize;
1805
1806	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
1807	Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
1808	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1809	if (rc == VINF_SUCCESS)
1810	{
1811	/* EIP has been updated already. */
1812
1813	/* Only resume if successful. */
1814	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1815	goto ResumeExecution;
1816	}
1817	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Vrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
1818	break;
1819	}
1820
1821	case SVM_EXIT_MONITOR:
1822	case SVM_EXIT_RDPMC:
1823	case SVM_EXIT_PAUSE:
1824	case SVM_EXIT_MWAIT_UNCOND:
1825	case SVM_EXIT_MWAIT_ARMED:
1826	case SVM_EXIT_TASK_SWITCH: /* can change CR3; emulate */
1827	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1828	break;
1829
1830	case SVM_EXIT_SHUTDOWN:
1831	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1832	break;
1833
1834	case SVM_EXIT_IDTR_READ:
1835	case SVM_EXIT_GDTR_READ:
1836	case SVM_EXIT_LDTR_READ:
1837	case SVM_EXIT_TR_READ:
1838	case SVM_EXIT_IDTR_WRITE:
1839	case SVM_EXIT_GDTR_WRITE:
1840	case SVM_EXIT_LDTR_WRITE:
1841	case SVM_EXIT_TR_WRITE:
1842	case SVM_EXIT_CR0_SEL_WRITE:
1843	default:
1844	/* Unexpected exit codes. */
1845	rc = VERR_EM_INTERNAL_ERROR;
1846	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
1847	break;
1848	}
1849
1850	end:
1851	if (fGuestStateSynced)
1852	{
1853	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1854	SVM_READ_SELREG(LDTR, ldtr);
1855	SVM_READ_SELREG(TR, tr);
1856
1857	pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1858	pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1859
1860	pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1861	pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1862
1863	/*
1864	* System MSRs
1865	*/
1866	pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1867	pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1868	pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1869	}
1870
1871	/* Signal changes for the recompiler. */
1872	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
1873
1874	/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
1875	if (exitCode == SVM_EXIT_INTR)
1876	{
1877	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1878	/* On the next entry we'll only sync the host context. */
1879	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
1880	}
1881	else
1882	{
1883	/* On the next entry we'll sync everything. */
1884	/** @todo we can do better than this */
1885	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
1886	}
1887
1888	/* translate into a less severe return code */
1889	if (rc == VERR_EM_INTERPRETER)
1890	rc = VINF_EM_RAW_EMULATE_INSTR;
1891
1892	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1893	return rc;
1894	}
1895
1896	/**
1897	* Enters the AMD-V session
1898	*
1899	* @returns VBox status code.
1900	* @param pVM The VM to operate on.
1901	* @param pCpu CPU info struct
1902	*/
1903	HWACCMR0DECL(int) SVMR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
1904	{
1905	Assert(pVM->hwaccm.s.svm.fSupported);
1906
1907	LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVM->hwaccm.s.svm.idLastCpu, pCpu->uCurrentASID));
1908	pVM->hwaccm.s.svm.fResumeVM = false;
1909
1910	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
1911	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_LDTR;
1912
1913	return VINF_SUCCESS;
1914	}
1915
1916
1917	/**
1918	* Leaves the AMD-V session
1919	*
1920	* @returns VBox status code.
1921	* @param pVM The VM to operate on.
1922	*/
1923	HWACCMR0DECL(int) SVMR0Leave(PVM pVM)
1924	{
1925	Assert(pVM->hwaccm.s.svm.fSupported);
1926	return VINF_SUCCESS;
1927	}
1928
1929
1930	static int svmInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1931	{
1932	OP_PARAMVAL param1;
1933	RTGCPTR addr;
1934
1935	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1936	if(VBOX_FAILURE(rc))
1937	return VERR_EM_INTERPRETER;
1938
1939	switch(param1.type)
1940	{
1941	case PARMTYPE_IMMEDIATE:
1942	case PARMTYPE_ADDRESS:
1943	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1944	return VERR_EM_INTERPRETER;
1945	addr = param1.val.val64;
1946	break;
1947
1948	default:
1949	return VERR_EM_INTERPRETER;
1950	}
1951
1952	/** @todo is addr always a flat linear address or ds based
1953	* (in absence of segment override prefixes)????
1954	*/
1955	rc = PGMInvalidatePage(pVM, addr);
1956	if (VBOX_SUCCESS(rc))
1957	{
1958	/* Manually invalidate the page for the VM's TLB. */
1959	Log(("SVMInvlpgA %VGv ASID=%d\n", addr, uASID));
1960	SVMInvlpgA(addr, uASID);
1961	return VINF_SUCCESS;
1962	}
1963	Assert(rc == VERR_REM_FLUSHED_PAGES_OVERFLOW);
1964	return rc;
1965	}
1966
1967	/**
1968	* Interprets INVLPG
1969	*
1970	* @returns VBox status code.
1971	* @retval VINF_* Scheduling instructions.
1972	* @retval VERR_EM_INTERPRETER Something we can't cope with.
1973	* @retval VERR_* Fatal errors.
1974	*
1975	* @param pVM The VM handle.
1976	* @param pRegFrame The register frame.
1977	* @param ASID Tagged TLB id for the guest
1978	*
1979	* Updates the EIP if an instruction was executed successfully.
1980	*/
1981	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1982	{
1983	/*
1984	* Only allow 32 & 64 bits code.
1985	*/
1986	DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
1987	if (enmMode != CPUMODE_16BIT)
1988	{
1989	RTGCPTR pbCode;
1990	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
1991	if (VBOX_SUCCESS(rc))
1992	{
1993	uint32_t cbOp;
1994	DISCPUSTATE Cpu;
1995
1996	Cpu.mode = enmMode;
1997	rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
1998	Assert(VBOX_FAILURE(rc) \|\| Cpu.pCurInstr->opcode == OP_INVLPG);
1999	if (VBOX_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
2000	{
2001	Assert(cbOp == Cpu.opsize);
2002	rc = svmInterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
2003	if (VBOX_SUCCESS(rc))
2004	{
2005	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
2006	}
2007	return rc;
2008	}
2009	}
2010	}
2011	return VERR_EM_INTERPRETER;
2012	}
2013
2014
2015	/**
2016	* Invalidates a guest page
2017	*
2018	* @returns VBox status code.
2019	* @param pVM The VM to operate on.
2020	* @param GCVirt Page to invalidate
2021	*/
2022	HWACCMR0DECL(int) SVMR0InvalidatePage(PVM pVM, RTGCPTR GCVirt)
2023	{
2024	bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB \| pVM->hwaccm.s.svm.fForceTLBFlush;
2025
2026	/* Skip it if a TLB flush is already pending. */
2027	if (!fFlushPending)
2028	{
2029	SVM_VMCB *pVMCB;
2030
2031	Log2(("SVMR0InvalidatePage %VGv\n", GCVirt));
2032	AssertReturn(pVM, VERR_INVALID_PARAMETER);
2033	Assert(pVM->hwaccm.s.svm.fSupported);
2034
2035	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
2036	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2037
2038	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageManual);
2039	SVMInvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2040	}
2041	return VINF_SUCCESS;
2042	}
2043
2044
2045	/**
2046	* Invalidates a guest page by physical address
2047	*
2048	* NOTE: Assumes the current instruction references this physical page though a virtual address!!
2049	*
2050	* @returns VBox status code.
2051	* @param pVM The VM to operate on.
2052	* @param GCPhys Page to invalidate
2053	*/
2054	HWACCMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys)
2055	{
2056	bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB \| pVM->hwaccm.s.svm.fForceTLBFlush;
2057
2058	Assert(pVM->hwaccm.s.fNestedPaging);
2059
2060	/* Skip it if a TLB flush is already pending. */
2061	if (!fFlushPending)
2062	{
2063	CPUMCTX *pCtx;
2064	int rc;
2065	SVM_VMCB *pVMCB;
2066
2067	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
2068	AssertRCReturn(rc, rc);
2069
2070	Log2(("SVMR0InvalidatePhysPage %VGp\n", GCPhys));
2071	AssertReturn(pVM, VERR_INVALID_PARAMETER);
2072	Assert(pVM->hwaccm.s.svm.fSupported);
2073
2074	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
2075	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2076
2077	/*
2078	* Only allow 32 & 64 bits code.
2079	*/
2080	DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid);
2081	if (enmMode != CPUMODE_16BIT)
2082	{
2083	RTGCPTR pbCode;
2084	int rc = SELMValidateAndConvertCSAddr(pVM, pCtx->eflags, pCtx->ss, pCtx->cs, &pCtx->csHid, (RTGCPTR)pCtx->rip, &pbCode);
2085	if (VBOX_SUCCESS(rc))
2086	{
2087	uint32_t cbOp;
2088	DISCPUSTATE Cpu;
2089	OP_PARAMVAL param1;
2090	RTGCPTR addr;
2091
2092	Cpu.mode = enmMode;
2093	rc = EMInterpretDisasOneEx(pVM, pbCode, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);
2094	AssertRCReturn(rc, rc);
2095	Assert(cbOp == Cpu.opsize);
2096
2097	int rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param1, &param1, PARAM_SOURCE);
2098	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2099
2100	switch(param1.type)
2101	{
2102	case PARMTYPE_IMMEDIATE:
2103	case PARMTYPE_ADDRESS:
2104	AssertReturn((param1.flags & (PARAM_VAL32\|PARAM_VAL64)), VERR_EM_INTERPRETER);
2105
2106	addr = param1.val.val64;
2107	break;
2108
2109	default:
2110	AssertFailed();
2111	return VERR_EM_INTERPRETER;
2112	}
2113
2114	/* Manually invalidate the page for the VM's TLB. */
2115	Log(("SVMR0InvalidatePhysPage Phys=%VGp Virt=%VGv ASID=%d\n", GCPhys, addr, pVMCB->ctrl.TLBCtrl.n.u32ASID));
2116	SVMInvlpgA(addr, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2117	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPhysPageManual);
2118
2119	return VINF_SUCCESS;
2120	}
2121	}
2122	AssertFailed();
2123	return VERR_EM_INTERPRETER;
2124	}
2125	return VINF_SUCCESS;
2126	}

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 10645

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