HWSVMR0.cpp@ 2708

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1	/* $Id: HWSVMR0.cpp 2699 2007-05-17 15:18:06Z vboxsync $ */
2	/** @file
3	* HWACCM SVM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_svm.h>
32	#include <VBox/pgm.h>
33	#include <VBox/pdm.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <VBox/selm.h>
37	#include <VBox/iom.h>
38	#include <VBox/dis.h>
39	#include <VBox/dbgf.h>
40	#include <VBox/disopcode.h>
41	#include <iprt/param.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm.h>
44	#include "HWSVMR0.h"
45
46	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
47
48	/**
49	* Sets up and activates SVM
50	*
51	* @returns VBox status code.
52	* @param pVM The VM to operate on.
53	*/
54	HWACCMR0DECL(int) SVMR0Setup(PVM pVM)
55	{
56	int rc = VINF_SUCCESS;
57	SVM_VMCB *pVMCB;
58
59	if (pVM == NULL)
60	return VERR_INVALID_PARAMETER;
61
62	/* Setup AMD SVM. */
63	Assert(pVM->hwaccm.s.svm.fSupported);
64
65	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
66	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
67
68	/* Program the control fields. Most of them never have to be changed again. */
69	/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
70	/** @note CR0 & CR4 can be safely read when guest and shadow copies are identical. */
71	pVMCB->ctrl.u16InterceptRdCRx = BIT(0) \| BIT(3) \| BIT(4) \| BIT(8);
72
73	/*
74	* CR0/3/4 writes must be intercepted for obvious reasons.
75	*/
76	pVMCB->ctrl.u16InterceptWrCRx = BIT(0) \| BIT(3) \| BIT(4) \| BIT(8);
77
78	/* Intercept all DRx reads and writes. */
79	pVMCB->ctrl.u16InterceptRdDRx = BIT(0) \| BIT(1) \| BIT(2) \| BIT(3) \| BIT(4) \| BIT(5) \| BIT(6) \| BIT(7);
80	pVMCB->ctrl.u16InterceptWrDRx = BIT(0) \| BIT(1) \| BIT(2) \| BIT(3) \| BIT(4) \| BIT(5) \| BIT(6) \| BIT(7);
81
82	/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
83	* All breakpoints are automatically cleared when the VM exits.
84	*/
85
86	/** @todo nested paging */
87	/* Intercept #NM only; #PF is not relevant due to nested paging (we get a seperate exit code (SVM_EXIT_NPF) for
88	* pagefaults that need our attention).
89	*/
90	pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
91
92	pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
93	\| SVM_CTRL1_INTERCEPT_VINTR
94	\| SVM_CTRL1_INTERCEPT_NMI
95	\| SVM_CTRL1_INTERCEPT_SMI
96	\| SVM_CTRL1_INTERCEPT_INIT
97	\| SVM_CTRL1_INTERCEPT_CR0 /** @todo redundant? */
98	\| SVM_CTRL1_INTERCEPT_RDPMC
99	\| SVM_CTRL1_INTERCEPT_CPUID
100	\| SVM_CTRL1_INTERCEPT_RSM
101	\| SVM_CTRL1_INTERCEPT_HLT
102	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
103	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
104	\| SVM_CTRL1_INTERCEPT_INVLPG
105	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
106	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
107	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
108	;
109	pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
110	\| SVM_CTRL2_INTERCEPT_VMMCALL
111	\| SVM_CTRL2_INTERCEPT_VMLOAD
112	\| SVM_CTRL2_INTERCEPT_VMSAVE
113	\| SVM_CTRL2_INTERCEPT_STGI
114	\| SVM_CTRL2_INTERCEPT_CLGI
115	\| SVM_CTRL2_INTERCEPT_SKINIT
116	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
117	;
118	Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
119	Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
120	Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
121
122	/* Virtualize masking of INTR interrupts. */
123	pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
124
125	/* Set IO and MSR bitmap addresses. */
126	pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
127	pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
128
129	/* Enable nested paging. */
130	/** @todo how to detect support for this?? */
131	pVMCB->ctrl.u64NestedPaging = 0; /** @todo SVM_NESTED_PAGING_ENABLE; */
132
133	/* No LBR virtualization. */
134	pVMCB->ctrl.u64LBRVirt = 0;
135
136	return rc;
137	}
138
139
140	/**
141	* Injects an event (trap or external interrupt)
142	*
143	* @param pVM The VM to operate on.
144	* @param pVMCB SVM control block
145	* @param pCtx CPU Context
146	* @param pIntInfo SVM interrupt info
147	*/
148	inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx, SVM_EVENT* pEvent)
149	{
150	#ifdef VBOX_STRICT
151	if (pEvent->n.u8Vector == 0xE)
152	Log(("SVM: Inject int %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
153	else
154	if (pEvent->n.u8Vector < 0x20)
155	Log(("SVM: Inject int %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode));
156	else
157	{
158	Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->eip));
159	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
160	Assert(pCtx->eflags.u32 & X86_EFL_IF);
161	}
162	#endif
163
164	/* Set event injection state. */
165	pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
166	}
167
168
169	/**
170	* Checks for pending guest interrupts and injects them
171	*
172	* @returns VBox status code.
173	* @param pVM The VM to operate on.
174	* @param pVMCB SVM control block
175	* @param pCtx CPU Context
176	*/
177	static int SVMR0CheckPendingInterrupt(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx)
178	{
179	int rc;
180
181	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
182	if (pVM->hwaccm.s.Event.fPending)
183	{
184	SVM_EVENT Event;
185
186	Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
187	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
188	Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
189	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
190
191	pVM->hwaccm.s.Event.fPending = false;
192	return VINF_SUCCESS;
193	}
194
195	/* When external interrupts are pending, we should exit the VM when IF is set. */
196	if ( !TRPMHasTrap(pVM)
197	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
198	{
199	if (!(pCtx->eflags.u32 & X86_EFL_IF))
200	{
201	Log2(("Enable irq window exit!\n"));
202	/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
203	//// pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
204	//// AssertRC(rc);
205	}
206	else
207	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
208	{
209	uint8_t u8Interrupt;
210
211	rc = PDMGetInterrupt(pVM, &u8Interrupt);
212	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
213	if (VBOX_SUCCESS(rc))
214	{
215	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
216	AssertRC(rc);
217	}
218	else
219	{
220	/* can't happen... */
221	AssertFailed();
222	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
223	return VINF_EM_RAW_INTERRUPT_PENDING;
224	}
225	}
226	else
227	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
228	}
229
230	#ifdef VBOX_STRICT
231	if (TRPMHasTrap(pVM))
232	{
233	uint8_t u8Vector;
234	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
235	AssertRC(rc);
236	}
237	#endif
238
239	if ( pCtx->eflags.u32 & X86_EFL_IF
240	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
241	&& TRPMHasTrap(pVM)
242	)
243	{
244	uint8_t u8Vector;
245	int rc;
246	TRPMEVENT enmType;
247	SVM_EVENT Event;
248	uint32_t u32ErrorCode;
249
250	Event.au64[0] = 0;
251
252	/* If a new event is pending, then dispatch it now. */
253	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &u32ErrorCode, 0);
254	AssertRC(rc);
255	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
256	Assert(enmType != TRPM_SOFTWARE_INT);
257
258	/* Clear the pending trap. */
259	rc = TRPMResetTrap(pVM);
260	AssertRC(rc);
261
262	Event.n.u8Vector = u8Vector;
263	Event.n.u1Valid = 1;
264	Event.n.u32ErrorCode = u32ErrorCode;
265
266	if (enmType == TRPM_TRAP)
267	{
268	switch (u8Vector) {
269	case 8:
270	case 10:
271	case 11:
272	case 12:
273	case 13:
274	case 14:
275	case 17:
276	/* Valid error codes. */
277	Event.n.u1ErrorCodeValid = 1;
278	break;
279	default:
280	break;
281	}
282	if (u8Vector == X86_XCPT_NMI)
283	Event.n.u3Type = SVM_EVENT_NMI;
284	else
285	Event.n.u3Type = SVM_EVENT_EXCEPTION;
286	}
287	else
288	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
289
290	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
291	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
292	} /* if (interrupts can be dispatched) */
293
294	return VINF_SUCCESS;
295	}
296
297
298	/**
299	* Loads the guest state
300	*
301	* @returns VBox status code.
302	* @param pVM The VM to operate on.
303	* @param pCtx Guest context
304	*/
305	HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
306	{
307	RTGCUINTPTR val;
308	SVM_VMCB *pVMCB;
309
310	if (pVM == NULL)
311	return VERR_INVALID_PARAMETER;
312
313	/* Setup AMD SVM. */
314	Assert(pVM->hwaccm.s.svm.fSupported);
315
316	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
317	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
318
319	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
320	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
321	{
322	SVM_WRITE_SELREG(CS, cs);
323	SVM_WRITE_SELREG(SS, ss);
324	SVM_WRITE_SELREG(DS, ds);
325	SVM_WRITE_SELREG(ES, es);
326	SVM_WRITE_SELREG(FS, fs);
327	SVM_WRITE_SELREG(GS, gs);
328	}
329
330	/* Guest CPU context: LDTR. */
331	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
332	{
333	SVM_WRITE_SELREG(LDTR, ldtr);
334	}
335
336	/* Guest CPU context: TR. */
337	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
338	{
339	SVM_WRITE_SELREG(TR, tr);
340	}
341
342	/* Guest CPU context: GDTR. */
343	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
344	{
345	pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
346	pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
347	}
348
349	/* Guest CPU context: IDTR. */
350	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
351	{
352	pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
353	pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
354	}
355
356	/*
357	* Sysenter MSRs
358	*/
359	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
360	{
361	pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
362	pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
363	pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
364	}
365
366	/* Control registers */
367	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
368	{
369	val = pCtx->cr0;
370	if (CPUMIsGuestFPUStateActive(pVM) == false)
371	{
372	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
373	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
374	}
375	else
376	{
377	Assert(pVM->hwaccm.s.svm.fResumeVM == true);
378	/** @todo check if we support the old style mess correctly. */
379	if (!(val & X86_CR0_NE))
380	{
381	Log(("Forcing X86_CR0_NE!!!\n"));
382
383	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
384	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
385	{
386	pVMCB->ctrl.u32InterceptException \|= BIT(16);
387	pVM->hwaccm.s.fFPUOldStyleOverride = true;
388	}
389	}
390	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
391	}
392	if (!(val & X86_CR0_CD))
393	val &= ~X86_CR0_NW; /* Illegal when cache is turned on. */
394
395	val \|= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
396	pVMCB->guest.u64CR0 = val;
397	}
398	/* CR2 as well */
399	pVMCB->guest.u64CR2 = pCtx->cr2;
400
401	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
402	{
403	/* Save our shadow CR3 register. */
404	pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
405	}
406
407	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
408	{
409	val = pCtx->cr4;
410	switch(pVM->hwaccm.s.enmShadowMode)
411	{
412	case PGMMODE_REAL:
413	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
414	AssertFailed();
415	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
416
417	case PGMMODE_32_BIT: /* 32-bit paging. */
418	break;
419
420	case PGMMODE_PAE: /* PAE paging. */
421	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
422	/** @todo use normal 32 bits paging */
423	val \|= X86_CR4_PAE;
424	break;
425
426	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
427	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
428	AssertFailed();
429	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
430
431	default: /* shut up gcc */
432	AssertFailed();
433	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
434	}
435	pVMCB->guest.u64CR4 = val;
436	}
437
438	/* Debug registers. */
439	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
440	{
441	/** @todo DR0-6 */
442	val = pCtx->dr7;
443	val &= ~(BIT(11) \| BIT(12) \| BIT(14) \| BIT(15)); /* must be zero */
444	val \|= 0x400; /* must be one */
445	#ifdef VBOX_STRICT
446	val = 0x400;
447	#endif
448	pVMCB->guest.u64DR7 = val;
449
450	pVMCB->guest.u64DR6 = pCtx->dr6;
451	}
452
453	/* EIP, ESP and EFLAGS */
454	pVMCB->guest.u64RIP = pCtx->eip;
455	pVMCB->guest.u64RSP = pCtx->esp;
456	pVMCB->guest.u64RFlags = pCtx->eflags.u32;
457
458	/* Set CPL */
459	pVMCB->guest.u8CPL = pCtx->ssHid.Attr.n.u2Dpl;
460
461	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
462	pVMCB->guest.u64RAX = pCtx->eax;
463
464	/* vmrun will fail otherwise. */
465	pVMCB->guest.u64EFER = MSR_K6_EFER_SVME;
466
467	/** @note We can do more complex things with tagged TLBs. */
468	pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
469
470	/** TSC offset. */
471	/** @todo use host tsc if safe, other intercept rdtsc */
472	pVMCB->ctrl.u64TSCOffset = TMCpuTickGetOffset(pVM);
473
474	/** @todo 64 bits stuff (?):
475	* - STAR
476	* - LSTAR
477	* - CSTAR
478	* - SFMASK
479	* - KernelGSBase
480	*/
481
482	#ifdef DEBUG
483	/* Intercept X86_XCPT_DB if stepping is enabled */
484	if (DBGFIsStepping(pVM))
485	pVMCB->ctrl.u32InterceptException \|= BIT(1);
486	else
487	pVMCB->ctrl.u32InterceptException &= ~BIT(1);
488	#endif
489
490	/* Done. */
491	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
492
493	return VINF_SUCCESS;
494	}
495
496
497	/**
498	* Runs guest code in an SVM VM.
499	*
500	* @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
501	*
502	* @returns VBox status code.
503	* @param pVM The VM to operate on.
504	* @param pCtx Guest context
505	*/
506	HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
507	{
508	int rc = VINF_SUCCESS;
509	uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
510	SVM_VMCB *pVMCB;
511	bool fForceTLBFlush = false;
512	bool fGuestStateSynced = false;
513
514	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
515
516	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
517	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
518
519	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
520	*/
521	ResumeExecution:
522
523	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
524	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
525	{
526	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
527	if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
528	{
529	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
530	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
531	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
532	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
533	*/
534	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
535	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
536	pVMCB->ctrl.u64IntShadow = 0;
537	}
538	}
539	else
540	{
541	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
542	pVMCB->ctrl.u64IntShadow = 0;
543	}
544
545	/* Check for pending actions that force us to go back to ring 3. */
546	#ifdef DEBUG
547	/* Intercept X86_XCPT_DB if stepping is enabled */
548	if (!DBGFIsStepping(pVM))
549	#endif
550	{
551	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
552	{
553	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
554	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
555	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
556	rc = VINF_EM_RAW_TO_R3;
557	goto end;
558	}
559	}
560
561	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
562	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
563	{
564	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
565	rc = VINF_EM_PENDING_REQUEST;
566	goto end;
567	}
568
569	/* When external interrupts are pending, we should exit the VM when IF is set. */
570	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
571	rc = SVMR0CheckPendingInterrupt(pVM, pVMCB, pCtx);
572	if (VBOX_FAILURE(rc))
573	{
574	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
575	goto end;
576	}
577
578	/* Load the guest state */
579	rc = SVMR0LoadGuestState(pVM, pCtx);
580	if (rc != VINF_SUCCESS)
581	{
582	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
583	goto end;
584	}
585	fGuestStateSynced = true;
586
587	/* All done! Let's start VM execution. */
588	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
589
590	/** Erratum #170 -> must force a TLB flush */
591	/** @todo supposed to be fixed in future by AMD */
592	fForceTLBFlush = true;
593
594	if ( pVM->hwaccm.s.svm.fResumeVM == false
595	\|\| fForceTLBFlush)
596	{
597	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1;
598	}
599	else
600	{
601	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 0;
602	}
603	/* In case we execute a goto ResumeExecution later on. */
604	pVM->hwaccm.s.svm.fResumeVM = true;
605	fForceTLBFlush = false;
606
607	Assert(sizeof(pVM->hwaccm.s.svm.pVMCBPhys) == 8);
608	Assert(pVMCB->ctrl.u32InterceptCtrl1 == ( SVM_CTRL1_INTERCEPT_INTR
609	\| SVM_CTRL1_INTERCEPT_VINTR
610	\| SVM_CTRL1_INTERCEPT_NMI
611	\| SVM_CTRL1_INTERCEPT_SMI
612	\| SVM_CTRL1_INTERCEPT_INIT
613	\| SVM_CTRL1_INTERCEPT_CR0 /** @todo redundant? */
614	\| SVM_CTRL1_INTERCEPT_RDPMC
615	\| SVM_CTRL1_INTERCEPT_CPUID
616	\| SVM_CTRL1_INTERCEPT_RSM
617	\| SVM_CTRL1_INTERCEPT_HLT
618	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
619	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
620	\| SVM_CTRL1_INTERCEPT_INVLPG
621	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
622	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
623	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE /* Legacy FPU FERR handling. */
624	));
625	Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
626	\| SVM_CTRL2_INTERCEPT_VMMCALL
627	\| SVM_CTRL2_INTERCEPT_VMLOAD
628	\| SVM_CTRL2_INTERCEPT_VMSAVE
629	\| SVM_CTRL2_INTERCEPT_STGI
630	\| SVM_CTRL2_INTERCEPT_CLGI
631	\| SVM_CTRL2_INTERCEPT_SKINIT
632	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
633	));
634	Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
635	Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
636	Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
637	Assert(pVMCB->ctrl.u64NestedPaging == 0);
638	Assert(pVMCB->ctrl.u64LBRVirt == 0);
639
640	SVMVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);
641	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
642
643	/**
644	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
645	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
646	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
647	*/
648
649	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
650
651	/* Reason for the VM exit */
652	exitCode = pVMCB->ctrl.u64ExitCode;
653
654	if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
655	{
656	HWACCMDumpRegs(pCtx);
657	#ifdef DEBUG
658	Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
659	Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
660	Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
661	Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
662	Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
663	Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
664	Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
665	Log(("ctrl.u64IOPMPhysAddr %VX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
666	Log(("ctrl.u64MSRPMPhysAddr %VX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
667	Log(("ctrl.u64TSCOffset %VX64\n", pVMCB->ctrl.u64TSCOffset));
668
669	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
670	Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
671	Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
672	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
673
674	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
675	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
676	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
677	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
678	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
679	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
680	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
681	Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
682	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
683	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
684
685	Log(("ctrl.u64IntShadow %VX64\n", pVMCB->ctrl.u64IntShadow));
686	Log(("ctrl.u64ExitCode %VX64\n", pVMCB->ctrl.u64ExitCode));
687	Log(("ctrl.u64ExitInfo1 %VX64\n", pVMCB->ctrl.u64ExitInfo1));
688	Log(("ctrl.u64ExitInfo2 %VX64\n", pVMCB->ctrl.u64ExitInfo2));
689	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
690	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
691	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
692	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
693	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
694	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
695	Log(("ctrl.u64NestedPaging %VX64\n", pVMCB->ctrl.u64NestedPaging));
696	Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
697	Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
698	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
699	Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
700	Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
701	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
702
703	Log(("ctrl.u64HostCR3 %VX64\n", pVMCB->ctrl.u64HostCR3));
704	Log(("ctrl.u64LBRVirt %VX64\n", pVMCB->ctrl.u64LBRVirt));
705
706	Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
707	Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
708	Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
709	Log(("guest.CS.u64Base %VX64\n", pVMCB->guest.CS.u64Base));
710	Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
711	Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
712	Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
713	Log(("guest.DS.u64Base %VX64\n", pVMCB->guest.DS.u64Base));
714	Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
715	Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
716	Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
717	Log(("guest.ES.u64Base %VX64\n", pVMCB->guest.ES.u64Base));
718	Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
719	Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
720	Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
721	Log(("guest.FS.u64Base %VX64\n", pVMCB->guest.FS.u64Base));
722	Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
723	Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
724	Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
725	Log(("guest.GS.u64Base %VX64\n", pVMCB->guest.GS.u64Base));
726
727	Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
728	Log(("guest.GDTR.u64Base %VX64\n", pVMCB->guest.GDTR.u64Base));
729
730	Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
731	Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
732	Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
733	Log(("guest.LDTR.u64Base %VX64\n", pVMCB->guest.LDTR.u64Base));
734
735	Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
736	Log(("guest.IDTR.u64Base %VX64\n", pVMCB->guest.IDTR.u64Base));
737
738	Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
739	Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
740	Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
741	Log(("guest.TR.u64Base %VX64\n", pVMCB->guest.TR.u64Base));
742
743	Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
744	Log(("guest.u64CR0 %VX64\n", pVMCB->guest.u64CR0));
745	Log(("guest.u64CR2 %VX64\n", pVMCB->guest.u64CR2));
746	Log(("guest.u64CR3 %VX64\n", pVMCB->guest.u64CR3));
747	Log(("guest.u64CR4 %VX64\n", pVMCB->guest.u64CR4));
748	Log(("guest.u64DR6 %VX64\n", pVMCB->guest.u64DR6));
749	Log(("guest.u64DR7 %VX64\n", pVMCB->guest.u64DR7));
750
751	Log(("guest.u64RIP %VX64\n", pVMCB->guest.u64RIP));
752	Log(("guest.u64RSP %VX64\n", pVMCB->guest.u64RSP));
753	Log(("guest.u64RAX %VX64\n", pVMCB->guest.u64RAX));
754	Log(("guest.u64RFlags %VX64\n", pVMCB->guest.u64RFlags));
755
756	Log(("guest.u64SysEnterCS %VX64\n", pVMCB->guest.u64SysEnterCS));
757	Log(("guest.u64SysEnterEIP %VX64\n", pVMCB->guest.u64SysEnterEIP));
758	Log(("guest.u64SysEnterESP %VX64\n", pVMCB->guest.u64SysEnterESP));
759
760	Log(("guest.u64EFER %VX64\n", pVMCB->guest.u64EFER));
761	Log(("guest.u64STAR %VX64\n", pVMCB->guest.u64STAR));
762	Log(("guest.u64LSTAR %VX64\n", pVMCB->guest.u64LSTAR));
763	Log(("guest.u64CSTAR %VX64\n", pVMCB->guest.u64CSTAR));
764	Log(("guest.u64SFMASK %VX64\n", pVMCB->guest.u64SFMASK));
765	Log(("guest.u64KernelGSBase %VX64\n", pVMCB->guest.u64KernelGSBase));
766	Log(("guest.u64GPAT %VX64\n", pVMCB->guest.u64GPAT));
767	Log(("guest.u64DBGCTL %VX64\n", pVMCB->guest.u64DBGCTL));
768	Log(("guest.u64BR_FROM %VX64\n", pVMCB->guest.u64BR_FROM));
769	Log(("guest.u64BR_TO %VX64\n", pVMCB->guest.u64BR_TO));
770	Log(("guest.u64LASTEXCPFROM %VX64\n", pVMCB->guest.u64LASTEXCPFROM));
771	Log(("guest.u64LASTEXCPTO %VX64\n", pVMCB->guest.u64LASTEXCPTO));
772
773	#endif
774	rc = VERR_SVM_UNABLE_TO_START_VM;
775	goto end;
776	}
777
778	/* Let's first sync back eip, esp, and eflags. */
779	pCtx->eip = pVMCB->guest.u64RIP;
780	pCtx->esp = pVMCB->guest.u64RSP;
781	pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
782	/* eax is saved/restore across the vmrun instruction */
783	pCtx->eax = pVMCB->guest.u64RAX;
784
785	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
786	SVM_READ_SELREG(SS, ss);
787	SVM_READ_SELREG(CS, cs);
788	SVM_READ_SELREG(DS, ds);
789	SVM_READ_SELREG(ES, es);
790	SVM_READ_SELREG(FS, fs);
791	SVM_READ_SELREG(GS, gs);
792
793	/** @note no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
794
795	/** @note NOW IT'S SAFE FOR LOGGING! */
796
797	/* Take care of instruction fusing (sti, mov ss) */
798	if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
799	{
800	Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->eip));
801	EMSetInhibitInterruptsPC(pVM, pCtx->eip);
802	}
803	else
804	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
805
806	Log2(("exitCode = %x\n", exitCode));
807
808	/* Check if an injected event was interrupted prematurely. */
809	pVM->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
810	if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
811	&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
812	{
813	Log(("Pending inject %VX64 at %08x exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitCode));
814	pVM->hwaccm.s.Event.fPending = true;
815	/* Error code present? (redundant) */
816	if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
817	{
818	pVM->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
819	}
820	else
821	pVM->hwaccm.s.Event.errCode = 0;
822	}
823	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
824
825	/* Deal with the reason of the VM-exit. */
826	switch (exitCode)
827	{
828	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
829	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
830	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
831	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
832	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
833	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
834	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
835	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
836	{
837	/* Pending trap. */
838	SVM_EVENT Event;
839	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
840
841	Log2(("Hardware/software interrupt %d\n", vector));
842	switch (vector)
843	{
844	#ifdef DEBUG
845	case X86_XCPT_DB:
846	rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), pVMCB->guest.u64DR6);
847	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
848	break;
849	#endif
850
851	case X86_XCPT_NM:
852	{
853	uint32_t oldCR0;
854
855	Log(("#NM fault at %VGv\n", pCtx->eip));
856
857	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
858	oldCR0 = ASMGetCR0();
859	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
860	rc = CPUMHandleLazyFPU(pVM);
861	if (rc == VINF_SUCCESS)
862	{
863	Assert(CPUMIsGuestFPUStateActive(pVM));
864
865	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
866	ASMSetCR0(oldCR0);
867
868	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
869
870	/* Continue execution. */
871	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
872	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
873
874	goto ResumeExecution;
875	}
876
877	Log(("Forward #NM fault to the guest\n"));
878	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
879
880	Event.au64[0] = 0;
881	Event.n.u3Type = SVM_EVENT_EXCEPTION;
882	Event.n.u1Valid = 1;
883	Event.n.u8Vector = X86_XCPT_NM;
884
885	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
886	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
887	goto ResumeExecution;
888	}
889
890	case X86_XCPT_PF: /* Page fault */
891	{
892	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
893	RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
894
895	Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
896	/* Exit qualification contains the linear address of the page fault. */
897	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
898	TRPMSetErrorCode(pVM, errCode);
899	TRPMSetFaultAddress(pVM, uFaultAddress);
900
901	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
902	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
903	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
904	if (rc == VINF_SUCCESS)
905	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
906	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
907	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
908
909	TRPMResetTrap(pVM);
910
911	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
912	goto ResumeExecution;
913	}
914	else
915	if (rc == VINF_EM_RAW_GUEST_TRAP)
916	{ /* A genuine pagefault.
917	* Forward the trap to the guest by injecting the exception and resuming execution.
918	*/
919	Log2(("Forward page fault to the guest\n"));
920	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
921	/* The error code might have been changed. */
922	errCode = TRPMGetErrorCode(pVM);
923
924	TRPMResetTrap(pVM);
925
926	/* Now we must update CR2. */
927	pCtx->cr2 = uFaultAddress;
928
929	Event.au64[0] = 0;
930	Event.n.u3Type = SVM_EVENT_EXCEPTION;
931	Event.n.u1Valid = 1;
932	Event.n.u8Vector = X86_XCPT_PF;
933	Event.n.u1ErrorCodeValid = 1;
934	Event.n.u32ErrorCode = errCode;
935
936	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
937
938	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
939	goto ResumeExecution;
940	}
941	#ifdef VBOX_STRICT
942	if (rc != VINF_EM_RAW_EMULATE_INSTR)
943	Log(("PGMTrap0eHandler failed with %d\n", rc));
944	#endif
945	/* Need to go back to the recompiler to emulate the instruction. */
946	TRPMResetTrap(pVM);
947	break;
948	}
949
950	case X86_XCPT_MF: /* Floating point exception. */
951	{
952	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
953	if (!(pCtx->cr0 & X86_CR0_NE))
954	{
955	/* old style FPU error reporting needs some extra work. */
956	/** @todo don't fall back to the recompiler, but do it manually. */
957	rc = VINF_EM_RAW_EMULATE_INSTR;
958	break;
959	}
960	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
961
962	Event.au64[0] = 0;
963	Event.n.u3Type = SVM_EVENT_EXCEPTION;
964	Event.n.u1Valid = 1;
965	Event.n.u8Vector = X86_XCPT_MF;
966
967	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
968
969	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
970	goto ResumeExecution;
971	}
972
973	#ifdef VBOX_STRICT
974	case X86_XCPT_GP: /* General protection failure exception.*/
975	case X86_XCPT_UD: /* Unknown opcode exception. */
976	case X86_XCPT_DE: /* Debug exception. */
977	case X86_XCPT_SS: /* Stack segment exception. */
978	case X86_XCPT_NP: /* Segment not present exception. */
979	{
980	Event.au64[0] = 0;
981	Event.n.u3Type = SVM_EVENT_EXCEPTION;
982	Event.n.u1Valid = 1;
983	Event.n.u8Vector = vector;
984
985	switch(vector)
986	{
987	case X86_XCPT_GP:
988	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
989	Event.n.u1ErrorCodeValid = 1;
990	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
991	break;
992	case X86_XCPT_DE:
993	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
994	break;
995	case X86_XCPT_UD:
996	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
997	break;
998	case X86_XCPT_SS:
999	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1000	Event.n.u1ErrorCodeValid = 1;
1001	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1002	break;
1003	case X86_XCPT_NP:
1004	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1005	Event.n.u1ErrorCodeValid = 1;
1006	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1007	break;
1008	}
1009	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1010	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1011
1012	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1013	goto ResumeExecution;
1014	}
1015	#endif
1016	default:
1017	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1018	rc = VERR_EM_INTERNAL_ERROR;
1019	break;
1020
1021	} /* switch (vector) */
1022	break;
1023	}
1024
1025	case SVM_EXIT_FERR_FREEZE:
1026	case SVM_EXIT_INTR:
1027	case SVM_EXIT_NMI:
1028	case SVM_EXIT_SMI:
1029	case SVM_EXIT_INIT:
1030	case SVM_EXIT_VINTR:
1031	/* External interrupt; leave to allow it to be dispatched again. */
1032	rc = VINF_EM_RAW_INTERRUPT;
1033	break;
1034
1035	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1036	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1037	/* Skip instruction and continue directly. */
1038	pCtx->eip += 2; /** @note hardcoded opcode size! */
1039	/* Continue execution.*/
1040	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1041	goto ResumeExecution;
1042
1043	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1044	{
1045	Log2(("SVM: Cpuid %x\n", pCtx->eax));
1046	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1047	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1048	if (rc == VINF_SUCCESS)
1049	{
1050	/* Update EIP and continue execution. */
1051	pCtx->eip += 2; /** @note hardcoded opcode size! */
1052	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1053	goto ResumeExecution;
1054	}
1055	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1056	rc = VINF_EM_RAW_EMULATE_INSTR;
1057	break;
1058	}
1059
1060	case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1061	{
1062	Log2(("SVM: Rdtsc\n"));
1063	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1064	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1065	if (rc == VINF_SUCCESS)
1066	{
1067	/* Update EIP and continue execution. */
1068	pCtx->eip += 2; /** @note hardcoded opcode size! */
1069	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1070	goto ResumeExecution;
1071	}
1072	AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1073	rc = VINF_EM_RAW_EMULATE_INSTR;
1074	break;
1075	}
1076
1077	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1078	{
1079	Log2(("SVM: invlpg\n"));
1080	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1081
1082	/* Truly a pita. Why can't SVM give the same information as VMX? */
1083	rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1084	break;
1085	}
1086
1087	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1088	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1089	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1090	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1091	{
1092	uint32_t cbSize;
1093
1094	Log2(("SVM: %VGv mov cr%d, \n", pCtx->eip, exitCode - SVM_EXIT_WRITE_CR0));
1095	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1096	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1097
1098	switch (exitCode - SVM_EXIT_WRITE_CR0)
1099	{
1100	case 0:
1101	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1102	break;
1103	case 2:
1104	break;
1105	case 3:
1106	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1107	break;
1108	case 4:
1109	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1110	break;
1111	default:
1112	AssertFailed();
1113	}
1114	/* Check if a sync operation is pending. */
1115	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1116	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1117	{
1118	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1119	AssertRC(rc);
1120
1121	/** @note Force a TLB flush. SVM requires us to do it manually. */
1122	fForceTLBFlush = true;
1123	}
1124	if (rc == VINF_SUCCESS)
1125	{
1126	/* EIP has been updated already. */
1127
1128	/* Only resume if successful. */
1129	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1130	goto ResumeExecution;
1131	}
1132	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1133	if (rc == VERR_EM_INTERPRETER)
1134	rc = VINF_EM_RAW_EMULATE_INSTR;
1135	break;
1136	}
1137
1138	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1139	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1140	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1141	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1142	{
1143	uint32_t cbSize;
1144
1145	Log2(("SVM: %VGv mov x, cr%d\n", pCtx->eip, exitCode - SVM_EXIT_READ_CR0));
1146	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1147	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1148	if (rc == VINF_SUCCESS)
1149	{
1150	/* EIP has been updated already. */
1151
1152	/* Only resume if successful. */
1153	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1154	goto ResumeExecution;
1155	}
1156	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1157	if (rc == VERR_EM_INTERPRETER)
1158	rc = VINF_EM_RAW_EMULATE_INSTR;
1159	break;
1160	}
1161
1162	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1163	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1164	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1165	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1166	{
1167	uint32_t cbSize;
1168
1169	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_WRITE_DR0));
1170	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1171	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1172	if (rc == VINF_SUCCESS)
1173	{
1174	/* EIP has been updated already. */
1175
1176	/* Only resume if successful. */
1177	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1178	goto ResumeExecution;
1179	}
1180	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1181	if (rc == VERR_EM_INTERPRETER)
1182	rc = VINF_EM_RAW_EMULATE_INSTR;
1183	break;
1184	}
1185
1186	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1187	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1188	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1189	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1190	{
1191	uint32_t cbSize;
1192
1193	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_READ_DR0));
1194	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1195	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1196	if (rc == VINF_SUCCESS)
1197	{
1198	/* EIP has been updated already. */
1199
1200	/* Only resume if successful. */
1201	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1202	goto ResumeExecution;
1203	}
1204	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1205	if (rc == VERR_EM_INTERPRETER)
1206	rc = VINF_EM_RAW_EMULATE_INSTR;
1207	break;
1208	}
1209
1210	/* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1211	case SVM_EXIT_IOIO: /* I/O instruction. */
1212	{
1213	SVM_IOIO_EXIT IoExitInfo;
1214	uint32_t uIOSize, uAndVal;
1215
1216	IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1217
1218	/** @todo could use a lookup table here */
1219	if (IoExitInfo.n.u1OP8)
1220	{
1221	uIOSize = 1;
1222	uAndVal = 0xff;
1223	}
1224	else
1225	if (IoExitInfo.n.u1OP16)
1226	{
1227	uIOSize = 2;
1228	uAndVal = 0xffff;
1229	}
1230	else
1231	if (IoExitInfo.n.u1OP32)
1232	{
1233	uIOSize = 4;
1234	uAndVal = 0xffffffff;
1235	}
1236	else
1237	{
1238	AssertFailed(); /* should be fatal. */
1239	rc = VINF_EM_RAW_EMULATE_INSTR;
1240	break;
1241	}
1242
1243	if (IoExitInfo.n.u1STR)
1244	{
1245	/* ins/outs */
1246	uint32_t prefix = 0;
1247	if (IoExitInfo.n.u1REP)
1248	prefix \|= PREFIX_REP;
1249
1250	if (IoExitInfo.n.u1Type == 0)
1251	{
1252	Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1253	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1254	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1255	}
1256	else
1257	{
1258	Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1259	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1260	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1261	}
1262	}
1263	else
1264	{
1265	/* normal in/out */
1266	Assert(!IoExitInfo.n.u1REP);
1267
1268	if (IoExitInfo.n.u1Type == 0)
1269	{
1270	Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1271	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1272	rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1273	}
1274	else
1275	{
1276	uint32_t u32Val = 0;
1277
1278	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1279	rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1280	if ( rc == VINF_SUCCESS
1281	\|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
1282	{
1283	/* Write back to the EAX register. */
1284	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1285	Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1286	}
1287	}
1288	}
1289	if ( rc == VINF_SUCCESS
1290	\|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
1291	{
1292	/* Update EIP and continue execution. */
1293	pCtx->eip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1294	if (RT_LIKELY(rc == VINF_SUCCESS))
1295	{
1296	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1297	goto ResumeExecution;
1298	}
1299	Log2(("EM status from IO at %VGv %x size %d: %Vrc\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize, rc));
1300	break;
1301	}
1302	#ifdef VBOX_STRICT
1303	if (rc == VINF_IOM_HC_IOPORT_READ)
1304	Assert(IoExitInfo.n.u1Type != 0);
1305	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1306	Assert(IoExitInfo.n.u1Type == 0);
1307	else
1308	AssertMsg(VBOX_FAILURE(rc) \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED \|\| rc == VINF_EM_RESCHEDULE_REM, ("%Vrc\n", rc));
1309	#endif
1310	Log2(("Failed IO at %VGv %x size %d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1311	break;
1312	}
1313
1314	case SVM_EXIT_HLT:
1315	/** Check if external interrupts are pending; if so, don't switch back. */
1316	if (VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1317	{
1318	pCtx->eip++; /* skip hlt */
1319	goto ResumeExecution;
1320	}
1321
1322	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1323	break;
1324
1325	case SVM_EXIT_RDPMC:
1326	case SVM_EXIT_RSM:
1327	case SVM_EXIT_INVLPGA:
1328	case SVM_EXIT_VMRUN:
1329	case SVM_EXIT_VMMCALL:
1330	case SVM_EXIT_VMLOAD:
1331	case SVM_EXIT_VMSAVE:
1332	case SVM_EXIT_STGI:
1333	case SVM_EXIT_CLGI:
1334	case SVM_EXIT_SKINIT:
1335	case SVM_EXIT_RDTSCP:
1336	{
1337	/* Unsupported instructions. */
1338	SVM_EVENT Event;
1339
1340	Event.au64[0] = 0;
1341	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1342	Event.n.u1Valid = 1;
1343	Event.n.u8Vector = X86_XCPT_UD;
1344
1345	Log(("Forced #UD trap at %VGv\n", pCtx->eip));
1346	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1347
1348	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1349	goto ResumeExecution;
1350	}
1351
1352	/* Emulate RDMSR & WRMSR in ring 3. */
1353	case SVM_EXIT_MSR:
1354	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1355	break;
1356
1357	case SVM_EXIT_NPF:
1358	AssertFailed(); /* unexpected */
1359	break;
1360
1361	case SVM_EXIT_SHUTDOWN:
1362	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1363	break;
1364
1365	case SVM_EXIT_PAUSE:
1366	case SVM_EXIT_IDTR_READ:
1367	case SVM_EXIT_GDTR_READ:
1368	case SVM_EXIT_LDTR_READ:
1369	case SVM_EXIT_TR_READ:
1370	case SVM_EXIT_IDTR_WRITE:
1371	case SVM_EXIT_GDTR_WRITE:
1372	case SVM_EXIT_LDTR_WRITE:
1373	case SVM_EXIT_TR_WRITE:
1374	case SVM_EXIT_CR0_SEL_WRITE:
1375	default:
1376	/* Unexpected exit codes. */
1377	rc = VERR_EM_INTERNAL_ERROR;
1378	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
1379	break;
1380	}
1381
1382	end:
1383	if (fGuestStateSynced)
1384	{
1385	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1386	SVM_READ_SELREG(LDTR, ldtr);
1387	SVM_READ_SELREG(TR, tr);
1388
1389	pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1390	pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1391
1392	pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1393	pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1394
1395	/*
1396	* System MSRs
1397	*/
1398	pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1399	pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1400	pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1401	}
1402
1403	/* Signal changes for the recompiler. */
1404	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
1405
1406	/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
1407	if (exitCode == SVM_EXIT_INTR)
1408	{
1409	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1410	/* On the next entry we'll only sync the host context. */
1411	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
1412	}
1413	else
1414	{
1415	/* On the next entry we'll sync everything. */
1416	/** @todo we can do better than this */
1417	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
1418	}
1419
1420	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1421	return rc;
1422	}
1423
1424	/**
1425	* Enable SVM
1426	*
1427	* @returns VBox status code.
1428	* @param pVM The VM to operate on.
1429	*/
1430	HWACCMR0DECL(int) SVMR0Enable(PVM pVM)
1431	{
1432	uint64_t val;
1433
1434	Assert(pVM->hwaccm.s.svm.fSupported);
1435
1436	/* We must turn on SVM and setup the host state physical address, as those MSRs are per-cpu/core. */
1437
1438	/* Turn on SVM in the EFER MSR. */
1439	val = ASMRdMsr(MSR_K6_EFER);
1440	if (!(val & MSR_K6_EFER_SVME))
1441	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
1442
1443	/* Write the physical page address where the CPU will store the host state while executing the VM. */
1444	ASMWrMsr(MSR_K8_VM_HSAVE_PA, pVM->hwaccm.s.svm.pHStatePhys);
1445
1446	/* Force a TLB flush on VM entry. */
1447	pVM->hwaccm.s.svm.fResumeVM = false;
1448
1449	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
1450	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_LDTR;
1451
1452	return VINF_SUCCESS;
1453	}
1454
1455
1456	/**
1457	* Disable SVM
1458	*
1459	* @returns VBox status code.
1460	* @param pVM The VM to operate on.
1461	*/
1462	HWACCMR0DECL(int) SVMR0Disable(PVM pVM)
1463	{
1464	/** @todo hopefully this is not very expensive. */
1465
1466	/* Turn off SVM in the EFER MSR. */
1467	uint64_t val = ASMRdMsr(MSR_K6_EFER);
1468	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
1469
1470	/* Invalidate host state physical address. */
1471	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
1472
1473	Assert(pVM->hwaccm.s.svm.fSupported);
1474	return VINF_SUCCESS;
1475	}
1476
1477
1478	static int svmInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1479	{
1480	OP_PARAMVAL param1;
1481	RTGCPTR addr;
1482
1483	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1484	if(VBOX_FAILURE(rc))
1485	return VERR_EM_INTERPRETER;
1486
1487	switch(param1.type)
1488	{
1489	case PARMTYPE_IMMEDIATE:
1490	case PARMTYPE_ADDRESS:
1491	if(!(param1.flags & PARAM_VAL32))
1492	return VERR_EM_INTERPRETER;
1493	addr = (RTGCPTR)param1.val.val32;
1494	break;
1495
1496	default:
1497	return VERR_EM_INTERPRETER;
1498	}
1499
1500	/** @todo is addr always a flat linear address or ds based
1501	* (in absence of segment override prefixes)????
1502	*/
1503	rc = PGMInvalidatePage(pVM, addr);
1504	if (VBOX_SUCCESS(rc))
1505	{
1506	/* Manually invalidate the page for the VM's TLB. */
1507	SVMInvlpgA(addr, uASID);
1508	return VINF_SUCCESS;
1509	}
1510	/** @todo r=bird: we shouldn't ignore returns codes like this... I'm 99% sure the error is fatal. */
1511	return VERR_EM_INTERPRETER;
1512	}
1513
1514	/**
1515	* Interprets INVLPG
1516	*
1517	* @returns VBox status code.
1518	* @retval VINF_* Scheduling instructions.
1519	* @retval VERR_EM_INTERPRETER Something we can't cope with.
1520	* @retval VERR_* Fatal errors.
1521	*
1522	* @param pVM The VM handle.
1523	* @param pRegFrame The register frame.
1524	* @param ASID Tagged TLB id for the guest
1525	*
1526	* Updates the EIP if an instruction was executed successfully.
1527	*/
1528	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1529	{
1530	/*
1531	* Only allow 32-bit code.
1532	*/
1533	if (SELMIsSelector32Bit(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid))
1534	{
1535	RTGCPTR pbCode;
1536	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pbCode);
1537	if (VBOX_SUCCESS(rc))
1538	{
1539	uint32_t cbOp;
1540	DISCPUSTATE Cpu;
1541
1542	Cpu.mode = CPUMODE_32BIT;
1543	rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
1544	Assert(VBOX_FAILURE(rc) \|\| Cpu.pCurInstr->opcode == OP_INVLPG);
1545	if (VBOX_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
1546	{
1547	Assert(cbOp == Cpu.opsize);
1548	rc = svmInterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
1549	if (VBOX_SUCCESS(rc))
1550	{
1551	pRegFrame->eip += cbOp; /* Move on to the next instruction. */
1552	}
1553	return rc;
1554	}
1555	}
1556	}
1557	return VERR_EM_INTERPRETER;
1558	}
1559

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 2708

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