HWSVMR0.cpp@ 41741

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1	/* $Id: HWSVMR0.cpp 41739 2012-06-15 01:31:29Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2012 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_HWACCM
22	#include <VBox/vmm/hwaccm.h>
23	#include <VBox/vmm/pgm.h>
24	#include <VBox/vmm/selm.h>
25	#include <VBox/vmm/iom.h>
26	#include <VBox/vmm/dbgf.h>
27	#include <VBox/vmm/dbgftrace.h>
28	#include <VBox/vmm/tm.h>
29	#include <VBox/vmm/pdmapi.h>
30	#include "HWACCMInternal.h"
31	#include <VBox/vmm/vm.h>
32	#include <VBox/vmm/hwacc_svm.h>
33	#include <VBox/err.h>
34	#include <VBox/log.h>
35	#include <VBox/dis.h>
36	#include <VBox/disopcode.h>
37	#include <iprt/param.h>
38	#include <iprt/assert.h>
39	#include <iprt/asm.h>
40	#include <iprt/asm-amd64-x86.h>
41	#include <iprt/cpuset.h>
42	#include <iprt/mp.h>
43	#include <iprt/time.h>
44	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
45	# include <iprt/thread.h>
46	#endif
47	#include <iprt/x86.h>
48	#include "HWSVMR0.h"
49
50	#include "dtrace/VBoxVMM.h"
51
52
53	/*******************************************************************************
54	* Internal Functions *
55	*******************************************************************************/
56	static int hmR0SvmInterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID);
57	static int hmR0SvmEmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
58	static void hmR0SvmSetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite);
59
60
61	/*******************************************************************************
62	* Global Variables *
63	*******************************************************************************/
64
65	/**
66	* Sets up and activates AMD-V on the current CPU.
67	*
68	* @returns VBox status code.
69	* @param pCpu Pointer to the CPU info struct.
70	* @param pVM Pointer to the VM (can be NULL after a resume!).
71	* @param pvCpuPage Pointer to the global CPU page.
72	* @param HCPhysCpuPage Physical address of the global CPU page.
73	*/
74	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
75	{
76	AssertReturn(HCPhysCpuPage != 0 && HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
77	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
78
79	/*
80	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per cpu/core.
81	*/
82	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
83	if (fEfer & MSR_K6_EFER_SVME)
84	{
85	/*
86	* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V.
87	*/
88	if ( pVM
89	&& pVM->hwaccm.s.svm.fIgnoreInUseError)
90	{
91	pCpu->fIgnoreAMDVInUseError = true;
92	}
93
94	if (!pCpu->fIgnoreAMDVInUseError)
95	return VERR_SVM_IN_USE;
96	}
97
98	/* Turn on AMD-V in the EFER MSR. */
99	ASMWrMsr(MSR_K6_EFER, fEfer \| MSR_K6_EFER_SVME);
100
101	/* Write the physical page address where the CPU will store the host state while executing the VM. */
102	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
103
104	/*
105	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
106	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
107	* upon VMRUN). Therefore, just set the fFlushASIDBeforeUse flag which instructs hmR0SvmSetupTLB()
108	* to flush the TLB with before using a new ASID.
109	*/
110	pCpu->fFlushASIDBeforeUse = true;
111	return VINF_SUCCESS;
112	}
113
114
115	/**
116	* Deactivates AMD-V on the current CPU.
117	*
118	* @returns VBox status code.
119	* @param pCpu Pointer to the CPU info struct.
120	* @param pvCpuPage Pointer to the global CPU page.
121	* @param HCPhysCpuPage Physical address of the global CPU page.
122	*/
123	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBLCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
124	{
125	AssertReturn(HCPhysCpuPage != 0 && HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
126	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
127	NOREF(pCpu);
128
129	/* Turn off AMD-V in the EFER MSR. */
130	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
131	ASMWrMsr(MSR_K6_EFER, fEfer & ~MSR_K6_EFER_SVME);
132
133	/* Invalidate host state physical address. */
134	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
135
136	return VINF_SUCCESS;
137	}
138
139
140	/**
141	* Does Ring-0 per VM AMD-V init.
142	*
143	* @returns VBox status code.
144	* @param pVM Pointer to the VM.
145	*/
146	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
147	{
148	int rc;
149
150	pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
151
152	/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
153	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
154	if (RT_FAILURE(rc))
155	return rc;
156
157	pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
158	pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
159	/* Set all bits to intercept all IO accesses. */
160	ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
161
162	/*
163	* Erratum 170 which requires a forced TLB flush for each world switch:
164	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
165	*
166	* All BH-G1/2 and DH-G1/2 models include a fix:
167	* Athlon X2: 0x6b 1/2
168	* 0x68 1/2
169	* Athlon 64: 0x7f 1
170	* 0x6f 2
171	* Sempron: 0x7f 1/2
172	* 0x6f 2
173	* 0x6c 2
174	* 0x7c 2
175	* Turion 64: 0x68 2
176	*/
177	uint32_t u32Dummy;
178	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
179	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
180	u32BaseFamily = (u32Version >> 8) & 0xf;
181	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
182	u32Model = ((u32Version >> 4) & 0xf);
183	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
184	u32Stepping = u32Version & 0xf;
185	if ( u32Family == 0xf
186	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
187	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
188	{
189	Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
190	pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
191	}
192
193	/* Allocate VMCBs for all guest CPUs. */
194	for (VMCPUID i = 0; i < pVM->cCpus; i++)
195	{
196	PVMCPU pVCpu = &pVM->aCpus[i];
197
198	pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
199	pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
200	pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
201
202	/* Allocate one page for the host context */
203	rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
204	if (RT_FAILURE(rc))
205	return rc;
206
207	pVCpu->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCBHost);
208	pVCpu->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 0);
209	Assert(pVCpu->hwaccm.s.svm.pVMCBHostPhys < _4G);
210	ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCBHost);
211
212	/* Allocate one page for the VM control block (VMCB). */
213	rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
214	if (RT_FAILURE(rc))
215	return rc;
216
217	pVCpu->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCB);
218	pVCpu->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCB, 0);
219	Assert(pVCpu->hwaccm.s.svm.pVMCBPhys < _4G);
220	ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCB);
221
222	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
223	rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
224	if (RT_FAILURE(rc))
225	return rc;
226
227	pVCpu->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap);
228	pVCpu->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 0);
229	/* Set all bits to intercept all MSR accesses. */
230	ASMMemFill32(pVCpu->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE * 2, 0xffffffff);
231	}
232
233	return VINF_SUCCESS;
234	}
235
236
237	/**
238	* Does Ring-0 per VM AMD-V termination.
239	*
240	* @returns VBox status code.
241	* @param pVM Pointer to the VM.
242	*/
243	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
244	{
245	for (VMCPUID i = 0; i < pVM->cCpus; i++)
246	{
247	PVMCPU pVCpu = &pVM->aCpus[i];
248
249	if (pVCpu->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ)
250	{
251	RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, false);
252	pVCpu->hwaccm.s.svm.pVMCBHost = 0;
253	pVCpu->hwaccm.s.svm.pVMCBHostPhys = 0;
254	pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
255	}
256
257	if (pVCpu->hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)
258	{
259	RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCB, false);
260	pVCpu->hwaccm.s.svm.pVMCB = 0;
261	pVCpu->hwaccm.s.svm.pVMCBPhys = 0;
262	pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
263	}
264	if (pVCpu->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
265	{
266	RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, false);
267	pVCpu->hwaccm.s.svm.pMSRBitmap = 0;
268	pVCpu->hwaccm.s.svm.pMSRBitmapPhys = 0;
269	pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
270	}
271	}
272	if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)
273	{
274	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
275	pVM->hwaccm.s.svm.pIOBitmap = 0;
276	pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
277	pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
278	}
279	return VINF_SUCCESS;
280	}
281
282
283	/**
284	* Sets up AMD-V for the specified VM.
285	*
286	* @returns VBox status code.
287	* @param pVM Pointer to the VM.
288	*/
289	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
290	{
291	int rc = VINF_SUCCESS;
292
293	AssertReturn(pVM, VERR_INVALID_PARAMETER);
294	Assert(pVM->hwaccm.s.svm.fSupported);
295
296	for (VMCPUID i = 0; i < pVM->cCpus; i++)
297	{
298	PVMCPU pVCpu = &pVM->aCpus[i];
299	SVM_VMCB pVMCB = (SVM_VMCB )pVM->aCpus[i].hwaccm.s.svm.pVMCB;
300
301	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_HMSVM_INVALID_PVMCB);
302
303	/*
304	* Program the control fields. Most of them never have to be changed again.
305	* CR0/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's.
306	* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical.
307	*/
308	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
309
310	/* CR0/4 writes must be intercepted for obvious reasons. */
311	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
312
313	/* Intercept all DRx reads and writes by default. Changed later on. */
314	pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
315	pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
316
317	/* Intercept traps; only #NM is always intercepted. */
318	pVMCB->ctrl.u32InterceptException = RT_BIT(X86_XCPT_NM);
319	#ifdef VBOX_ALWAYS_TRAP_PF
320	pVMCB->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
321	#endif
322	#ifdef VBOX_STRICT
323	pVMCB->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_BP)
324	\| RT_BIT(X86_XCPT_DB)
325	\| RT_BIT(X86_XCPT_DE)
326	\| RT_BIT(X86_XCPT_UD)
327	\| RT_BIT(X86_XCPT_NP)
328	\| RT_BIT(X86_XCPT_SS)
329	\| RT_BIT(X86_XCPT_GP)
330	\| RT_BIT(X86_XCPT_MF)
331	;
332	#endif
333
334	/* Set up instruction and miscellaneous intercepts. */
335	pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
336	\| SVM_CTRL1_INTERCEPT_VINTR
337	\| SVM_CTRL1_INTERCEPT_NMI
338	\| SVM_CTRL1_INTERCEPT_SMI
339	\| SVM_CTRL1_INTERCEPT_INIT
340	\| SVM_CTRL1_INTERCEPT_RDPMC
341	\| SVM_CTRL1_INTERCEPT_CPUID
342	\| SVM_CTRL1_INTERCEPT_RSM
343	\| SVM_CTRL1_INTERCEPT_HLT
344	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
345	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
346	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
347	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
348	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
349	;
350	pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
351	\| SVM_CTRL2_INTERCEPT_VMMCALL
352	\| SVM_CTRL2_INTERCEPT_VMLOAD
353	\| SVM_CTRL2_INTERCEPT_VMSAVE
354	\| SVM_CTRL2_INTERCEPT_STGI
355	\| SVM_CTRL2_INTERCEPT_CLGI
356	\| SVM_CTRL2_INTERCEPT_SKINIT
357	\| SVM_CTRL2_INTERCEPT_WBINVD
358	\| SVM_CTRL2_INTERCEPT_MONITOR
359	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the
360	guest (host thinks the cpu load is high) */
361
362	Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
363	Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
364	Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
365
366	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
367	pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
368
369	/* Ignore the priority in the TPR; just deliver it when we tell it to. */
370	pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
371
372	/* Set IO and MSR bitmap addresses. */
373	pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
374	pVMCB->ctrl.u64MSRPMPhysAddr = pVCpu->hwaccm.s.svm.pMSRBitmapPhys;
375
376	/* No LBR virtualization. */
377	pVMCB->ctrl.u64LBRVirt = 0;
378
379	/* The ASID must start at 1; the host uses 0. */
380	pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
381
382	/*
383	* Setup the PAT MSR (nested paging only)
384	* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
385	* so choose type 6 for all PAT slots.
386	*/
387	pVMCB->guest.u64GPAT = 0x0006060606060606ULL;
388
389	/* If nested paging is not in use, additional intercepts have to be set up. */
390	if (!pVM->hwaccm.s.fNestedPaging)
391	{
392	/* CR3 reads/writes must be intercepted; our shadow values are different from guest's. */
393	pVMCB->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
394	pVMCB->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
395
396	/*
397	* We must also intercept:
398	* - INVLPG (must go through shadow paging)
399	* - task switches (may change CR3/EFLAGS/LDT)
400	*/
401	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_INVLPG
402	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH;
403
404	/* Page faults must be intercepted to implement shadow paging. */
405	pVMCB->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
406	}
407
408	/*
409	* The following MSRs are saved automatically by vmload/vmsave, so we allow the guest
410	* to modify them directly.
411	*/
412	hmR0SvmSetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
413	hmR0SvmSetMSRPermission(pVCpu, MSR_K8_CSTAR, true, true);
414	hmR0SvmSetMSRPermission(pVCpu, MSR_K6_STAR, true, true);
415	hmR0SvmSetMSRPermission(pVCpu, MSR_K8_SF_MASK, true, true);
416	hmR0SvmSetMSRPermission(pVCpu, MSR_K8_FS_BASE, true, true);
417	hmR0SvmSetMSRPermission(pVCpu, MSR_K8_GS_BASE, true, true);
418	hmR0SvmSetMSRPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, true, true);
419	hmR0SvmSetMSRPermission(pVCpu, MSR_IA32_SYSENTER_CS, true, true);
420	hmR0SvmSetMSRPermission(pVCpu, MSR_IA32_SYSENTER_ESP, true, true);
421	hmR0SvmSetMSRPermission(pVCpu, MSR_IA32_SYSENTER_EIP, true, true);
422	}
423
424	return rc;
425	}
426
427
428	/**
429	* Sets the permission bits for the specified MSR.
430	*
431	* @param pVCpu Pointer to the VMCPU.
432	* @param ulMSR MSR value.
433	* @param fRead Whether reading is allowed.
434	* @param fWrite Whether writing is allowed.
435	*/
436	static void hmR0SvmSetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite)
437	{
438	unsigned ulBit;
439	uint8_t pMSRBitmap = (uint8_t )pVCpu->hwaccm.s.svm.pMSRBitmap;
440
441	if (ulMSR <= 0x00001FFF)
442	{
443	/* Pentium-compatible MSRs */
444	ulBit = ulMSR * 2;
445	}
446	else if ( ulMSR >= 0xC0000000
447	&& ulMSR <= 0xC0001FFF)
448	{
449	/* AMD Sixth Generation x86 Processor MSRs and SYSCALL */
450	ulBit = (ulMSR - 0xC0000000) * 2;
451	pMSRBitmap += 0x800;
452	}
453	else if ( ulMSR >= 0xC0010000
454	&& ulMSR <= 0xC0011FFF)
455	{
456	/* AMD Seventh and Eighth Generation Processor MSRs */
457	ulBit = (ulMSR - 0xC0001000) * 2;
458	pMSRBitmap += 0x1000;
459	}
460	else
461	{
462	AssertFailed();
463	return;
464	}
465	Assert(ulBit < 16 * 1024 - 1);
466	if (fRead)
467	ASMBitClear(pMSRBitmap, ulBit);
468	else
469	ASMBitSet(pMSRBitmap, ulBit);
470
471	if (fWrite)
472	ASMBitClear(pMSRBitmap, ulBit + 1);
473	else
474	ASMBitSet(pMSRBitmap, ulBit + 1);
475	}
476
477
478	/**
479	* Injects an event (trap or external interrupt).
480	*
481	* @param pVCpu Pointer to the VMCPU.
482	* @param pVMCB Pointer to the VMCB.
483	* @param pCtx Pointer to the guest CPU context.
484	* @param pIntInfo Pointer to the SVM interrupt info.
485	*/
486	DECLINLINE(void) hmR0SvmInjectEvent(PVMCPU pVCpu, SVM_VMCB pVMCB, CPUMCTX pCtx, SVM_EVENT *pEvent)
487	{
488	#ifdef VBOX_WITH_STATISTICS
489	STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
490	#endif
491
492	#ifdef VBOX_STRICT
493	if (pEvent->n.u8Vector == 0xE)
494	{
495	Log(("SVM: Inject int %d at %RGv error code=%02x CR2=%RGv intInfo=%08x\n", pEvent->n.u8Vector,
496	(RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode, (RTGCPTR)pCtx->cr2, pEvent->au64[0]));
497	}
498	else if (pEvent->n.u8Vector < 0x20)
499	Log(("SVM: Inject int %d at %RGv error code=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode));
500	else
501	{
502	Log(("INJ-EI: %x at %RGv\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip));
503	Assert(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
504	Assert(pCtx->eflags.u32 & X86_EFL_IF);
505	}
506	#endif
507
508	/* Set event injection state. */
509	pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
510	}
511
512
513	/**
514	* Checks for pending guest interrupts and injects them.
515	*
516	* @returns VBox status code.
517	* @param pVM Pointer to the VM.
518	* @param pVCpu The VM CPU to operate on.
519	* @param pVMCB Pointer to the VMCB.
520	* @param pCtx Pointer to the guest CPU Context.
521	*/
522	static int hmR0SvmCheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, SVM_VMCB pVMCB, CPUMCTX pCtx)
523	{
524	int rc;
525	NOREF(pVM);
526
527	/*
528	* Dispatch any pending interrupts (injected before, but a VM-exit occurred prematurely).
529	*/
530	if (pVCpu->hwaccm.s.Event.fPending)
531	{
532	SVM_EVENT Event;
533
534	Log(("Reinjecting event %08x %08x at %RGv\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode,
535	(RTGCPTR)pCtx->rip));
536	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
537	Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
538	hmR0SvmInjectEvent(pVCpu, pVMCB, pCtx, &Event);
539
540	pVCpu->hwaccm.s.Event.fPending = false;
541	return VINF_SUCCESS;
542	}
543
544	/*
545	* If an active trap is already pending, we must forward it first!
546	*/
547	if (!TRPMHasTrap(pVCpu))
548	{
549	if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI))
550	{
551	SVM_EVENT Event;
552
553	Log(("CPU%d: injecting #NMI\n", pVCpu->idCpu));
554	Event.n.u8Vector = X86_XCPT_NMI;
555	Event.n.u1Valid = 1;
556	Event.n.u32ErrorCode = 0;
557	Event.n.u3Type = SVM_EVENT_NMI;
558
559	hmR0SvmInjectEvent(pVCpu, pVMCB, pCtx, &Event);
560	return VINF_SUCCESS;
561	}
562
563	/** @todo SMI interrupts. */
564
565	/*
566	* When external interrupts are pending, we should exit the VM when IF is set.
567	*/
568	if (VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC\|VMCPU_FF_INTERRUPT_PIC)))
569	{
570	if ( !(pCtx->eflags.u32 & X86_EFL_IF)
571	\|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
572	{
573	if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
574	{
575	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
576	LogFlow(("Enable irq window exit!\n"));
577	else
578	{
579	Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n",
580	(RTGCPTR)pCtx->rip));
581	}
582
583	/** @todo Use virtual interrupt method to inject a pending IRQ; dispatched as
584	* soon as guest.IF is set. */
585	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
586	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
587	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
588	}
589	}
590	else
591	{
592	uint8_t u8Interrupt;
593
594	rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
595	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
596	if (RT_SUCCESS(rc))
597	{
598	rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
599	AssertRC(rc);
600	}
601	else
602	{
603	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
604	Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC\|VMCPU_FF_INTERRUPT_PIC)));
605	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
606	/* Just continue */
607	}
608	}
609	}
610	}
611
612	#ifdef VBOX_STRICT
613	if (TRPMHasTrap(pVCpu))
614	{
615	uint8_t u8Vector;
616	rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
617	AssertRC(rc);
618	}
619	#endif
620
621	if ( (pCtx->eflags.u32 & X86_EFL_IF)
622	&& (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
623	&& TRPMHasTrap(pVCpu)
624	)
625	{
626	uint8_t u8Vector;
627	TRPMEVENT enmType;
628	SVM_EVENT Event;
629	RTGCUINT u32ErrorCode;
630
631	Event.au64[0] = 0;
632
633	/* If a new event is pending, then dispatch it now. */
634	rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &u32ErrorCode, 0);
635	AssertRC(rc);
636	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
637	Assert(enmType != TRPM_SOFTWARE_INT);
638
639	/* Clear the pending trap. */
640	rc = TRPMResetTrap(pVCpu);
641	AssertRC(rc);
642
643	Event.n.u8Vector = u8Vector;
644	Event.n.u1Valid = 1;
645	Event.n.u32ErrorCode = u32ErrorCode;
646
647	if (enmType == TRPM_TRAP)
648	{
649	switch (u8Vector)
650	{
651	case X86_XCPT_DF:
652	case X86_XCPT_TS:
653	case X86_XCPT_NP:
654	case X86_XCPT_SS:
655	case X86_XCPT_GP:
656	case X86_XCPT_PF:
657	case X86_XCPT_AC:
658	/* Valid error codes. */
659	Event.n.u1ErrorCodeValid = 1;
660	break;
661	default:
662	break;
663	}
664	if (u8Vector == X86_XCPT_NMI)
665	Event.n.u3Type = SVM_EVENT_NMI;
666	else
667	Event.n.u3Type = SVM_EVENT_EXCEPTION;
668	}
669	else
670	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
671
672	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
673	hmR0SvmInjectEvent(pVCpu, pVMCB, pCtx, &Event);
674	} /* if (interrupts can be dispatched) */
675
676	return VINF_SUCCESS;
677	}
678
679
680	/**
681	* Save the host state.
682	*
683	* @returns VBox status code.
684	* @param pVM Pointer to the VM.
685	* @param pVCpu The VM CPU to operate on.
686	*/
687	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
688	{
689	NOREF(pVM);
690	NOREF(pVCpu);
691	/* Nothing to do here. */
692	return VINF_SUCCESS;
693	}
694
695
696	/**
697	* Loads the guest state.
698	*
699	* NOTE: Don't do anything here that can cause a jump back to ring-3!!!
700	*
701	* @returns VBox status code.
702	* @param pVM Pointer to the VM.
703	* @param pVCpu The VM CPU to operate on.
704	* @param pCtx Pointer to the guest CPU context.
705	*/
706	VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
707	{
708	RTGCUINTPTR val;
709	SVM_VMCB *pVMCB;
710
711	if (pVM == NULL)
712	return VERR_INVALID_PARAMETER;
713
714	/* Setup AMD SVM. */
715	Assert(pVM->hwaccm.s.svm.fSupported);
716
717	pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
718	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_HMSVM_INVALID_PVMCB);
719
720	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
721	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
722	{
723	SVM_WRITE_SELREG(CS, cs);
724	SVM_WRITE_SELREG(SS, ss);
725	SVM_WRITE_SELREG(DS, ds);
726	SVM_WRITE_SELREG(ES, es);
727	SVM_WRITE_SELREG(FS, fs);
728	SVM_WRITE_SELREG(GS, gs);
729	}
730
731	/* Guest CPU context: LDTR. */
732	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
733	{
734	SVM_WRITE_SELREG(LDTR, ldtr);
735	}
736
737	/* Guest CPU context: TR. */
738	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
739	{
740	SVM_WRITE_SELREG(TR, tr);
741	}
742
743	/* Guest CPU context: GDTR. */
744	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
745	{
746	pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
747	pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
748	}
749
750	/* Guest CPU context: IDTR. */
751	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
752	{
753	pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
754	pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
755	}
756
757	/*
758	* Sysenter MSRs (unconditional)
759	*/
760	pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
761	pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
762	pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
763
764	/* Control registers */
765	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
766	{
767	val = pCtx->cr0;
768	if (!CPUMIsGuestFPUStateActive(pVCpu))
769	{
770	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
771	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
772	}
773	else
774	{
775	/** @todo check if we support the old style mess correctly. */
776	if (!(val & X86_CR0_NE))
777	{
778	Log(("Forcing X86_CR0_NE!!!\n"));
779
780	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
781	if (!pVCpu->hwaccm.s.fFPUOldStyleOverride)
782	{
783	pVMCB->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_MF);
784	pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
785	}
786	}
787	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
788	}
789	/* Always enable caching. */
790	val &= ~(X86_CR0_CD\|X86_CR0_NW);
791
792	/*
793	* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level.
794	* Note: In nested paging mode, the guest is allowed to run with paging disabled; the guest-physical to host-physical
795	* translation will remain active.
796	*/
797	if (!pVM->hwaccm.s.fNestedPaging)
798	{
799	val \|= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
800	val \|= X86_CR0_WP; /* Must set this as we rely on protecting various pages and supervisor writes must be caught. */
801	}
802	pVMCB->guest.u64CR0 = val;
803	}
804	/* CR2 as well */
805	pVMCB->guest.u64CR2 = pCtx->cr2;
806
807	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
808	{
809	/* Save our shadow CR3 register. */
810	if (pVM->hwaccm.s.fNestedPaging)
811	{
812	PGMMODE enmShwPagingMode;
813
814	#if HC_ARCH_BITS == 32
815	if (CPUMIsGuestInLongModeEx(pCtx))
816	enmShwPagingMode = PGMMODE_AMD64_NX;
817	else
818	#endif
819	enmShwPagingMode = PGMGetHostMode(pVM);
820
821	pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
822	Assert(pVMCB->ctrl.u64NestedPagingCR3);
823	pVMCB->guest.u64CR3 = pCtx->cr3;
824	}
825	else
826	{
827	pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
828	Assert(pVMCB->guest.u64CR3 \|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
829	}
830	}
831
832	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
833	{
834	val = pCtx->cr4;
835	if (!pVM->hwaccm.s.fNestedPaging)
836	{
837	switch(pVCpu->hwaccm.s.enmShadowMode)
838	{
839	case PGMMODE_REAL:
840	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
841	AssertFailed();
842	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
843
844	case PGMMODE_32_BIT: /* 32-bit paging. */
845	val &= ~X86_CR4_PAE;
846	break;
847
848	case PGMMODE_PAE: /* PAE paging. */
849	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
850	/** Must use PAE paging as we could use physical memory > 4 GB */
851	val \|= X86_CR4_PAE;
852	break;
853
854	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
855	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
856	#ifdef VBOX_ENABLE_64_BITS_GUESTS
857	break;
858	#else
859	AssertFailed();
860	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
861	#endif
862
863	default: /* shut up gcc */
864	AssertFailed();
865	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
866	}
867	}
868	pVMCB->guest.u64CR4 = val;
869	}
870
871	/* Debug registers. */
872	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
873	{
874	pCtx->dr[6] \|= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
875	pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
876
877	pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
878	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
879	pCtx->dr[7] \|= 0x400; /* must be one */
880
881	pVMCB->guest.u64DR7 = pCtx->dr[7];
882	pVMCB->guest.u64DR6 = pCtx->dr[6];
883
884	#ifdef DEBUG
885	/* Sync the hypervisor debug state now if any breakpoint is armed. */
886	if ( CPUMGetHyperDR7(pVCpu) & (X86_DR7_ENABLED_MASK\|X86_DR7_GD)
887	&& !CPUMIsHyperDebugStateActive(pVCpu)
888	&& !DBGFIsStepping(pVCpu))
889	{
890	/* Save the host and load the hypervisor debug state. */
891	int rc = CPUMR0LoadHyperDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
892	AssertRC(rc);
893
894	/* DRx intercepts remain enabled. */
895
896	/* Override dr6 & dr7 with the hypervisor values. */
897	pVMCB->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
898	pVMCB->guest.u64DR6 = CPUMGetHyperDR6(pVCpu);
899	}
900	else
901	#endif
902	/* Sync the debug state now if any breakpoint is armed. */
903	if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK\|X86_DR7_GD))
904	&& !CPUMIsGuestDebugStateActive(pVCpu)
905	&& !DBGFIsStepping(pVCpu))
906	{
907	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
908
909	/* Disable drx move intercepts. */
910	pVMCB->ctrl.u16InterceptRdDRx = 0;
911	pVMCB->ctrl.u16InterceptWrDRx = 0;
912
913	/* Save the host and load the guest debug state. */
914	int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
915	AssertRC(rc);
916	}
917	}
918
919	/* EIP, ESP and EFLAGS */
920	pVMCB->guest.u64RIP = pCtx->rip;
921	pVMCB->guest.u64RSP = pCtx->rsp;
922	pVMCB->guest.u64RFlags = pCtx->eflags.u32;
923
924	/* Set CPL */
925	pVMCB->guest.u8CPL = pCtx->ssHid.Attr.n.u2Dpl;
926
927	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
928	pVMCB->guest.u64RAX = pCtx->rax;
929
930	/* vmrun will fail without MSR_K6_EFER_SVME. */
931	pVMCB->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
932
933	/* 64 bits guest mode? */
934	if (CPUMIsGuestInLongModeEx(pCtx))
935	{
936	#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
937	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
938	#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
939	pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
940	#else
941	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
942	if (!pVM->hwaccm.s.fAllow64BitGuests)
943	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
944	# endif
945	pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun64;
946	#endif
947	/* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
948	pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
949	pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
950	}
951	else
952	{
953	/* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
954	pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
955
956	pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun;
957	}
958
959	/* TSC offset. */
960	if (TMCpuTickCanUseRealTSC(pVCpu, &pVMCB->ctrl.u64TSCOffset))
961	{
962	uint64_t u64CurTSC = ASMReadTSC();
963	if (u64CurTSC + pVMCB->ctrl.u64TSCOffset >= TMCpuTickGetLastSeen(pVCpu))
964	{
965	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
966	pVMCB->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
967	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
968	}
969	else
970	{
971	/* Fall back to rdtsc emulation as we would otherwise pass decreasing tsc values to the guest. */
972	LogFlow(("TSC %RX64 offset %RX64 time=%RX64 last=%RX64 (diff=%RX64, virt_tsc=%RX64)\n", u64CurTSC,
973	pVMCB->ctrl.u64TSCOffset, u64CurTSC + pVMCB->ctrl.u64TSCOffset, TMCpuTickGetLastSeen(pVCpu),
974	TMCpuTickGetLastSeen(pVCpu) - u64CurTSC - pVMCB->ctrl.u64TSCOffset, TMCpuTickGet(pVCpu)));
975	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
976	pVMCB->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
977	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow);
978	}
979	}
980	else
981	{
982	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
983	pVMCB->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
984	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
985	}
986
987	/* Sync the various MSRs for 64-bit mode. */
988	pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
989	pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64-bit mode syscall rip */
990	pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
991	pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
992	pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* SWAPGS exchange value */
993
994	#ifdef DEBUG
995	/* Intercept X86_XCPT_DB if stepping is enabled */
996	if ( DBGFIsStepping(pVCpu)
997	\|\| CPUMIsHyperDebugStateActive(pVCpu))
998	pVMCB->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_DB);
999	else
1000	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_DB);
1001	#endif
1002
1003	/* Done. */
1004	pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1005
1006	return VINF_SUCCESS;
1007	}
1008
1009
1010	/**
1011	* Setup TLB for ASID.
1012	*
1013	* @param pVM Pointer to the VM.
1014	* @param pVCpu The VM CPU to operate on.
1015	*/
1016	static void hmR0SvmSetupTLB(PVM pVM, PVMCPU pVCpu)
1017	{
1018	PHMGLOBLCPUINFO pCpu;
1019
1020	AssertPtr(pVM);
1021	AssertPtr(pVCpu);
1022
1023	SVM_VMCB pVMCB = (SVM_VMCB )pVCpu->hwaccm.s.svm.pVMCB;
1024	pCpu = HWACCMR0GetCurrentCpu();
1025
1026	/*
1027	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
1028	* This can happen both for start & resume due to long jumps back to ring-3.
1029	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
1030	* so we cannot reuse the ASIDs without flushing.
1031	*/
1032	bool fNewASID = false;
1033	if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1034	\|\| pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1035	{
1036	pVCpu->hwaccm.s.fForceTLBFlush = true;
1037	fNewASID = true;
1038	}
1039
1040	/*
1041	* Set TLB flush state as checked until we return from the world switch.
1042	*/
1043	ASMAtomicWriteBool(&pVCpu->hwaccm.s.fCheckedTLBFlush, true);
1044
1045	/*
1046	* Check for TLB shootdown flushes.
1047	*/
1048	if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1049	pVCpu->hwaccm.s.fForceTLBFlush = true;
1050
1051	pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1052	pVMCB->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
1053
1054	if (RT_UNLIKELY(pVM->hwaccm.s.svm.fAlwaysFlushTLB))
1055	{
1056	/*
1057	* This is the AMD erratum 170. We need to flush the entire TLB for each world switch. Sad.
1058	*/
1059	pCpu->uCurrentASID = 1;
1060	pVCpu->hwaccm.s.uCurrentASID = 1;
1061	pVMCB->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1062	}
1063	else if (pVCpu->hwaccm.s.fForceTLBFlush)
1064	{
1065	if (fNewASID)
1066	{
1067	++pCpu->uCurrentASID;
1068	bool fHitASIDLimit = false;
1069	if (pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID)
1070	{
1071	pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1072	pCpu->cTLBFlushes++;
1073	fHitASIDLimit = true;
1074
1075	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
1076	{
1077	pVMCB->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
1078	pCpu->fFlushASIDBeforeUse = true;
1079	}
1080	else
1081	{
1082	pVMCB->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1083	pCpu->fFlushASIDBeforeUse = false;
1084	}
1085	}
1086
1087	if ( !fHitASIDLimit
1088	&& pCpu->fFlushASIDBeforeUse)
1089	{
1090	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
1091	pVMCB->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
1092	else
1093	{
1094	pVMCB->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1095	pCpu->fFlushASIDBeforeUse = false;
1096	}
1097	}
1098
1099	pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1100	pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1101	}
1102	else
1103	{
1104	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
1105	pVMCB->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
1106	else
1107	pVMCB->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1108	}
1109
1110	pVCpu->hwaccm.s.fForceTLBFlush = false;
1111	}
1112	else
1113	{
1114	/** @todo We never set VMCPU_FF_TLB_SHOOTDOWN anywhere so this path should
1115	* not be executed. See hwaccmQueueInvlPage() where it is commented
1116	* out. Support individual entry flushing someday. */
1117	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1118	{
1119	/* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1120	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1121	for (unsigned i = 0; i < pVCpu->hwaccm.s.TlbShootdown.cPages; i++)
1122	SVMR0InvlpgA(pVCpu->hwaccm.s.TlbShootdown.aPages[i], pVMCB->ctrl.TLBCtrl.n.u32ASID);
1123	}
1124	}
1125
1126	pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1127	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1128
1129	/* Update VMCB with the ASID. */
1130	pVMCB->ctrl.TLBCtrl.n.u32ASID = pVCpu->hwaccm.s.uCurrentASID;
1131
1132	AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes,
1133	("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1134	AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID,
1135	("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1136	AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID,
1137	("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1138
1139	#ifdef VBOX_WITH_STATISTICS
1140	if (pVMCB->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
1141	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1142	else if ( pVMCB->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
1143	\|\| pVMCB->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
1144	{
1145	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1146	}
1147	else
1148	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1149	#endif
1150	}
1151
1152
1153	/**
1154	* Runs guest code in an AMD-V VM.
1155	*
1156	* @returns VBox status code.
1157	* @param pVM Pointer to the VM.
1158	* @param pVCpu The VM CPU to operate on.
1159	* @param pCtx Pointer to the guest CPU context.
1160	*/
1161	VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1162	{
1163	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
1164	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hwaccm.s.StatExit1);
1165	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hwaccm.s.StatExit2);
1166
1167	VBOXSTRICTRC rc = VINF_SUCCESS;
1168	int rc2;
1169	uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
1170	SVM_VMCB *pVMCB = NULL;
1171	bool fSyncTPR = false;
1172	unsigned cResume = 0;
1173	uint8_t u8LastTPR = 0; /* Initialized for potentially stupid compilers. */
1174	PHMGLOBLCPUINFO pCpu = 0;
1175	RTCCUINTREG uOldEFlags = ~(RTCCUINTREG)0;
1176	#ifdef VBOX_STRICT
1177	RTCPUID idCpuCheck;
1178	#endif
1179	#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
1180	uint64_t u64LastTime = RTTimeMilliTS();
1181	#endif
1182
1183	pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
1184	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_HMSVM_INVALID_PVMCB);
1185
1186	/*
1187	* We can jump to this point to resume execution after determining that a VM-exit is innocent.
1188	*/
1189	ResumeExecution:
1190	if (!STAM_PROFILE_ADV_IS_RUNNING(&pVCpu->hwaccm.s.StatEntry))
1191	STAM_PROFILE_ADV_STOP_START(&pVCpu->hwaccm.s.StatExit2, &pVCpu->hwaccm.s.StatEntry, x);
1192	Assert(!HWACCMR0SuspendPending());
1193
1194	/*
1195	* Safety precaution; looping for too long here can have a very bad effect on the host.
1196	*/
1197	if (RT_UNLIKELY(++cResume > pVM->hwaccm.s.cMaxResumeLoops))
1198	{
1199	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
1200	rc = VINF_EM_RAW_INTERRUPT;
1201	goto end;
1202	}
1203
1204	/*
1205	* Check for IRQ inhibition due to instruction fusing (sti, mov ss).
1206	*/
1207	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1208	{
1209	Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
1210	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
1211	{
1212	/*
1213	* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1214	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1215	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1216	* break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
1217	*/
1218	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1219	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
1220	pVMCB->ctrl.u64IntShadow = 0;
1221	}
1222	}
1223	else
1224	{
1225	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
1226	pVMCB->ctrl.u64IntShadow = 0;
1227	}
1228
1229	#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
1230	if (RT_UNLIKELY((cResume & 0xf) == 0))
1231	{
1232	uint64_t u64CurTime = RTTimeMilliTS();
1233
1234	if (RT_UNLIKELY(u64CurTime > u64LastTime))
1235	{
1236	u64LastTime = u64CurTime;
1237	TMTimerPollVoid(pVM, pVCpu);
1238	}
1239	}
1240	#endif
1241
1242	/*
1243	* Check for pending actions that force us to go back to ring-3.
1244	*/
1245	if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
1246	\|\| VMCPU_FF_ISPENDING(pVCpu,
1247	VMCPU_FF_HWACCM_TO_R3_MASK
1248	\| VMCPU_FF_PGM_SYNC_CR3
1249	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL
1250	\| VMCPU_FF_REQUEST))
1251	{
1252	/* Check if a sync operation is pending. */
1253	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1254	{
1255	rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1256	AssertRC(VBOXSTRICTRC_VAL(rc));
1257	if (rc != VINF_SUCCESS)
1258	{
1259	Log(("Pending pool sync is forcing us back to ring 3; rc=%d\n", VBOXSTRICTRC_VAL(rc)));
1260	goto end;
1261	}
1262	}
1263
1264	#ifdef DEBUG
1265	/* Intercept X86_XCPT_DB if stepping is enabled */
1266	if (!DBGFIsStepping(pVCpu))
1267	#endif
1268	{
1269	if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK)
1270	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
1271	{
1272	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
1273	rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
1274	goto end;
1275	}
1276	}
1277
1278	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1279	if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
1280	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
1281	{
1282	rc = VINF_EM_PENDING_REQUEST;
1283	goto end;
1284	}
1285
1286	/* Check if a pgm pool flush is in progress. */
1287	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
1288	{
1289	rc = VINF_PGM_POOL_FLUSH_PENDING;
1290	goto end;
1291	}
1292
1293	/* Check if DMA work is pending (2nd+ run). */
1294	if (VM_FF_ISPENDING(pVM, VM_FF_PDM_DMA) && cResume > 1)
1295	{
1296	rc = VINF_EM_RAW_TO_R3;
1297	goto end;
1298	}
1299	}
1300
1301	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1302	/*
1303	* Exit to ring-3 preemption/work is pending.
1304	*
1305	* Interrupts are disabled before the call to make sure we don't miss any interrupt
1306	* that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
1307	* further down, but hmR0SvmCheckPendingInterrupt makes that impossible.)
1308	*
1309	* Note! Interrupts must be disabled done before we check for TLB flushes; TLB
1310	* shootdowns rely on this.
1311	*/
1312	uOldEFlags = ASMIntDisableFlags();
1313	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
1314	{
1315	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);
1316	rc = VINF_EM_RAW_INTERRUPT;
1317	goto end;
1318	}
1319	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1320	#endif
1321
1322	/*
1323	* When external interrupts are pending, we should exit the VM when IF is set.
1324	* Note: After VM_FF_INHIBIT_INTERRUPTS check!!
1325	*/
1326	rc = hmR0SvmCheckPendingInterrupt(pVM, pVCpu, pVMCB, pCtx);
1327	if (RT_FAILURE(rc))
1328	goto end;
1329
1330	/*
1331	* TPR caching using CR8 is only available in 64-bit mode or with 32-bit guests when X86_CPUID_AMD_FEATURE_ECX_CR8L is
1332	* supported.
1333	* Note: we can't do this in LoddGuestState as PDMApicGetTPR can jump back to ring 3 (lock)! (no longer true)
1334	*/
1335	/** @todo query and update the TPR only when it could have been changed (mmio access)
1336	*/
1337	if (pVM->hwaccm.s.fHasIoApic)
1338	{
1339	/* TPR caching in CR8 */
1340	bool fPending;
1341	rc2 = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);
1342	AssertRC(rc2);
1343
1344	if (pVM->hwaccm.s.fTPRPatchingActive)
1345	{
1346	/* Our patch code uses LSTAR for TPR caching. */
1347	pCtx->msrLSTAR = u8LastTPR;
1348
1349	if (fPending)
1350	{
1351	/* A TPR change could activate a pending interrupt, so catch lstar writes. */
1352	hmR0SvmSetMSRPermission(pVCpu, MSR_K8_LSTAR, true, false);
1353	}
1354	else
1355	{
1356	/*
1357	* No interrupts are pending, so we don't need to be explicitely notified.
1358	* There are enough world switches for detecting pending interrupts.
1359	*/
1360	hmR0SvmSetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
1361	}
1362	}
1363	else
1364	{
1365	/* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1366	pVMCB->ctrl.IntCtrl.n.u8VTPR = (u8LastTPR >> 4);
1367
1368	if (fPending)
1369	{
1370	/* A TPR change could activate a pending interrupt, so catch cr8 writes. */
1371	pVMCB->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
1372	}
1373	else
1374	{
1375	/*
1376	* No interrupts are pending, so we don't need to be explicitely notified.
1377	* There are enough world switches for detecting pending interrupts.
1378	*/
1379	pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1380	}
1381	}
1382	fSyncTPR = !fPending;
1383	}
1384
1385	/* All done! Let's start VM execution. */
1386
1387	/* Enable nested paging if necessary (disabled each time after #VMEXIT). */
1388	pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
1389
1390	#ifdef LOG_ENABLED
1391	pCpu = HWACCMR0GetCurrentCpu();
1392	if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1393	\|\| pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1394	{
1395	if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
1396	{
1397	LogFlow(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu,
1398	pCpu->idCpu));
1399	}
1400	else
1401	{
1402	LogFlow(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes,
1403	pCpu->cTLBFlushes));
1404	}
1405	}
1406	else if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH))
1407	LogFlow(("Manual TLB flush\n"));
1408	#endif
1409
1410	/*
1411	* NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1412	* (until the actual world switch)
1413	*/
1414	#ifdef VBOX_STRICT
1415	idCpuCheck = RTMpCpuId();
1416	#endif
1417	VMMR0LogFlushDisable(pVCpu);
1418
1419	/*
1420	* Load the guest state; must be here as it sets up the shadow CR0 for lazy FPU syncing!
1421	*/
1422	rc = SVMR0LoadGuestState(pVM, pVCpu, pCtx);
1423	if (RT_UNLIKELY(rc != VINF_SUCCESS))
1424	{
1425	VMMR0LogFlushEnable(pVCpu);
1426	goto end;
1427	}
1428
1429	#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1430	/*
1431	* Disable interrupts to make sure a poke will interrupt execution.
1432	* This must be done before we check for TLB flushes; TLB shootdowns rely on this.
1433	*/
1434	uOldEFlags = ASMIntDisableFlags();
1435	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1436	#endif
1437	STAM_PROFILE_ADV_STOP_START(&pVCpu->hwaccm.s.StatEntry, &pVCpu->hwaccm.s.StatInGC, x);
1438
1439	/* Setup TLB control and ASID in the VMCB. */
1440	hmR0SvmSetupTLB(pVM, pVCpu);
1441
1442	/* In case we execute a goto ResumeExecution later on. */
1443	pVCpu->hwaccm.s.fResumeVM = true;
1444	pVCpu->hwaccm.s.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
1445
1446	Assert(sizeof(pVCpu->hwaccm.s.svm.pVMCBPhys) == 8);
1447	Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
1448	Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
1449	Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVCpu->hwaccm.s.svm.pMSRBitmapPhys);
1450	Assert(pVMCB->ctrl.u64LBRVirt == 0);
1451
1452	#ifdef VBOX_STRICT
1453	Assert(idCpuCheck == RTMpCpuId());
1454	#endif
1455	TMNotifyStartOfExecution(pVCpu);
1456	#ifdef VBOX_WITH_KERNEL_USING_XMM
1457	hwaccmR0SVMRunWrapXMM(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu,
1458	pVCpu->hwaccm.s.svm.pfnVMRun);
1459	#else
1460	pVCpu->hwaccm.s.svm.pfnVMRun(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu);
1461	#endif
1462	ASMAtomicWriteBool(&pVCpu->hwaccm.s.fCheckedTLBFlush, false);
1463	ASMAtomicIncU32(&pVCpu->hwaccm.s.cWorldSwitchExits);
1464	/* Possibly the last TSC value seen by the guest (too high) (only when we're in TSC offset mode). */
1465	if (!(pVMCB->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
1466	{
1467	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() +
1468	pVMCB->ctrl.u64TSCOffset - 0x400 /* guestimate of world switch overhead in clock ticks */);
1469	}
1470	TMNotifyEndOfExecution(pVCpu);
1471	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
1472	STAM_PROFILE_ADV_STOP_START(&pVCpu->hwaccm.s.StatInGC, &pVCpu->hwaccm.s.StatExit1, x);
1473	ASMSetFlags(uOldEFlags);
1474	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1475	uOldEFlags = ~(RTCCUINTREG)0;
1476	#endif
1477
1478	/*
1479	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1480	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING-3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1481	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1482	*/
1483
1484	/* Reason for the VM exit */
1485	exitCode = pVMCB->ctrl.u64ExitCode;
1486
1487	if (RT_UNLIKELY(exitCode == (uint64_t)SVM_EXIT_INVALID)) /* Invalid guest state. */
1488	{
1489	HWACCMDumpRegs(pVM, pVCpu, pCtx);
1490	#ifdef DEBUG
1491	Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
1492	Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
1493	Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
1494	Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
1495	Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
1496	Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
1497	Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
1498	Log(("ctrl.u64IOPMPhysAddr %RX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
1499	Log(("ctrl.u64MSRPMPhysAddr %RX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
1500	Log(("ctrl.u64TSCOffset %RX64\n", pVMCB->ctrl.u64TSCOffset));
1501
1502	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
1503	Log(("ctrl.TLBCtrl.u8TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u8TLBFlush));
1504	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
1505
1506	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
1507	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
1508	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
1509	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
1510	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
1511	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
1512	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
1513	Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
1514	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
1515	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
1516
1517	Log(("ctrl.u64IntShadow %RX64\n", pVMCB->ctrl.u64IntShadow));
1518	Log(("ctrl.u64ExitCode %RX64\n", pVMCB->ctrl.u64ExitCode));
1519	Log(("ctrl.u64ExitInfo1 %RX64\n", pVMCB->ctrl.u64ExitInfo1));
1520	Log(("ctrl.u64ExitInfo2 %RX64\n", pVMCB->ctrl.u64ExitInfo2));
1521	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
1522	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
1523	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
1524	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
1525	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
1526	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
1527	Log(("ctrl.NestedPaging %RX64\n", pVMCB->ctrl.NestedPaging.au64));
1528	Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
1529	Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
1530	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
1531	Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
1532	Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
1533	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
1534
1535	Log(("ctrl.u64NestedPagingCR3 %RX64\n", pVMCB->ctrl.u64NestedPagingCR3));
1536	Log(("ctrl.u64LBRVirt %RX64\n", pVMCB->ctrl.u64LBRVirt));
1537
1538	Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
1539	Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1540	Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1541	Log(("guest.CS.u64Base %RX64\n", pVMCB->guest.CS.u64Base));
1542	Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1543	Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1544	Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1545	Log(("guest.DS.u64Base %RX64\n", pVMCB->guest.DS.u64Base));
1546	Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1547	Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1548	Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1549	Log(("guest.ES.u64Base %RX64\n", pVMCB->guest.ES.u64Base));
1550	Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1551	Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1552	Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1553	Log(("guest.FS.u64Base %RX64\n", pVMCB->guest.FS.u64Base));
1554	Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1555	Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1556	Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1557	Log(("guest.GS.u64Base %RX64\n", pVMCB->guest.GS.u64Base));
1558
1559	Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1560	Log(("guest.GDTR.u64Base %RX64\n", pVMCB->guest.GDTR.u64Base));
1561
1562	Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1563	Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1564	Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1565	Log(("guest.LDTR.u64Base %RX64\n", pVMCB->guest.LDTR.u64Base));
1566
1567	Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1568	Log(("guest.IDTR.u64Base %RX64\n", pVMCB->guest.IDTR.u64Base));
1569
1570	Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1571	Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1572	Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1573	Log(("guest.TR.u64Base %RX64\n", pVMCB->guest.TR.u64Base));
1574
1575	Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1576	Log(("guest.u64CR0 %RX64\n", pVMCB->guest.u64CR0));
1577	Log(("guest.u64CR2 %RX64\n", pVMCB->guest.u64CR2));
1578	Log(("guest.u64CR3 %RX64\n", pVMCB->guest.u64CR3));
1579	Log(("guest.u64CR4 %RX64\n", pVMCB->guest.u64CR4));
1580	Log(("guest.u64DR6 %RX64\n", pVMCB->guest.u64DR6));
1581	Log(("guest.u64DR7 %RX64\n", pVMCB->guest.u64DR7));
1582
1583	Log(("guest.u64RIP %RX64\n", pVMCB->guest.u64RIP));
1584	Log(("guest.u64RSP %RX64\n", pVMCB->guest.u64RSP));
1585	Log(("guest.u64RAX %RX64\n", pVMCB->guest.u64RAX));
1586	Log(("guest.u64RFlags %RX64\n", pVMCB->guest.u64RFlags));
1587
1588	Log(("guest.u64SysEnterCS %RX64\n", pVMCB->guest.u64SysEnterCS));
1589	Log(("guest.u64SysEnterEIP %RX64\n", pVMCB->guest.u64SysEnterEIP));
1590	Log(("guest.u64SysEnterESP %RX64\n", pVMCB->guest.u64SysEnterESP));
1591
1592	Log(("guest.u64EFER %RX64\n", pVMCB->guest.u64EFER));
1593	Log(("guest.u64STAR %RX64\n", pVMCB->guest.u64STAR));
1594	Log(("guest.u64LSTAR %RX64\n", pVMCB->guest.u64LSTAR));
1595	Log(("guest.u64CSTAR %RX64\n", pVMCB->guest.u64CSTAR));
1596	Log(("guest.u64SFMASK %RX64\n", pVMCB->guest.u64SFMASK));
1597	Log(("guest.u64KernelGSBase %RX64\n", pVMCB->guest.u64KernelGSBase));
1598	Log(("guest.u64GPAT %RX64\n", pVMCB->guest.u64GPAT));
1599	Log(("guest.u64DBGCTL %RX64\n", pVMCB->guest.u64DBGCTL));
1600	Log(("guest.u64BR_FROM %RX64\n", pVMCB->guest.u64BR_FROM));
1601	Log(("guest.u64BR_TO %RX64\n", pVMCB->guest.u64BR_TO));
1602	Log(("guest.u64LASTEXCPFROM %RX64\n", pVMCB->guest.u64LASTEXCPFROM));
1603	Log(("guest.u64LASTEXCPTO %RX64\n", pVMCB->guest.u64LASTEXCPTO));
1604
1605	#endif
1606	rc = VERR_SVM_UNABLE_TO_START_VM;
1607	VMMR0LogFlushEnable(pVCpu);
1608	goto end;
1609	}
1610
1611	/* Let's first sync back EIP, ESP, and EFLAGS. */
1612	pCtx->rip = pVMCB->guest.u64RIP;
1613	pCtx->rsp = pVMCB->guest.u64RSP;
1614	pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1615	/* eax is saved/restore across the vmrun instruction */
1616	pCtx->rax = pVMCB->guest.u64RAX;
1617
1618	/*
1619	* Save all the MSRs that can be changed by the guest without causing a world switch.
1620	* FS & GS base are saved with SVM_READ_SELREG.
1621	*/
1622	pCtx->msrSTAR = pVMCB->guest.u64STAR; /* legacy syscall eip, cs & ss */
1623	pCtx->msrLSTAR = pVMCB->guest.u64LSTAR; /* 64-bit mode syscall rip */
1624	pCtx->msrCSTAR = pVMCB->guest.u64CSTAR; /* compatibility mode syscall rip */
1625	pCtx->msrSFMASK = pVMCB->guest.u64SFMASK; /* syscall flag mask */
1626	pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
1627	pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1628	pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1629	pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1630
1631	/* Can be updated behind our back in the nested paging case. */
1632	pCtx->cr2 = pVMCB->guest.u64CR2;
1633
1634	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1635	SVM_READ_SELREG(SS, ss);
1636	SVM_READ_SELREG(CS, cs);
1637	SVM_READ_SELREG(DS, ds);
1638	SVM_READ_SELREG(ES, es);
1639	SVM_READ_SELREG(FS, fs);
1640	SVM_READ_SELREG(GS, gs);
1641
1642	/*
1643	* Correct the hidden CS granularity flag. Haven't seen it being wrong in any other
1644	* register (yet).
1645	*/
1646	if ( !pCtx->csHid.Attr.n.u1Granularity
1647	&& pCtx->csHid.Attr.n.u1Present
1648	&& pCtx->csHid.u32Limit > UINT32_C(0xfffff))
1649	{
1650	Assert((pCtx->csHid.u32Limit & 0xfff) == 0xfff);
1651	pCtx->csHid.Attr.n.u1Granularity = 1;
1652	}
1653	#define SVM_ASSERT_SEL_GRANULARITY(reg) \
1654	AssertMsg( !pCtx->reg##Hid.Attr.n.u1Present \
1655	\|\| ( pCtx->reg##Hid.Attr.n.u1Granularity \
1656	? (pCtx->reg##Hid.u32Limit & 0xfff) == 0xfff \
1657	: pCtx->reg##Hid.u32Limit <= 0xfffff), \
1658	("%#x %#x %#llx\n", pCtx->reg##Hid.u32Limit, pCtx->reg##Hid.Attr.u, pCtx->reg##Hid.u64Base))
1659	SVM_ASSERT_SEL_GRANULARITY(ss);
1660	SVM_ASSERT_SEL_GRANULARITY(cs);
1661	SVM_ASSERT_SEL_GRANULARITY(ds);
1662	SVM_ASSERT_SEL_GRANULARITY(es);
1663	SVM_ASSERT_SEL_GRANULARITY(fs);
1664	SVM_ASSERT_SEL_GRANULARITY(gs);
1665	#undef SVM_ASSERT_SEL_GRANULARITY
1666
1667	/*
1668	* Correct the hidden SS DPL field. It can be wrong on certain CPUs
1669	* sometimes (seen it on AMD Fusion CPUs with 64-bit guests). The CPU
1670	* always uses the CPL field in the VMCB instead of the DPL in the hidden
1671	* SS (chapter AMD spec. 15.5.1 Basic operation).
1672	*/
1673	Assert(!(pVMCB->guest.u8CPL & ~0x3));
1674	pCtx->ssHid.Attr.n.u2Dpl = pVMCB->guest.u8CPL & 0x3;
1675
1676	/*
1677	* Remaining guest CPU context: TR, IDTR, GDTR, LDTR;
1678	* must sync everything otherwise we can get out of sync when jumping back to ring-3.
1679	*/
1680	SVM_READ_SELREG(LDTR, ldtr);
1681	SVM_READ_SELREG(TR, tr);
1682
1683	pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1684	pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1685
1686	pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1687	pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1688
1689	/*
1690	* No reason to sync back the CRx and DRx registers as they cannot be changed by the guest
1691	* unless in the nested paging case where CR3 & CR3 can be changed by the guest.
1692	*/
1693	if ( pVM->hwaccm.s.fNestedPaging
1694	&& pCtx->cr3 != pVMCB->guest.u64CR3)
1695	{
1696	CPUMSetGuestCR3(pVCpu, pVMCB->guest.u64CR3);
1697	PGMUpdateCR3(pVCpu, pVMCB->guest.u64CR3);
1698	}
1699
1700	/* Note! NOW IT'S SAFE FOR LOGGING! */
1701	VMMR0LogFlushEnable(pVCpu);
1702
1703	/* Take care of instruction fusing (sti, mov ss) (see AMD spec. 15.20.5 Interrupt Shadows) */
1704	if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1705	{
1706	Log(("uInterruptState %x rip=%RGv\n", pVMCB->ctrl.u64IntShadow, (RTGCPTR)pCtx->rip));
1707	EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
1708	}
1709	else
1710	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1711
1712	Log2(("exitCode = %x\n", exitCode));
1713
1714	/* Sync back DR6 as it could have been changed by hitting breakpoints. */
1715	pCtx->dr[6] = pVMCB->guest.u64DR6;
1716	/* DR7.GD can be cleared by debug exceptions, so sync it back as well. */
1717	pCtx->dr[7] = pVMCB->guest.u64DR7;
1718
1719	/* Check if an injected event was interrupted prematurely. */
1720	pVCpu->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1721	if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1722	/* we don't care about 'int xx' as the instruction will be restarted. */
1723	&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT)
1724	{
1725	Log(("Pending inject %RX64 at %RGv exit=%08x\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitCode));
1726
1727	#ifdef LOG_ENABLED
1728	SVM_EVENT Event;
1729	Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
1730
1731	if ( exitCode == SVM_EXIT_EXCEPTION_E
1732	&& Event.n.u8Vector == 0xE)
1733	{
1734	Log(("Double fault!\n"));
1735	}
1736	#endif
1737
1738	pVCpu->hwaccm.s.Event.fPending = true;
1739	/* Error code present? (redundant) */
1740	if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1741	pVCpu->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1742	else
1743	pVCpu->hwaccm.s.Event.errCode = 0;
1744	}
1745	#ifdef VBOX_WITH_STATISTICS
1746	if (exitCode == SVM_EXIT_NPF)
1747	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
1748	else
1749	STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1750	#endif
1751
1752	/* Sync back the TPR if it was changed. */
1753	if (fSyncTPR)
1754	{
1755	if (pVM->hwaccm.s.fTPRPatchingActive)
1756	{
1757	if ((pCtx->msrLSTAR & 0xff) != u8LastTPR)
1758	{
1759	/* Our patch code uses LSTAR for TPR caching. */
1760	rc2 = PDMApicSetTPR(pVCpu, pCtx->msrLSTAR & 0xff);
1761	AssertRC(rc2);
1762	}
1763	}
1764	else
1765	{
1766	if ((uint8_t)(u8LastTPR >> 4) != pVMCB->ctrl.IntCtrl.n.u8VTPR)
1767	{
1768	/* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1769	rc2 = PDMApicSetTPR(pVCpu, pVMCB->ctrl.IntCtrl.n.u8VTPR << 4);
1770	AssertRC(rc2);
1771	}
1772	}
1773	}
1774
1775	#ifdef DBGFTRACE_ENABLED /** @todo DTrace */
1776	RTTraceBufAddMsgF(pVM->CTX_SUFF(hTraceBuf), "vmexit %08x at %04:%08RX64 %RX64 %RX64 %RX64",
1777	exitCode, pCtx->cs, pCtx->rip,
1778	pVMCB->ctrl.u64ExitInfo1, pVMCB->ctrl.u64ExitInfo2, pVMCB->ctrl.ExitIntInfo.au64[0]);
1779	#endif
1780	#if ARCH_BITS == 64 /* for the time being */
1781	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, exitCode, pVMCB->ctrl.u64ExitInfo1, pVMCB->ctrl.u64ExitInfo2,
1782	pVMCB->ctrl.ExitIntInfo.au64[0], UINT64_MAX);
1783	#endif
1784	STAM_PROFILE_ADV_STOP_START(&pVCpu->hwaccm.s.StatExit1, &pVCpu->hwaccm.s.StatExit2, x);
1785
1786	/* Deal with the reason of the VM-exit. */
1787	switch (exitCode)
1788	{
1789	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1790	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1791	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1792	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1793	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1794	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1795	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1796	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1797	{
1798	/* Pending trap. */
1799	SVM_EVENT Event;
1800	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1801
1802	Log2(("Hardware/software interrupt %d\n", vector));
1803	switch (vector)
1804	{
1805	case X86_XCPT_DB:
1806	{
1807	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
1808
1809	/* Note that we don't support guest and host-initiated debugging at the same time. */
1810	Assert(DBGFIsStepping(pVCpu) \|\| CPUMIsHyperDebugStateActive(pVCpu));
1811
1812	rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
1813	if (rc == VINF_EM_RAW_GUEST_TRAP)
1814	{
1815	Log(("Trap %x (debug) at %016RX64\n", vector, pCtx->rip));
1816
1817	/* Reinject the exception. */
1818	Event.au64[0] = 0;
1819	Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
1820	Event.n.u1Valid = 1;
1821	Event.n.u8Vector = X86_XCPT_DB;
1822
1823	hmR0SvmInjectEvent(pVCpu, pVMCB, pCtx, &Event);
1824	goto ResumeExecution;
1825	}
1826	/* Return to ring 3 to deal with the debug exit code. */
1827	Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, VBOXSTRICTRC_VAL(rc)));
1828	break;
1829	}
1830
1831	case X86_XCPT_NM:
1832	{
1833	Log(("#NM fault at %RGv\n", (RTGCPTR)pCtx->rip));
1834
1835	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1836	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1837	rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
1838	if (rc == VINF_SUCCESS)
1839	{
1840	Assert(CPUMIsGuestFPUStateActive(pVCpu));
1841	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
1842
1843	/* Continue execution. */
1844	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1845
1846	goto ResumeExecution;
1847	}
1848
1849	Log(("Forward #NM fault to the guest\n"));
1850	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
1851
1852	Event.au64[0] = 0;
1853	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1854	Event.n.u1Valid = 1;
1855	Event.n.u8Vector = X86_XCPT_NM;
1856
1857	hmR0SvmInjectEvent(pVCpu, pVMCB, pCtx, &Event);
1858	goto ResumeExecution;
1859	}
1860
1861	case X86_XCPT_PF: /* Page fault */
1862	{
1863	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1864	RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1865
1866	#ifdef VBOX_ALWAYS_TRAP_PF
1867	if (pVM->hwaccm.s.fNestedPaging)
1868	{
1869	/*
1870	* A genuine pagefault. Forward the trap to the guest by injecting the exception and resuming execution.
1871	*/
1872	Log(("Guest page fault at %04X:%RGv cr2=%RGv error code %x rsp=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip,
1873	uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
1874	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1875
1876	/* Now we must update CR2. */
1877	pCtx->cr2 = uFaultAddress;
1878
1879	Event.au64[0] = 0;
1880	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1881	Event.n.u1Valid = 1;
1882	Event.n.u8Vector = X86_XCPT_PF;
1883	Event.n.u1ErrorCodeValid = 1;
1884	Event.n.u32ErrorCode = errCode;
1885
1886	hmR0SvmInjectEvent(pVCpu, pVMCB, pCtx, &Event);
1887	goto ResumeExecution;
1888	}
1889	#endif
1890	Assert(!pVM->hwaccm.s.fNestedPaging);
1891
1892	#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
1893	/* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1894	if ( pVM->hwaccm.s.fTRPPatchingAllowed
1895	&& (uFaultAddress & 0xfff) == 0x080
1896	&& !(errCode & X86_TRAP_PF_P) /* not present */
1897	&& CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
1898	&& !CPUMIsGuestInLongModeEx(pCtx)
1899	&& pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches))
1900	{
1901	RTGCPHYS GCPhysApicBase, GCPhys;
1902	PDMApicGetBase(pVM, &GCPhysApicBase); /** @todo cache this */
1903	GCPhysApicBase &= PAGE_BASE_GC_MASK;
1904
1905	rc = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL, &GCPhys);
1906	if ( rc == VINF_SUCCESS
1907	&& GCPhys == GCPhysApicBase)
1908	{
1909	/* Only attempt to patch the instruction once. */
1910	PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1911	if (!pPatch)
1912	{
1913	rc = VINF_EM_HWACCM_PATCH_TPR_INSTR;
1914	break;
1915	}
1916	}
1917	}
1918	#endif
1919
1920	Log2(("Page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1921	/* Exit qualification contains the linear address of the page fault. */
1922	TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1923	TRPMSetErrorCode(pVCpu, errCode);
1924	TRPMSetFaultAddress(pVCpu, uFaultAddress);
1925
1926	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1927	rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1928	Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, VBOXSTRICTRC_VAL(rc)));
1929	if (rc == VINF_SUCCESS)
1930	{
1931	/* We've successfully synced our shadow pages, so let's just continue execution. */
1932	Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1933	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1934
1935	TRPMResetTrap(pVCpu);
1936	goto ResumeExecution;
1937	}
1938	else if (rc == VINF_EM_RAW_GUEST_TRAP)
1939	{
1940	/*
1941	* A genuine pagefault. Forward the trap to the guest by injecting the exception and resuming execution.
1942	*/
1943	Log2(("Forward page fault to the guest\n"));
1944	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1945	/* The error code might have been changed. */
1946	errCode = TRPMGetErrorCode(pVCpu);
1947
1948	TRPMResetTrap(pVCpu);
1949
1950	/* Now we must update CR2. */
1951	pCtx->cr2 = uFaultAddress;
1952
1953	Event.au64[0] = 0;
1954	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1955	Event.n.u1Valid = 1;
1956	Event.n.u8Vector = X86_XCPT_PF;
1957	Event.n.u1ErrorCodeValid = 1;
1958	Event.n.u32ErrorCode = errCode;
1959
1960	hmR0SvmInjectEvent(pVCpu, pVMCB, pCtx, &Event);
1961	goto ResumeExecution;
1962	}
1963	#ifdef VBOX_STRICT
1964	if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
1965	LogFlow(("PGMTrap0eHandler failed with %d\n", VBOXSTRICTRC_VAL(rc)));
1966	#endif
1967	/* Need to go back to the recompiler to emulate the instruction. */
1968	TRPMResetTrap(pVCpu);
1969	break;
1970	}
1971
1972	case X86_XCPT_MF: /* Floating point exception. */
1973	{
1974	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
1975	if (!(pCtx->cr0 & X86_CR0_NE))
1976	{
1977	/* old style FPU error reporting needs some extra work. */
1978	/** @todo don't fall back to the recompiler, but do it manually. */
1979	rc = VINF_EM_RAW_EMULATE_INSTR;
1980	break;
1981	}
1982	Log(("Trap %x at %RGv\n", vector, (RTGCPTR)pCtx->rip));
1983
1984	Event.au64[0] = 0;
1985	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1986	Event.n.u1Valid = 1;
1987	Event.n.u8Vector = X86_XCPT_MF;
1988
1989	hmR0SvmInjectEvent(pVCpu, pVMCB, pCtx, &Event);
1990	goto ResumeExecution;
1991	}
1992
1993	#ifdef VBOX_STRICT
1994	case X86_XCPT_BP: /* Breakpoint. */
1995	case X86_XCPT_GP: /* General protection failure exception.*/
1996	case X86_XCPT_UD: /* Unknown opcode exception. */
1997	case X86_XCPT_DE: /* Divide error. */
1998	case X86_XCPT_SS: /* Stack segment exception. */
1999	case X86_XCPT_NP: /* Segment not present exception. */
2000	{
2001	Event.au64[0] = 0;
2002	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2003	Event.n.u1Valid = 1;
2004	Event.n.u8Vector = vector;
2005
2006	switch (vector)
2007	{
2008	case X86_XCPT_GP:
2009	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
2010	Event.n.u1ErrorCodeValid = 1;
2011	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
2012	break;
2013	case X86_XCPT_BP:
2014	/** Saves the wrong EIP on the stack (pointing to the int3 instead of the next instruction. */
2015	break;
2016	case X86_XCPT_DE:
2017	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
2018	break;
2019	case X86_XCPT_UD:
2020	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
2021	break;
2022	case X86_XCPT_SS:
2023	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
2024	Event.n.u1ErrorCodeValid = 1;
2025	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
2026	break;
2027	case X86_XCPT_NP:
2028	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
2029	Event.n.u1ErrorCodeValid = 1;
2030	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
2031	break;
2032	}
2033	Log(("Trap %x at %04x:%RGv esi=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->esi));
2034	hmR0SvmInjectEvent(pVCpu, pVMCB, pCtx, &Event);
2035	goto ResumeExecution;
2036	}
2037	#endif
2038	default:
2039	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
2040	rc = VERR_HMSVM_UNEXPECTED_XCPT_EXIT;
2041	break;
2042
2043	} /* switch (vector) */
2044	break;
2045	}
2046
2047	case SVM_EXIT_NPF:
2048	{
2049	/* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
2050	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
2051	RTGCPHYS GCPhysFault = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
2052	PGMMODE enmShwPagingMode;
2053
2054	Assert(pVM->hwaccm.s.fNestedPaging);
2055	LogFlow(("Nested page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, GCPhysFault, errCode));
2056
2057	#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2058	/* Shortcut for APIC TPR reads and writes; 32 bits guests only */
2059	if ( pVM->hwaccm.s.fTRPPatchingAllowed
2060	&& (GCPhysFault & PAGE_OFFSET_MASK) == 0x080
2061	&& ( !(errCode & X86_TRAP_PF_P) /* not present */
2062	\|\| (errCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD) /* mmio optimization */)
2063	&& CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
2064	&& !CPUMIsGuestInLongModeEx(pCtx)
2065	&& pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches))
2066	{
2067	RTGCPHYS GCPhysApicBase;
2068	PDMApicGetBase(pVM, &GCPhysApicBase); /** @todo cache this */
2069	GCPhysApicBase &= PAGE_BASE_GC_MASK;
2070
2071	if (GCPhysFault == GCPhysApicBase + 0x80)
2072	{
2073	/* Only attempt to patch the instruction once. */
2074	PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2075	if (!pPatch)
2076	{
2077	rc = VINF_EM_HWACCM_PATCH_TPR_INSTR;
2078	break;
2079	}
2080	}
2081	}
2082	#endif
2083
2084	/* Handle the pagefault trap for the nested shadow table. */
2085	#if HC_ARCH_BITS == 32 /** @todo shadow this in a variable. */
2086	if (CPUMIsGuestInLongModeEx(pCtx))
2087	enmShwPagingMode = PGMMODE_AMD64_NX;
2088	else
2089	#endif
2090	enmShwPagingMode = PGMGetHostMode(pVM);
2091
2092	/* MMIO optimization */
2093	Assert((errCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
2094	if ((errCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2095	{
2096	rc = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmShwPagingMode, CPUMCTX2CORE(pCtx), GCPhysFault, errCode);
2097
2098	/*
2099	* If we succeed, resume execution.
2100	* Or, if fail in interpreting the instruction because we couldn't get the guest physical address
2101	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
2102	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
2103	* weird case. See #6043.
2104	*/
2105	if ( rc == VINF_SUCCESS
2106	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
2107	\|\| rc == VERR_PAGE_NOT_PRESENT)
2108	{
2109	Log2(("PGMR0Trap0eHandlerNPMisconfig(,,,%RGp) at %RGv -> resume\n", GCPhysFault, (RTGCPTR)pCtx->rip));
2110	goto ResumeExecution;
2111	}
2112	Log2(("PGMR0Trap0eHandlerNPMisconfig(,,,%RGp) at %RGv -> resume\n", GCPhysFault, (RTGCPTR)pCtx->rip));
2113	break;
2114	}
2115
2116	/* Exit qualification contains the linear address of the page fault. */
2117	TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
2118	TRPMSetErrorCode(pVCpu, errCode);
2119	TRPMSetFaultAddress(pVCpu, GCPhysFault);
2120
2121	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmShwPagingMode, errCode, CPUMCTX2CORE(pCtx), GCPhysFault);
2122	Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, VBOXSTRICTRC_VAL(rc)));
2123
2124	/*
2125	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, #6043.
2126	*/
2127	if ( rc == VINF_SUCCESS
2128	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
2129	\|\| rc == VERR_PAGE_NOT_PRESENT)
2130	{
2131	/* We've successfully synced our shadow pages, so let's just continue execution. */
2132	Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, GCPhysFault, errCode));
2133	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
2134
2135	TRPMResetTrap(pVCpu);
2136	goto ResumeExecution;
2137	}
2138
2139	#ifdef VBOX_STRICT
2140	if (rc != VINF_EM_RAW_EMULATE_INSTR)
2141	LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", VBOXSTRICTRC_VAL(rc)));
2142	#endif
2143	/* Need to go back to the recompiler to emulate the instruction. */
2144	TRPMResetTrap(pVCpu);
2145	break;
2146	}
2147
2148	case SVM_EXIT_VINTR:
2149	/* A virtual interrupt is about to be delivered, which means IF=1. */
2150	Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
2151	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
2152	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
2153	goto ResumeExecution;
2154
2155	case SVM_EXIT_FERR_FREEZE:
2156	case SVM_EXIT_INTR:
2157	case SVM_EXIT_NMI:
2158	case SVM_EXIT_SMI:
2159	case SVM_EXIT_INIT:
2160	/* External interrupt; leave to allow it to be dispatched again. */
2161	rc = VINF_EM_RAW_INTERRUPT;
2162	break;
2163
2164	case SVM_EXIT_WBINVD:
2165	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
2166	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
2167	/* Skip instruction and continue directly. */
2168	pCtx->rip += 2; /* Note! hardcoded opcode size! */
2169	/* Continue execution.*/
2170	goto ResumeExecution;
2171
2172	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
2173	{
2174	Log2(("SVM: Cpuid at %RGv for %x\n", (RTGCPTR)pCtx->rip, pCtx->eax));
2175	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
2176	rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2177	if (rc == VINF_SUCCESS)
2178	{
2179	/* Update EIP and continue execution. */
2180	pCtx->rip += 2; /* Note! hardcoded opcode size! */
2181	goto ResumeExecution;
2182	}
2183	AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
2184	rc = VINF_EM_RAW_EMULATE_INSTR;
2185	break;
2186	}
2187
2188	case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
2189	{
2190	Log2(("SVM: Rdtsc\n"));
2191	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
2192	rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2193	if (rc == VINF_SUCCESS)
2194	{
2195	/* Update EIP and continue execution. */
2196	pCtx->rip += 2; /* Note! hardcoded opcode size! */
2197	goto ResumeExecution;
2198	}
2199	rc = VINF_EM_RAW_EMULATE_INSTR;
2200	break;
2201	}
2202
2203	case SVM_EXIT_RDPMC: /* Guest software attempted to execute RDPMC. */
2204	{
2205	Log2(("SVM: Rdpmc %x\n", pCtx->ecx));
2206	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdpmc);
2207	rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2208	if (rc == VINF_SUCCESS)
2209	{
2210	/* Update EIP and continue execution. */
2211	pCtx->rip += 2; /* Note! hardcoded opcode size! */
2212	goto ResumeExecution;
2213	}
2214	rc = VINF_EM_RAW_EMULATE_INSTR;
2215	break;
2216	}
2217
2218	case SVM_EXIT_RDTSCP: /* Guest software attempted to execute RDTSCP. */
2219	{
2220	Log2(("SVM: Rdtscp\n"));
2221	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
2222	rc = EMInterpretRdtscp(pVM, pVCpu, pCtx);
2223	if (rc == VINF_SUCCESS)
2224	{
2225	/* Update EIP and continue execution. */
2226	pCtx->rip += 3; /* Note! hardcoded opcode size! */
2227	goto ResumeExecution;
2228	}
2229	AssertMsgFailed(("EMU: rdtscp failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
2230	rc = VINF_EM_RAW_EMULATE_INSTR;
2231	break;
2232	}
2233
2234	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
2235	{
2236	Log2(("SVM: invlpg\n"));
2237	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
2238
2239	Assert(!pVM->hwaccm.s.fNestedPaging);
2240
2241	/* Truly a pita. Why can't SVM give the same information as VT-x? */
2242	rc = hmR0SvmInterpretInvpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
2243	if (rc == VINF_SUCCESS)
2244	{
2245	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushPageInvlpg);
2246	goto ResumeExecution; /* eip already updated */
2247	}
2248	break;
2249	}
2250
2251	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
2252	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
2253	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
2254	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
2255	{
2256	Log2(("SVM: %RGv mov cr%d, \n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
2257	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[exitCode - SVM_EXIT_WRITE_CR0]);
2258	rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0);
2259
2260	switch (exitCode - SVM_EXIT_WRITE_CR0)
2261	{
2262	case 0:
2263	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
2264	break;
2265	case 2:
2266	break;
2267	case 3:
2268	Assert(!pVM->hwaccm.s.fNestedPaging);
2269	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
2270	break;
2271	case 4:
2272	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
2273	break;
2274	case 8:
2275	break;
2276	default:
2277	AssertFailed();
2278	}
2279	if (rc == VINF_SUCCESS)
2280	{
2281	/* EIP has been updated already. */
2282	/* Only resume if successful. */
2283	goto ResumeExecution;
2284	}
2285	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
2286	break;
2287	}
2288
2289	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
2290	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
2291	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
2292	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
2293	{
2294	Log2(("SVM: %RGv mov x, cr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
2295	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[exitCode - SVM_EXIT_READ_CR0]);
2296	rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0);
2297	if (rc == VINF_SUCCESS)
2298	{
2299	/* EIP has been updated already. */
2300	/* Only resume if successful. */
2301	goto ResumeExecution;
2302	}
2303	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
2304	break;
2305	}
2306
2307	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
2308	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
2309	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
2310	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
2311	{
2312	Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
2313	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
2314
2315	if ( !DBGFIsStepping(pVCpu)
2316	&& !CPUMIsHyperDebugStateActive(pVCpu))
2317	{
2318	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2319
2320	/* Disable drx move intercepts. */
2321	pVMCB->ctrl.u16InterceptRdDRx = 0;
2322	pVMCB->ctrl.u16InterceptWrDRx = 0;
2323
2324	/* Save the host and load the guest debug state. */
2325	rc2 = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2326	AssertRC(rc2);
2327	goto ResumeExecution;
2328	}
2329
2330	rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0);
2331	if (rc == VINF_SUCCESS)
2332	{
2333	/* EIP has been updated already. */
2334	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_DEBUG;
2335
2336	/* Only resume if successful. */
2337	goto ResumeExecution;
2338	}
2339	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
2340	break;
2341	}
2342
2343	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
2344	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
2345	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
2346	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
2347	{
2348	Log2(("SVM: %RGv mov x, dr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
2349	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
2350
2351	if (!DBGFIsStepping(pVCpu))
2352	{
2353	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2354
2355	/* Disable DRx move intercepts. */
2356	pVMCB->ctrl.u16InterceptRdDRx = 0;
2357	pVMCB->ctrl.u16InterceptWrDRx = 0;
2358
2359	/* Save the host and load the guest debug state. */
2360	rc2 = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2361	AssertRC(rc2);
2362	goto ResumeExecution;
2363	}
2364
2365	rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0);
2366	if (rc == VINF_SUCCESS)
2367	{
2368	/* EIP has been updated already. */
2369	/* Only resume if successful. */
2370	goto ResumeExecution;
2371	}
2372	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
2373	break;
2374	}
2375
2376	/* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2377	case SVM_EXIT_IOIO: /* I/O instruction. */
2378	{
2379	SVM_IOIO_EXIT IoExitInfo;
2380	uint32_t uIOSize, uAndVal;
2381
2382	IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
2383
2384	/** @todo could use a lookup table here */
2385	if (IoExitInfo.n.u1OP8)
2386	{
2387	uIOSize = 1;
2388	uAndVal = 0xff;
2389	}
2390	else if (IoExitInfo.n.u1OP16)
2391	{
2392	uIOSize = 2;
2393	uAndVal = 0xffff;
2394	}
2395	else if (IoExitInfo.n.u1OP32)
2396	{
2397	uIOSize = 4;
2398	uAndVal = 0xffffffff;
2399	}
2400	else
2401	{
2402	AssertFailed(); /* should be fatal. */
2403	rc = VINF_EM_RAW_EMULATE_INSTR;
2404	break;
2405	}
2406
2407	if (IoExitInfo.n.u1STR)
2408	{
2409	/* ins/outs */
2410	PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2411
2412	/* Disassemble manually to deal with segment prefixes. */
2413	rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL);
2414	if (rc == VINF_SUCCESS)
2415	{
2416	if (IoExitInfo.n.u1Type == 0)
2417	{
2418	Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2419	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
2420	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix, (DISCPUMODE)pDis->uAddrMode, uIOSize);
2421	}
2422	else
2423	{
2424	Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2425	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
2426	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix, (DISCPUMODE)pDis->uAddrMode, uIOSize);
2427	}
2428	}
2429	else
2430	rc = VINF_EM_RAW_EMULATE_INSTR;
2431	}
2432	else
2433	{
2434	/* Normal in/out */
2435	Assert(!IoExitInfo.n.u1REP);
2436
2437	if (IoExitInfo.n.u1Type == 0)
2438	{
2439	Log2(("IOMIOPortWrite %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal,
2440	uIOSize));
2441	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
2442	rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
2443	if (rc == VINF_IOM_R3_IOPORT_WRITE)
2444	{
2445	HWACCMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port,
2446	uAndVal, uIOSize);
2447	}
2448	}
2449	else
2450	{
2451	uint32_t u32Val = 0;
2452
2453	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
2454	rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
2455	if (IOM_SUCCESS(rc))
2456	{
2457	/* Write back to the EAX register. */
2458	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
2459	Log2(("IOMIOPortRead %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal,
2460	uIOSize));
2461	}
2462	else if (rc == VINF_IOM_R3_IOPORT_READ)
2463	{
2464	HWACCMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port,
2465	uAndVal, uIOSize);
2466	}
2467	}
2468	}
2469
2470	/*
2471	* Handled the I/O return codes.
2472	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2473	*/
2474	if (IOM_SUCCESS(rc))
2475	{
2476	/* Update EIP and continue execution. */
2477	pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
2478	if (RT_LIKELY(rc == VINF_SUCCESS))
2479	{
2480	/* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
2481	if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
2482	{
2483	/* IO operation lookup arrays. */
2484	static uint32_t const aIOSize[4] = { 1, 2, 0, 4 };
2485
2486	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
2487	for (unsigned i = 0; i < 4; i++)
2488	{
2489	unsigned uBPLen = aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
2490
2491	if ( (IoExitInfo.n.u16Port >= pCtx->dr[i] && IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen)
2492	&& (pCtx->dr[7] & (X86_DR7_L(i) \| X86_DR7_G(i)))
2493	&& (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
2494	{
2495	SVM_EVENT Event;
2496
2497	Assert(CPUMIsGuestDebugStateActive(pVCpu));
2498
2499	/* Clear all breakpoint status flags and set the one we just hit. */
2500	pCtx->dr[6] &= ~(X86_DR6_B0\|X86_DR6_B1\|X86_DR6_B2\|X86_DR6_B3);
2501	pCtx->dr[6] \|= (uint64_t)RT_BIT(i);
2502
2503	/*
2504	* Note: AMD64 Architecture Programmer's Manual 13.1:
2505	* Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared
2506	* by software after the contents have been read.
2507	*/
2508	pVMCB->guest.u64DR6 = pCtx->dr[6];
2509
2510	/* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2511	pCtx->dr[7] &= ~X86_DR7_GD;
2512
2513	/* Paranoia. */
2514	pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2515	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
2516	pCtx->dr[7] \|= 0x400; /* must be one */
2517
2518	pVMCB->guest.u64DR7 = pCtx->dr[7];
2519
2520	/* Inject the exception. */
2521	Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
2522
2523	Event.au64[0] = 0;
2524	Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
2525	Event.n.u1Valid = 1;
2526	Event.n.u8Vector = X86_XCPT_DB;
2527
2528	hmR0SvmInjectEvent(pVCpu, pVMCB, pCtx, &Event);
2529	goto ResumeExecution;
2530	}
2531	}
2532	}
2533	goto ResumeExecution;
2534	}
2535	Log2(("EM status from IO at %RGv %x size %d: %Rrc\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize,
2536	VBOXSTRICTRC_VAL(rc)));
2537	break;
2538	}
2539
2540	#ifdef VBOX_STRICT
2541	if (rc == VINF_IOM_R3_IOPORT_READ)
2542	Assert(IoExitInfo.n.u1Type != 0);
2543	else if (rc == VINF_IOM_R3_IOPORT_WRITE)
2544	Assert(IoExitInfo.n.u1Type == 0);
2545	else
2546	{
2547	AssertMsg( RT_FAILURE(rc)
2548	\|\| rc == VINF_EM_RAW_EMULATE_INSTR
2549	\|\| rc == VINF_EM_RAW_GUEST_TRAP
2550	\|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rc)));
2551	}
2552	#endif
2553	Log2(("Failed IO at %RGv %x size %d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2554	break;
2555	}
2556
2557	case SVM_EXIT_HLT:
2558	/* Check if external interrupts are pending; if so, don't switch back. */
2559	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
2560	pCtx->rip++; /* skip hlt */
2561	if (EMShouldContinueAfterHalt(pVCpu, pCtx))
2562	goto ResumeExecution;
2563
2564	rc = VINF_EM_HALT;
2565	break;
2566
2567	case SVM_EXIT_MWAIT_UNCOND:
2568	Log2(("SVM: mwait\n"));
2569	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMwait);
2570	rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2571	if ( rc == VINF_EM_HALT
2572	\|\| rc == VINF_SUCCESS)
2573	{
2574	/* Update EIP and continue execution. */
2575	pCtx->rip += 3; /* Note: hardcoded opcode size assumption! */
2576
2577	/* Check if external interrupts are pending; if so, don't switch back. */
2578	if ( rc == VINF_SUCCESS
2579	\|\| ( rc == VINF_EM_HALT
2580	&& EMShouldContinueAfterHalt(pVCpu, pCtx))
2581	)
2582	goto ResumeExecution;
2583	}
2584	AssertMsg(rc == VERR_EM_INTERPRETER \|\| rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
2585	break;
2586
2587	case SVM_EXIT_MONITOR:
2588	{
2589	Log2(("SVM: monitor\n"));
2590
2591	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMonitor);
2592	rc = EMInterpretMonitor(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2593	if (rc == VINF_SUCCESS)
2594	{
2595	/* Update EIP and continue execution. */
2596	pCtx->rip += 3; /* Note: hardcoded opcode size assumption! */
2597	goto ResumeExecution;
2598	}
2599	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: monitor failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
2600	break;
2601	}
2602
2603	case SVM_EXIT_VMMCALL:
2604	rc = hmR0SvmEmulateTprVMMCall(pVM, pVCpu, pCtx);
2605	if (rc == VINF_SUCCESS)
2606	{
2607	goto ResumeExecution; /* rip already updated. */
2608	}
2609	/* no break */
2610
2611	case SVM_EXIT_RSM:
2612	case SVM_EXIT_INVLPGA:
2613	case SVM_EXIT_VMRUN:
2614	case SVM_EXIT_VMLOAD:
2615	case SVM_EXIT_VMSAVE:
2616	case SVM_EXIT_STGI:
2617	case SVM_EXIT_CLGI:
2618	case SVM_EXIT_SKINIT:
2619	{
2620	/* Unsupported instructions. */
2621	SVM_EVENT Event;
2622
2623	Event.au64[0] = 0;
2624	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2625	Event.n.u1Valid = 1;
2626	Event.n.u8Vector = X86_XCPT_UD;
2627
2628	Log(("Forced #UD trap at %RGv\n", (RTGCPTR)pCtx->rip));
2629	hmR0SvmInjectEvent(pVCpu, pVMCB, pCtx, &Event);
2630	goto ResumeExecution;
2631	}
2632
2633	/* Emulate in ring-3. */
2634	case SVM_EXIT_MSR:
2635	{
2636	/* When an interrupt is pending, we'll let MSR_K8_LSTAR writes fault in our TPR patch code. */
2637	if ( pVM->hwaccm.s.fTPRPatchingActive
2638	&& pCtx->ecx == MSR_K8_LSTAR
2639	&& pVMCB->ctrl.u64ExitInfo1 == 1 /* wrmsr */)
2640	{
2641	if ((pCtx->eax & 0xff) != u8LastTPR)
2642	{
2643	Log(("SVM: Faulting MSR_K8_LSTAR write with new TPR value %x\n", pCtx->eax & 0xff));
2644
2645	/* Our patch code uses LSTAR for TPR caching. */
2646	rc2 = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
2647	AssertRC(rc2);
2648	}
2649
2650	/* Skip the instruction and continue. */
2651	pCtx->rip += 2; /* wrmsr = [0F 30] */
2652
2653	/* Only resume if successful. */
2654	goto ResumeExecution;
2655	}
2656
2657	/*
2658	* The Intel spec. claims there's an REX version of RDMSR that's slightly different,
2659	* so we play safe by completely disassembling the instruction.
2660	*/
2661	STAM_COUNTER_INC((pVMCB->ctrl.u64ExitInfo1 == 0) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
2662	Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
2663	rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0);
2664	if (rc == VINF_SUCCESS)
2665	{
2666	/* EIP has been updated already. */
2667	/* Only resume if successful. */
2668	goto ResumeExecution;
2669	}
2670	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr",
2671	VBOXSTRICTRC_VAL(rc)));
2672	break;
2673	}
2674
2675	case SVM_EXIT_TASK_SWITCH: /* too complicated to emulate, so fall back to the recompiler */
2676	Log(("SVM_EXIT_TASK_SWITCH: exit2=%RX64\n", pVMCB->ctrl.u64ExitInfo2));
2677	if ( !(pVMCB->ctrl.u64ExitInfo2 & (SVM_EXIT2_TASK_SWITCH_IRET \| SVM_EXIT2_TASK_SWITCH_JMP))
2678	&& pVCpu->hwaccm.s.Event.fPending)
2679	{
2680	SVM_EVENT Event;
2681	Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
2682
2683	/* Caused by an injected interrupt. */
2684	pVCpu->hwaccm.s.Event.fPending = false;
2685	switch (Event.n.u3Type)
2686	{
2687	case SVM_EVENT_EXTERNAL_IRQ:
2688	case SVM_EVENT_NMI:
2689	Log(("SVM_EXIT_TASK_SWITCH: reassert trap %d\n", Event.n.u8Vector));
2690	Assert(!Event.n.u1ErrorCodeValid);
2691	rc2 = TRPMAssertTrap(pVCpu, Event.n.u8Vector, TRPM_HARDWARE_INT);
2692	AssertRC(rc2);
2693	break;
2694
2695	default:
2696	/* Exceptions and software interrupts can just be restarted. */
2697	break;
2698	}
2699	}
2700	rc = VERR_EM_INTERPRETER;
2701	break;
2702
2703	case SVM_EXIT_PAUSE:
2704	case SVM_EXIT_MWAIT_ARMED:
2705	rc = VERR_EM_INTERPRETER;
2706	break;
2707
2708	case SVM_EXIT_SHUTDOWN:
2709	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2710	break;
2711
2712	case SVM_EXIT_IDTR_READ:
2713	case SVM_EXIT_GDTR_READ:
2714	case SVM_EXIT_LDTR_READ:
2715	case SVM_EXIT_TR_READ:
2716	case SVM_EXIT_IDTR_WRITE:
2717	case SVM_EXIT_GDTR_WRITE:
2718	case SVM_EXIT_LDTR_WRITE:
2719	case SVM_EXIT_TR_WRITE:
2720	case SVM_EXIT_CR0_SEL_WRITE:
2721	default:
2722	/* Unexpected exit codes. */
2723	rc = VERR_HMSVM_UNEXPECTED_EXIT;
2724	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
2725	break;
2726	}
2727
2728	end:
2729
2730	/*
2731	* We are now going back to ring-3, so clear the forced action flag.
2732	*/
2733	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2734
2735	/*
2736	* Signal changes to the recompiler.
2737	*/
2738	CPUMSetChangedFlags(pVCpu,
2739	CPUM_CHANGED_SYSENTER_MSR
2740	\| CPUM_CHANGED_LDTR
2741	\| CPUM_CHANGED_GDTR
2742	\| CPUM_CHANGED_IDTR
2743	\| CPUM_CHANGED_TR
2744	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
2745
2746	/*
2747	* If we executed vmrun and an external IRQ was pending, then we don't have to do a full sync the next time.
2748	*/
2749	if (exitCode == SVM_EXIT_INTR)
2750	{
2751	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
2752	/* On the next entry we'll only sync the host context. */
2753	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
2754	}
2755	else
2756	{
2757	/* On the next entry we'll sync everything. */
2758	/** @todo we can do better than this */
2759	/* Not in the VINF_PGM_CHANGE_MODE though! */
2760	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
2761	}
2762
2763	/* Translate into a less severe return code */
2764	if (rc == VERR_EM_INTERPRETER)
2765	rc = VINF_EM_RAW_EMULATE_INSTR;
2766
2767	/* Just set the correct state here instead of trying to catch every goto above. */
2768	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
2769
2770	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2771	/* Restore interrupts if we exitted after disabling them. */
2772	if (uOldEFlags != ~(RTCCUINTREG)0)
2773	ASMSetFlags(uOldEFlags);
2774	#endif
2775
2776	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, x);
2777	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2778	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
2779	return VBOXSTRICTRC_TODO(rc);
2780	}
2781
2782
2783	/**
2784	* Emulate simple mov tpr instruction.
2785	*
2786	* @returns VBox status code.
2787	* @param pVM Pointer to the VM.
2788	* @param pVCpu The VM CPU to operate on.
2789	* @param pCtx Pointer to the guest CPU context.
2790	*/
2791	static int hmR0SvmEmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2792	{
2793	int rc;
2794
2795	LogFlow(("Emulated VMMCall TPR access replacement at %RGv\n", pCtx->rip));
2796
2797	for (;;)
2798	{
2799	bool fPending;
2800	uint8_t u8Tpr;
2801
2802	PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2803	if (!pPatch)
2804	break;
2805
2806	switch(pPatch->enmType)
2807	{
2808	case HWACCMTPRINSTR_READ:
2809	/* TPR caching in CR8 */
2810	rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending);
2811	AssertRC(rc);
2812
2813	rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
2814	AssertRC(rc);
2815
2816	LogFlow(("Emulated read successfully\n"));
2817	pCtx->rip += pPatch->cbOp;
2818	break;
2819
2820	case HWACCMTPRINSTR_WRITE_REG:
2821	case HWACCMTPRINSTR_WRITE_IMM:
2822	/* Fetch the new TPR value */
2823	if (pPatch->enmType == HWACCMTPRINSTR_WRITE_REG)
2824	{
2825	uint32_t val;
2826
2827	rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &val);
2828	AssertRC(rc);
2829	u8Tpr = val;
2830	}
2831	else
2832	u8Tpr = (uint8_t)pPatch->uSrcOperand;
2833
2834	rc = PDMApicSetTPR(pVCpu, u8Tpr);
2835	AssertRC(rc);
2836	LogFlow(("Emulated write successfully\n"));
2837	pCtx->rip += pPatch->cbOp;
2838	break;
2839
2840	default:
2841	AssertMsgFailedReturn(("Unexpected type %d\n", pPatch->enmType), VERR_HMSVM_UNEXPECTED_PATCH_TYPE);
2842	}
2843	}
2844	return VINF_SUCCESS;
2845	}
2846
2847
2848	/**
2849	* Enters the AMD-V session.
2850	*
2851	* @returns VBox status code.
2852	* @param pVM Pointer to the VM.
2853	* @param pVCpu The VM CPU to operate on.
2854	* @param pCpu Pointer to the CPU info struct.
2855	*/
2856	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBLCPUINFO pCpu)
2857	{
2858	Assert(pVM->hwaccm.s.svm.fSupported);
2859
2860	LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVCpu->hwaccm.s.idLastCpu, pVCpu->hwaccm.s.uCurrentASID));
2861	pVCpu->hwaccm.s.fResumeVM = false;
2862
2863	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
2864	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_LDTR;
2865
2866	return VINF_SUCCESS;
2867	}
2868
2869
2870	/**
2871	* Leaves the AMD-V session.
2872	*
2873	* @returns VBox status code.
2874	* @param pVM Pointer to the VM.
2875	* @param pVCpu The VM CPU to operate on.
2876	* @param pCtx Pointer to the guest CPU context.
2877	*/
2878	VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2879	{
2880	SVM_VMCB pVMCB = (SVM_VMCB )pVCpu->hwaccm.s.svm.pVMCB;
2881
2882	Assert(pVM->hwaccm.s.svm.fSupported);
2883
2884	#ifdef DEBUG
2885	if (CPUMIsHyperDebugStateActive(pVCpu))
2886	{
2887	CPUMR0LoadHostDebugState(pVM, pVCpu);
2888	}
2889	else
2890	#endif
2891	/* Save the guest debug state if necessary. */
2892	if (CPUMIsGuestDebugStateActive(pVCpu))
2893	{
2894	CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, false /* skip DR6 */);
2895
2896	/* Intercept all DRx reads and writes again. Changed later on. */
2897	pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
2898	pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
2899
2900	/* Resync the debug registers the next time. */
2901	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_DEBUG;
2902	}
2903	else
2904	Assert(pVMCB->ctrl.u16InterceptRdDRx == 0xFFFF && pVMCB->ctrl.u16InterceptWrDRx == 0xFFFF);
2905
2906	return VINF_SUCCESS;
2907	}
2908
2909
2910	/**
2911	* Interprets INVLPG.
2912	*
2913	* @return VBox status code.
2914	* @param pVCpu Pointer to the VMCPU.
2915	* @param pCpu Pointer to the CPU info struct.
2916	* @param pRegFrame Pointer to the register frame.
2917	* @param ASID Tagged TLB id for the guest.
2918	*/
2919	static int hmR0svmInterpretInvlPg(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2920	{
2921	DISQPVPARAMVAL param1;
2922	RTGCPTR addr;
2923	NOREF(uASID);
2924
2925	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->Param1, &param1, DISQPVWHICH_SRC);
2926	if (RT_FAILURE(rc))
2927	return VERR_EM_INTERPRETER;
2928
2929	switch (param1.type)
2930	{
2931	case DISQPV_TYPE_IMMEDIATE:
2932	case DISQPV_TYPE_ADDRESS:
2933	if (!(param1.flags & (DISQPV_FLAG_32 \| DISQPV_FLAG_64)))
2934	return VERR_EM_INTERPRETER;
2935	addr = param1.val.val64;
2936	break;
2937
2938	default:
2939	return VERR_EM_INTERPRETER;
2940	}
2941
2942	/** @todo is addr always a flat linear address or ds based
2943	* (in absence of segment override prefixes)????
2944	*/
2945	rc = PGMInvalidatePage(pVCpu, addr);
2946	if (RT_SUCCESS(rc))
2947	return VINF_SUCCESS;
2948
2949	AssertRC(rc);
2950	return rc;
2951	}
2952
2953
2954	/**
2955	* Interprets INVLPG.
2956	*
2957	* @returns VBox status code.
2958	* @retval VINF_* Scheduling instructions.
2959	* @retval VERR_EM_INTERPRETER Something we can't cope with.
2960	* @retval VERR_* Fatal errors.
2961	*
2962	* @param pVM Pointer to the VM.
2963	* @param pRegFrame Pointer to the register frame.
2964	* @param ASID Tagged TLB id for the guest.
2965	*
2966	* @remarks Updates the EIP if an instruction was executed successfully.
2967	*/
2968	static int hmR0SvmInterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2969	{
2970	/*
2971	* Only allow 32 & 64 bit code.
2972	*/
2973	DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVCpu, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
2974	if (enmMode != DISCPUMODE_16BIT)
2975	{
2976	RTGCPTR pbCode;
2977	int rc = SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs,
2978	&pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
2979	if (RT_SUCCESS(rc))
2980	{
2981	uint32_t cbOp;
2982	PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2983
2984	pDis->uCpuMode = enmMode;
2985	rc = EMInterpretDisasOneEx(pVM, pVCpu, pbCode, pRegFrame, pDis, &cbOp);
2986	Assert(RT_FAILURE(rc) \|\| pDis->pCurInstr->uOpcode == OP_INVLPG);
2987	if (RT_SUCCESS(rc) && pDis->pCurInstr->uOpcode == OP_INVLPG)
2988	{
2989	Assert(cbOp == pDis->cbInstr);
2990	rc = hmR0svmInterpretInvlPg(pVCpu, pDis, pRegFrame, uASID);
2991	if (RT_SUCCESS(rc))
2992	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
2993
2994	return rc;
2995	}
2996	}
2997	}
2998	return VERR_EM_INTERPRETER;
2999	}
3000
3001
3002	/**
3003	* Invalidates a guest page by guest virtual address.
3004	*
3005	* @returns VBox status code.
3006	* @param pVM Pointer to the VM.
3007	* @param pVCpu The VM CPU to operate on.
3008	* @param GCVirt Guest virtual address of the page to invalidate.
3009	*/
3010	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
3011	{
3012	bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB \| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH);
3013
3014	/* Skip it if a TLB flush is already pending. */
3015	if (!fFlushPending)
3016	{
3017	SVM_VMCB *pVMCB;
3018
3019	Log2(("SVMR0InvalidatePage %RGv\n", GCVirt));
3020	AssertReturn(pVM, VERR_INVALID_PARAMETER);
3021	Assert(pVM->hwaccm.s.svm.fSupported);
3022
3023	pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
3024	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_HMSVM_INVALID_PVMCB);
3025
3026	#if HC_ARCH_BITS == 32
3027	/* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invlpga takes only 32 bits addresses. */
3028	if (CPUMIsGuestInLongMode(pVCpu))
3029	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
3030	else
3031	#endif
3032	SVMR0InvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
3033	}
3034	return VINF_SUCCESS;
3035	}
3036
3037
3038	#if 0 /* obsolete, but left here for clarification. */
3039	/**
3040	* Invalidates a guest page by physical address.
3041	*
3042	* @returns VBox status code.
3043	* @param pVM Pointer to the VM.
3044	* @param pVCpu The VM CPU to operate on.
3045	* @param GCPhys Guest physical address of the page to invalidate.
3046	*/
3047	VMMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
3048	{
3049	Assert(pVM->hwaccm.s.fNestedPaging);
3050	/* invlpga only invalidates TLB entries for guest virtual addresses; we have no choice but to force a TLB flush here. */
3051	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
3052	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBInvlpga);
3053	return VINF_SUCCESS;
3054	}
3055	#endif
3056
3057
3058	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3059	/**
3060	* Prepares for and executes VMRUN (64-bit guests from a 32-bit host).
3061	*
3062	* @returns VBox status code.
3063	* @param pVMCBHostPhys Physical address of host VMCB.
3064	* @param pVMCBPhys Physical address of the VMCB.
3065	* @param pCtx Pointer to the guest CPU context.
3066	* @param pVM Pointer to the VM.
3067	* @param pVCpu Pointer to the VMCPU.
3068	*/
3069	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
3070	{
3071	uint32_t aParam[4];
3072
3073	aParam[0] = (uint32_t)(pVMCBHostPhys); /* Param 1: pVMCBHostPhys - Lo. */
3074	aParam[1] = (uint32_t)(pVMCBHostPhys >> 32); /* Param 1: pVMCBHostPhys - Hi. */
3075	aParam[2] = (uint32_t)(pVMCBPhys); /* Param 2: pVMCBPhys - Lo. */
3076	aParam[3] = (uint32_t)(pVMCBPhys >> 32); /* Param 2: pVMCBPhys - Hi. */
3077
3078	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSVMGCVMRun64, 4, &aParam[0]);
3079	}
3080
3081
3082	/**
3083	* Executes the specified handler in 64-bit mode.
3084	*
3085	* @returns VBox status code.
3086	* @param pVM Pointer to the VM.
3087	* @param pVCpu Pointer to the VMCPU.
3088	* @param pCtx Pointer to the guest CPU context.
3089	* @param pfnHandler Pointer to the RC handler function.
3090	* @param cbParam Number of parameters.
3091	* @param paParam Array of 32-bit parameters.
3092	*/
3093	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam,
3094	uint32_t *paParam)
3095	{
3096	int rc;
3097	RTHCUINTREG uOldEFlags;
3098
3099	Assert(pfnHandler);
3100
3101	/* Disable interrupts. */
3102	uOldEFlags = ASMIntDisableFlags();
3103
3104	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
3105	RTCPUID idHostCpu = RTMpCpuId();
3106	CPUMR0SetLApic(pVM, idHostCpu);
3107	#endif
3108
3109	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
3110	CPUMSetHyperEIP(pVCpu, pfnHandler);
3111	for (int i=(int)cbParam-1;i>=0;i--)
3112	CPUMPushHyper(pVCpu, paParam[i]);
3113
3114	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
3115	/* Call switcher. */
3116	rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
3117	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
3118
3119	ASMSetFlags(uOldEFlags);
3120	return rc;
3121	}
3122
3123	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
3124

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 41741

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