HWSVMR0.cpp@ 8213

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1	/* $Id: HWSVMR0.cpp 8155 2008-04-18 15:16:47Z vboxsync $ */
2	/** @file
3	* HWACCM SVM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_svm.h>
32	#include <VBox/pgm.h>
33	#include <VBox/pdm.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <VBox/selm.h>
37	#include <VBox/iom.h>
38	#include <VBox/dis.h>
39	#include <VBox/dbgf.h>
40	#include <VBox/disopcode.h>
41	#include <iprt/param.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm.h>
44	#include "HWSVMR0.h"
45
46	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
47
48	/**
49	* Sets up and activates AMD-V on the current CPU
50	*
51	* @returns VBox status code.
52	* @param idCpu The identifier for the CPU the function is called on.
53	* @param pVM The VM to operate on.
54	* @param pvPageCpu Pointer to the global cpu page
55	* @param pPageCpuPhys Physical address of the global cpu page
56	*/
57	HWACCMR0DECL(int) SVMR0EnableCpu(RTCPUID idCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
58	{
59	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
60	AssertReturn(pVM, VERR_INVALID_PARAMETER);
61	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
62
63	/* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
64
65	/* Turn on AMD-V in the EFER MSR. */
66	uint64_t val = ASMRdMsr(MSR_K6_EFER);
67	if (!(val & MSR_K6_EFER_SVME))
68	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
69
70	/* Write the physical page address where the CPU will store the host state while executing the VM. */
71	ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
72	return VINF_SUCCESS;
73	}
74
75	/**
76	* Deactivates AMD-V on the current CPU
77	*
78	* @returns VBox status code.
79	* @param idCpu The identifier for the CPU the function is called on.
80	* @param pvPageCpu Pointer to the global cpu page
81	* @param pPageCpuPhys Physical address of the global cpu page
82	*/
83	HWACCMR0DECL(int) SVMR0DisableCpu(RTCPUID idCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
84	{
85	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
86	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
87
88	/* Turn off AMD-V in the EFER MSR. */
89	uint64_t val = ASMRdMsr(MSR_K6_EFER);
90	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
91
92	/* Invalidate host state physical address. */
93	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
94	return VINF_SUCCESS;
95	}
96
97	/**
98	* Does Ring-0 per VM AMD-V init.
99	*
100	* @returns VBox status code.
101	* @param pVM The VM to operate on.
102	*/
103	HWACCMR0DECL(int) SVMR0InitVM(PVM pVM)
104	{
105	int rc;
106
107	/* Allocate one page for the VM control block (VMCB). */
108	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
109	if (RT_FAILURE(rc))
110	return rc;
111
112	pVM->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCB);
113	pVM->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCB, 0);
114	ASMMemZero32(pVM->hwaccm.s.svm.pVMCB, PAGE_SIZE);
115
116	/* Allocate one page for the host context */
117	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
118	if (RT_FAILURE(rc))
119	return rc;
120
121	pVM->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCBHost);
122	pVM->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCBHost, 0);
123	ASMMemZero32(pVM->hwaccm.s.svm.pVMCBHost, PAGE_SIZE);
124
125	/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
126	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
127	if (RT_FAILURE(rc))
128	return rc;
129
130	pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
131	pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
132	/* Set all bits to intercept all IO accesses. */
133	ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
134
135	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
136	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
137	if (RT_FAILURE(rc))
138	return rc;
139
140	pVM->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
141	pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
142	/* Set all bits to intercept all MSR accesses. */
143	ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
144
145	return VINF_SUCCESS;
146	}
147
148	/**
149	* Does Ring-0 per VM AMD-V termination.
150	*
151	* @returns VBox status code.
152	* @param pVM The VM to operate on.
153	*/
154	HWACCMR0DECL(int) SVMR0TermVM(PVM pVM)
155	{
156	if (pVM->hwaccm.s.svm.pMemObjVMCB)
157	{
158	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCB, false);
159	pVM->hwaccm.s.svm.pVMCB = 0;
160	pVM->hwaccm.s.svm.pVMCBPhys = 0;
161	pVM->hwaccm.s.svm.pMemObjVMCB = 0;
162	}
163	if (pVM->hwaccm.s.svm.pMemObjVMCBHost)
164	{
165	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCBHost, false);
166	pVM->hwaccm.s.svm.pVMCBHost = 0;
167	pVM->hwaccm.s.svm.pVMCBHostPhys = 0;
168	pVM->hwaccm.s.svm.pMemObjVMCBHost = 0;
169	}
170	if (pVM->hwaccm.s.svm.pMemObjIOBitmap)
171	{
172	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
173	pVM->hwaccm.s.svm.pIOBitmap = 0;
174	pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
175	pVM->hwaccm.s.svm.pMemObjIOBitmap = 0;
176	}
177	if (pVM->hwaccm.s.svm.pMemObjMSRBitmap)
178	{
179	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
180	pVM->hwaccm.s.svm.pMSRBitmap = 0;
181	pVM->hwaccm.s.svm.pMSRBitmapPhys = 0;
182	pVM->hwaccm.s.svm.pMemObjMSRBitmap = 0;
183	}
184	return VINF_SUCCESS;
185	}
186
187	/**
188	* Sets up AMD-V for the specified VM
189	*
190	* @returns VBox status code.
191	* @param pVM The VM to operate on.
192	*/
193	HWACCMR0DECL(int) SVMR0SetupVM(PVM pVM)
194	{
195	int rc = VINF_SUCCESS;
196	SVM_VMCB *pVMCB;
197
198	AssertReturn(pVM, VERR_INVALID_PARAMETER);
199
200	Assert(pVM->hwaccm.s.svm.fSupported);
201
202	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
203	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
204
205	/* Program the control fields. Most of them never have to be changed again. */
206	/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
207	/** @note CR0 & CR4 can be safely read when guest and shadow copies are identical. */
208	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(8);
209
210	/*
211	* CR0/3/4 writes must be intercepted for obvious reasons.
212	*/
213	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(8);
214
215	/* Intercept all DRx reads and writes. */
216	pVMCB->ctrl.u16InterceptRdDRx = RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7);
217	pVMCB->ctrl.u16InterceptWrDRx = RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7);
218
219	/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
220	* All breakpoints are automatically cleared when the VM exits.
221	*/
222
223	/** @todo nested paging */
224	/* Intercept #NM only; #PF is not relevant due to nested paging (we get a seperate exit code (SVM_EXIT_NPF) for
225	* pagefaults that need our attention).
226	*/
227	pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
228
229	pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
230	\| SVM_CTRL1_INTERCEPT_VINTR
231	\| SVM_CTRL1_INTERCEPT_NMI
232	\| SVM_CTRL1_INTERCEPT_SMI
233	\| SVM_CTRL1_INTERCEPT_INIT
234	\| SVM_CTRL1_INTERCEPT_CR0 /** @todo redundant? */
235	\| SVM_CTRL1_INTERCEPT_RDPMC
236	\| SVM_CTRL1_INTERCEPT_CPUID
237	\| SVM_CTRL1_INTERCEPT_RSM
238	\| SVM_CTRL1_INTERCEPT_HLT
239	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
240	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
241	\| SVM_CTRL1_INTERCEPT_INVLPG
242	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
243	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
244	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
245	;
246	pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
247	\| SVM_CTRL2_INTERCEPT_VMMCALL
248	\| SVM_CTRL2_INTERCEPT_VMLOAD
249	\| SVM_CTRL2_INTERCEPT_VMSAVE
250	\| SVM_CTRL2_INTERCEPT_STGI
251	\| SVM_CTRL2_INTERCEPT_CLGI
252	\| SVM_CTRL2_INTERCEPT_SKINIT
253	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
254	;
255	Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
256	Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
257	Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
258
259	/* Virtualize masking of INTR interrupts. */
260	pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
261
262	/* Set IO and MSR bitmap addresses. */
263	pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
264	pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
265
266	/* Enable nested paging. */
267	/** @todo how to detect support for this?? */
268	pVMCB->ctrl.u64NestedPaging = 0; /** @todo SVM_NESTED_PAGING_ENABLE; */
269
270	/* No LBR virtualization. */
271	pVMCB->ctrl.u64LBRVirt = 0;
272
273	return rc;
274	}
275
276
277	/**
278	* Injects an event (trap or external interrupt)
279	*
280	* @param pVM The VM to operate on.
281	* @param pVMCB SVM control block
282	* @param pCtx CPU Context
283	* @param pIntInfo SVM interrupt info
284	*/
285	inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx, SVM_EVENT* pEvent)
286	{
287	#ifdef VBOX_STRICT
288	if (pEvent->n.u8Vector == 0xE)
289	Log(("SVM: Inject int %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
290	else
291	if (pEvent->n.u8Vector < 0x20)
292	Log(("SVM: Inject int %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode));
293	else
294	{
295	Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->eip));
296	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
297	Assert(pCtx->eflags.u32 & X86_EFL_IF);
298	}
299	#endif
300
301	/* Set event injection state. */
302	pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
303	}
304
305
306	/**
307	* Checks for pending guest interrupts and injects them
308	*
309	* @returns VBox status code.
310	* @param pVM The VM to operate on.
311	* @param pVMCB SVM control block
312	* @param pCtx CPU Context
313	*/
314	static int SVMR0CheckPendingInterrupt(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx)
315	{
316	int rc;
317
318	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
319	if (pVM->hwaccm.s.Event.fPending)
320	{
321	SVM_EVENT Event;
322
323	Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
324	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
325	Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
326	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
327
328	pVM->hwaccm.s.Event.fPending = false;
329	return VINF_SUCCESS;
330	}
331
332	/* When external interrupts are pending, we should exit the VM when IF is set. */
333	if ( !TRPMHasTrap(pVM)
334	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
335	{
336	if (!(pCtx->eflags.u32 & X86_EFL_IF))
337	{
338	Log2(("Enable irq window exit!\n"));
339	/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
340	//// pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
341	//// AssertRC(rc);
342	}
343	else
344	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
345	{
346	uint8_t u8Interrupt;
347
348	rc = PDMGetInterrupt(pVM, &u8Interrupt);
349	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
350	if (VBOX_SUCCESS(rc))
351	{
352	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
353	AssertRC(rc);
354	}
355	else
356	{
357	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
358	Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)));
359	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
360	/* Just continue */
361	}
362	}
363	else
364	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
365	}
366
367	#ifdef VBOX_STRICT
368	if (TRPMHasTrap(pVM))
369	{
370	uint8_t u8Vector;
371	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
372	AssertRC(rc);
373	}
374	#endif
375
376	if ( pCtx->eflags.u32 & X86_EFL_IF
377	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
378	&& TRPMHasTrap(pVM)
379	)
380	{
381	uint8_t u8Vector;
382	int rc;
383	TRPMEVENT enmType;
384	SVM_EVENT Event;
385	uint32_t u32ErrorCode;
386
387	Event.au64[0] = 0;
388
389	/* If a new event is pending, then dispatch it now. */
390	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &u32ErrorCode, 0);
391	AssertRC(rc);
392	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
393	Assert(enmType != TRPM_SOFTWARE_INT);
394
395	/* Clear the pending trap. */
396	rc = TRPMResetTrap(pVM);
397	AssertRC(rc);
398
399	Event.n.u8Vector = u8Vector;
400	Event.n.u1Valid = 1;
401	Event.n.u32ErrorCode = u32ErrorCode;
402
403	if (enmType == TRPM_TRAP)
404	{
405	switch (u8Vector) {
406	case 8:
407	case 10:
408	case 11:
409	case 12:
410	case 13:
411	case 14:
412	case 17:
413	/* Valid error codes. */
414	Event.n.u1ErrorCodeValid = 1;
415	break;
416	default:
417	break;
418	}
419	if (u8Vector == X86_XCPT_NMI)
420	Event.n.u3Type = SVM_EVENT_NMI;
421	else
422	Event.n.u3Type = SVM_EVENT_EXCEPTION;
423	}
424	else
425	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
426
427	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
428	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
429	} /* if (interrupts can be dispatched) */
430
431	return VINF_SUCCESS;
432	}
433
434
435	/**
436	* Loads the guest state
437	*
438	* @returns VBox status code.
439	* @param pVM The VM to operate on.
440	* @param pCtx Guest context
441	*/
442	HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
443	{
444	RTGCUINTPTR val;
445	SVM_VMCB *pVMCB;
446
447	if (pVM == NULL)
448	return VERR_INVALID_PARAMETER;
449
450	/* Setup AMD SVM. */
451	Assert(pVM->hwaccm.s.svm.fSupported);
452
453	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
454	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
455
456	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
457	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
458	{
459	SVM_WRITE_SELREG(CS, cs);
460	SVM_WRITE_SELREG(SS, ss);
461	SVM_WRITE_SELREG(DS, ds);
462	SVM_WRITE_SELREG(ES, es);
463	SVM_WRITE_SELREG(FS, fs);
464	SVM_WRITE_SELREG(GS, gs);
465	}
466
467	/* Guest CPU context: LDTR. */
468	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
469	{
470	SVM_WRITE_SELREG(LDTR, ldtr);
471	}
472
473	/* Guest CPU context: TR. */
474	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
475	{
476	SVM_WRITE_SELREG(TR, tr);
477	}
478
479	/* Guest CPU context: GDTR. */
480	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
481	{
482	pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
483	pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
484	}
485
486	/* Guest CPU context: IDTR. */
487	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
488	{
489	pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
490	pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
491	}
492
493	/*
494	* Sysenter MSRs
495	*/
496	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
497	{
498	pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
499	pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
500	pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
501	}
502
503	/* Control registers */
504	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
505	{
506	val = pCtx->cr0;
507	if (CPUMIsGuestFPUStateActive(pVM) == false)
508	{
509	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
510	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
511	}
512	else
513	{
514	Assert(pVM->hwaccm.s.svm.fResumeVM == true);
515	/** @todo check if we support the old style mess correctly. */
516	if (!(val & X86_CR0_NE))
517	{
518	Log(("Forcing X86_CR0_NE!!!\n"));
519
520	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
521	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
522	{
523	pVMCB->ctrl.u32InterceptException \|= RT_BIT(16);
524	pVM->hwaccm.s.fFPUOldStyleOverride = true;
525	}
526	}
527	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
528	}
529	if (!(val & X86_CR0_CD))
530	val &= ~X86_CR0_NW; /* Illegal when cache is turned on. */
531
532	val \|= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
533	val \|= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
534	pVMCB->guest.u64CR0 = val;
535	}
536	/* CR2 as well */
537	pVMCB->guest.u64CR2 = pCtx->cr2;
538
539	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
540	{
541	/* Save our shadow CR3 register. */
542	pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
543	}
544
545	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
546	{
547	val = pCtx->cr4;
548	switch(pVM->hwaccm.s.enmShadowMode)
549	{
550	case PGMMODE_REAL:
551	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
552	AssertFailed();
553	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
554
555	case PGMMODE_32_BIT: /* 32-bit paging. */
556	break;
557
558	case PGMMODE_PAE: /* PAE paging. */
559	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
560	/** @todo use normal 32 bits paging */
561	val \|= X86_CR4_PAE;
562	break;
563
564	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
565	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
566	AssertFailed();
567	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
568
569	default: /* shut up gcc */
570	AssertFailed();
571	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
572	}
573	pVMCB->guest.u64CR4 = val;
574	}
575
576	/* Debug registers. */
577	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
578	{
579	/** @todo DR0-6 */
580	val = pCtx->dr7;
581	val &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
582	val \|= 0x400; /* must be one */
583	#ifdef VBOX_STRICT
584	val = 0x400;
585	#endif
586	pVMCB->guest.u64DR7 = val;
587
588	pVMCB->guest.u64DR6 = pCtx->dr6;
589	}
590
591	/* EIP, ESP and EFLAGS */
592	pVMCB->guest.u64RIP = pCtx->eip;
593	pVMCB->guest.u64RSP = pCtx->esp;
594	pVMCB->guest.u64RFlags = pCtx->eflags.u32;
595
596	/* Set CPL */
597	pVMCB->guest.u8CPL = pCtx->ssHid.Attr.n.u2Dpl;
598
599	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
600	pVMCB->guest.u64RAX = pCtx->eax;
601
602	/* vmrun will fail otherwise. */
603	pVMCB->guest.u64EFER = MSR_K6_EFER_SVME;
604
605	/** @note We can do more complex things with tagged TLBs. */
606	pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
607
608	/** TSC offset. */
609	if (TMCpuTickCanUseRealTSC(pVM, &pVMCB->ctrl.u64TSCOffset))
610	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
611	else
612	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
613
614	/** @todo 64 bits stuff (?):
615	* - STAR
616	* - LSTAR
617	* - CSTAR
618	* - SFMASK
619	* - KernelGSBase
620	*/
621
622	#ifdef DEBUG
623	/* Intercept X86_XCPT_DB if stepping is enabled */
624	if (DBGFIsStepping(pVM))
625	pVMCB->ctrl.u32InterceptException \|= RT_BIT(1);
626	else
627	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(1);
628	#endif
629
630	/* Done. */
631	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
632
633	return VINF_SUCCESS;
634	}
635
636
637	/**
638	* Runs guest code in an SVM VM.
639	*
640	* @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
641	*
642	* @returns VBox status code.
643	* @param pVM The VM to operate on.
644	* @param pCtx Guest context
645	*/
646	HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
647	{
648	int rc = VINF_SUCCESS;
649	uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
650	SVM_VMCB *pVMCB;
651	bool fForceTLBFlush = false;
652	bool fGuestStateSynced = false;
653	unsigned cResume = 0;
654
655	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
656
657	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
658	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
659
660	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
661	*/
662	ResumeExecution:
663	/* Safety precaution; looping for too long here can have a very bad effect on the host */
664	if (++cResume > HWACCM_MAX_RESUME_LOOPS)
665	{
666	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
667	rc = VINF_EM_RAW_INTERRUPT;
668	goto end;
669	}
670
671	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
672	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
673	{
674	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
675	if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
676	{
677	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
678	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
679	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
680	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
681	*/
682	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
683	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
684	pVMCB->ctrl.u64IntShadow = 0;
685	}
686	}
687	else
688	{
689	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
690	pVMCB->ctrl.u64IntShadow = 0;
691	}
692
693	/* Check for pending actions that force us to go back to ring 3. */
694	#ifdef DEBUG
695	/* Intercept X86_XCPT_DB if stepping is enabled */
696	if (!DBGFIsStepping(pVM))
697	#endif
698	{
699	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
700	{
701	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
702	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
703	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
704	rc = VINF_EM_RAW_TO_R3;
705	goto end;
706	}
707	}
708
709	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
710	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
711	{
712	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
713	rc = VINF_EM_PENDING_REQUEST;
714	goto end;
715	}
716
717	/* When external interrupts are pending, we should exit the VM when IF is set. */
718	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
719	rc = SVMR0CheckPendingInterrupt(pVM, pVMCB, pCtx);
720	if (VBOX_FAILURE(rc))
721	{
722	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
723	goto end;
724	}
725
726	/* Load the guest state */
727	rc = SVMR0LoadGuestState(pVM, pCtx);
728	if (rc != VINF_SUCCESS)
729	{
730	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
731	goto end;
732	}
733	fGuestStateSynced = true;
734
735	/* All done! Let's start VM execution. */
736	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
737
738	/** Erratum #170 -> must force a TLB flush */
739	/** @todo supposed to be fixed in future by AMD */
740	fForceTLBFlush = true;
741
742	if ( pVM->hwaccm.s.svm.fResumeVM == false
743	\|\| fForceTLBFlush)
744	{
745	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1;
746	}
747	else
748	{
749	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 0;
750	}
751	/* In case we execute a goto ResumeExecution later on. */
752	pVM->hwaccm.s.svm.fResumeVM = true;
753	fForceTLBFlush = false;
754
755	Assert(sizeof(pVM->hwaccm.s.svm.pVMCBPhys) == 8);
756	Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
757	\| SVM_CTRL2_INTERCEPT_VMMCALL
758	\| SVM_CTRL2_INTERCEPT_VMLOAD
759	\| SVM_CTRL2_INTERCEPT_VMSAVE
760	\| SVM_CTRL2_INTERCEPT_STGI
761	\| SVM_CTRL2_INTERCEPT_CLGI
762	\| SVM_CTRL2_INTERCEPT_SKINIT
763	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
764	));
765	Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
766	Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
767	Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
768	Assert(pVMCB->ctrl.u64NestedPaging == 0);
769	Assert(pVMCB->ctrl.u64LBRVirt == 0);
770
771	SVMVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);
772	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
773
774	/**
775	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
776	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
777	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
778	*/
779
780	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
781
782	/* Reason for the VM exit */
783	exitCode = pVMCB->ctrl.u64ExitCode;
784
785	if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
786	{
787	HWACCMDumpRegs(pCtx);
788	#ifdef DEBUG
789	Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
790	Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
791	Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
792	Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
793	Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
794	Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
795	Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
796	Log(("ctrl.u64IOPMPhysAddr %VX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
797	Log(("ctrl.u64MSRPMPhysAddr %VX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
798	Log(("ctrl.u64TSCOffset %VX64\n", pVMCB->ctrl.u64TSCOffset));
799
800	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
801	Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
802	Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
803	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
804
805	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
806	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
807	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
808	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
809	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
810	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
811	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
812	Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
813	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
814	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
815
816	Log(("ctrl.u64IntShadow %VX64\n", pVMCB->ctrl.u64IntShadow));
817	Log(("ctrl.u64ExitCode %VX64\n", pVMCB->ctrl.u64ExitCode));
818	Log(("ctrl.u64ExitInfo1 %VX64\n", pVMCB->ctrl.u64ExitInfo1));
819	Log(("ctrl.u64ExitInfo2 %VX64\n", pVMCB->ctrl.u64ExitInfo2));
820	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
821	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
822	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
823	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
824	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
825	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
826	Log(("ctrl.u64NestedPaging %VX64\n", pVMCB->ctrl.u64NestedPaging));
827	Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
828	Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
829	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
830	Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
831	Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
832	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
833
834	Log(("ctrl.u64HostCR3 %VX64\n", pVMCB->ctrl.u64HostCR3));
835	Log(("ctrl.u64LBRVirt %VX64\n", pVMCB->ctrl.u64LBRVirt));
836
837	Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
838	Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
839	Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
840	Log(("guest.CS.u64Base %VX64\n", pVMCB->guest.CS.u64Base));
841	Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
842	Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
843	Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
844	Log(("guest.DS.u64Base %VX64\n", pVMCB->guest.DS.u64Base));
845	Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
846	Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
847	Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
848	Log(("guest.ES.u64Base %VX64\n", pVMCB->guest.ES.u64Base));
849	Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
850	Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
851	Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
852	Log(("guest.FS.u64Base %VX64\n", pVMCB->guest.FS.u64Base));
853	Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
854	Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
855	Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
856	Log(("guest.GS.u64Base %VX64\n", pVMCB->guest.GS.u64Base));
857
858	Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
859	Log(("guest.GDTR.u64Base %VX64\n", pVMCB->guest.GDTR.u64Base));
860
861	Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
862	Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
863	Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
864	Log(("guest.LDTR.u64Base %VX64\n", pVMCB->guest.LDTR.u64Base));
865
866	Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
867	Log(("guest.IDTR.u64Base %VX64\n", pVMCB->guest.IDTR.u64Base));
868
869	Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
870	Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
871	Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
872	Log(("guest.TR.u64Base %VX64\n", pVMCB->guest.TR.u64Base));
873
874	Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
875	Log(("guest.u64CR0 %VX64\n", pVMCB->guest.u64CR0));
876	Log(("guest.u64CR2 %VX64\n", pVMCB->guest.u64CR2));
877	Log(("guest.u64CR3 %VX64\n", pVMCB->guest.u64CR3));
878	Log(("guest.u64CR4 %VX64\n", pVMCB->guest.u64CR4));
879	Log(("guest.u64DR6 %VX64\n", pVMCB->guest.u64DR6));
880	Log(("guest.u64DR7 %VX64\n", pVMCB->guest.u64DR7));
881
882	Log(("guest.u64RIP %VX64\n", pVMCB->guest.u64RIP));
883	Log(("guest.u64RSP %VX64\n", pVMCB->guest.u64RSP));
884	Log(("guest.u64RAX %VX64\n", pVMCB->guest.u64RAX));
885	Log(("guest.u64RFlags %VX64\n", pVMCB->guest.u64RFlags));
886
887	Log(("guest.u64SysEnterCS %VX64\n", pVMCB->guest.u64SysEnterCS));
888	Log(("guest.u64SysEnterEIP %VX64\n", pVMCB->guest.u64SysEnterEIP));
889	Log(("guest.u64SysEnterESP %VX64\n", pVMCB->guest.u64SysEnterESP));
890
891	Log(("guest.u64EFER %VX64\n", pVMCB->guest.u64EFER));
892	Log(("guest.u64STAR %VX64\n", pVMCB->guest.u64STAR));
893	Log(("guest.u64LSTAR %VX64\n", pVMCB->guest.u64LSTAR));
894	Log(("guest.u64CSTAR %VX64\n", pVMCB->guest.u64CSTAR));
895	Log(("guest.u64SFMASK %VX64\n", pVMCB->guest.u64SFMASK));
896	Log(("guest.u64KernelGSBase %VX64\n", pVMCB->guest.u64KernelGSBase));
897	Log(("guest.u64GPAT %VX64\n", pVMCB->guest.u64GPAT));
898	Log(("guest.u64DBGCTL %VX64\n", pVMCB->guest.u64DBGCTL));
899	Log(("guest.u64BR_FROM %VX64\n", pVMCB->guest.u64BR_FROM));
900	Log(("guest.u64BR_TO %VX64\n", pVMCB->guest.u64BR_TO));
901	Log(("guest.u64LASTEXCPFROM %VX64\n", pVMCB->guest.u64LASTEXCPFROM));
902	Log(("guest.u64LASTEXCPTO %VX64\n", pVMCB->guest.u64LASTEXCPTO));
903
904	#endif
905	rc = VERR_SVM_UNABLE_TO_START_VM;
906	goto end;
907	}
908
909	/* Let's first sync back eip, esp, and eflags. */
910	pCtx->eip = pVMCB->guest.u64RIP;
911	pCtx->esp = pVMCB->guest.u64RSP;
912	pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
913	/* eax is saved/restore across the vmrun instruction */
914	pCtx->eax = pVMCB->guest.u64RAX;
915
916	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
917	SVM_READ_SELREG(SS, ss);
918	SVM_READ_SELREG(CS, cs);
919	SVM_READ_SELREG(DS, ds);
920	SVM_READ_SELREG(ES, es);
921	SVM_READ_SELREG(FS, fs);
922	SVM_READ_SELREG(GS, gs);
923
924	/** @note no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
925
926	/** @note NOW IT'S SAFE FOR LOGGING! */
927
928	/* Take care of instruction fusing (sti, mov ss) */
929	if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
930	{
931	Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->eip));
932	EMSetInhibitInterruptsPC(pVM, pCtx->eip);
933	}
934	else
935	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
936
937	Log2(("exitCode = %x\n", exitCode));
938
939	/* Check if an injected event was interrupted prematurely. */
940	pVM->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
941	if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
942	&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
943	{
944	Log(("Pending inject %VX64 at %08x exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitCode));
945	pVM->hwaccm.s.Event.fPending = true;
946	/* Error code present? (redundant) */
947	if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
948	{
949	pVM->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
950	}
951	else
952	pVM->hwaccm.s.Event.errCode = 0;
953	}
954	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
955
956	/* Deal with the reason of the VM-exit. */
957	switch (exitCode)
958	{
959	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
960	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
961	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
962	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
963	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
964	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
965	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
966	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
967	{
968	/* Pending trap. */
969	SVM_EVENT Event;
970	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
971
972	Log2(("Hardware/software interrupt %d\n", vector));
973	switch (vector)
974	{
975	#ifdef DEBUG
976	case X86_XCPT_DB:
977	rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), pVMCB->guest.u64DR6);
978	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
979	break;
980	#endif
981
982	case X86_XCPT_NM:
983	{
984	uint32_t oldCR0;
985
986	Log(("#NM fault at %VGv\n", pCtx->eip));
987
988	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
989	oldCR0 = ASMGetCR0();
990	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
991	rc = CPUMHandleLazyFPU(pVM);
992	if (rc == VINF_SUCCESS)
993	{
994	Assert(CPUMIsGuestFPUStateActive(pVM));
995
996	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
997	ASMSetCR0(oldCR0);
998
999	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1000
1001	/* Continue execution. */
1002	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1003	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1004
1005	goto ResumeExecution;
1006	}
1007
1008	Log(("Forward #NM fault to the guest\n"));
1009	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1010
1011	Event.au64[0] = 0;
1012	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1013	Event.n.u1Valid = 1;
1014	Event.n.u8Vector = X86_XCPT_NM;
1015
1016	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1017	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1018	goto ResumeExecution;
1019	}
1020
1021	case X86_XCPT_PF: /* Page fault */
1022	{
1023	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1024	RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1025
1026	Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
1027	/* Exit qualification contains the linear address of the page fault. */
1028	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1029	TRPMSetErrorCode(pVM, errCode);
1030	TRPMSetFaultAddress(pVM, uFaultAddress);
1031
1032	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1033	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1034	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
1035	if (rc == VINF_SUCCESS)
1036	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1037	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
1038	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1039
1040	TRPMResetTrap(pVM);
1041
1042	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1043	goto ResumeExecution;
1044	}
1045	else
1046	if (rc == VINF_EM_RAW_GUEST_TRAP)
1047	{ /* A genuine pagefault.
1048	* Forward the trap to the guest by injecting the exception and resuming execution.
1049	*/
1050	Log2(("Forward page fault to the guest\n"));
1051	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1052	/* The error code might have been changed. */
1053	errCode = TRPMGetErrorCode(pVM);
1054
1055	TRPMResetTrap(pVM);
1056
1057	/* Now we must update CR2. */
1058	pCtx->cr2 = uFaultAddress;
1059
1060	Event.au64[0] = 0;
1061	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1062	Event.n.u1Valid = 1;
1063	Event.n.u8Vector = X86_XCPT_PF;
1064	Event.n.u1ErrorCodeValid = 1;
1065	Event.n.u32ErrorCode = errCode;
1066
1067	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1068
1069	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1070	goto ResumeExecution;
1071	}
1072	#ifdef VBOX_STRICT
1073	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1074	Log(("PGMTrap0eHandler failed with %d\n", rc));
1075	#endif
1076	/* Need to go back to the recompiler to emulate the instruction. */
1077	TRPMResetTrap(pVM);
1078	break;
1079	}
1080
1081	case X86_XCPT_MF: /* Floating point exception. */
1082	{
1083	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1084	if (!(pCtx->cr0 & X86_CR0_NE))
1085	{
1086	/* old style FPU error reporting needs some extra work. */
1087	/** @todo don't fall back to the recompiler, but do it manually. */
1088	rc = VINF_EM_RAW_EMULATE_INSTR;
1089	break;
1090	}
1091	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1092
1093	Event.au64[0] = 0;
1094	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1095	Event.n.u1Valid = 1;
1096	Event.n.u8Vector = X86_XCPT_MF;
1097
1098	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1099
1100	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1101	goto ResumeExecution;
1102	}
1103
1104	#ifdef VBOX_STRICT
1105	case X86_XCPT_GP: /* General protection failure exception.*/
1106	case X86_XCPT_UD: /* Unknown opcode exception. */
1107	case X86_XCPT_DE: /* Debug exception. */
1108	case X86_XCPT_SS: /* Stack segment exception. */
1109	case X86_XCPT_NP: /* Segment not present exception. */
1110	{
1111	Event.au64[0] = 0;
1112	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1113	Event.n.u1Valid = 1;
1114	Event.n.u8Vector = vector;
1115
1116	switch(vector)
1117	{
1118	case X86_XCPT_GP:
1119	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1120	Event.n.u1ErrorCodeValid = 1;
1121	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1122	break;
1123	case X86_XCPT_DE:
1124	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1125	break;
1126	case X86_XCPT_UD:
1127	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1128	break;
1129	case X86_XCPT_SS:
1130	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1131	Event.n.u1ErrorCodeValid = 1;
1132	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1133	break;
1134	case X86_XCPT_NP:
1135	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1136	Event.n.u1ErrorCodeValid = 1;
1137	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1138	break;
1139	}
1140	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1141	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1142
1143	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1144	goto ResumeExecution;
1145	}
1146	#endif
1147	default:
1148	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1149	rc = VERR_EM_INTERNAL_ERROR;
1150	break;
1151
1152	} /* switch (vector) */
1153	break;
1154	}
1155
1156	case SVM_EXIT_FERR_FREEZE:
1157	case SVM_EXIT_INTR:
1158	case SVM_EXIT_NMI:
1159	case SVM_EXIT_SMI:
1160	case SVM_EXIT_INIT:
1161	case SVM_EXIT_VINTR:
1162	/* External interrupt; leave to allow it to be dispatched again. */
1163	rc = VINF_EM_RAW_INTERRUPT;
1164	break;
1165
1166	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1167	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1168	/* Skip instruction and continue directly. */
1169	pCtx->eip += 2; /** @note hardcoded opcode size! */
1170	/* Continue execution.*/
1171	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1172	goto ResumeExecution;
1173
1174	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1175	{
1176	Log2(("SVM: Cpuid %x\n", pCtx->eax));
1177	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1178	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1179	if (rc == VINF_SUCCESS)
1180	{
1181	/* Update EIP and continue execution. */
1182	pCtx->eip += 2; /** @note hardcoded opcode size! */
1183	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1184	goto ResumeExecution;
1185	}
1186	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1187	rc = VINF_EM_RAW_EMULATE_INSTR;
1188	break;
1189	}
1190
1191	case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1192	{
1193	Log2(("SVM: Rdtsc\n"));
1194	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1195	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1196	if (rc == VINF_SUCCESS)
1197	{
1198	/* Update EIP and continue execution. */
1199	pCtx->eip += 2; /** @note hardcoded opcode size! */
1200	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1201	goto ResumeExecution;
1202	}
1203	AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1204	rc = VINF_EM_RAW_EMULATE_INSTR;
1205	break;
1206	}
1207
1208	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1209	{
1210	Log2(("SVM: invlpg\n"));
1211	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1212
1213	/* Truly a pita. Why can't SVM give the same information as VMX? */
1214	rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1215	if (rc == VINF_SUCCESS)
1216	goto ResumeExecution; /* eip already updated */
1217	break;
1218	}
1219
1220	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1221	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1222	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1223	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1224	{
1225	uint32_t cbSize;
1226
1227	Log2(("SVM: %VGv mov cr%d, \n", pCtx->eip, exitCode - SVM_EXIT_WRITE_CR0));
1228	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1229	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1230
1231	switch (exitCode - SVM_EXIT_WRITE_CR0)
1232	{
1233	case 0:
1234	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1235	break;
1236	case 2:
1237	break;
1238	case 3:
1239	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1240	break;
1241	case 4:
1242	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1243	break;
1244	default:
1245	AssertFailed();
1246	}
1247	/* Check if a sync operation is pending. */
1248	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1249	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1250	{
1251	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1252	AssertRC(rc);
1253
1254	/** @note Force a TLB flush. SVM requires us to do it manually. */
1255	fForceTLBFlush = true;
1256	}
1257	if (rc == VINF_SUCCESS)
1258	{
1259	/* EIP has been updated already. */
1260
1261	/* Only resume if successful. */
1262	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1263	goto ResumeExecution;
1264	}
1265	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1266	break;
1267	}
1268
1269	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1270	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1271	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1272	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1273	{
1274	uint32_t cbSize;
1275
1276	Log2(("SVM: %VGv mov x, cr%d\n", pCtx->eip, exitCode - SVM_EXIT_READ_CR0));
1277	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1278	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1279	if (rc == VINF_SUCCESS)
1280	{
1281	/* EIP has been updated already. */
1282
1283	/* Only resume if successful. */
1284	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1285	goto ResumeExecution;
1286	}
1287	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1288	break;
1289	}
1290
1291	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1292	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1293	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1294	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1295	{
1296	uint32_t cbSize;
1297
1298	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_WRITE_DR0));
1299	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1300	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1301	if (rc == VINF_SUCCESS)
1302	{
1303	/* EIP has been updated already. */
1304
1305	/* Only resume if successful. */
1306	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1307	goto ResumeExecution;
1308	}
1309	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1310	break;
1311	}
1312
1313	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1314	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1315	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1316	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1317	{
1318	uint32_t cbSize;
1319
1320	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_READ_DR0));
1321	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1322	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1323	if (rc == VINF_SUCCESS)
1324	{
1325	/* EIP has been updated already. */
1326
1327	/* Only resume if successful. */
1328	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1329	goto ResumeExecution;
1330	}
1331	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1332	break;
1333	}
1334
1335	/* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1336	case SVM_EXIT_IOIO: /* I/O instruction. */
1337	{
1338	SVM_IOIO_EXIT IoExitInfo;
1339	uint32_t uIOSize, uAndVal;
1340
1341	IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1342
1343	/** @todo could use a lookup table here */
1344	if (IoExitInfo.n.u1OP8)
1345	{
1346	uIOSize = 1;
1347	uAndVal = 0xff;
1348	}
1349	else
1350	if (IoExitInfo.n.u1OP16)
1351	{
1352	uIOSize = 2;
1353	uAndVal = 0xffff;
1354	}
1355	else
1356	if (IoExitInfo.n.u1OP32)
1357	{
1358	uIOSize = 4;
1359	uAndVal = 0xffffffff;
1360	}
1361	else
1362	{
1363	AssertFailed(); /* should be fatal. */
1364	rc = VINF_EM_RAW_EMULATE_INSTR;
1365	break;
1366	}
1367
1368	if (IoExitInfo.n.u1STR)
1369	{
1370	/* ins/outs */
1371	uint32_t prefix = 0;
1372	if (IoExitInfo.n.u1REP)
1373	prefix \|= PREFIX_REP;
1374
1375	if (IoExitInfo.n.u1Type == 0)
1376	{
1377	Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1378	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1379	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1380	}
1381	else
1382	{
1383	Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1384	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1385	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1386	}
1387	}
1388	else
1389	{
1390	/* normal in/out */
1391	Assert(!IoExitInfo.n.u1REP);
1392
1393	if (IoExitInfo.n.u1Type == 0)
1394	{
1395	Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1396	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1397	rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1398	}
1399	else
1400	{
1401	uint32_t u32Val = 0;
1402
1403	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1404	rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1405	if (IOM_SUCCESS(rc))
1406	{
1407	/* Write back to the EAX register. */
1408	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1409	Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1410	}
1411	}
1412	}
1413	/*
1414	* Handled the I/O return codes.
1415	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1416	*/
1417	if (IOM_SUCCESS(rc))
1418	{
1419	/* Update EIP and continue execution. */
1420	pCtx->eip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1421	if (RT_LIKELY(rc == VINF_SUCCESS))
1422	{
1423	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1424	goto ResumeExecution;
1425	}
1426	Log2(("EM status from IO at %VGv %x size %d: %Vrc\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize, rc));
1427	break;
1428	}
1429
1430	#ifdef VBOX_STRICT
1431	if (rc == VINF_IOM_HC_IOPORT_READ)
1432	Assert(IoExitInfo.n.u1Type != 0);
1433	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1434	Assert(IoExitInfo.n.u1Type == 0);
1435	else
1436	AssertMsg(VBOX_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1437	#endif
1438	Log2(("Failed IO at %VGv %x size %d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1439	break;
1440	}
1441
1442	case SVM_EXIT_HLT:
1443	/** Check if external interrupts are pending; if so, don't switch back. */
1444	if (VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1445	{
1446	pCtx->eip++; /* skip hlt */
1447	goto ResumeExecution;
1448	}
1449
1450	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1451	break;
1452
1453	case SVM_EXIT_RDPMC:
1454	case SVM_EXIT_RSM:
1455	case SVM_EXIT_INVLPGA:
1456	case SVM_EXIT_VMRUN:
1457	case SVM_EXIT_VMMCALL:
1458	case SVM_EXIT_VMLOAD:
1459	case SVM_EXIT_VMSAVE:
1460	case SVM_EXIT_STGI:
1461	case SVM_EXIT_CLGI:
1462	case SVM_EXIT_SKINIT:
1463	case SVM_EXIT_RDTSCP:
1464	{
1465	/* Unsupported instructions. */
1466	SVM_EVENT Event;
1467
1468	Event.au64[0] = 0;
1469	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1470	Event.n.u1Valid = 1;
1471	Event.n.u8Vector = X86_XCPT_UD;
1472
1473	Log(("Forced #UD trap at %VGv\n", pCtx->eip));
1474	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1475
1476	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1477	goto ResumeExecution;
1478	}
1479
1480	/* Emulate RDMSR & WRMSR in ring 3. */
1481	case SVM_EXIT_MSR:
1482	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1483	break;
1484
1485	case SVM_EXIT_NPF:
1486	AssertFailed(); /* unexpected */
1487	break;
1488
1489	case SVM_EXIT_SHUTDOWN:
1490	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1491	break;
1492
1493	case SVM_EXIT_PAUSE:
1494	case SVM_EXIT_IDTR_READ:
1495	case SVM_EXIT_GDTR_READ:
1496	case SVM_EXIT_LDTR_READ:
1497	case SVM_EXIT_TR_READ:
1498	case SVM_EXIT_IDTR_WRITE:
1499	case SVM_EXIT_GDTR_WRITE:
1500	case SVM_EXIT_LDTR_WRITE:
1501	case SVM_EXIT_TR_WRITE:
1502	case SVM_EXIT_CR0_SEL_WRITE:
1503	default:
1504	/* Unexpected exit codes. */
1505	rc = VERR_EM_INTERNAL_ERROR;
1506	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
1507	break;
1508	}
1509
1510	end:
1511	if (fGuestStateSynced)
1512	{
1513	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1514	SVM_READ_SELREG(LDTR, ldtr);
1515	SVM_READ_SELREG(TR, tr);
1516
1517	pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1518	pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1519
1520	pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1521	pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1522
1523	/*
1524	* System MSRs
1525	*/
1526	pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1527	pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1528	pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1529	}
1530
1531	/* Signal changes for the recompiler. */
1532	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
1533
1534	/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
1535	if (exitCode == SVM_EXIT_INTR)
1536	{
1537	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1538	/* On the next entry we'll only sync the host context. */
1539	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
1540	}
1541	else
1542	{
1543	/* On the next entry we'll sync everything. */
1544	/** @todo we can do better than this */
1545	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
1546	}
1547
1548	/* translate into a less severe return code */
1549	if (rc == VERR_EM_INTERPRETER)
1550	rc = VINF_EM_RAW_EMULATE_INSTR;
1551
1552	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1553	return rc;
1554	}
1555
1556	/**
1557	* Enters the AMD-V session
1558	*
1559	* @returns VBox status code.
1560	* @param pVM The VM to operate on.
1561	*/
1562	HWACCMR0DECL(int) SVMR0Enter(PVM pVM)
1563	{
1564	Assert(pVM->hwaccm.s.svm.fSupported);
1565
1566	/* Force a TLB flush on VM entry. */
1567	pVM->hwaccm.s.svm.fResumeVM = false;
1568
1569	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
1570	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_LDTR;
1571
1572	return VINF_SUCCESS;
1573	}
1574
1575
1576	/**
1577	* Leaves the AMD-V session
1578	*
1579	* @returns VBox status code.
1580	* @param pVM The VM to operate on.
1581	*/
1582	HWACCMR0DECL(int) SVMR0Leave(PVM pVM)
1583	{
1584	Assert(pVM->hwaccm.s.svm.fSupported);
1585	return VINF_SUCCESS;
1586	}
1587
1588
1589	static int svmInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1590	{
1591	OP_PARAMVAL param1;
1592	RTGCPTR addr;
1593
1594	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1595	if(VBOX_FAILURE(rc))
1596	return VERR_EM_INTERPRETER;
1597
1598	switch(param1.type)
1599	{
1600	case PARMTYPE_IMMEDIATE:
1601	case PARMTYPE_ADDRESS:
1602	if(!(param1.flags & PARAM_VAL32))
1603	return VERR_EM_INTERPRETER;
1604	addr = (RTGCPTR)param1.val.val32;
1605	break;
1606
1607	default:
1608	return VERR_EM_INTERPRETER;
1609	}
1610
1611	/** @todo is addr always a flat linear address or ds based
1612	* (in absence of segment override prefixes)????
1613	*/
1614	rc = PGMInvalidatePage(pVM, addr);
1615	if (VBOX_SUCCESS(rc))
1616	{
1617	/* Manually invalidate the page for the VM's TLB. */
1618	SVMInvlpgA(addr, uASID);
1619	return VINF_SUCCESS;
1620	}
1621	/** @todo r=bird: we shouldn't ignore returns codes like this... I'm 99% sure the error is fatal. */
1622	return VERR_EM_INTERPRETER;
1623	}
1624
1625	/**
1626	* Interprets INVLPG
1627	*
1628	* @returns VBox status code.
1629	* @retval VINF_* Scheduling instructions.
1630	* @retval VERR_EM_INTERPRETER Something we can't cope with.
1631	* @retval VERR_* Fatal errors.
1632	*
1633	* @param pVM The VM handle.
1634	* @param pRegFrame The register frame.
1635	* @param ASID Tagged TLB id for the guest
1636	*
1637	* Updates the EIP if an instruction was executed successfully.
1638	*/
1639	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1640	{
1641	/*
1642	* Only allow 32-bit code.
1643	*/
1644	if (SELMIsSelector32Bit(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid))
1645	{
1646	RTGCPTR pbCode;
1647	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pbCode);
1648	if (VBOX_SUCCESS(rc))
1649	{
1650	uint32_t cbOp;
1651	DISCPUSTATE Cpu;
1652
1653	Cpu.mode = CPUMODE_32BIT;
1654	rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
1655	Assert(VBOX_FAILURE(rc) \|\| Cpu.pCurInstr->opcode == OP_INVLPG);
1656	if (VBOX_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
1657	{
1658	Assert(cbOp == Cpu.opsize);
1659	rc = svmInterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
1660	if (VBOX_SUCCESS(rc))
1661	{
1662	pRegFrame->eip += cbOp; /* Move on to the next instruction. */
1663	}
1664	return rc;
1665	}
1666	}
1667	}
1668	return VERR_EM_INTERPRETER;
1669	}
1670

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 8213

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