HWSVMR0.cpp@ 10014

Last change on this file since 10014 was 10014, checked in by vboxsync, 16 years ago
Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. (protected mode without paging; right before switching to long mode)
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File size: 80.6 KB

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1	/* $Id: HWSVMR0.cpp 10014 2008-06-30 12:02:49Z vboxsync $ */
2	/** @file
3	* HWACCM SVM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_svm.h>
32	#include <VBox/pgm.h>
33	#include <VBox/pdm.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <VBox/selm.h>
37	#include <VBox/iom.h>
38	#include <VBox/dis.h>
39	#include <VBox/dbgf.h>
40	#include <VBox/disopcode.h>
41	#include <iprt/param.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm.h>
44	#include <iprt/cpuset.h>
45	#include <iprt/mp.h>
46	#include "HWSVMR0.h"
47
48	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
49
50	/**
51	* Sets up and activates AMD-V on the current CPU
52	*
53	* @returns VBox status code.
54	* @param pCpu CPU info struct
55	* @param pVM The VM to operate on.
56	* @param pvPageCpu Pointer to the global cpu page
57	* @param pPageCpuPhys Physical address of the global cpu page
58	*/
59	HWACCMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
60	{
61	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
62	AssertReturn(pVM, VERR_INVALID_PARAMETER);
63	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
64
65	/* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
66
67	#ifdef LOG_ENABLED
68	SUPR0Printf("SVMR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
69	#endif
70
71	/* Turn on AMD-V in the EFER MSR. */
72	uint64_t val = ASMRdMsr(MSR_K6_EFER);
73	if (!(val & MSR_K6_EFER_SVME))
74	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
75
76	/* Write the physical page address where the CPU will store the host state while executing the VM. */
77	ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
78
79	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
80	pCpu->cTLBFlushes = 0;
81	return VINF_SUCCESS;
82	}
83
84	/**
85	* Deactivates AMD-V on the current CPU
86	*
87	* @returns VBox status code.
88	* @param pCpu CPU info struct
89	* @param pvPageCpu Pointer to the global cpu page
90	* @param pPageCpuPhys Physical address of the global cpu page
91	*/
92	HWACCMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
93	{
94	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
95	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
96
97	#ifdef LOG_ENABLED
98	SUPR0Printf("SVMR0DisableCpu cpu %d\n", pCpu->idCpu);
99	#endif
100
101	/* Turn off AMD-V in the EFER MSR. */
102	uint64_t val = ASMRdMsr(MSR_K6_EFER);
103	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
104
105	/* Invalidate host state physical address. */
106	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
107	pCpu->uCurrentASID = 0;
108
109	return VINF_SUCCESS;
110	}
111
112	/**
113	* Does Ring-0 per VM AMD-V init.
114	*
115	* @returns VBox status code.
116	* @param pVM The VM to operate on.
117	*/
118	HWACCMR0DECL(int) SVMR0InitVM(PVM pVM)
119	{
120	int rc;
121
122	/* Allocate one page for the VM control block (VMCB). */
123	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
124	if (RT_FAILURE(rc))
125	return rc;
126
127	pVM->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCB);
128	pVM->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCB, 0);
129	ASMMemZero32(pVM->hwaccm.s.svm.pVMCB, PAGE_SIZE);
130
131	/* Allocate one page for the host context */
132	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
133	if (RT_FAILURE(rc))
134	return rc;
135
136	pVM->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCBHost);
137	pVM->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCBHost, 0);
138	ASMMemZero32(pVM->hwaccm.s.svm.pVMCBHost, PAGE_SIZE);
139
140	/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
141	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
142	if (RT_FAILURE(rc))
143	return rc;
144
145	pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
146	pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
147	/* Set all bits to intercept all IO accesses. */
148	ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
149
150	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
151	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
152	if (RT_FAILURE(rc))
153	return rc;
154
155	pVM->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
156	pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
157	/* Set all bits to intercept all MSR accesses. */
158	ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
159
160	/* Erratum 170 which requires a forced TLB flush for each world switch:
161	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
162	*
163	* All BH-G1/2 and DH-G1/2 models include a fix:
164	* Athlon X2: 0x6b 1/2
165	* 0x68 1/2
166	* Athlon 64: 0x7f 1
167	* 0x6f 2
168	* Sempron: 0x7f 1/2
169	* 0x6f 2
170	* 0x6c 2
171	* 0x7c 2
172	* Turion 64: 0x68 2
173	*
174	*/
175	uint32_t u32Dummy;
176	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
177	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
178	u32BaseFamily= (u32Version >> 8) & 0xf;
179	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
180	u32Model = ((u32Version >> 4) & 0xf);
181	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
182	u32Stepping = u32Version & 0xf;
183	if ( u32Family == 0xf
184	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
185	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
186	{
187	Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
188	pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
189	}
190
191	/* Invalidate the last cpu we were running on. */
192	pVM->hwaccm.s.svm.idLastCpu = NIL_RTCPUID;
193	return VINF_SUCCESS;
194	}
195
196	/**
197	* Does Ring-0 per VM AMD-V termination.
198	*
199	* @returns VBox status code.
200	* @param pVM The VM to operate on.
201	*/
202	HWACCMR0DECL(int) SVMR0TermVM(PVM pVM)
203	{
204	if (pVM->hwaccm.s.svm.pMemObjVMCB)
205	{
206	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCB, false);
207	pVM->hwaccm.s.svm.pVMCB = 0;
208	pVM->hwaccm.s.svm.pVMCBPhys = 0;
209	pVM->hwaccm.s.svm.pMemObjVMCB = 0;
210	}
211	if (pVM->hwaccm.s.svm.pMemObjVMCBHost)
212	{
213	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCBHost, false);
214	pVM->hwaccm.s.svm.pVMCBHost = 0;
215	pVM->hwaccm.s.svm.pVMCBHostPhys = 0;
216	pVM->hwaccm.s.svm.pMemObjVMCBHost = 0;
217	}
218	if (pVM->hwaccm.s.svm.pMemObjIOBitmap)
219	{
220	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
221	pVM->hwaccm.s.svm.pIOBitmap = 0;
222	pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
223	pVM->hwaccm.s.svm.pMemObjIOBitmap = 0;
224	}
225	if (pVM->hwaccm.s.svm.pMemObjMSRBitmap)
226	{
227	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
228	pVM->hwaccm.s.svm.pMSRBitmap = 0;
229	pVM->hwaccm.s.svm.pMSRBitmapPhys = 0;
230	pVM->hwaccm.s.svm.pMemObjMSRBitmap = 0;
231	}
232	return VINF_SUCCESS;
233	}
234
235	/**
236	* Sets up AMD-V for the specified VM
237	*
238	* @returns VBox status code.
239	* @param pVM The VM to operate on.
240	*/
241	HWACCMR0DECL(int) SVMR0SetupVM(PVM pVM)
242	{
243	int rc = VINF_SUCCESS;
244	SVM_VMCB *pVMCB;
245
246	AssertReturn(pVM, VERR_INVALID_PARAMETER);
247
248	Assert(pVM->hwaccm.s.svm.fSupported);
249
250	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
251	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
252
253	/* Program the control fields. Most of them never have to be changed again. */
254	/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
255	/* Note: CR8 reads will refer to V_TPR, so no need to catch them. */
256	/** @note CR0 & CR4 can be safely read when guest and shadow copies are identical. */
257	if (!pVM->hwaccm.s.fNestedPaging)
258	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
259	else
260	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
261
262	/*
263	* CR0/3/4 writes must be intercepted for obvious reasons.
264	*/
265	if (!pVM->hwaccm.s.fNestedPaging)
266	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(8);
267	else
268	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4) \| RT_BIT(8);
269
270	/* Intercept all DRx reads and writes. */
271	pVMCB->ctrl.u16InterceptRdDRx = RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7);
272	pVMCB->ctrl.u16InterceptWrDRx = RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7);
273
274	/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
275	* All breakpoints are automatically cleared when the VM exits.
276	*/
277
278	pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
279	#ifndef DEBUG
280	if (pVM->hwaccm.s.fNestedPaging)
281	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(14); /* no longer need to intercept #PF. */
282	#endif
283
284	pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
285	\| SVM_CTRL1_INTERCEPT_VINTR
286	\| SVM_CTRL1_INTERCEPT_NMI
287	\| SVM_CTRL1_INTERCEPT_SMI
288	\| SVM_CTRL1_INTERCEPT_INIT
289	\| SVM_CTRL1_INTERCEPT_RDPMC
290	\| SVM_CTRL1_INTERCEPT_CPUID
291	\| SVM_CTRL1_INTERCEPT_RSM
292	\| SVM_CTRL1_INTERCEPT_HLT
293	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
294	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
295	\| SVM_CTRL1_INTERCEPT_INVLPG
296	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
297	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH
298	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
299	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
300	;
301	/* With nested paging we don't care about invlpg anymore. */
302	if (pVM->hwaccm.s.fNestedPaging)
303	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
304
305	pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
306	\| SVM_CTRL2_INTERCEPT_VMMCALL
307	\| SVM_CTRL2_INTERCEPT_VMLOAD
308	\| SVM_CTRL2_INTERCEPT_VMSAVE
309	\| SVM_CTRL2_INTERCEPT_STGI
310	\| SVM_CTRL2_INTERCEPT_CLGI
311	\| SVM_CTRL2_INTERCEPT_SKINIT
312	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
313	\| SVM_CTRL2_INTERCEPT_WBINVD
314	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
315	;
316	Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
317	Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
318	Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
319
320	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
321	pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
322
323	/* Set IO and MSR bitmap addresses. */
324	pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
325	pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
326
327	/* No LBR virtualization. */
328	pVMCB->ctrl.u64LBRVirt = 0;
329
330	/** The ASID must start at 1; the host uses 0. */
331	pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
332
333	/** Setup the PAT msr (nested paging only) */
334	pVMCB->guest.u64GPAT = 0x0007040600070406ULL;
335	return rc;
336	}
337
338
339	/**
340	* Injects an event (trap or external interrupt)
341	*
342	* @param pVM The VM to operate on.
343	* @param pVMCB SVM control block
344	* @param pCtx CPU Context
345	* @param pIntInfo SVM interrupt info
346	*/
347	inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx, SVM_EVENT* pEvent)
348	{
349	#ifdef VBOX_STRICT
350	if (pEvent->n.u8Vector == 0xE)
351	Log(("SVM: Inject int %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", pEvent->n.u8Vector, pCtx->rip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
352	else
353	if (pEvent->n.u8Vector < 0x20)
354	Log(("SVM: Inject int %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->rip, pEvent->n.u32ErrorCode));
355	else
356	{
357	Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->rip));
358	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
359	Assert(pCtx->eflags.u32 & X86_EFL_IF);
360	}
361	#endif
362
363	/* Set event injection state. */
364	pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
365	}
366
367
368	/**
369	* Checks for pending guest interrupts and injects them
370	*
371	* @returns VBox status code.
372	* @param pVM The VM to operate on.
373	* @param pVMCB SVM control block
374	* @param pCtx CPU Context
375	*/
376	static int SVMR0CheckPendingInterrupt(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx)
377	{
378	int rc;
379
380	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
381	if (pVM->hwaccm.s.Event.fPending)
382	{
383	SVM_EVENT Event;
384
385	Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip));
386	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
387	Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
388	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
389
390	pVM->hwaccm.s.Event.fPending = false;
391	return VINF_SUCCESS;
392	}
393
394	/* When external interrupts are pending, we should exit the VM when IF is set. */
395	if ( !TRPMHasTrap(pVM)
396	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
397	{
398	if (!(pCtx->eflags.u32 & X86_EFL_IF))
399	{
400	if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
401	{
402	LogFlow(("Enable irq window exit!\n"));
403	/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
404	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
405	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
406	pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1; /* ignore the priority in the TPR; just deliver it */
407	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
408	}
409	}
410	else
411	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
412	{
413	uint8_t u8Interrupt;
414
415	rc = PDMGetInterrupt(pVM, &u8Interrupt);
416	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
417	if (VBOX_SUCCESS(rc))
418	{
419	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
420	AssertRC(rc);
421	}
422	else
423	{
424	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
425	Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)));
426	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
427	/* Just continue */
428	}
429	}
430	else
431	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->rip));
432	}
433
434	#ifdef VBOX_STRICT
435	if (TRPMHasTrap(pVM))
436	{
437	uint8_t u8Vector;
438	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
439	AssertRC(rc);
440	}
441	#endif
442
443	if ( pCtx->eflags.u32 & X86_EFL_IF
444	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
445	&& TRPMHasTrap(pVM)
446	)
447	{
448	uint8_t u8Vector;
449	int rc;
450	TRPMEVENT enmType;
451	SVM_EVENT Event;
452	RTGCUINT u32ErrorCode;
453
454	Event.au64[0] = 0;
455
456	/* If a new event is pending, then dispatch it now. */
457	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &u32ErrorCode, 0);
458	AssertRC(rc);
459	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
460	Assert(enmType != TRPM_SOFTWARE_INT);
461
462	/* Clear the pending trap. */
463	rc = TRPMResetTrap(pVM);
464	AssertRC(rc);
465
466	Event.n.u8Vector = u8Vector;
467	Event.n.u1Valid = 1;
468	Event.n.u32ErrorCode = u32ErrorCode;
469
470	if (enmType == TRPM_TRAP)
471	{
472	switch (u8Vector) {
473	case 8:
474	case 10:
475	case 11:
476	case 12:
477	case 13:
478	case 14:
479	case 17:
480	/* Valid error codes. */
481	Event.n.u1ErrorCodeValid = 1;
482	break;
483	default:
484	break;
485	}
486	if (u8Vector == X86_XCPT_NMI)
487	Event.n.u3Type = SVM_EVENT_NMI;
488	else
489	Event.n.u3Type = SVM_EVENT_EXCEPTION;
490	}
491	else
492	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
493
494	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
495	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
496	} /* if (interrupts can be dispatched) */
497
498	return VINF_SUCCESS;
499	}
500
501	/**
502	* Save the host state
503	*
504	* @returns VBox status code.
505	* @param pVM The VM to operate on.
506	*/
507	HWACCMR0DECL(int) SVMR0SaveHostState(PVM pVM)
508	{
509	/* Nothing to do here. */
510	return VINF_SUCCESS;
511	}
512
513	/**
514	* Loads the guest state
515	*
516	* @returns VBox status code.
517	* @param pVM The VM to operate on.
518	* @param pCtx Guest context
519	*/
520	HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
521	{
522	RTGCUINTPTR val;
523	SVM_VMCB *pVMCB;
524
525	if (pVM == NULL)
526	return VERR_INVALID_PARAMETER;
527
528	/* Setup AMD SVM. */
529	Assert(pVM->hwaccm.s.svm.fSupported);
530
531	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
532	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
533
534	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
535	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
536	{
537	SVM_WRITE_SELREG(CS, cs);
538	SVM_WRITE_SELREG(SS, ss);
539	SVM_WRITE_SELREG(DS, ds);
540	SVM_WRITE_SELREG(ES, es);
541	SVM_WRITE_SELREG(FS, fs);
542	SVM_WRITE_SELREG(GS, gs);
543	}
544
545	/* Guest CPU context: LDTR. */
546	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
547	{
548	SVM_WRITE_SELREG(LDTR, ldtr);
549	}
550
551	/* Guest CPU context: TR. */
552	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
553	{
554	SVM_WRITE_SELREG(TR, tr);
555	}
556
557	/* Guest CPU context: GDTR. */
558	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
559	{
560	pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
561	pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
562	}
563
564	/* Guest CPU context: IDTR. */
565	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
566	{
567	pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
568	pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
569	}
570
571	/*
572	* Sysenter MSRs (unconditional)
573	*/
574	pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
575	pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
576	pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
577
578	/* Control registers */
579	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
580	{
581	val = pCtx->cr0;
582	if (CPUMIsGuestFPUStateActive(pVM) == false)
583	{
584	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
585	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
586	}
587	else
588	{
589	Assert(pVM->hwaccm.s.svm.fResumeVM == true);
590	/** @todo check if we support the old style mess correctly. */
591	if (!(val & X86_CR0_NE))
592	{
593	Log(("Forcing X86_CR0_NE!!!\n"));
594
595	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
596	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
597	{
598	pVMCB->ctrl.u32InterceptException \|= RT_BIT(16);
599	pVM->hwaccm.s.fFPUOldStyleOverride = true;
600	}
601	}
602	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
603	}
604	/* Always enable caching. */
605	val &= ~(X86_CR0_CD\|X86_CR0_NW);
606
607	/* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
608	/* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
609	if (!pVM->hwaccm.s.fNestedPaging)
610	{
611	val \|= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
612	val \|= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
613	}
614	pVMCB->guest.u64CR0 = val;
615	}
616	/* CR2 as well */
617	pVMCB->guest.u64CR2 = pCtx->cr2;
618
619	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
620	{
621	/* Save our shadow CR3 register. */
622	if (pVM->hwaccm.s.fNestedPaging)
623	{
624	pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVM, PGMGetHostMode(pVM));
625	pVMCB->guest.u64CR3 = pCtx->cr3;
626	}
627	else
628	pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
629	}
630
631	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
632	{
633	val = pCtx->cr4;
634	if (!pVM->hwaccm.s.fNestedPaging)
635	{
636	switch(pVM->hwaccm.s.enmShadowMode)
637	{
638	case PGMMODE_REAL:
639	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
640	AssertFailed();
641	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
642
643	case PGMMODE_32_BIT: /* 32-bit paging. */
644	break;
645
646	case PGMMODE_PAE: /* PAE paging. */
647	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
648	/** @todo use normal 32 bits paging */
649	val \|= X86_CR4_PAE;
650	break;
651
652	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
653	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
654	#ifdef VBOX_ENABLE_64_BITS_GUESTS
655	break;
656	#else
657	AssertFailed();
658	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
659	#endif
660
661	default: /* shut up gcc */
662	AssertFailed();
663	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
664	}
665	}
666	pVMCB->guest.u64CR4 = val;
667	}
668
669	/* Debug registers. */
670	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
671	{
672	/** @todo DR0-6 */
673	val = pCtx->dr7;
674	val &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
675	val \|= 0x400; /* must be one */
676	#ifdef VBOX_STRICT
677	val = 0x400;
678	#endif
679	pVMCB->guest.u64DR7 = val;
680
681	pVMCB->guest.u64DR6 = pCtx->dr6;
682	}
683
684	/* EIP, ESP and EFLAGS */
685	pVMCB->guest.u64RIP = pCtx->rip;
686	pVMCB->guest.u64RSP = pCtx->rsp;
687	pVMCB->guest.u64RFlags = pCtx->eflags.u32;
688
689	/* Set CPL */
690	pVMCB->guest.u8CPL = pCtx->ssHid.Attr.n.u2Dpl;
691
692	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
693	pVMCB->guest.u64RAX = pCtx->rax;
694
695	/* vmrun will fail without MSR_K6_EFER_SVME. */
696	pVMCB->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
697
698	/* 64 bits guest mode? */
699	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
700	{
701	#if !defined(VBOX_WITH_64_BITS_GUESTS) \|\| HC_ARCH_BITS != 64
702	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
703	#else
704	pVM->hwaccm.s.svm.pfnVMRun = SVMVMRun64;
705	#endif
706	/* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
707	pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
708	pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
709	}
710	else
711	{
712	/* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
713	pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
714
715	pVM->hwaccm.s.svm.pfnVMRun = SVMVMRun;
716	}
717
718	/** TSC offset. */
719	if (TMCpuTickCanUseRealTSC(pVM, &pVMCB->ctrl.u64TSCOffset))
720	{
721	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
722	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
723	}
724	else
725	{
726	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
727	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
728	}
729
730	/* Sync the various msrs for 64 bits mode. */
731	pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
732	pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
733	pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
734	pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
735	pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
736
737	#ifdef DEBUG
738	/* Intercept X86_XCPT_DB if stepping is enabled */
739	if (DBGFIsStepping(pVM))
740	pVMCB->ctrl.u32InterceptException \|= RT_BIT(1);
741	else
742	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(1);
743	#endif
744
745	/* Done. */
746	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
747
748	return VINF_SUCCESS;
749	}
750
751
752	/**
753	* Runs guest code in an SVM VM.
754	*
755	* @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
756	*
757	* @returns VBox status code.
758	* @param pVM The VM to operate on.
759	* @param pCtx Guest context
760	* @param pCpu CPU info struct
761	*/
762	HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx, PHWACCM_CPUINFO pCpu)
763	{
764	int rc = VINF_SUCCESS;
765	uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
766	SVM_VMCB *pVMCB;
767	bool fGuestStateSynced = false;
768	unsigned cResume = 0;
769
770	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
771
772	AssertReturn(pCpu->fConfigured, VERR_EM_INTERNAL_ERROR);
773
774	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
775	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
776
777	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
778	*/
779	ResumeExecution:
780	/* Safety precaution; looping for too long here can have a very bad effect on the host */
781	if (++cResume > HWACCM_MAX_RESUME_LOOPS)
782	{
783	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
784	rc = VINF_EM_RAW_INTERRUPT;
785	goto end;
786	}
787
788	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
789	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
790	{
791	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
792	if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
793	{
794	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
795	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
796	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
797	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
798	*/
799	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
800	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
801	pVMCB->ctrl.u64IntShadow = 0;
802	}
803	}
804	else
805	{
806	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
807	pVMCB->ctrl.u64IntShadow = 0;
808	}
809
810	/* Check for pending actions that force us to go back to ring 3. */
811	#ifdef DEBUG
812	/* Intercept X86_XCPT_DB if stepping is enabled */
813	if (!DBGFIsStepping(pVM))
814	#endif
815	{
816	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
817	{
818	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
819	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
820	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
821	rc = VINF_EM_RAW_TO_R3;
822	goto end;
823	}
824	}
825
826	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
827	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
828	{
829	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
830	rc = VINF_EM_PENDING_REQUEST;
831	goto end;
832	}
833
834	/* When external interrupts are pending, we should exit the VM when IF is set. */
835	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
836	rc = SVMR0CheckPendingInterrupt(pVM, pVMCB, pCtx);
837	if (VBOX_FAILURE(rc))
838	{
839	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
840	goto end;
841	}
842
843	/* Load the guest state */
844	rc = SVMR0LoadGuestState(pVM, pCtx);
845	if (rc != VINF_SUCCESS)
846	{
847	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
848	goto end;
849	}
850	fGuestStateSynced = true;
851
852	/* All done! Let's start VM execution. */
853	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
854
855	/* Enable nested paging if necessary (disabled each time after #VMEXIT). */
856	pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
857
858	/* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
859	if (!pVM->hwaccm.s.svm.fResumeVM)
860	{
861	if ( pVM->hwaccm.s.svm.idLastCpu != pCpu->idCpu
862	/* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
863	\|\| pVM->hwaccm.s.svm.cTLBFlushes != pCpu->cTLBFlushes)
864	{
865	/* Force a TLB flush on VM entry. */
866	pVM->hwaccm.s.svm.fForceTLBFlush = true;
867	}
868	pVM->hwaccm.s.svm.idLastCpu = pCpu->idCpu;
869	}
870
871	/* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
872	if ( pVM->hwaccm.s.svm.fForceTLBFlush
873	&& !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
874	{
875	if (++pCpu->uCurrentASID >= pVM->hwaccm.s.svm.u32MaxASID)
876	{
877	pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
878	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
879	pCpu->cTLBFlushes++;
880	}
881	else
882	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushASID);
883
884	pVM->hwaccm.s.svm.cTLBFlushes = pCpu->cTLBFlushes;
885	}
886	else
887	{
888	/* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
889	if (!pCpu->uCurrentASID)
890	pCpu->uCurrentASID = 1;
891
892	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVM->hwaccm.s.svm.fForceTLBFlush;
893	}
894
895	AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.svm.u32MaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
896	pVMCB->ctrl.TLBCtrl.n.u32ASID = pCpu->uCurrentASID;
897
898	#ifdef VBOX_WITH_STATISTICS
899	if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
900	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBWorldSwitch);
901	else
902	STAM_COUNTER_INC(&pVM->hwaccm.s.StatNoFlushTLBWorldSwitch);
903	#endif
904
905	/* In case we execute a goto ResumeExecution later on. */
906	pVM->hwaccm.s.svm.fResumeVM = true;
907	pVM->hwaccm.s.svm.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
908
909	Assert(sizeof(pVM->hwaccm.s.svm.pVMCBPhys) == 8);
910	Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
911	\| SVM_CTRL2_INTERCEPT_VMMCALL
912	\| SVM_CTRL2_INTERCEPT_VMLOAD
913	\| SVM_CTRL2_INTERCEPT_VMSAVE
914	\| SVM_CTRL2_INTERCEPT_STGI
915	\| SVM_CTRL2_INTERCEPT_CLGI
916	\| SVM_CTRL2_INTERCEPT_SKINIT
917	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
918	\| SVM_CTRL2_INTERCEPT_WBINVD
919	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
920	));
921	Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
922	Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
923	Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
924	Assert(pVMCB->ctrl.u64LBRVirt == 0);
925
926	pVM->hwaccm.s.svm.pfnVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);
927	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
928
929	/**
930	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
931	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
932	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
933	*/
934
935	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
936
937	/* Reason for the VM exit */
938	exitCode = pVMCB->ctrl.u64ExitCode;
939
940	if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
941	{
942	HWACCMDumpRegs(pCtx);
943	#ifdef DEBUG
944	Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
945	Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
946	Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
947	Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
948	Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
949	Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
950	Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
951	Log(("ctrl.u64IOPMPhysAddr %VX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
952	Log(("ctrl.u64MSRPMPhysAddr %VX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
953	Log(("ctrl.u64TSCOffset %VX64\n", pVMCB->ctrl.u64TSCOffset));
954
955	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
956	Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
957	Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
958	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
959
960	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
961	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
962	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
963	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
964	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
965	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
966	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
967	Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
968	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
969	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
970
971	Log(("ctrl.u64IntShadow %VX64\n", pVMCB->ctrl.u64IntShadow));
972	Log(("ctrl.u64ExitCode %VX64\n", pVMCB->ctrl.u64ExitCode));
973	Log(("ctrl.u64ExitInfo1 %VX64\n", pVMCB->ctrl.u64ExitInfo1));
974	Log(("ctrl.u64ExitInfo2 %VX64\n", pVMCB->ctrl.u64ExitInfo2));
975	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
976	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
977	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
978	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
979	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
980	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
981	Log(("ctrl.NestedPaging %VX64\n", pVMCB->ctrl.NestedPaging.au64));
982	Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
983	Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
984	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
985	Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
986	Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
987	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
988
989	Log(("ctrl.u64NestedPagingCR3 %VX64\n", pVMCB->ctrl.u64NestedPagingCR3));
990	Log(("ctrl.u64LBRVirt %VX64\n", pVMCB->ctrl.u64LBRVirt));
991
992	Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
993	Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
994	Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
995	Log(("guest.CS.u64Base %VX64\n", pVMCB->guest.CS.u64Base));
996	Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
997	Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
998	Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
999	Log(("guest.DS.u64Base %VX64\n", pVMCB->guest.DS.u64Base));
1000	Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1001	Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1002	Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1003	Log(("guest.ES.u64Base %VX64\n", pVMCB->guest.ES.u64Base));
1004	Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1005	Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1006	Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1007	Log(("guest.FS.u64Base %VX64\n", pVMCB->guest.FS.u64Base));
1008	Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1009	Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1010	Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1011	Log(("guest.GS.u64Base %VX64\n", pVMCB->guest.GS.u64Base));
1012
1013	Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1014	Log(("guest.GDTR.u64Base %VX64\n", pVMCB->guest.GDTR.u64Base));
1015
1016	Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1017	Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1018	Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1019	Log(("guest.LDTR.u64Base %VX64\n", pVMCB->guest.LDTR.u64Base));
1020
1021	Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1022	Log(("guest.IDTR.u64Base %VX64\n", pVMCB->guest.IDTR.u64Base));
1023
1024	Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1025	Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1026	Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1027	Log(("guest.TR.u64Base %VX64\n", pVMCB->guest.TR.u64Base));
1028
1029	Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1030	Log(("guest.u64CR0 %VX64\n", pVMCB->guest.u64CR0));
1031	Log(("guest.u64CR2 %VX64\n", pVMCB->guest.u64CR2));
1032	Log(("guest.u64CR3 %VX64\n", pVMCB->guest.u64CR3));
1033	Log(("guest.u64CR4 %VX64\n", pVMCB->guest.u64CR4));
1034	Log(("guest.u64DR6 %VX64\n", pVMCB->guest.u64DR6));
1035	Log(("guest.u64DR7 %VX64\n", pVMCB->guest.u64DR7));
1036
1037	Log(("guest.u64RIP %VX64\n", pVMCB->guest.u64RIP));
1038	Log(("guest.u64RSP %VX64\n", pVMCB->guest.u64RSP));
1039	Log(("guest.u64RAX %VX64\n", pVMCB->guest.u64RAX));
1040	Log(("guest.u64RFlags %VX64\n", pVMCB->guest.u64RFlags));
1041
1042	Log(("guest.u64SysEnterCS %VX64\n", pVMCB->guest.u64SysEnterCS));
1043	Log(("guest.u64SysEnterEIP %VX64\n", pVMCB->guest.u64SysEnterEIP));
1044	Log(("guest.u64SysEnterESP %VX64\n", pVMCB->guest.u64SysEnterESP));
1045
1046	Log(("guest.u64EFER %VX64\n", pVMCB->guest.u64EFER));
1047	Log(("guest.u64STAR %VX64\n", pVMCB->guest.u64STAR));
1048	Log(("guest.u64LSTAR %VX64\n", pVMCB->guest.u64LSTAR));
1049	Log(("guest.u64CSTAR %VX64\n", pVMCB->guest.u64CSTAR));
1050	Log(("guest.u64SFMASK %VX64\n", pVMCB->guest.u64SFMASK));
1051	Log(("guest.u64KernelGSBase %VX64\n", pVMCB->guest.u64KernelGSBase));
1052	Log(("guest.u64GPAT %VX64\n", pVMCB->guest.u64GPAT));
1053	Log(("guest.u64DBGCTL %VX64\n", pVMCB->guest.u64DBGCTL));
1054	Log(("guest.u64BR_FROM %VX64\n", pVMCB->guest.u64BR_FROM));
1055	Log(("guest.u64BR_TO %VX64\n", pVMCB->guest.u64BR_TO));
1056	Log(("guest.u64LASTEXCPFROM %VX64\n", pVMCB->guest.u64LASTEXCPFROM));
1057	Log(("guest.u64LASTEXCPTO %VX64\n", pVMCB->guest.u64LASTEXCPTO));
1058
1059	#endif
1060	rc = VERR_SVM_UNABLE_TO_START_VM;
1061	goto end;
1062	}
1063
1064	/* Let's first sync back eip, esp, and eflags. */
1065	pCtx->rip = pVMCB->guest.u64RIP;
1066	pCtx->rsp = pVMCB->guest.u64RSP;
1067	pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1068	/* eax is saved/restore across the vmrun instruction */
1069	pCtx->rax = pVMCB->guest.u64RAX;
1070
1071	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1072	SVM_READ_SELREG(SS, ss);
1073	SVM_READ_SELREG(CS, cs);
1074	SVM_READ_SELREG(DS, ds);
1075	SVM_READ_SELREG(ES, es);
1076	SVM_READ_SELREG(FS, fs);
1077	SVM_READ_SELREG(GS, gs);
1078
1079	/* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1080	/* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1081	if ( pVM->hwaccm.s.fNestedPaging
1082	&& pCtx->cr3 != pVMCB->guest.u64CR3)
1083	{
1084	CPUMSetGuestCR3(pVM, pVMCB->guest.u64CR3);
1085	PGMUpdateCR3(pVM, pVMCB->guest.u64CR3);
1086	}
1087
1088	/** @note NOW IT'S SAFE FOR LOGGING! */
1089
1090	/* Take care of instruction fusing (sti, mov ss) */
1091	if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1092	{
1093	Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->rip));
1094	EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1095	}
1096	else
1097	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1098
1099	Log2(("exitCode = %x\n", exitCode));
1100
1101	/* Sync back the debug registers. */
1102	/** @todo Implement debug registers correctly. */
1103	pCtx->dr6 = pVMCB->guest.u64DR6;
1104	pCtx->dr7 = pVMCB->guest.u64DR7;
1105
1106	/* Check if an injected event was interrupted prematurely. */
1107	pVM->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1108	if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1109	&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1110	{
1111	Log(("Pending inject %VX64 at %VGv exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitCode));
1112	pVM->hwaccm.s.Event.fPending = true;
1113	/* Error code present? (redundant) */
1114	if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1115	{
1116	pVM->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1117	}
1118	else
1119	pVM->hwaccm.s.Event.errCode = 0;
1120	}
1121	#ifdef VBOX_WITH_STATISTICS
1122	if (exitCode == SVM_EXIT_NPF)
1123	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitReasonNPF);
1124	else
1125	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1126	#endif
1127
1128	/* Deal with the reason of the VM-exit. */
1129	switch (exitCode)
1130	{
1131	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1132	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1133	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1134	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1135	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1136	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1137	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1138	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1139	{
1140	/* Pending trap. */
1141	SVM_EVENT Event;
1142	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1143
1144	Log2(("Hardware/software interrupt %d\n", vector));
1145	switch (vector)
1146	{
1147	#ifdef DEBUG
1148	case X86_XCPT_DB:
1149	rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), pVMCB->guest.u64DR6);
1150	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
1151	break;
1152	#endif
1153
1154	case X86_XCPT_NM:
1155	{
1156	uint32_t oldCR0;
1157
1158	Log(("#NM fault at %VGv\n", pCtx->rip));
1159
1160	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1161	oldCR0 = ASMGetCR0();
1162	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1163	rc = CPUMHandleLazyFPU(pVM);
1164	if (rc == VINF_SUCCESS)
1165	{
1166	Assert(CPUMIsGuestFPUStateActive(pVM));
1167
1168	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
1169	ASMSetCR0(oldCR0);
1170
1171	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1172
1173	/* Continue execution. */
1174	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1175	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1176
1177	goto ResumeExecution;
1178	}
1179
1180	Log(("Forward #NM fault to the guest\n"));
1181	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1182
1183	Event.au64[0] = 0;
1184	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1185	Event.n.u1Valid = 1;
1186	Event.n.u8Vector = X86_XCPT_NM;
1187
1188	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1189	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1190	goto ResumeExecution;
1191	}
1192
1193	case X86_XCPT_PF: /* Page fault */
1194	{
1195	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1196	RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1197
1198	#ifdef DEBUG
1199	if (pVM->hwaccm.s.fNestedPaging)
1200	{ /* A genuine pagefault.
1201	* Forward the trap to the guest by injecting the exception and resuming execution.
1202	*/
1203	Log(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, uFaultAddress, errCode));
1204	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1205
1206	/* Now we must update CR2. */
1207	pCtx->cr2 = uFaultAddress;
1208
1209	Event.au64[0] = 0;
1210	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1211	Event.n.u1Valid = 1;
1212	Event.n.u8Vector = X86_XCPT_PF;
1213	Event.n.u1ErrorCodeValid = 1;
1214	Event.n.u32ErrorCode = errCode;
1215
1216	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1217
1218	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1219	goto ResumeExecution;
1220	}
1221	#endif
1222	Assert(!pVM->hwaccm.s.fNestedPaging);
1223
1224	Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, uFaultAddress, errCode));
1225	/* Exit qualification contains the linear address of the page fault. */
1226	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1227	TRPMSetErrorCode(pVM, errCode);
1228	TRPMSetFaultAddress(pVM, uFaultAddress);
1229
1230	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1231	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1232	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
1233	if (rc == VINF_SUCCESS)
1234	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1235	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, uFaultAddress, errCode));
1236	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1237
1238	TRPMResetTrap(pVM);
1239
1240	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1241	goto ResumeExecution;
1242	}
1243	else
1244	if (rc == VINF_EM_RAW_GUEST_TRAP)
1245	{ /* A genuine pagefault.
1246	* Forward the trap to the guest by injecting the exception and resuming execution.
1247	*/
1248	Log2(("Forward page fault to the guest\n"));
1249	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1250	/* The error code might have been changed. */
1251	errCode = TRPMGetErrorCode(pVM);
1252
1253	TRPMResetTrap(pVM);
1254
1255	/* Now we must update CR2. */
1256	pCtx->cr2 = uFaultAddress;
1257
1258	Event.au64[0] = 0;
1259	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1260	Event.n.u1Valid = 1;
1261	Event.n.u8Vector = X86_XCPT_PF;
1262	Event.n.u1ErrorCodeValid = 1;
1263	Event.n.u32ErrorCode = errCode;
1264
1265	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1266
1267	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1268	goto ResumeExecution;
1269	}
1270	#ifdef VBOX_STRICT
1271	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1272	LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
1273	#endif
1274	/* Need to go back to the recompiler to emulate the instruction. */
1275	TRPMResetTrap(pVM);
1276	break;
1277	}
1278
1279	case X86_XCPT_MF: /* Floating point exception. */
1280	{
1281	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1282	if (!(pCtx->cr0 & X86_CR0_NE))
1283	{
1284	/* old style FPU error reporting needs some extra work. */
1285	/** @todo don't fall back to the recompiler, but do it manually. */
1286	rc = VINF_EM_RAW_EMULATE_INSTR;
1287	break;
1288	}
1289	Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1290
1291	Event.au64[0] = 0;
1292	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1293	Event.n.u1Valid = 1;
1294	Event.n.u8Vector = X86_XCPT_MF;
1295
1296	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1297
1298	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1299	goto ResumeExecution;
1300	}
1301
1302	#ifdef VBOX_STRICT
1303	case X86_XCPT_GP: /* General protection failure exception.*/
1304	case X86_XCPT_UD: /* Unknown opcode exception. */
1305	case X86_XCPT_DE: /* Debug exception. */
1306	case X86_XCPT_SS: /* Stack segment exception. */
1307	case X86_XCPT_NP: /* Segment not present exception. */
1308	{
1309	Event.au64[0] = 0;
1310	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1311	Event.n.u1Valid = 1;
1312	Event.n.u8Vector = vector;
1313
1314	switch(vector)
1315	{
1316	case X86_XCPT_GP:
1317	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1318	Event.n.u1ErrorCodeValid = 1;
1319	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1320	break;
1321	case X86_XCPT_DE:
1322	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1323	break;
1324	case X86_XCPT_UD:
1325	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1326	break;
1327	case X86_XCPT_SS:
1328	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1329	Event.n.u1ErrorCodeValid = 1;
1330	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1331	break;
1332	case X86_XCPT_NP:
1333	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1334	Event.n.u1ErrorCodeValid = 1;
1335	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1336	break;
1337	}
1338	Log(("Trap %x at %VGv esi=%x\n", vector, pCtx->rip, pCtx->esi));
1339	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1340
1341	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1342	goto ResumeExecution;
1343	}
1344	#endif
1345	default:
1346	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1347	rc = VERR_EM_INTERNAL_ERROR;
1348	break;
1349
1350	} /* switch (vector) */
1351	break;
1352	}
1353
1354	case SVM_EXIT_NPF:
1355	{
1356	/* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1357	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1358	RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1359
1360	Assert(pVM->hwaccm.s.fNestedPaging);
1361
1362	Log(("Nested page fault at %VGv cr2=%VGp error code %x\n", pCtx->rip, uFaultAddress, errCode));
1363	/* Exit qualification contains the linear address of the page fault. */
1364	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1365	TRPMSetErrorCode(pVM, errCode);
1366	TRPMSetFaultAddress(pVM, uFaultAddress);
1367
1368	/* Handle the pagefault trap for the nested shadow table. */
1369	rc = PGMR0Trap0eHandlerNestedPaging(pVM, PGMGetHostMode(pVM), errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1370	Log2(("PGMR0Trap0eHandlerNestedPaging %VGv returned %Vrc\n", pCtx->rip, rc));
1371	if (rc == VINF_SUCCESS)
1372	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1373	Log2(("Shadow page fault at %VGv cr2=%VGp error code %x\n", pCtx->rip, uFaultAddress, errCode));
1374	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1375
1376	TRPMResetTrap(pVM);
1377
1378	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1379	goto ResumeExecution;
1380	}
1381
1382	#ifdef VBOX_STRICT
1383	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1384	LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
1385	#endif
1386	/* Need to go back to the recompiler to emulate the instruction. */
1387	TRPMResetTrap(pVM);
1388	break;
1389	}
1390
1391	case SVM_EXIT_VINTR:
1392	/* A virtual interrupt is about to be delivered, which means IF=1. */
1393	Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1394	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1395	pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 0;
1396	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1397	goto ResumeExecution;
1398
1399	case SVM_EXIT_FERR_FREEZE:
1400	case SVM_EXIT_INTR:
1401	case SVM_EXIT_NMI:
1402	case SVM_EXIT_SMI:
1403	case SVM_EXIT_INIT:
1404	/* External interrupt; leave to allow it to be dispatched again. */
1405	rc = VINF_EM_RAW_INTERRUPT;
1406	break;
1407
1408	case SVM_EXIT_WBINVD:
1409	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1410	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1411	/* Skip instruction and continue directly. */
1412	pCtx->rip += 2; /** @note hardcoded opcode size! */
1413	/* Continue execution.*/
1414	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1415	goto ResumeExecution;
1416
1417	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1418	{
1419	Log2(("SVM: Cpuid %x\n", pCtx->eax));
1420	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1421	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1422	if (rc == VINF_SUCCESS)
1423	{
1424	/* Update EIP and continue execution. */
1425	pCtx->rip += 2; /** @note hardcoded opcode size! */
1426	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1427	goto ResumeExecution;
1428	}
1429	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1430	rc = VINF_EM_RAW_EMULATE_INSTR;
1431	break;
1432	}
1433
1434	case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1435	{
1436	Log2(("SVM: Rdtsc\n"));
1437	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1438	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1439	if (rc == VINF_SUCCESS)
1440	{
1441	/* Update EIP and continue execution. */
1442	pCtx->rip += 2; /** @note hardcoded opcode size! */
1443	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1444	goto ResumeExecution;
1445	}
1446	AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1447	rc = VINF_EM_RAW_EMULATE_INSTR;
1448	break;
1449	}
1450
1451	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1452	{
1453	Log2(("SVM: invlpg\n"));
1454	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1455
1456	Assert(!pVM->hwaccm.s.fNestedPaging);
1457
1458	/* Truly a pita. Why can't SVM give the same information as VT-x? */
1459	rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1460	if (rc == VINF_SUCCESS)
1461	{
1462	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageInvlpg);
1463	goto ResumeExecution; /* eip already updated */
1464	}
1465	break;
1466	}
1467
1468	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1469	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1470	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1471	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1472	{
1473	uint32_t cbSize;
1474
1475	Log2(("SVM: %VGv mov cr%d, \n", pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
1476	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1477	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1478
1479	switch (exitCode - SVM_EXIT_WRITE_CR0)
1480	{
1481	case 0:
1482	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1483	break;
1484	case 2:
1485	break;
1486	case 3:
1487	Assert(!pVM->hwaccm.s.fNestedPaging);
1488	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1489	break;
1490	case 4:
1491	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1492	break;
1493	default:
1494	AssertFailed();
1495	}
1496	/* Check if a sync operation is pending. */
1497	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1498	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1499	{
1500	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1501	AssertRC(rc);
1502
1503	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBCRxChange);
1504
1505	/** @note Force a TLB flush. SVM requires us to do it manually. */
1506	pVM->hwaccm.s.svm.fForceTLBFlush = true;
1507	}
1508	if (rc == VINF_SUCCESS)
1509	{
1510	/* EIP has been updated already. */
1511
1512	/* Only resume if successful. */
1513	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1514	goto ResumeExecution;
1515	}
1516	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1517	break;
1518	}
1519
1520	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1521	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1522	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1523	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1524	{
1525	uint32_t cbSize;
1526
1527	Log2(("SVM: %VGv mov x, cr%d\n", pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
1528	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1529	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1530	if (rc == VINF_SUCCESS)
1531	{
1532	/* EIP has been updated already. */
1533
1534	/* Only resume if successful. */
1535	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1536	goto ResumeExecution;
1537	}
1538	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1539	break;
1540	}
1541
1542	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1543	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1544	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1545	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1546	{
1547	uint32_t cbSize;
1548
1549	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
1550	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1551	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1552	if (rc == VINF_SUCCESS)
1553	{
1554	/* EIP has been updated already. */
1555
1556	/* Only resume if successful. */
1557	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1558	goto ResumeExecution;
1559	}
1560	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1561	break;
1562	}
1563
1564	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1565	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1566	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1567	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1568	{
1569	uint32_t cbSize;
1570
1571	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
1572	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1573	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1574	if (rc == VINF_SUCCESS)
1575	{
1576	/* EIP has been updated already. */
1577
1578	/* Only resume if successful. */
1579	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1580	goto ResumeExecution;
1581	}
1582	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1583	break;
1584	}
1585
1586	/* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1587	case SVM_EXIT_IOIO: /* I/O instruction. */
1588	{
1589	SVM_IOIO_EXIT IoExitInfo;
1590	uint32_t uIOSize, uAndVal;
1591
1592	IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1593
1594	/** @todo could use a lookup table here */
1595	if (IoExitInfo.n.u1OP8)
1596	{
1597	uIOSize = 1;
1598	uAndVal = 0xff;
1599	}
1600	else
1601	if (IoExitInfo.n.u1OP16)
1602	{
1603	uIOSize = 2;
1604	uAndVal = 0xffff;
1605	}
1606	else
1607	if (IoExitInfo.n.u1OP32)
1608	{
1609	uIOSize = 4;
1610	uAndVal = 0xffffffff;
1611	}
1612	else
1613	{
1614	AssertFailed(); /* should be fatal. */
1615	rc = VINF_EM_RAW_EMULATE_INSTR;
1616	break;
1617	}
1618
1619	if (IoExitInfo.n.u1STR)
1620	{
1621	/* ins/outs */
1622	uint32_t prefix = 0;
1623	if (IoExitInfo.n.u1REP)
1624	prefix \|= PREFIX_REP;
1625
1626	if (IoExitInfo.n.u1Type == 0)
1627	{
1628	Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1629	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1630	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1631	}
1632	else
1633	{
1634	Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1635	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1636	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1637	}
1638	}
1639	else
1640	{
1641	/* normal in/out */
1642	Assert(!IoExitInfo.n.u1REP);
1643
1644	if (IoExitInfo.n.u1Type == 0)
1645	{
1646	Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1647	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1648	rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1649	}
1650	else
1651	{
1652	uint32_t u32Val = 0;
1653
1654	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1655	rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1656	if (IOM_SUCCESS(rc))
1657	{
1658	/* Write back to the EAX register. */
1659	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1660	Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1661	}
1662	}
1663	}
1664	/*
1665	* Handled the I/O return codes.
1666	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1667	*/
1668	if (IOM_SUCCESS(rc))
1669	{
1670	/* Update EIP and continue execution. */
1671	pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1672	if (RT_LIKELY(rc == VINF_SUCCESS))
1673	{
1674	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1675	goto ResumeExecution;
1676	}
1677	Log2(("EM status from IO at %VGv %x size %d: %Vrc\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
1678	break;
1679	}
1680
1681	#ifdef VBOX_STRICT
1682	if (rc == VINF_IOM_HC_IOPORT_READ)
1683	Assert(IoExitInfo.n.u1Type != 0);
1684	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1685	Assert(IoExitInfo.n.u1Type == 0);
1686	else
1687	AssertMsg(VBOX_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1688	#endif
1689	Log2(("Failed IO at %VGv %x size %d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1690	break;
1691	}
1692
1693	case SVM_EXIT_HLT:
1694	/** Check if external interrupts are pending; if so, don't switch back. */
1695	if ( pCtx->eflags.Bits.u1IF
1696	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1697	{
1698	pCtx->rip++; /* skip hlt */
1699	goto ResumeExecution;
1700	}
1701
1702	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1703	break;
1704
1705	case SVM_EXIT_RSM:
1706	case SVM_EXIT_INVLPGA:
1707	case SVM_EXIT_VMRUN:
1708	case SVM_EXIT_VMMCALL:
1709	case SVM_EXIT_VMLOAD:
1710	case SVM_EXIT_VMSAVE:
1711	case SVM_EXIT_STGI:
1712	case SVM_EXIT_CLGI:
1713	case SVM_EXIT_SKINIT:
1714	case SVM_EXIT_RDTSCP:
1715	{
1716	/* Unsupported instructions. */
1717	SVM_EVENT Event;
1718
1719	Event.au64[0] = 0;
1720	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1721	Event.n.u1Valid = 1;
1722	Event.n.u8Vector = X86_XCPT_UD;
1723
1724	Log(("Forced #UD trap at %VGv\n", pCtx->rip));
1725	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1726
1727	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1728	goto ResumeExecution;
1729	}
1730
1731	/* Emulate in ring 3. */
1732	case SVM_EXIT_MSR:
1733	{
1734	uint32_t cbSize;
1735
1736	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
1737	Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
1738	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1739	if (rc == VINF_SUCCESS)
1740	{
1741	/* EIP has been updated already. */
1742
1743	/* Only resume if successful. */
1744	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1745	goto ResumeExecution;
1746	}
1747	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Vrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
1748	break;
1749	}
1750
1751	case SVM_EXIT_MONITOR:
1752	case SVM_EXIT_RDPMC:
1753	case SVM_EXIT_PAUSE:
1754	case SVM_EXIT_MWAIT_UNCOND:
1755	case SVM_EXIT_MWAIT_ARMED:
1756	case SVM_EXIT_TASK_SWITCH: /* can change CR3; emulate */
1757	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1758	break;
1759
1760	case SVM_EXIT_SHUTDOWN:
1761	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1762	break;
1763
1764	case SVM_EXIT_IDTR_READ:
1765	case SVM_EXIT_GDTR_READ:
1766	case SVM_EXIT_LDTR_READ:
1767	case SVM_EXIT_TR_READ:
1768	case SVM_EXIT_IDTR_WRITE:
1769	case SVM_EXIT_GDTR_WRITE:
1770	case SVM_EXIT_LDTR_WRITE:
1771	case SVM_EXIT_TR_WRITE:
1772	case SVM_EXIT_CR0_SEL_WRITE:
1773	default:
1774	/* Unexpected exit codes. */
1775	rc = VERR_EM_INTERNAL_ERROR;
1776	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
1777	break;
1778	}
1779
1780	end:
1781	if (fGuestStateSynced)
1782	{
1783	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1784	SVM_READ_SELREG(LDTR, ldtr);
1785	SVM_READ_SELREG(TR, tr);
1786
1787	pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1788	pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1789
1790	pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1791	pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1792
1793	/*
1794	* System MSRs
1795	*/
1796	pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1797	pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1798	pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1799	}
1800
1801	/* Signal changes for the recompiler. */
1802	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
1803
1804	/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
1805	if (exitCode == SVM_EXIT_INTR)
1806	{
1807	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1808	/* On the next entry we'll only sync the host context. */
1809	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
1810	}
1811	else
1812	{
1813	/* On the next entry we'll sync everything. */
1814	/** @todo we can do better than this */
1815	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
1816	}
1817
1818	/* translate into a less severe return code */
1819	if (rc == VERR_EM_INTERPRETER)
1820	rc = VINF_EM_RAW_EMULATE_INSTR;
1821
1822	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1823	return rc;
1824	}
1825
1826	/**
1827	* Enters the AMD-V session
1828	*
1829	* @returns VBox status code.
1830	* @param pVM The VM to operate on.
1831	* @param pCpu CPU info struct
1832	*/
1833	HWACCMR0DECL(int) SVMR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
1834	{
1835	Assert(pVM->hwaccm.s.svm.fSupported);
1836
1837	LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVM->hwaccm.s.svm.idLastCpu, pCpu->uCurrentASID));
1838	pVM->hwaccm.s.svm.fResumeVM = false;
1839
1840	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
1841	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_LDTR;
1842
1843	return VINF_SUCCESS;
1844	}
1845
1846
1847	/**
1848	* Leaves the AMD-V session
1849	*
1850	* @returns VBox status code.
1851	* @param pVM The VM to operate on.
1852	*/
1853	HWACCMR0DECL(int) SVMR0Leave(PVM pVM)
1854	{
1855	Assert(pVM->hwaccm.s.svm.fSupported);
1856	return VINF_SUCCESS;
1857	}
1858
1859
1860	static int svmInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1861	{
1862	OP_PARAMVAL param1;
1863	RTGCPTR addr;
1864
1865	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1866	if(VBOX_FAILURE(rc))
1867	return VERR_EM_INTERPRETER;
1868
1869	switch(param1.type)
1870	{
1871	case PARMTYPE_IMMEDIATE:
1872	case PARMTYPE_ADDRESS:
1873	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1874	return VERR_EM_INTERPRETER;
1875	addr = param1.val.val64;
1876	break;
1877
1878	default:
1879	return VERR_EM_INTERPRETER;
1880	}
1881
1882	/** @todo is addr always a flat linear address or ds based
1883	* (in absence of segment override prefixes)????
1884	*/
1885	rc = PGMInvalidatePage(pVM, addr);
1886	if (VBOX_SUCCESS(rc))
1887	{
1888	/* Manually invalidate the page for the VM's TLB. */
1889	Log(("SVMInvlpgA %VGv ASID=%d\n", addr, uASID));
1890	SVMInvlpgA(addr, uASID);
1891	return VINF_SUCCESS;
1892	}
1893	Assert(rc == VERR_REM_FLUSHED_PAGES_OVERFLOW);
1894	return rc;
1895	}
1896
1897	/**
1898	* Interprets INVLPG
1899	*
1900	* @returns VBox status code.
1901	* @retval VINF_* Scheduling instructions.
1902	* @retval VERR_EM_INTERPRETER Something we can't cope with.
1903	* @retval VERR_* Fatal errors.
1904	*
1905	* @param pVM The VM handle.
1906	* @param pRegFrame The register frame.
1907	* @param ASID Tagged TLB id for the guest
1908	*
1909	* Updates the EIP if an instruction was executed successfully.
1910	*/
1911	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1912	{
1913	/*
1914	* Only allow 32 & 64 bits code.
1915	*/
1916	DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
1917	if (enmMode != CPUMODE_16BIT)
1918	{
1919	RTGCPTR pbCode;
1920	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
1921	if (VBOX_SUCCESS(rc))
1922	{
1923	uint32_t cbOp;
1924	DISCPUSTATE Cpu;
1925
1926	Cpu.mode = enmMode;
1927	rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
1928	Assert(VBOX_FAILURE(rc) \|\| Cpu.pCurInstr->opcode == OP_INVLPG);
1929	if (VBOX_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
1930	{
1931	Assert(cbOp == Cpu.opsize);
1932	rc = svmInterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
1933	if (VBOX_SUCCESS(rc))
1934	{
1935	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
1936	}
1937	return rc;
1938	}
1939	}
1940	}
1941	return VERR_EM_INTERPRETER;
1942	}
1943
1944
1945	/**
1946	* Invalidates a guest page
1947	*
1948	* @returns VBox status code.
1949	* @param pVM The VM to operate on.
1950	* @param GCVirt Page to invalidate
1951	*/
1952	HWACCMR0DECL(int) SVMR0InvalidatePage(PVM pVM, RTGCPTR GCVirt)
1953	{
1954	bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB \| pVM->hwaccm.s.svm.fForceTLBFlush;
1955
1956	/* Skip it if a TLB flush is already pending. */
1957	if (!fFlushPending)
1958	{
1959	SVM_VMCB *pVMCB;
1960
1961	Log2(("SVMR0InvalidatePage %VGv\n", GCVirt));
1962	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1963	Assert(pVM->hwaccm.s.svm.fSupported);
1964
1965	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
1966	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
1967
1968	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageManual);
1969	SVMInvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
1970	}
1971	return VINF_SUCCESS;
1972	}
1973
1974
1975	/**
1976	* Invalidates a guest page by physical address
1977	*
1978	* NOTE: Assumes the current instruction references this physical page though a virtual address!!
1979	*
1980	* @returns VBox status code.
1981	* @param pVM The VM to operate on.
1982	* @param GCPhys Page to invalidate
1983	*/
1984	HWACCMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys)
1985	{
1986	bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB \| pVM->hwaccm.s.svm.fForceTLBFlush;
1987
1988	Assert(pVM->hwaccm.s.fNestedPaging);
1989
1990	/* Skip it if a TLB flush is already pending. */
1991	if (!fFlushPending)
1992	{
1993	CPUMCTX *pCtx;
1994	int rc;
1995	SVM_VMCB *pVMCB;
1996
1997	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
1998	AssertRCReturn(rc, rc);
1999
2000	Log2(("SVMR0InvalidatePhysPage %VGp\n", GCPhys));
2001	AssertReturn(pVM, VERR_INVALID_PARAMETER);
2002	Assert(pVM->hwaccm.s.svm.fSupported);
2003
2004	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
2005	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2006
2007	/*
2008	* Only allow 32 & 64 bits code.
2009	*/
2010	DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid);
2011	if (enmMode != CPUMODE_16BIT)
2012	{
2013	RTGCPTR pbCode;
2014	int rc = SELMValidateAndConvertCSAddr(pVM, pCtx->eflags, pCtx->ss, pCtx->cs, &pCtx->csHid, (RTGCPTR)pCtx->rip, &pbCode);
2015	if (VBOX_SUCCESS(rc))
2016	{
2017	uint32_t cbOp;
2018	DISCPUSTATE Cpu;
2019	OP_PARAMVAL param1;
2020	RTGCPTR addr;
2021
2022	Cpu.mode = enmMode;
2023	rc = EMInterpretDisasOneEx(pVM, pbCode, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);
2024	AssertRCReturn(rc, rc);
2025	Assert(cbOp == Cpu.opsize);
2026
2027	int rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param1, &param1, PARAM_SOURCE);
2028	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2029
2030	switch(param1.type)
2031	{
2032	case PARMTYPE_IMMEDIATE:
2033	case PARMTYPE_ADDRESS:
2034	AssertReturn((param1.flags & (PARAM_VAL32\|PARAM_VAL64)), VERR_EM_INTERPRETER);
2035
2036	addr = param1.val.val64;
2037	break;
2038
2039	default:
2040	AssertFailed();
2041	return VERR_EM_INTERPRETER;
2042	}
2043
2044	/* Manually invalidate the page for the VM's TLB. */
2045	Log(("SVMR0InvalidatePhysPage Phys=%VGp Virt=%VGv ASID=%d\n", GCPhys, addr, pVMCB->ctrl.TLBCtrl.n.u32ASID));
2046	SVMInvlpgA(addr, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2047	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPhysPageManual);
2048
2049	return VINF_SUCCESS;
2050	}
2051	}
2052	AssertFailed();
2053	return VERR_EM_INTERPRETER;
2054	}
2055	return VINF_SUCCESS;
2056	}

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 10014

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