HWSVMR0.cpp@ 10110

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1	/* $Id: HWSVMR0.cpp 10110 2008-07-02 14:22:41Z vboxsync $ */
2	/** @file
3	* HWACCM SVM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_svm.h>
32	#include <VBox/pgm.h>
33	#include <VBox/pdm.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <VBox/selm.h>
37	#include <VBox/iom.h>
38	#include <VBox/dis.h>
39	#include <VBox/dbgf.h>
40	#include <VBox/disopcode.h>
41	#include <iprt/param.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm.h>
44	#include <iprt/cpuset.h>
45	#include <iprt/mp.h>
46	#include "HWSVMR0.h"
47
48	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
49
50	/**
51	* Sets up and activates AMD-V on the current CPU
52	*
53	* @returns VBox status code.
54	* @param pCpu CPU info struct
55	* @param pVM The VM to operate on.
56	* @param pvPageCpu Pointer to the global cpu page
57	* @param pPageCpuPhys Physical address of the global cpu page
58	*/
59	HWACCMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
60	{
61	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
62	AssertReturn(pVM, VERR_INVALID_PARAMETER);
63	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
64
65	/* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
66
67	#ifdef LOG_ENABLED
68	SUPR0Printf("SVMR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
69	#endif
70
71	/* Turn on AMD-V in the EFER MSR. */
72	uint64_t val = ASMRdMsr(MSR_K6_EFER);
73	if (!(val & MSR_K6_EFER_SVME))
74	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
75
76	/* Write the physical page address where the CPU will store the host state while executing the VM. */
77	ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
78
79	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
80	pCpu->cTLBFlushes = 0;
81	return VINF_SUCCESS;
82	}
83
84	/**
85	* Deactivates AMD-V on the current CPU
86	*
87	* @returns VBox status code.
88	* @param pCpu CPU info struct
89	* @param pvPageCpu Pointer to the global cpu page
90	* @param pPageCpuPhys Physical address of the global cpu page
91	*/
92	HWACCMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
93	{
94	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
95	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
96
97	#ifdef LOG_ENABLED
98	SUPR0Printf("SVMR0DisableCpu cpu %d\n", pCpu->idCpu);
99	#endif
100
101	/* Turn off AMD-V in the EFER MSR. */
102	uint64_t val = ASMRdMsr(MSR_K6_EFER);
103	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
104
105	/* Invalidate host state physical address. */
106	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
107	pCpu->uCurrentASID = 0;
108
109	return VINF_SUCCESS;
110	}
111
112	/**
113	* Does Ring-0 per VM AMD-V init.
114	*
115	* @returns VBox status code.
116	* @param pVM The VM to operate on.
117	*/
118	HWACCMR0DECL(int) SVMR0InitVM(PVM pVM)
119	{
120	int rc;
121
122	/* Allocate one page for the VM control block (VMCB). */
123	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
124	if (RT_FAILURE(rc))
125	return rc;
126
127	pVM->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCB);
128	pVM->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCB, 0);
129	ASMMemZero32(pVM->hwaccm.s.svm.pVMCB, PAGE_SIZE);
130
131	/* Allocate one page for the host context */
132	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
133	if (RT_FAILURE(rc))
134	return rc;
135
136	pVM->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCBHost);
137	pVM->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCBHost, 0);
138	ASMMemZero32(pVM->hwaccm.s.svm.pVMCBHost, PAGE_SIZE);
139
140	/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
141	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
142	if (RT_FAILURE(rc))
143	return rc;
144
145	pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
146	pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
147	/* Set all bits to intercept all IO accesses. */
148	ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
149
150	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
151	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
152	if (RT_FAILURE(rc))
153	return rc;
154
155	pVM->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
156	pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
157	/* Set all bits to intercept all MSR accesses. */
158	ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
159
160	/* Erratum 170 which requires a forced TLB flush for each world switch:
161	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
162	*
163	* All BH-G1/2 and DH-G1/2 models include a fix:
164	* Athlon X2: 0x6b 1/2
165	* 0x68 1/2
166	* Athlon 64: 0x7f 1
167	* 0x6f 2
168	* Sempron: 0x7f 1/2
169	* 0x6f 2
170	* 0x6c 2
171	* 0x7c 2
172	* Turion 64: 0x68 2
173	*
174	*/
175	uint32_t u32Dummy;
176	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
177	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
178	u32BaseFamily= (u32Version >> 8) & 0xf;
179	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
180	u32Model = ((u32Version >> 4) & 0xf);
181	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
182	u32Stepping = u32Version & 0xf;
183	if ( u32Family == 0xf
184	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
185	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
186	{
187	Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
188	pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
189	}
190
191	/* Invalidate the last cpu we were running on. */
192	pVM->hwaccm.s.svm.idLastCpu = NIL_RTCPUID;
193	return VINF_SUCCESS;
194	}
195
196	/**
197	* Does Ring-0 per VM AMD-V termination.
198	*
199	* @returns VBox status code.
200	* @param pVM The VM to operate on.
201	*/
202	HWACCMR0DECL(int) SVMR0TermVM(PVM pVM)
203	{
204	if (pVM->hwaccm.s.svm.pMemObjVMCB)
205	{
206	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCB, false);
207	pVM->hwaccm.s.svm.pVMCB = 0;
208	pVM->hwaccm.s.svm.pVMCBPhys = 0;
209	pVM->hwaccm.s.svm.pMemObjVMCB = 0;
210	}
211	if (pVM->hwaccm.s.svm.pMemObjVMCBHost)
212	{
213	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCBHost, false);
214	pVM->hwaccm.s.svm.pVMCBHost = 0;
215	pVM->hwaccm.s.svm.pVMCBHostPhys = 0;
216	pVM->hwaccm.s.svm.pMemObjVMCBHost = 0;
217	}
218	if (pVM->hwaccm.s.svm.pMemObjIOBitmap)
219	{
220	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
221	pVM->hwaccm.s.svm.pIOBitmap = 0;
222	pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
223	pVM->hwaccm.s.svm.pMemObjIOBitmap = 0;
224	}
225	if (pVM->hwaccm.s.svm.pMemObjMSRBitmap)
226	{
227	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
228	pVM->hwaccm.s.svm.pMSRBitmap = 0;
229	pVM->hwaccm.s.svm.pMSRBitmapPhys = 0;
230	pVM->hwaccm.s.svm.pMemObjMSRBitmap = 0;
231	}
232	return VINF_SUCCESS;
233	}
234
235	/**
236	* Sets up AMD-V for the specified VM
237	*
238	* @returns VBox status code.
239	* @param pVM The VM to operate on.
240	*/
241	HWACCMR0DECL(int) SVMR0SetupVM(PVM pVM)
242	{
243	int rc = VINF_SUCCESS;
244	SVM_VMCB *pVMCB;
245
246	AssertReturn(pVM, VERR_INVALID_PARAMETER);
247
248	Assert(pVM->hwaccm.s.svm.fSupported);
249
250	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
251	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
252
253	/* Program the control fields. Most of them never have to be changed again. */
254	/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
255	/** @note CR0 & CR4 can be safely read when guest and shadow copies are identical. */
256	if (!pVM->hwaccm.s.fNestedPaging)
257	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
258	else
259	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
260
261	/*
262	* CR0/3/4 writes must be intercepted for obvious reasons.
263	*/
264	if (!pVM->hwaccm.s.fNestedPaging)
265	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
266	else
267	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
268
269	/* Intercept all DRx reads and writes. */
270	pVMCB->ctrl.u16InterceptRdDRx = RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7);
271	pVMCB->ctrl.u16InterceptWrDRx = RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7);
272
273	/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
274	* All breakpoints are automatically cleared when the VM exits.
275	*/
276
277	pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
278	#ifndef DEBUG
279	if (pVM->hwaccm.s.fNestedPaging)
280	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(14); /* no longer need to intercept #PF. */
281	#endif
282
283	pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
284	\| SVM_CTRL1_INTERCEPT_VINTR
285	\| SVM_CTRL1_INTERCEPT_NMI
286	\| SVM_CTRL1_INTERCEPT_SMI
287	\| SVM_CTRL1_INTERCEPT_INIT
288	\| SVM_CTRL1_INTERCEPT_RDPMC
289	\| SVM_CTRL1_INTERCEPT_CPUID
290	\| SVM_CTRL1_INTERCEPT_RSM
291	\| SVM_CTRL1_INTERCEPT_HLT
292	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
293	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
294	\| SVM_CTRL1_INTERCEPT_INVLPG
295	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
296	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH
297	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
298	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
299	;
300	/* With nested paging we don't care about invlpg anymore. */
301	if (pVM->hwaccm.s.fNestedPaging)
302	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
303
304	pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
305	\| SVM_CTRL2_INTERCEPT_VMMCALL
306	\| SVM_CTRL2_INTERCEPT_VMLOAD
307	\| SVM_CTRL2_INTERCEPT_VMSAVE
308	\| SVM_CTRL2_INTERCEPT_STGI
309	\| SVM_CTRL2_INTERCEPT_CLGI
310	\| SVM_CTRL2_INTERCEPT_SKINIT
311	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
312	\| SVM_CTRL2_INTERCEPT_WBINVD
313	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
314	;
315	Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
316	Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
317	Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
318
319	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
320	pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
321
322	/* Set IO and MSR bitmap addresses. */
323	pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
324	pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
325
326	/* No LBR virtualization. */
327	pVMCB->ctrl.u64LBRVirt = 0;
328
329	/** The ASID must start at 1; the host uses 0. */
330	pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
331
332	/** Setup the PAT msr (nested paging only) */
333	pVMCB->guest.u64GPAT = 0x0007040600070406ULL;
334	return rc;
335	}
336
337
338	/**
339	* Injects an event (trap or external interrupt)
340	*
341	* @param pVM The VM to operate on.
342	* @param pVMCB SVM control block
343	* @param pCtx CPU Context
344	* @param pIntInfo SVM interrupt info
345	*/
346	inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx, SVM_EVENT* pEvent)
347	{
348	#ifdef VBOX_STRICT
349	if (pEvent->n.u8Vector == 0xE)
350	Log(("SVM: Inject int %d at %VGv error code=%02x CR2=%VGv intInfo=%08x\n", pEvent->n.u8Vector, pCtx->rip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
351	else
352	if (pEvent->n.u8Vector < 0x20)
353	Log(("SVM: Inject int %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->rip, pEvent->n.u32ErrorCode));
354	else
355	{
356	Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->rip));
357	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
358	Assert(pCtx->eflags.u32 & X86_EFL_IF);
359	}
360	#endif
361
362	/* Set event injection state. */
363	pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
364	}
365
366
367	/**
368	* Checks for pending guest interrupts and injects them
369	*
370	* @returns VBox status code.
371	* @param pVM The VM to operate on.
372	* @param pVMCB SVM control block
373	* @param pCtx CPU Context
374	*/
375	static int SVMR0CheckPendingInterrupt(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx)
376	{
377	int rc;
378
379	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
380	if (pVM->hwaccm.s.Event.fPending)
381	{
382	SVM_EVENT Event;
383
384	Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip));
385	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
386	Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
387	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
388
389	pVM->hwaccm.s.Event.fPending = false;
390	return VINF_SUCCESS;
391	}
392
393	/* When external interrupts are pending, we should exit the VM when IF is set. */
394	if ( !TRPMHasTrap(pVM)
395	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
396	{
397	if (!(pCtx->eflags.u32 & X86_EFL_IF))
398	{
399	if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
400	{
401	LogFlow(("Enable irq window exit!\n"));
402	/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
403	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
404	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
405	pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1; /* ignore the priority in the TPR; just deliver it */
406	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
407	}
408	}
409	else
410	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
411	{
412	uint8_t u8Interrupt;
413
414	rc = PDMGetInterrupt(pVM, &u8Interrupt);
415	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
416	if (VBOX_SUCCESS(rc))
417	{
418	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
419	AssertRC(rc);
420	}
421	else
422	{
423	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
424	Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)));
425	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
426	/* Just continue */
427	}
428	}
429	else
430	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->rip));
431	}
432
433	#ifdef VBOX_STRICT
434	if (TRPMHasTrap(pVM))
435	{
436	uint8_t u8Vector;
437	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
438	AssertRC(rc);
439	}
440	#endif
441
442	if ( pCtx->eflags.u32 & X86_EFL_IF
443	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
444	&& TRPMHasTrap(pVM)
445	)
446	{
447	uint8_t u8Vector;
448	int rc;
449	TRPMEVENT enmType;
450	SVM_EVENT Event;
451	RTGCUINT u32ErrorCode;
452
453	Event.au64[0] = 0;
454
455	/* If a new event is pending, then dispatch it now. */
456	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &u32ErrorCode, 0);
457	AssertRC(rc);
458	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
459	Assert(enmType != TRPM_SOFTWARE_INT);
460
461	/* Clear the pending trap. */
462	rc = TRPMResetTrap(pVM);
463	AssertRC(rc);
464
465	Event.n.u8Vector = u8Vector;
466	Event.n.u1Valid = 1;
467	Event.n.u32ErrorCode = u32ErrorCode;
468
469	if (enmType == TRPM_TRAP)
470	{
471	switch (u8Vector) {
472	case 8:
473	case 10:
474	case 11:
475	case 12:
476	case 13:
477	case 14:
478	case 17:
479	/* Valid error codes. */
480	Event.n.u1ErrorCodeValid = 1;
481	break;
482	default:
483	break;
484	}
485	if (u8Vector == X86_XCPT_NMI)
486	Event.n.u3Type = SVM_EVENT_NMI;
487	else
488	Event.n.u3Type = SVM_EVENT_EXCEPTION;
489	}
490	else
491	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
492
493	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
494	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
495	} /* if (interrupts can be dispatched) */
496
497	return VINF_SUCCESS;
498	}
499
500	/**
501	* Save the host state
502	*
503	* @returns VBox status code.
504	* @param pVM The VM to operate on.
505	*/
506	HWACCMR0DECL(int) SVMR0SaveHostState(PVM pVM)
507	{
508	/* Nothing to do here. */
509	return VINF_SUCCESS;
510	}
511
512	/**
513	* Loads the guest state
514	*
515	* @returns VBox status code.
516	* @param pVM The VM to operate on.
517	* @param pCtx Guest context
518	*/
519	HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
520	{
521	RTGCUINTPTR val;
522	SVM_VMCB *pVMCB;
523
524	if (pVM == NULL)
525	return VERR_INVALID_PARAMETER;
526
527	/* Setup AMD SVM. */
528	Assert(pVM->hwaccm.s.svm.fSupported);
529
530	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
531	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
532
533	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
534	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
535	{
536	SVM_WRITE_SELREG(CS, cs);
537	SVM_WRITE_SELREG(SS, ss);
538	SVM_WRITE_SELREG(DS, ds);
539	SVM_WRITE_SELREG(ES, es);
540	SVM_WRITE_SELREG(FS, fs);
541	SVM_WRITE_SELREG(GS, gs);
542	}
543
544	/* Guest CPU context: LDTR. */
545	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
546	{
547	SVM_WRITE_SELREG(LDTR, ldtr);
548	}
549
550	/* Guest CPU context: TR. */
551	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
552	{
553	SVM_WRITE_SELREG(TR, tr);
554	}
555
556	/* Guest CPU context: GDTR. */
557	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
558	{
559	pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
560	pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
561	}
562
563	/* Guest CPU context: IDTR. */
564	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
565	{
566	pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
567	pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
568	}
569
570	/*
571	* Sysenter MSRs (unconditional)
572	*/
573	pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
574	pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
575	pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
576
577	/* Control registers */
578	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
579	{
580	val = pCtx->cr0;
581	if (CPUMIsGuestFPUStateActive(pVM) == false)
582	{
583	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
584	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
585	}
586	else
587	{
588	Assert(pVM->hwaccm.s.svm.fResumeVM == true);
589	/** @todo check if we support the old style mess correctly. */
590	if (!(val & X86_CR0_NE))
591	{
592	Log(("Forcing X86_CR0_NE!!!\n"));
593
594	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
595	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
596	{
597	pVMCB->ctrl.u32InterceptException \|= RT_BIT(16);
598	pVM->hwaccm.s.fFPUOldStyleOverride = true;
599	}
600	}
601	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
602	}
603	/* Always enable caching. */
604	val &= ~(X86_CR0_CD\|X86_CR0_NW);
605
606	/* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
607	/* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
608	if (!pVM->hwaccm.s.fNestedPaging)
609	{
610	val \|= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
611	val \|= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
612	}
613	pVMCB->guest.u64CR0 = val;
614	}
615	/* CR2 as well */
616	pVMCB->guest.u64CR2 = pCtx->cr2;
617
618	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
619	{
620	/* Save our shadow CR3 register. */
621	if (pVM->hwaccm.s.fNestedPaging)
622	{
623	pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVM, PGMGetHostMode(pVM));
624	Assert(pVMCB->ctrl.u64NestedPagingCR3);
625	pVMCB->guest.u64CR3 = pCtx->cr3;
626	}
627	else
628	pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
629	}
630
631	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
632	{
633	val = pCtx->cr4;
634	if (!pVM->hwaccm.s.fNestedPaging)
635	{
636	switch(pVM->hwaccm.s.enmShadowMode)
637	{
638	case PGMMODE_REAL:
639	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
640	AssertFailed();
641	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
642
643	case PGMMODE_32_BIT: /* 32-bit paging. */
644	break;
645
646	case PGMMODE_PAE: /* PAE paging. */
647	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
648	/** @todo use normal 32 bits paging */
649	val \|= X86_CR4_PAE;
650	break;
651
652	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
653	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
654	#ifdef VBOX_ENABLE_64_BITS_GUESTS
655	break;
656	#else
657	AssertFailed();
658	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
659	#endif
660
661	default: /* shut up gcc */
662	AssertFailed();
663	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
664	}
665	}
666	pVMCB->guest.u64CR4 = val;
667	}
668
669	/* Debug registers. */
670	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
671	{
672	/** @todo DR0-6 */
673	val = pCtx->dr7;
674	val &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
675	val \|= 0x400; /* must be one */
676	#ifdef VBOX_STRICT
677	val = 0x400;
678	#endif
679	pVMCB->guest.u64DR7 = val;
680
681	pVMCB->guest.u64DR6 = pCtx->dr6;
682	}
683
684	/* EIP, ESP and EFLAGS */
685	pVMCB->guest.u64RIP = pCtx->rip;
686	pVMCB->guest.u64RSP = pCtx->rsp;
687	pVMCB->guest.u64RFlags = pCtx->eflags.u32;
688
689	/* Set CPL */
690	pVMCB->guest.u8CPL = pCtx->csHid.Attr.n.u2Dpl;
691
692	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
693	pVMCB->guest.u64RAX = pCtx->rax;
694
695	/* vmrun will fail without MSR_K6_EFER_SVME. */
696	pVMCB->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
697
698	/* 64 bits guest mode? */
699	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
700	{
701	#if !defined(VBOX_WITH_64_BITS_GUESTS) \|\| HC_ARCH_BITS != 64
702	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
703	#else
704	pVM->hwaccm.s.svm.pfnVMRun = SVMVMRun64;
705	#endif
706	/* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
707	pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
708	pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
709	}
710	else
711	{
712	/* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
713	pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
714
715	pVM->hwaccm.s.svm.pfnVMRun = SVMVMRun;
716	}
717
718	/** TSC offset. */
719	if (TMCpuTickCanUseRealTSC(pVM, &pVMCB->ctrl.u64TSCOffset))
720	{
721	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
722	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
723	}
724	else
725	{
726	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
727	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
728	}
729
730	/* Sync the various msrs for 64 bits mode. */
731	pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
732	pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
733	pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
734	pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
735	pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
736
737	#ifdef DEBUG
738	/* Intercept X86_XCPT_DB if stepping is enabled */
739	if (DBGFIsStepping(pVM))
740	pVMCB->ctrl.u32InterceptException \|= RT_BIT(1);
741	else
742	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(1);
743	#endif
744
745	/* TPR caching in CR8 */
746	uint8_t u8TPR;
747	int rc = PDMApicGetTPR(pVM, &u8TPR);
748	AssertRC(rc);
749	pCtx->cr8 = u8TPR;
750	pVMCB->ctrl.IntCtrl.n.u8VTPR = u8TPR;
751
752	/* Done. */
753	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
754
755	return VINF_SUCCESS;
756	}
757
758
759	/**
760	* Runs guest code in an SVM VM.
761	*
762	* @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
763	*
764	* @returns VBox status code.
765	* @param pVM The VM to operate on.
766	* @param pCtx Guest context
767	* @param pCpu CPU info struct
768	*/
769	HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx, PHWACCM_CPUINFO pCpu)
770	{
771	int rc = VINF_SUCCESS;
772	uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
773	SVM_VMCB *pVMCB;
774	bool fGuestStateSynced = false;
775	unsigned cResume = 0;
776
777	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
778
779	AssertReturn(pCpu->fConfigured, VERR_EM_INTERNAL_ERROR);
780
781	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
782	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
783
784	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
785	*/
786	ResumeExecution:
787	/* Safety precaution; looping for too long here can have a very bad effect on the host */
788	if (++cResume > HWACCM_MAX_RESUME_LOOPS)
789	{
790	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
791	rc = VINF_EM_RAW_INTERRUPT;
792	goto end;
793	}
794
795	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
796	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
797	{
798	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
799	if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
800	{
801	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
802	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
803	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
804	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
805	*/
806	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
807	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
808	pVMCB->ctrl.u64IntShadow = 0;
809	}
810	}
811	else
812	{
813	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
814	pVMCB->ctrl.u64IntShadow = 0;
815	}
816
817	/* Check for pending actions that force us to go back to ring 3. */
818	#ifdef DEBUG
819	/* Intercept X86_XCPT_DB if stepping is enabled */
820	if (!DBGFIsStepping(pVM))
821	#endif
822	{
823	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
824	{
825	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
826	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
827	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
828	rc = VINF_EM_RAW_TO_R3;
829	goto end;
830	}
831	}
832
833	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
834	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
835	{
836	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
837	rc = VINF_EM_PENDING_REQUEST;
838	goto end;
839	}
840
841	/* When external interrupts are pending, we should exit the VM when IF is set. */
842	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
843	rc = SVMR0CheckPendingInterrupt(pVM, pVMCB, pCtx);
844	if (VBOX_FAILURE(rc))
845	{
846	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
847	goto end;
848	}
849
850	/* Load the guest state */
851	rc = SVMR0LoadGuestState(pVM, pCtx);
852	if (rc != VINF_SUCCESS)
853	{
854	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
855	goto end;
856	}
857	fGuestStateSynced = true;
858
859	/* All done! Let's start VM execution. */
860	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
861
862	/* Enable nested paging if necessary (disabled each time after #VMEXIT). */
863	pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
864
865	/* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
866	if (!pVM->hwaccm.s.svm.fResumeVM)
867	{
868	if ( pVM->hwaccm.s.svm.idLastCpu != pCpu->idCpu
869	/* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
870	\|\| pVM->hwaccm.s.svm.cTLBFlushes != pCpu->cTLBFlushes)
871	{
872	/* Force a TLB flush on VM entry. */
873	pVM->hwaccm.s.svm.fForceTLBFlush = true;
874	}
875	pVM->hwaccm.s.svm.idLastCpu = pCpu->idCpu;
876	}
877
878	/* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
879	if ( pVM->hwaccm.s.svm.fForceTLBFlush
880	&& !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
881	{
882	if (++pCpu->uCurrentASID >= pVM->hwaccm.s.svm.u32MaxASID)
883	{
884	pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
885	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
886	pCpu->cTLBFlushes++;
887	}
888	else
889	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushASID);
890
891	pVM->hwaccm.s.svm.cTLBFlushes = pCpu->cTLBFlushes;
892	}
893	else
894	{
895	/* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
896	if (!pCpu->uCurrentASID)
897	pCpu->uCurrentASID = 1;
898
899	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVM->hwaccm.s.svm.fForceTLBFlush;
900	}
901
902	AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.svm.u32MaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
903	pVMCB->ctrl.TLBCtrl.n.u32ASID = pCpu->uCurrentASID;
904
905	#ifdef VBOX_WITH_STATISTICS
906	if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
907	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBWorldSwitch);
908	else
909	STAM_COUNTER_INC(&pVM->hwaccm.s.StatNoFlushTLBWorldSwitch);
910	#endif
911
912	/* In case we execute a goto ResumeExecution later on. */
913	pVM->hwaccm.s.svm.fResumeVM = true;
914	pVM->hwaccm.s.svm.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
915
916	Assert(sizeof(pVM->hwaccm.s.svm.pVMCBPhys) == 8);
917	Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
918	\| SVM_CTRL2_INTERCEPT_VMMCALL
919	\| SVM_CTRL2_INTERCEPT_VMLOAD
920	\| SVM_CTRL2_INTERCEPT_VMSAVE
921	\| SVM_CTRL2_INTERCEPT_STGI
922	\| SVM_CTRL2_INTERCEPT_CLGI
923	\| SVM_CTRL2_INTERCEPT_SKINIT
924	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
925	\| SVM_CTRL2_INTERCEPT_WBINVD
926	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
927	));
928	Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
929	Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
930	Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
931	Assert(pVMCB->ctrl.u64LBRVirt == 0);
932
933	pVM->hwaccm.s.svm.pfnVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);
934	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
935
936	/**
937	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
938	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
939	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
940	*/
941
942	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
943
944	/* Reason for the VM exit */
945	exitCode = pVMCB->ctrl.u64ExitCode;
946
947	if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
948	{
949	HWACCMDumpRegs(pCtx);
950	#ifdef DEBUG
951	Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
952	Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
953	Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
954	Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
955	Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
956	Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
957	Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
958	Log(("ctrl.u64IOPMPhysAddr %VX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
959	Log(("ctrl.u64MSRPMPhysAddr %VX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
960	Log(("ctrl.u64TSCOffset %VX64\n", pVMCB->ctrl.u64TSCOffset));
961
962	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
963	Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
964	Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
965	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
966
967	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
968	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
969	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
970	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
971	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
972	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
973	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
974	Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
975	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
976	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
977
978	Log(("ctrl.u64IntShadow %VX64\n", pVMCB->ctrl.u64IntShadow));
979	Log(("ctrl.u64ExitCode %VX64\n", pVMCB->ctrl.u64ExitCode));
980	Log(("ctrl.u64ExitInfo1 %VX64\n", pVMCB->ctrl.u64ExitInfo1));
981	Log(("ctrl.u64ExitInfo2 %VX64\n", pVMCB->ctrl.u64ExitInfo2));
982	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
983	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
984	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
985	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
986	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
987	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
988	Log(("ctrl.NestedPaging %VX64\n", pVMCB->ctrl.NestedPaging.au64));
989	Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
990	Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
991	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
992	Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
993	Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
994	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
995
996	Log(("ctrl.u64NestedPagingCR3 %VX64\n", pVMCB->ctrl.u64NestedPagingCR3));
997	Log(("ctrl.u64LBRVirt %VX64\n", pVMCB->ctrl.u64LBRVirt));
998
999	Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
1000	Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1001	Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1002	Log(("guest.CS.u64Base %VX64\n", pVMCB->guest.CS.u64Base));
1003	Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1004	Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1005	Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1006	Log(("guest.DS.u64Base %VX64\n", pVMCB->guest.DS.u64Base));
1007	Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1008	Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1009	Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1010	Log(("guest.ES.u64Base %VX64\n", pVMCB->guest.ES.u64Base));
1011	Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1012	Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1013	Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1014	Log(("guest.FS.u64Base %VX64\n", pVMCB->guest.FS.u64Base));
1015	Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1016	Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1017	Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1018	Log(("guest.GS.u64Base %VX64\n", pVMCB->guest.GS.u64Base));
1019
1020	Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1021	Log(("guest.GDTR.u64Base %VX64\n", pVMCB->guest.GDTR.u64Base));
1022
1023	Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1024	Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1025	Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1026	Log(("guest.LDTR.u64Base %VX64\n", pVMCB->guest.LDTR.u64Base));
1027
1028	Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1029	Log(("guest.IDTR.u64Base %VX64\n", pVMCB->guest.IDTR.u64Base));
1030
1031	Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1032	Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1033	Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1034	Log(("guest.TR.u64Base %VX64\n", pVMCB->guest.TR.u64Base));
1035
1036	Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1037	Log(("guest.u64CR0 %VX64\n", pVMCB->guest.u64CR0));
1038	Log(("guest.u64CR2 %VX64\n", pVMCB->guest.u64CR2));
1039	Log(("guest.u64CR3 %VX64\n", pVMCB->guest.u64CR3));
1040	Log(("guest.u64CR4 %VX64\n", pVMCB->guest.u64CR4));
1041	Log(("guest.u64DR6 %VX64\n", pVMCB->guest.u64DR6));
1042	Log(("guest.u64DR7 %VX64\n", pVMCB->guest.u64DR7));
1043
1044	Log(("guest.u64RIP %VX64\n", pVMCB->guest.u64RIP));
1045	Log(("guest.u64RSP %VX64\n", pVMCB->guest.u64RSP));
1046	Log(("guest.u64RAX %VX64\n", pVMCB->guest.u64RAX));
1047	Log(("guest.u64RFlags %VX64\n", pVMCB->guest.u64RFlags));
1048
1049	Log(("guest.u64SysEnterCS %VX64\n", pVMCB->guest.u64SysEnterCS));
1050	Log(("guest.u64SysEnterEIP %VX64\n", pVMCB->guest.u64SysEnterEIP));
1051	Log(("guest.u64SysEnterESP %VX64\n", pVMCB->guest.u64SysEnterESP));
1052
1053	Log(("guest.u64EFER %VX64\n", pVMCB->guest.u64EFER));
1054	Log(("guest.u64STAR %VX64\n", pVMCB->guest.u64STAR));
1055	Log(("guest.u64LSTAR %VX64\n", pVMCB->guest.u64LSTAR));
1056	Log(("guest.u64CSTAR %VX64\n", pVMCB->guest.u64CSTAR));
1057	Log(("guest.u64SFMASK %VX64\n", pVMCB->guest.u64SFMASK));
1058	Log(("guest.u64KernelGSBase %VX64\n", pVMCB->guest.u64KernelGSBase));
1059	Log(("guest.u64GPAT %VX64\n", pVMCB->guest.u64GPAT));
1060	Log(("guest.u64DBGCTL %VX64\n", pVMCB->guest.u64DBGCTL));
1061	Log(("guest.u64BR_FROM %VX64\n", pVMCB->guest.u64BR_FROM));
1062	Log(("guest.u64BR_TO %VX64\n", pVMCB->guest.u64BR_TO));
1063	Log(("guest.u64LASTEXCPFROM %VX64\n", pVMCB->guest.u64LASTEXCPFROM));
1064	Log(("guest.u64LASTEXCPTO %VX64\n", pVMCB->guest.u64LASTEXCPTO));
1065
1066	#endif
1067	rc = VERR_SVM_UNABLE_TO_START_VM;
1068	goto end;
1069	}
1070
1071	/* Let's first sync back eip, esp, and eflags. */
1072	pCtx->rip = pVMCB->guest.u64RIP;
1073	pCtx->rsp = pVMCB->guest.u64RSP;
1074	pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1075	/* eax is saved/restore across the vmrun instruction */
1076	pCtx->rax = pVMCB->guest.u64RAX;
1077
1078	pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
1079
1080	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1081	SVM_READ_SELREG(SS, ss);
1082	SVM_READ_SELREG(CS, cs);
1083	SVM_READ_SELREG(DS, ds);
1084	SVM_READ_SELREG(ES, es);
1085	SVM_READ_SELREG(FS, fs);
1086	SVM_READ_SELREG(GS, gs);
1087
1088	/* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1089	/* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1090	if ( pVM->hwaccm.s.fNestedPaging
1091	&& pCtx->cr3 != pVMCB->guest.u64CR3)
1092	{
1093	CPUMSetGuestCR3(pVM, pVMCB->guest.u64CR3);
1094	PGMUpdateCR3(pVM, pVMCB->guest.u64CR3);
1095	}
1096
1097	/** @note NOW IT'S SAFE FOR LOGGING! */
1098
1099	/* Take care of instruction fusing (sti, mov ss) */
1100	if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1101	{
1102	Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->rip));
1103	EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1104	}
1105	else
1106	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1107
1108	Log2(("exitCode = %x\n", exitCode));
1109
1110	/* Sync back the debug registers. */
1111	/** @todo Implement debug registers correctly. */
1112	pCtx->dr6 = pVMCB->guest.u64DR6;
1113	pCtx->dr7 = pVMCB->guest.u64DR7;
1114
1115	/* Update the APIC if the cached TPR value has changed. */
1116	if (pVMCB->ctrl.IntCtrl.n.u8VTPR != pCtx->cr8)
1117	{
1118	rc = PDMApicSetTPR(pVM, pVMCB->ctrl.IntCtrl.n.u8VTPR);
1119	AssertRC(rc);
1120	pCtx->cr8 = pVMCB->ctrl.IntCtrl.n.u8VTPR;
1121	}
1122	pVMCB->ctrl.IntCtrl.n.u8VTPR = pCtx->cr8;
1123
1124	/* Check if an injected event was interrupted prematurely. */
1125	pVM->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1126	if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1127	&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1128	{
1129	Log(("Pending inject %VX64 at %VGv exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitCode));
1130	pVM->hwaccm.s.Event.fPending = true;
1131	/* Error code present? (redundant) */
1132	if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1133	{
1134	pVM->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1135	}
1136	else
1137	pVM->hwaccm.s.Event.errCode = 0;
1138	}
1139	#ifdef VBOX_WITH_STATISTICS
1140	if (exitCode == SVM_EXIT_NPF)
1141	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitReasonNPF);
1142	else
1143	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1144	#endif
1145
1146	/* Deal with the reason of the VM-exit. */
1147	switch (exitCode)
1148	{
1149	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1150	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1151	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1152	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1153	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1154	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1155	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1156	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1157	{
1158	/* Pending trap. */
1159	SVM_EVENT Event;
1160	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1161
1162	Log2(("Hardware/software interrupt %d\n", vector));
1163	switch (vector)
1164	{
1165	#ifdef DEBUG
1166	case X86_XCPT_DB:
1167	rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), pVMCB->guest.u64DR6);
1168	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
1169	break;
1170	#endif
1171
1172	case X86_XCPT_NM:
1173	{
1174	uint32_t oldCR0;
1175
1176	Log(("#NM fault at %VGv\n", pCtx->rip));
1177
1178	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1179	oldCR0 = ASMGetCR0();
1180	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1181	rc = CPUMHandleLazyFPU(pVM);
1182	if (rc == VINF_SUCCESS)
1183	{
1184	Assert(CPUMIsGuestFPUStateActive(pVM));
1185
1186	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
1187	ASMSetCR0(oldCR0);
1188
1189	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1190
1191	/* Continue execution. */
1192	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1193	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1194
1195	goto ResumeExecution;
1196	}
1197
1198	Log(("Forward #NM fault to the guest\n"));
1199	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1200
1201	Event.au64[0] = 0;
1202	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1203	Event.n.u1Valid = 1;
1204	Event.n.u8Vector = X86_XCPT_NM;
1205
1206	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1207	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1208	goto ResumeExecution;
1209	}
1210
1211	case X86_XCPT_PF: /* Page fault */
1212	{
1213	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1214	RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1215
1216	#ifdef DEBUG
1217	if (pVM->hwaccm.s.fNestedPaging)
1218	{ /* A genuine pagefault.
1219	* Forward the trap to the guest by injecting the exception and resuming execution.
1220	*/
1221	Log(("Guest page fault at %VGv cr2=%VGv error code %x rsp=%RX64\n", pCtx->rip, uFaultAddress, errCode, pCtx->rsp));
1222	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1223
1224	/* Now we must update CR2. */
1225	pCtx->cr2 = uFaultAddress;
1226
1227	Event.au64[0] = 0;
1228	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1229	Event.n.u1Valid = 1;
1230	Event.n.u8Vector = X86_XCPT_PF;
1231	Event.n.u1ErrorCodeValid = 1;
1232	Event.n.u32ErrorCode = errCode;
1233
1234	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1235
1236	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1237	goto ResumeExecution;
1238	}
1239	#endif
1240	Assert(!pVM->hwaccm.s.fNestedPaging);
1241
1242	Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, uFaultAddress, errCode));
1243	/* Exit qualification contains the linear address of the page fault. */
1244	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1245	TRPMSetErrorCode(pVM, errCode);
1246	TRPMSetFaultAddress(pVM, uFaultAddress);
1247
1248	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1249	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1250	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
1251	if (rc == VINF_SUCCESS)
1252	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1253	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, uFaultAddress, errCode));
1254	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1255
1256	TRPMResetTrap(pVM);
1257
1258	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1259	goto ResumeExecution;
1260	}
1261	else
1262	if (rc == VINF_EM_RAW_GUEST_TRAP)
1263	{ /* A genuine pagefault.
1264	* Forward the trap to the guest by injecting the exception and resuming execution.
1265	*/
1266	Log2(("Forward page fault to the guest\n"));
1267	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1268	/* The error code might have been changed. */
1269	errCode = TRPMGetErrorCode(pVM);
1270
1271	TRPMResetTrap(pVM);
1272
1273	/* Now we must update CR2. */
1274	pCtx->cr2 = uFaultAddress;
1275
1276	Event.au64[0] = 0;
1277	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1278	Event.n.u1Valid = 1;
1279	Event.n.u8Vector = X86_XCPT_PF;
1280	Event.n.u1ErrorCodeValid = 1;
1281	Event.n.u32ErrorCode = errCode;
1282
1283	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1284
1285	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1286	goto ResumeExecution;
1287	}
1288	#ifdef VBOX_STRICT
1289	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1290	LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
1291	#endif
1292	/* Need to go back to the recompiler to emulate the instruction. */
1293	TRPMResetTrap(pVM);
1294	break;
1295	}
1296
1297	case X86_XCPT_MF: /* Floating point exception. */
1298	{
1299	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1300	if (!(pCtx->cr0 & X86_CR0_NE))
1301	{
1302	/* old style FPU error reporting needs some extra work. */
1303	/** @todo don't fall back to the recompiler, but do it manually. */
1304	rc = VINF_EM_RAW_EMULATE_INSTR;
1305	break;
1306	}
1307	Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1308
1309	Event.au64[0] = 0;
1310	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1311	Event.n.u1Valid = 1;
1312	Event.n.u8Vector = X86_XCPT_MF;
1313
1314	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1315
1316	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1317	goto ResumeExecution;
1318	}
1319
1320	#ifdef VBOX_STRICT
1321	case X86_XCPT_GP: /* General protection failure exception.*/
1322	case X86_XCPT_UD: /* Unknown opcode exception. */
1323	case X86_XCPT_DE: /* Debug exception. */
1324	case X86_XCPT_SS: /* Stack segment exception. */
1325	case X86_XCPT_NP: /* Segment not present exception. */
1326	{
1327	Event.au64[0] = 0;
1328	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1329	Event.n.u1Valid = 1;
1330	Event.n.u8Vector = vector;
1331
1332	switch(vector)
1333	{
1334	case X86_XCPT_GP:
1335	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1336	Event.n.u1ErrorCodeValid = 1;
1337	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1338	break;
1339	case X86_XCPT_DE:
1340	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1341	break;
1342	case X86_XCPT_UD:
1343	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1344	break;
1345	case X86_XCPT_SS:
1346	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1347	Event.n.u1ErrorCodeValid = 1;
1348	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1349	break;
1350	case X86_XCPT_NP:
1351	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1352	Event.n.u1ErrorCodeValid = 1;
1353	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1354	break;
1355	}
1356	Log(("Trap %x at %VGv esi=%x\n", vector, pCtx->rip, pCtx->esi));
1357	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1358
1359	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1360	goto ResumeExecution;
1361	}
1362	#endif
1363	default:
1364	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1365	rc = VERR_EM_INTERNAL_ERROR;
1366	break;
1367
1368	} /* switch (vector) */
1369	break;
1370	}
1371
1372	case SVM_EXIT_NPF:
1373	{
1374	/* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1375	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1376	RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1377
1378	Assert(pVM->hwaccm.s.fNestedPaging);
1379	Log(("Nested page fault at %VGv cr2=%VGp error code %x\n", pCtx->rip, uFaultAddress, errCode));
1380	/* Exit qualification contains the linear address of the page fault. */
1381	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1382	TRPMSetErrorCode(pVM, errCode);
1383	TRPMSetFaultAddress(pVM, uFaultAddress);
1384
1385	/* Handle the pagefault trap for the nested shadow table. */
1386	rc = PGMR0Trap0eHandlerNestedPaging(pVM, PGMGetHostMode(pVM), errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1387	Log2(("PGMR0Trap0eHandlerNestedPaging %VGv returned %Vrc\n", pCtx->rip, rc));
1388	if (rc == VINF_SUCCESS)
1389	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1390	Log2(("Shadow page fault at %VGv cr2=%VGp error code %x\n", pCtx->rip, uFaultAddress, errCode));
1391	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1392
1393	TRPMResetTrap(pVM);
1394
1395	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1396	goto ResumeExecution;
1397	}
1398
1399	#ifdef VBOX_STRICT
1400	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1401	LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
1402	#endif
1403	/* Need to go back to the recompiler to emulate the instruction. */
1404	TRPMResetTrap(pVM);
1405	break;
1406	}
1407
1408	case SVM_EXIT_VINTR:
1409	/* A virtual interrupt is about to be delivered, which means IF=1. */
1410	Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1411	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1412	pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 0;
1413	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1414	goto ResumeExecution;
1415
1416	case SVM_EXIT_FERR_FREEZE:
1417	case SVM_EXIT_INTR:
1418	case SVM_EXIT_NMI:
1419	case SVM_EXIT_SMI:
1420	case SVM_EXIT_INIT:
1421	/* External interrupt; leave to allow it to be dispatched again. */
1422	rc = VINF_EM_RAW_INTERRUPT;
1423	break;
1424
1425	case SVM_EXIT_WBINVD:
1426	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1427	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1428	/* Skip instruction and continue directly. */
1429	pCtx->rip += 2; /** @note hardcoded opcode size! */
1430	/* Continue execution.*/
1431	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1432	goto ResumeExecution;
1433
1434	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1435	{
1436	Log2(("SVM: Cpuid %x\n", pCtx->eax));
1437	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1438	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1439	if (rc == VINF_SUCCESS)
1440	{
1441	/* Update EIP and continue execution. */
1442	pCtx->rip += 2; /** @note hardcoded opcode size! */
1443	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1444	goto ResumeExecution;
1445	}
1446	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1447	rc = VINF_EM_RAW_EMULATE_INSTR;
1448	break;
1449	}
1450
1451	case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1452	{
1453	Log2(("SVM: Rdtsc\n"));
1454	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1455	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1456	if (rc == VINF_SUCCESS)
1457	{
1458	/* Update EIP and continue execution. */
1459	pCtx->rip += 2; /** @note hardcoded opcode size! */
1460	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1461	goto ResumeExecution;
1462	}
1463	AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1464	rc = VINF_EM_RAW_EMULATE_INSTR;
1465	break;
1466	}
1467
1468	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1469	{
1470	Log2(("SVM: invlpg\n"));
1471	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1472
1473	Assert(!pVM->hwaccm.s.fNestedPaging);
1474
1475	/* Truly a pita. Why can't SVM give the same information as VT-x? */
1476	rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1477	if (rc == VINF_SUCCESS)
1478	{
1479	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageInvlpg);
1480	goto ResumeExecution; /* eip already updated */
1481	}
1482	break;
1483	}
1484
1485	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1486	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1487	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1488	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1489	{
1490	uint32_t cbSize;
1491
1492	Log2(("SVM: %VGv mov cr%d, \n", pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
1493	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1494	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1495
1496	switch (exitCode - SVM_EXIT_WRITE_CR0)
1497	{
1498	case 0:
1499	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1500	break;
1501	case 2:
1502	break;
1503	case 3:
1504	Assert(!pVM->hwaccm.s.fNestedPaging);
1505	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1506	break;
1507	case 4:
1508	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1509	break;
1510	case 8:
1511	AssertFailed(); /* shouldn't come here anymore */
1512	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR8;
1513	break;
1514	default:
1515	AssertFailed();
1516	}
1517	/* Check if a sync operation is pending. */
1518	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1519	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1520	{
1521	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1522	AssertRC(rc);
1523
1524	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBCRxChange);
1525
1526	/** @note Force a TLB flush. SVM requires us to do it manually. */
1527	pVM->hwaccm.s.svm.fForceTLBFlush = true;
1528	}
1529	if (rc == VINF_SUCCESS)
1530	{
1531	/* EIP has been updated already. */
1532
1533	/* Only resume if successful. */
1534	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1535	goto ResumeExecution;
1536	}
1537	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1538	break;
1539	}
1540
1541	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1542	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1543	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1544	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1545	{
1546	uint32_t cbSize;
1547
1548	Log2(("SVM: %VGv mov x, cr%d\n", pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
1549	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1550	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1551	if (rc == VINF_SUCCESS)
1552	{
1553	/* EIP has been updated already. */
1554
1555	/* Only resume if successful. */
1556	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1557	goto ResumeExecution;
1558	}
1559	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1560	break;
1561	}
1562
1563	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1564	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1565	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1566	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1567	{
1568	uint32_t cbSize;
1569
1570	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
1571	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1572	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1573	if (rc == VINF_SUCCESS)
1574	{
1575	/* EIP has been updated already. */
1576
1577	/* Only resume if successful. */
1578	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1579	goto ResumeExecution;
1580	}
1581	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1582	break;
1583	}
1584
1585	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1586	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1587	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1588	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1589	{
1590	uint32_t cbSize;
1591
1592	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
1593	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1594	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1595	if (rc == VINF_SUCCESS)
1596	{
1597	/* EIP has been updated already. */
1598
1599	/* Only resume if successful. */
1600	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1601	goto ResumeExecution;
1602	}
1603	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1604	break;
1605	}
1606
1607	/* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1608	case SVM_EXIT_IOIO: /* I/O instruction. */
1609	{
1610	SVM_IOIO_EXIT IoExitInfo;
1611	uint32_t uIOSize, uAndVal;
1612
1613	IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1614
1615	/** @todo could use a lookup table here */
1616	if (IoExitInfo.n.u1OP8)
1617	{
1618	uIOSize = 1;
1619	uAndVal = 0xff;
1620	}
1621	else
1622	if (IoExitInfo.n.u1OP16)
1623	{
1624	uIOSize = 2;
1625	uAndVal = 0xffff;
1626	}
1627	else
1628	if (IoExitInfo.n.u1OP32)
1629	{
1630	uIOSize = 4;
1631	uAndVal = 0xffffffff;
1632	}
1633	else
1634	{
1635	AssertFailed(); /* should be fatal. */
1636	rc = VINF_EM_RAW_EMULATE_INSTR;
1637	break;
1638	}
1639
1640	if (IoExitInfo.n.u1STR)
1641	{
1642	/* ins/outs */
1643	uint32_t prefix = 0;
1644	if (IoExitInfo.n.u1REP)
1645	prefix \|= PREFIX_REP;
1646
1647	if (IoExitInfo.n.u1Type == 0)
1648	{
1649	Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1650	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1651	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1652	}
1653	else
1654	{
1655	Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1656	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1657	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1658	}
1659	}
1660	else
1661	{
1662	/* normal in/out */
1663	Assert(!IoExitInfo.n.u1REP);
1664
1665	if (IoExitInfo.n.u1Type == 0)
1666	{
1667	Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1668	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1669	rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1670	}
1671	else
1672	{
1673	uint32_t u32Val = 0;
1674
1675	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1676	rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1677	if (IOM_SUCCESS(rc))
1678	{
1679	/* Write back to the EAX register. */
1680	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1681	Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1682	}
1683	}
1684	}
1685	/*
1686	* Handled the I/O return codes.
1687	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1688	*/
1689	if (IOM_SUCCESS(rc))
1690	{
1691	/* Update EIP and continue execution. */
1692	pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1693	if (RT_LIKELY(rc == VINF_SUCCESS))
1694	{
1695	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1696	goto ResumeExecution;
1697	}
1698	Log2(("EM status from IO at %VGv %x size %d: %Vrc\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
1699	break;
1700	}
1701
1702	#ifdef VBOX_STRICT
1703	if (rc == VINF_IOM_HC_IOPORT_READ)
1704	Assert(IoExitInfo.n.u1Type != 0);
1705	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1706	Assert(IoExitInfo.n.u1Type == 0);
1707	else
1708	AssertMsg(VBOX_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1709	#endif
1710	Log2(("Failed IO at %VGv %x size %d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1711	break;
1712	}
1713
1714	case SVM_EXIT_HLT:
1715	/** Check if external interrupts are pending; if so, don't switch back. */
1716	if ( pCtx->eflags.Bits.u1IF
1717	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1718	{
1719	pCtx->rip++; /* skip hlt */
1720	goto ResumeExecution;
1721	}
1722
1723	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1724	break;
1725
1726	case SVM_EXIT_RSM:
1727	case SVM_EXIT_INVLPGA:
1728	case SVM_EXIT_VMRUN:
1729	case SVM_EXIT_VMMCALL:
1730	case SVM_EXIT_VMLOAD:
1731	case SVM_EXIT_VMSAVE:
1732	case SVM_EXIT_STGI:
1733	case SVM_EXIT_CLGI:
1734	case SVM_EXIT_SKINIT:
1735	case SVM_EXIT_RDTSCP:
1736	{
1737	/* Unsupported instructions. */
1738	SVM_EVENT Event;
1739
1740	Event.au64[0] = 0;
1741	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1742	Event.n.u1Valid = 1;
1743	Event.n.u8Vector = X86_XCPT_UD;
1744
1745	Log(("Forced #UD trap at %VGv\n", pCtx->rip));
1746	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1747
1748	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1749	goto ResumeExecution;
1750	}
1751
1752	/* Emulate in ring 3. */
1753	case SVM_EXIT_MSR:
1754	{
1755	uint32_t cbSize;
1756
1757	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
1758	Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
1759	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1760	if (rc == VINF_SUCCESS)
1761	{
1762	/* EIP has been updated already. */
1763
1764	/* Only resume if successful. */
1765	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1766	goto ResumeExecution;
1767	}
1768	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Vrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
1769	break;
1770	}
1771
1772	case SVM_EXIT_MONITOR:
1773	case SVM_EXIT_RDPMC:
1774	case SVM_EXIT_PAUSE:
1775	case SVM_EXIT_MWAIT_UNCOND:
1776	case SVM_EXIT_MWAIT_ARMED:
1777	case SVM_EXIT_TASK_SWITCH: /* can change CR3; emulate */
1778	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1779	break;
1780
1781	case SVM_EXIT_SHUTDOWN:
1782	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1783	break;
1784
1785	case SVM_EXIT_IDTR_READ:
1786	case SVM_EXIT_GDTR_READ:
1787	case SVM_EXIT_LDTR_READ:
1788	case SVM_EXIT_TR_READ:
1789	case SVM_EXIT_IDTR_WRITE:
1790	case SVM_EXIT_GDTR_WRITE:
1791	case SVM_EXIT_LDTR_WRITE:
1792	case SVM_EXIT_TR_WRITE:
1793	case SVM_EXIT_CR0_SEL_WRITE:
1794	default:
1795	/* Unexpected exit codes. */
1796	rc = VERR_EM_INTERNAL_ERROR;
1797	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
1798	break;
1799	}
1800
1801	end:
1802	if (fGuestStateSynced)
1803	{
1804	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1805	SVM_READ_SELREG(LDTR, ldtr);
1806	SVM_READ_SELREG(TR, tr);
1807
1808	pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1809	pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1810
1811	pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1812	pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1813
1814	/*
1815	* System MSRs
1816	*/
1817	pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1818	pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1819	pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1820	}
1821
1822	/* Signal changes for the recompiler. */
1823	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
1824
1825	/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
1826	if (exitCode == SVM_EXIT_INTR)
1827	{
1828	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1829	/* On the next entry we'll only sync the host context. */
1830	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
1831	}
1832	else
1833	{
1834	/* On the next entry we'll sync everything. */
1835	/** @todo we can do better than this */
1836	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
1837	}
1838
1839	/* translate into a less severe return code */
1840	if (rc == VERR_EM_INTERPRETER)
1841	rc = VINF_EM_RAW_EMULATE_INSTR;
1842
1843	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1844	return rc;
1845	}
1846
1847	/**
1848	* Enters the AMD-V session
1849	*
1850	* @returns VBox status code.
1851	* @param pVM The VM to operate on.
1852	* @param pCpu CPU info struct
1853	*/
1854	HWACCMR0DECL(int) SVMR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
1855	{
1856	Assert(pVM->hwaccm.s.svm.fSupported);
1857
1858	LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVM->hwaccm.s.svm.idLastCpu, pCpu->uCurrentASID));
1859	pVM->hwaccm.s.svm.fResumeVM = false;
1860
1861	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
1862	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_LDTR;
1863
1864	return VINF_SUCCESS;
1865	}
1866
1867
1868	/**
1869	* Leaves the AMD-V session
1870	*
1871	* @returns VBox status code.
1872	* @param pVM The VM to operate on.
1873	*/
1874	HWACCMR0DECL(int) SVMR0Leave(PVM pVM)
1875	{
1876	Assert(pVM->hwaccm.s.svm.fSupported);
1877	return VINF_SUCCESS;
1878	}
1879
1880
1881	static int svmInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1882	{
1883	OP_PARAMVAL param1;
1884	RTGCPTR addr;
1885
1886	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1887	if(VBOX_FAILURE(rc))
1888	return VERR_EM_INTERPRETER;
1889
1890	switch(param1.type)
1891	{
1892	case PARMTYPE_IMMEDIATE:
1893	case PARMTYPE_ADDRESS:
1894	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1895	return VERR_EM_INTERPRETER;
1896	addr = param1.val.val64;
1897	break;
1898
1899	default:
1900	return VERR_EM_INTERPRETER;
1901	}
1902
1903	/** @todo is addr always a flat linear address or ds based
1904	* (in absence of segment override prefixes)????
1905	*/
1906	rc = PGMInvalidatePage(pVM, addr);
1907	if (VBOX_SUCCESS(rc))
1908	{
1909	/* Manually invalidate the page for the VM's TLB. */
1910	Log(("SVMInvlpgA %VGv ASID=%d\n", addr, uASID));
1911	SVMInvlpgA(addr, uASID);
1912	return VINF_SUCCESS;
1913	}
1914	Assert(rc == VERR_REM_FLUSHED_PAGES_OVERFLOW);
1915	return rc;
1916	}
1917
1918	/**
1919	* Interprets INVLPG
1920	*
1921	* @returns VBox status code.
1922	* @retval VINF_* Scheduling instructions.
1923	* @retval VERR_EM_INTERPRETER Something we can't cope with.
1924	* @retval VERR_* Fatal errors.
1925	*
1926	* @param pVM The VM handle.
1927	* @param pRegFrame The register frame.
1928	* @param ASID Tagged TLB id for the guest
1929	*
1930	* Updates the EIP if an instruction was executed successfully.
1931	*/
1932	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1933	{
1934	/*
1935	* Only allow 32 & 64 bits code.
1936	*/
1937	DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
1938	if (enmMode != CPUMODE_16BIT)
1939	{
1940	RTGCPTR pbCode;
1941	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
1942	if (VBOX_SUCCESS(rc))
1943	{
1944	uint32_t cbOp;
1945	DISCPUSTATE Cpu;
1946
1947	Cpu.mode = enmMode;
1948	rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
1949	Assert(VBOX_FAILURE(rc) \|\| Cpu.pCurInstr->opcode == OP_INVLPG);
1950	if (VBOX_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
1951	{
1952	Assert(cbOp == Cpu.opsize);
1953	rc = svmInterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
1954	if (VBOX_SUCCESS(rc))
1955	{
1956	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
1957	}
1958	return rc;
1959	}
1960	}
1961	}
1962	return VERR_EM_INTERPRETER;
1963	}
1964
1965
1966	/**
1967	* Invalidates a guest page
1968	*
1969	* @returns VBox status code.
1970	* @param pVM The VM to operate on.
1971	* @param GCVirt Page to invalidate
1972	*/
1973	HWACCMR0DECL(int) SVMR0InvalidatePage(PVM pVM, RTGCPTR GCVirt)
1974	{
1975	bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB \| pVM->hwaccm.s.svm.fForceTLBFlush;
1976
1977	/* Skip it if a TLB flush is already pending. */
1978	if (!fFlushPending)
1979	{
1980	SVM_VMCB *pVMCB;
1981
1982	Log2(("SVMR0InvalidatePage %VGv\n", GCVirt));
1983	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1984	Assert(pVM->hwaccm.s.svm.fSupported);
1985
1986	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
1987	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
1988
1989	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageManual);
1990	SVMInvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
1991	}
1992	return VINF_SUCCESS;
1993	}
1994
1995
1996	/**
1997	* Invalidates a guest page by physical address
1998	*
1999	* NOTE: Assumes the current instruction references this physical page though a virtual address!!
2000	*
2001	* @returns VBox status code.
2002	* @param pVM The VM to operate on.
2003	* @param GCPhys Page to invalidate
2004	*/
2005	HWACCMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys)
2006	{
2007	bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB \| pVM->hwaccm.s.svm.fForceTLBFlush;
2008
2009	Assert(pVM->hwaccm.s.fNestedPaging);
2010
2011	/* Skip it if a TLB flush is already pending. */
2012	if (!fFlushPending)
2013	{
2014	CPUMCTX *pCtx;
2015	int rc;
2016	SVM_VMCB *pVMCB;
2017
2018	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
2019	AssertRCReturn(rc, rc);
2020
2021	Log2(("SVMR0InvalidatePhysPage %VGp\n", GCPhys));
2022	AssertReturn(pVM, VERR_INVALID_PARAMETER);
2023	Assert(pVM->hwaccm.s.svm.fSupported);
2024
2025	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
2026	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2027
2028	/*
2029	* Only allow 32 & 64 bits code.
2030	*/
2031	DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid);
2032	if (enmMode != CPUMODE_16BIT)
2033	{
2034	RTGCPTR pbCode;
2035	int rc = SELMValidateAndConvertCSAddr(pVM, pCtx->eflags, pCtx->ss, pCtx->cs, &pCtx->csHid, (RTGCPTR)pCtx->rip, &pbCode);
2036	if (VBOX_SUCCESS(rc))
2037	{
2038	uint32_t cbOp;
2039	DISCPUSTATE Cpu;
2040	OP_PARAMVAL param1;
2041	RTGCPTR addr;
2042
2043	Cpu.mode = enmMode;
2044	rc = EMInterpretDisasOneEx(pVM, pbCode, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);
2045	AssertRCReturn(rc, rc);
2046	Assert(cbOp == Cpu.opsize);
2047
2048	int rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param1, &param1, PARAM_SOURCE);
2049	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2050
2051	switch(param1.type)
2052	{
2053	case PARMTYPE_IMMEDIATE:
2054	case PARMTYPE_ADDRESS:
2055	AssertReturn((param1.flags & (PARAM_VAL32\|PARAM_VAL64)), VERR_EM_INTERPRETER);
2056
2057	addr = param1.val.val64;
2058	break;
2059
2060	default:
2061	AssertFailed();
2062	return VERR_EM_INTERPRETER;
2063	}
2064
2065	/* Manually invalidate the page for the VM's TLB. */
2066	Log(("SVMR0InvalidatePhysPage Phys=%VGp Virt=%VGv ASID=%d\n", GCPhys, addr, pVMCB->ctrl.TLBCtrl.n.u32ASID));
2067	SVMInvlpgA(addr, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2068	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPhysPageManual);
2069
2070	return VINF_SUCCESS;
2071	}
2072	}
2073	AssertFailed();
2074	return VERR_EM_INTERPRETER;
2075	}
2076	return VINF_SUCCESS;
2077	}

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 10110

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