HWSVMR0.cpp@ 10331

Last change on this file since 10331 was 10331, checked in by vboxsync, 17 years ago
Removed the assertion completely.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 82.0 KB

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1	/* $Id: HWSVMR0.cpp 10331 2008-07-07 14:22:29Z vboxsync $ */
2	/** @file
3	* HWACCM SVM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_svm.h>
32	#include <VBox/pgm.h>
33	#include <VBox/pdm.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <VBox/selm.h>
37	#include <VBox/iom.h>
38	#include <VBox/dis.h>
39	#include <VBox/dbgf.h>
40	#include <VBox/disopcode.h>
41	#include <iprt/param.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm.h>
44	#include <iprt/cpuset.h>
45	#include <iprt/mp.h>
46	#include "HWSVMR0.h"
47
48	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
49
50	/**
51	* Sets up and activates AMD-V on the current CPU
52	*
53	* @returns VBox status code.
54	* @param pCpu CPU info struct
55	* @param pVM The VM to operate on.
56	* @param pvPageCpu Pointer to the global cpu page
57	* @param pPageCpuPhys Physical address of the global cpu page
58	*/
59	HWACCMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
60	{
61	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
62	AssertReturn(pVM, VERR_INVALID_PARAMETER);
63	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
64
65	/* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
66
67	#ifdef LOG_ENABLED
68	SUPR0Printf("SVMR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
69	#endif
70
71	/* Turn on AMD-V in the EFER MSR. */
72	uint64_t val = ASMRdMsr(MSR_K6_EFER);
73	if (!(val & MSR_K6_EFER_SVME))
74	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
75
76	/* Write the physical page address where the CPU will store the host state while executing the VM. */
77	ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
78
79	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
80	pCpu->cTLBFlushes = 0;
81	return VINF_SUCCESS;
82	}
83
84	/**
85	* Deactivates AMD-V on the current CPU
86	*
87	* @returns VBox status code.
88	* @param pCpu CPU info struct
89	* @param pvPageCpu Pointer to the global cpu page
90	* @param pPageCpuPhys Physical address of the global cpu page
91	*/
92	HWACCMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
93	{
94	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
95	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
96
97	#ifdef LOG_ENABLED
98	SUPR0Printf("SVMR0DisableCpu cpu %d\n", pCpu->idCpu);
99	#endif
100
101	/* Turn off AMD-V in the EFER MSR. */
102	uint64_t val = ASMRdMsr(MSR_K6_EFER);
103	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
104
105	/* Invalidate host state physical address. */
106	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
107	pCpu->uCurrentASID = 0;
108
109	return VINF_SUCCESS;
110	}
111
112	/**
113	* Does Ring-0 per VM AMD-V init.
114	*
115	* @returns VBox status code.
116	* @param pVM The VM to operate on.
117	*/
118	HWACCMR0DECL(int) SVMR0InitVM(PVM pVM)
119	{
120	int rc;
121
122	/* Allocate one page for the VM control block (VMCB). */
123	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
124	if (RT_FAILURE(rc))
125	return rc;
126
127	pVM->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCB);
128	pVM->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCB, 0);
129	ASMMemZero32(pVM->hwaccm.s.svm.pVMCB, PAGE_SIZE);
130
131	/* Allocate one page for the host context */
132	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
133	if (RT_FAILURE(rc))
134	return rc;
135
136	pVM->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCBHost);
137	pVM->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCBHost, 0);
138	ASMMemZero32(pVM->hwaccm.s.svm.pVMCBHost, PAGE_SIZE);
139
140	/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
141	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
142	if (RT_FAILURE(rc))
143	return rc;
144
145	pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
146	pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
147	/* Set all bits to intercept all IO accesses. */
148	ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
149
150	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
151	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
152	if (RT_FAILURE(rc))
153	return rc;
154
155	pVM->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
156	pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
157	/* Set all bits to intercept all MSR accesses. */
158	ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
159
160	/* Erratum 170 which requires a forced TLB flush for each world switch:
161	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
162	*
163	* All BH-G1/2 and DH-G1/2 models include a fix:
164	* Athlon X2: 0x6b 1/2
165	* 0x68 1/2
166	* Athlon 64: 0x7f 1
167	* 0x6f 2
168	* Sempron: 0x7f 1/2
169	* 0x6f 2
170	* 0x6c 2
171	* 0x7c 2
172	* Turion 64: 0x68 2
173	*
174	*/
175	uint32_t u32Dummy;
176	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
177	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
178	u32BaseFamily= (u32Version >> 8) & 0xf;
179	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
180	u32Model = ((u32Version >> 4) & 0xf);
181	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
182	u32Stepping = u32Version & 0xf;
183	if ( u32Family == 0xf
184	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
185	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
186	{
187	Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
188	pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
189	}
190
191	/* Invalidate the last cpu we were running on. */
192	pVM->hwaccm.s.svm.idLastCpu = NIL_RTCPUID;
193	return VINF_SUCCESS;
194	}
195
196	/**
197	* Does Ring-0 per VM AMD-V termination.
198	*
199	* @returns VBox status code.
200	* @param pVM The VM to operate on.
201	*/
202	HWACCMR0DECL(int) SVMR0TermVM(PVM pVM)
203	{
204	if (pVM->hwaccm.s.svm.pMemObjVMCB)
205	{
206	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCB, false);
207	pVM->hwaccm.s.svm.pVMCB = 0;
208	pVM->hwaccm.s.svm.pVMCBPhys = 0;
209	pVM->hwaccm.s.svm.pMemObjVMCB = 0;
210	}
211	if (pVM->hwaccm.s.svm.pMemObjVMCBHost)
212	{
213	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCBHost, false);
214	pVM->hwaccm.s.svm.pVMCBHost = 0;
215	pVM->hwaccm.s.svm.pVMCBHostPhys = 0;
216	pVM->hwaccm.s.svm.pMemObjVMCBHost = 0;
217	}
218	if (pVM->hwaccm.s.svm.pMemObjIOBitmap)
219	{
220	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
221	pVM->hwaccm.s.svm.pIOBitmap = 0;
222	pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
223	pVM->hwaccm.s.svm.pMemObjIOBitmap = 0;
224	}
225	if (pVM->hwaccm.s.svm.pMemObjMSRBitmap)
226	{
227	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
228	pVM->hwaccm.s.svm.pMSRBitmap = 0;
229	pVM->hwaccm.s.svm.pMSRBitmapPhys = 0;
230	pVM->hwaccm.s.svm.pMemObjMSRBitmap = 0;
231	}
232	return VINF_SUCCESS;
233	}
234
235	/**
236	* Sets up AMD-V for the specified VM
237	*
238	* @returns VBox status code.
239	* @param pVM The VM to operate on.
240	*/
241	HWACCMR0DECL(int) SVMR0SetupVM(PVM pVM)
242	{
243	int rc = VINF_SUCCESS;
244	SVM_VMCB *pVMCB;
245
246	AssertReturn(pVM, VERR_INVALID_PARAMETER);
247
248	Assert(pVM->hwaccm.s.svm.fSupported);
249
250	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
251	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
252
253	/* Program the control fields. Most of them never have to be changed again. */
254	/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
255	/** @note CR0 & CR4 can be safely read when guest and shadow copies are identical. */
256	if (!pVM->hwaccm.s.fNestedPaging)
257	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
258	else
259	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
260
261	/*
262	* CR0/3/4 writes must be intercepted for obvious reasons.
263	*/
264	if (!pVM->hwaccm.s.fNestedPaging)
265	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
266	else
267	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
268
269	/* Intercept all DRx reads and writes. */
270	pVMCB->ctrl.u16InterceptRdDRx = RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7);
271	pVMCB->ctrl.u16InterceptWrDRx = RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7);
272
273	/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
274	* All breakpoints are automatically cleared when the VM exits.
275	*/
276
277	pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
278	#ifndef DEBUG
279	if (pVM->hwaccm.s.fNestedPaging)
280	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(14); /* no longer need to intercept #PF. */
281	#endif
282
283	pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
284	\| SVM_CTRL1_INTERCEPT_VINTR
285	\| SVM_CTRL1_INTERCEPT_NMI
286	\| SVM_CTRL1_INTERCEPT_SMI
287	\| SVM_CTRL1_INTERCEPT_INIT
288	\| SVM_CTRL1_INTERCEPT_RDPMC
289	\| SVM_CTRL1_INTERCEPT_CPUID
290	\| SVM_CTRL1_INTERCEPT_RSM
291	\| SVM_CTRL1_INTERCEPT_HLT
292	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
293	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
294	\| SVM_CTRL1_INTERCEPT_INVLPG
295	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
296	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH
297	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
298	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
299	;
300	/* With nested paging we don't care about invlpg anymore. */
301	if (pVM->hwaccm.s.fNestedPaging)
302	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
303
304	pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
305	\| SVM_CTRL2_INTERCEPT_VMMCALL
306	\| SVM_CTRL2_INTERCEPT_VMLOAD
307	\| SVM_CTRL2_INTERCEPT_VMSAVE
308	\| SVM_CTRL2_INTERCEPT_STGI
309	\| SVM_CTRL2_INTERCEPT_CLGI
310	\| SVM_CTRL2_INTERCEPT_SKINIT
311	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
312	\| SVM_CTRL2_INTERCEPT_WBINVD
313	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
314	;
315	Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
316	Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
317	Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
318
319	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
320	pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
321
322	/* Set IO and MSR bitmap addresses. */
323	pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
324	pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
325
326	/* No LBR virtualization. */
327	pVMCB->ctrl.u64LBRVirt = 0;
328
329	/** The ASID must start at 1; the host uses 0. */
330	pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
331
332	/** Setup the PAT msr (nested paging only) */
333	pVMCB->guest.u64GPAT = 0x0007040600070406ULL;
334	return rc;
335	}
336
337
338	/**
339	* Injects an event (trap or external interrupt)
340	*
341	* @param pVM The VM to operate on.
342	* @param pVMCB SVM control block
343	* @param pCtx CPU Context
344	* @param pIntInfo SVM interrupt info
345	*/
346	inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx, SVM_EVENT* pEvent)
347	{
348	#ifdef VBOX_STRICT
349	if (pEvent->n.u8Vector == 0xE)
350	Log(("SVM: Inject int %d at %VGv error code=%02x CR2=%VGv intInfo=%08x\n", pEvent->n.u8Vector, pCtx->rip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
351	else
352	if (pEvent->n.u8Vector < 0x20)
353	Log(("SVM: Inject int %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->rip, pEvent->n.u32ErrorCode));
354	else
355	{
356	Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->rip));
357	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
358	Assert(pCtx->eflags.u32 & X86_EFL_IF);
359	}
360	#endif
361
362	/* Set event injection state. */
363	pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
364	}
365
366
367	/**
368	* Checks for pending guest interrupts and injects them
369	*
370	* @returns VBox status code.
371	* @param pVM The VM to operate on.
372	* @param pVMCB SVM control block
373	* @param pCtx CPU Context
374	*/
375	static int SVMR0CheckPendingInterrupt(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx)
376	{
377	int rc;
378
379	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
380	if (pVM->hwaccm.s.Event.fPending)
381	{
382	SVM_EVENT Event;
383
384	Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip));
385	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
386	Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
387	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
388
389	pVM->hwaccm.s.Event.fPending = false;
390	return VINF_SUCCESS;
391	}
392
393	/* When external interrupts are pending, we should exit the VM when IF is set. */
394	if ( !TRPMHasTrap(pVM)
395	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
396	{
397	if (!(pCtx->eflags.u32 & X86_EFL_IF))
398	{
399	if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
400	{
401	LogFlow(("Enable irq window exit!\n"));
402	/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
403	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
404	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
405	pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1; /* ignore the priority in the TPR; just deliver it */
406	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
407	}
408	}
409	else
410	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
411	{
412	uint8_t u8Interrupt;
413
414	rc = PDMGetInterrupt(pVM, &u8Interrupt);
415	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
416	if (VBOX_SUCCESS(rc))
417	{
418	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
419	AssertRC(rc);
420	}
421	else
422	{
423	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
424	Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)));
425	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
426	/* Just continue */
427	}
428	}
429	else
430	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->rip));
431	}
432
433	#ifdef VBOX_STRICT
434	if (TRPMHasTrap(pVM))
435	{
436	uint8_t u8Vector;
437	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
438	AssertRC(rc);
439	}
440	#endif
441
442	if ( pCtx->eflags.u32 & X86_EFL_IF
443	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
444	&& TRPMHasTrap(pVM)
445	)
446	{
447	uint8_t u8Vector;
448	int rc;
449	TRPMEVENT enmType;
450	SVM_EVENT Event;
451	RTGCUINT u32ErrorCode;
452
453	Event.au64[0] = 0;
454
455	/* If a new event is pending, then dispatch it now. */
456	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &u32ErrorCode, 0);
457	AssertRC(rc);
458	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
459	Assert(enmType != TRPM_SOFTWARE_INT);
460
461	/* Clear the pending trap. */
462	rc = TRPMResetTrap(pVM);
463	AssertRC(rc);
464
465	Event.n.u8Vector = u8Vector;
466	Event.n.u1Valid = 1;
467	Event.n.u32ErrorCode = u32ErrorCode;
468
469	if (enmType == TRPM_TRAP)
470	{
471	switch (u8Vector) {
472	case 8:
473	case 10:
474	case 11:
475	case 12:
476	case 13:
477	case 14:
478	case 17:
479	/* Valid error codes. */
480	Event.n.u1ErrorCodeValid = 1;
481	break;
482	default:
483	break;
484	}
485	if (u8Vector == X86_XCPT_NMI)
486	Event.n.u3Type = SVM_EVENT_NMI;
487	else
488	Event.n.u3Type = SVM_EVENT_EXCEPTION;
489	}
490	else
491	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
492
493	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
494	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
495	} /* if (interrupts can be dispatched) */
496
497	return VINF_SUCCESS;
498	}
499
500	/**
501	* Save the host state
502	*
503	* @returns VBox status code.
504	* @param pVM The VM to operate on.
505	*/
506	HWACCMR0DECL(int) SVMR0SaveHostState(PVM pVM)
507	{
508	/* Nothing to do here. */
509	return VINF_SUCCESS;
510	}
511
512	/**
513	* Loads the guest state
514	*
515	* NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
516	*
517	* @returns VBox status code.
518	* @param pVM The VM to operate on.
519	* @param pCtx Guest context
520	*/
521	HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
522	{
523	RTGCUINTPTR val;
524	SVM_VMCB *pVMCB;
525
526	if (pVM == NULL)
527	return VERR_INVALID_PARAMETER;
528
529	/* Setup AMD SVM. */
530	Assert(pVM->hwaccm.s.svm.fSupported);
531
532	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
533	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
534
535	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
536	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
537	{
538	SVM_WRITE_SELREG(CS, cs);
539	SVM_WRITE_SELREG(SS, ss);
540	SVM_WRITE_SELREG(DS, ds);
541	SVM_WRITE_SELREG(ES, es);
542	SVM_WRITE_SELREG(FS, fs);
543	SVM_WRITE_SELREG(GS, gs);
544	}
545
546	/* Guest CPU context: LDTR. */
547	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
548	{
549	SVM_WRITE_SELREG(LDTR, ldtr);
550	}
551
552	/* Guest CPU context: TR. */
553	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
554	{
555	SVM_WRITE_SELREG(TR, tr);
556	}
557
558	/* Guest CPU context: GDTR. */
559	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
560	{
561	pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
562	pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
563	}
564
565	/* Guest CPU context: IDTR. */
566	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
567	{
568	pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
569	pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
570	}
571
572	/*
573	* Sysenter MSRs (unconditional)
574	*/
575	pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
576	pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
577	pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
578
579	/* Control registers */
580	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
581	{
582	val = pCtx->cr0;
583	if (!CPUMIsGuestFPUStateActive(pVM))
584	{
585	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
586	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
587	}
588	else
589	{
590	/** @todo check if we support the old style mess correctly. */
591	if (!(val & X86_CR0_NE))
592	{
593	Log(("Forcing X86_CR0_NE!!!\n"));
594
595	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
596	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
597	{
598	pVMCB->ctrl.u32InterceptException \|= RT_BIT(16);
599	pVM->hwaccm.s.fFPUOldStyleOverride = true;
600	}
601	}
602	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
603	}
604	/* Always enable caching. */
605	val &= ~(X86_CR0_CD\|X86_CR0_NW);
606
607	/* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
608	/* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
609	if (!pVM->hwaccm.s.fNestedPaging)
610	{
611	val \|= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
612	val \|= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
613	}
614	pVMCB->guest.u64CR0 = val;
615	}
616	/* CR2 as well */
617	pVMCB->guest.u64CR2 = pCtx->cr2;
618
619	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
620	{
621	/* Save our shadow CR3 register. */
622	if (pVM->hwaccm.s.fNestedPaging)
623	{
624	pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVM, PGMGetHostMode(pVM));
625	Assert(pVMCB->ctrl.u64NestedPagingCR3);
626	pVMCB->guest.u64CR3 = pCtx->cr3;
627	}
628	else
629	pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
630	}
631
632	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
633	{
634	val = pCtx->cr4;
635	if (!pVM->hwaccm.s.fNestedPaging)
636	{
637	switch(pVM->hwaccm.s.enmShadowMode)
638	{
639	case PGMMODE_REAL:
640	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
641	AssertFailed();
642	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
643
644	case PGMMODE_32_BIT: /* 32-bit paging. */
645	break;
646
647	case PGMMODE_PAE: /* PAE paging. */
648	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
649	/** @todo use normal 32 bits paging */
650	val \|= X86_CR4_PAE;
651	break;
652
653	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
654	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
655	#ifdef VBOX_ENABLE_64_BITS_GUESTS
656	break;
657	#else
658	AssertFailed();
659	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
660	#endif
661
662	default: /* shut up gcc */
663	AssertFailed();
664	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
665	}
666	}
667	pVMCB->guest.u64CR4 = val;
668	}
669
670	/* Debug registers. */
671	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
672	{
673	/** @todo DR0-6 */
674	val = pCtx->dr7;
675	val &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
676	val \|= 0x400; /* must be one */
677	#ifdef VBOX_STRICT
678	val = 0x400;
679	#endif
680	pVMCB->guest.u64DR7 = val;
681
682	pVMCB->guest.u64DR6 = pCtx->dr6;
683	}
684
685	/* EIP, ESP and EFLAGS */
686	pVMCB->guest.u64RIP = pCtx->rip;
687	pVMCB->guest.u64RSP = pCtx->rsp;
688	pVMCB->guest.u64RFlags = pCtx->eflags.u32;
689
690	/* Set CPL */
691	pVMCB->guest.u8CPL = pCtx->csHid.Attr.n.u2Dpl;
692
693	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
694	pVMCB->guest.u64RAX = pCtx->rax;
695
696	/* vmrun will fail without MSR_K6_EFER_SVME. */
697	pVMCB->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
698
699	/* 64 bits guest mode? */
700	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
701	{
702	#if !defined(VBOX_WITH_64_BITS_GUESTS) \|\| HC_ARCH_BITS != 64
703	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
704	#else
705	pVM->hwaccm.s.svm.pfnVMRun = SVMVMRun64;
706	#endif
707	/* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
708	pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
709	pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
710	}
711	else
712	{
713	/* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
714	pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
715
716	pVM->hwaccm.s.svm.pfnVMRun = SVMVMRun;
717	}
718
719	/** TSC offset. */
720	if (TMCpuTickCanUseRealTSC(pVM, &pVMCB->ctrl.u64TSCOffset))
721	{
722	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
723	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
724	}
725	else
726	{
727	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
728	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
729	}
730
731	/* Sync the various msrs for 64 bits mode. */
732	pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
733	pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
734	pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
735	pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
736	pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
737
738	#ifdef DEBUG
739	/* Intercept X86_XCPT_DB if stepping is enabled */
740	if (DBGFIsStepping(pVM))
741	pVMCB->ctrl.u32InterceptException \|= RT_BIT(1);
742	else
743	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(1);
744	#endif
745
746	/* Done. */
747	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
748
749	return VINF_SUCCESS;
750	}
751
752
753	/**
754	* Runs guest code in an SVM VM.
755	*
756	* @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
757	*
758	* @returns VBox status code.
759	* @param pVM The VM to operate on.
760	* @param pCtx Guest context
761	* @param pCpu CPU info struct
762	*/
763	HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx, PHWACCM_CPUINFO pCpu)
764	{
765	int rc = VINF_SUCCESS;
766	uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
767	SVM_VMCB *pVMCB;
768	bool fGuestStateSynced = false;
769	unsigned cResume = 0;
770
771	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
772
773	AssertReturn(pCpu->fConfigured, VERR_EM_INTERNAL_ERROR);
774
775	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
776	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
777
778	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
779	*/
780	ResumeExecution:
781	/* Safety precaution; looping for too long here can have a very bad effect on the host */
782	if (++cResume > HWACCM_MAX_RESUME_LOOPS)
783	{
784	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
785	rc = VINF_EM_RAW_INTERRUPT;
786	goto end;
787	}
788
789	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
790	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
791	{
792	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
793	if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
794	{
795	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
796	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
797	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
798	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
799	*/
800	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
801	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
802	pVMCB->ctrl.u64IntShadow = 0;
803	}
804	}
805	else
806	{
807	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
808	pVMCB->ctrl.u64IntShadow = 0;
809	}
810
811	/* Check for pending actions that force us to go back to ring 3. */
812	#ifdef DEBUG
813	/* Intercept X86_XCPT_DB if stepping is enabled */
814	if (!DBGFIsStepping(pVM))
815	#endif
816	{
817	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
818	{
819	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
820	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
821	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
822	rc = VINF_EM_RAW_TO_R3;
823	goto end;
824	}
825	}
826
827	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
828	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
829	{
830	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
831	rc = VINF_EM_PENDING_REQUEST;
832	goto end;
833	}
834
835	/* When external interrupts are pending, we should exit the VM when IF is set. */
836	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
837	rc = SVMR0CheckPendingInterrupt(pVM, pVMCB, pCtx);
838	if (VBOX_FAILURE(rc))
839	{
840	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
841	goto end;
842	}
843
844	/* Load the guest state */
845	rc = SVMR0LoadGuestState(pVM, pCtx);
846	if (rc != VINF_SUCCESS)
847	{
848	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
849	goto end;
850	}
851	fGuestStateSynced = true;
852
853	/* TPR caching using CR8 is only available in 64 bits mode */
854	/* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
855	/* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock). */
856	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
857	{
858	/* TPR caching in CR8 */
859	uint8_t u8TPR;
860	int rc = PDMApicGetTPR(pVM, &u8TPR);
861	AssertRC(rc);
862	pCtx->cr8 = u8TPR;
863	pVMCB->ctrl.IntCtrl.n.u8VTPR = u8TPR;
864	}
865
866	/* All done! Let's start VM execution. */
867	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
868
869	/* Enable nested paging if necessary (disabled each time after #VMEXIT). */
870	pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
871
872	/* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
873	if (!pVM->hwaccm.s.svm.fResumeVM)
874	{
875	if ( pVM->hwaccm.s.svm.idLastCpu != pCpu->idCpu
876	/* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
877	\|\| pVM->hwaccm.s.svm.cTLBFlushes != pCpu->cTLBFlushes)
878	{
879	/* Force a TLB flush on VM entry. */
880	pVM->hwaccm.s.svm.fForceTLBFlush = true;
881	}
882	pVM->hwaccm.s.svm.idLastCpu = pCpu->idCpu;
883	}
884	else
885	Assert(pVM->hwaccm.s.svm.idLastCpu == pCpu->idCpu);
886
887	/* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
888	if ( pVM->hwaccm.s.svm.fForceTLBFlush
889	&& !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
890	{
891	if (++pCpu->uCurrentASID >= pVM->hwaccm.s.svm.u32MaxASID)
892	{
893	pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
894	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
895	pCpu->cTLBFlushes++;
896	}
897	else
898	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushASID);
899
900	pVM->hwaccm.s.svm.cTLBFlushes = pCpu->cTLBFlushes;
901	}
902	else
903	{
904	/* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
905	if (!pCpu->uCurrentASID)
906	pCpu->uCurrentASID = 1;
907
908	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVM->hwaccm.s.svm.fForceTLBFlush;
909	}
910
911	AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.svm.u32MaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
912	pVMCB->ctrl.TLBCtrl.n.u32ASID = pCpu->uCurrentASID;
913
914	#ifdef VBOX_WITH_STATISTICS
915	if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
916	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBWorldSwitch);
917	else
918	STAM_COUNTER_INC(&pVM->hwaccm.s.StatNoFlushTLBWorldSwitch);
919	#endif
920
921	/* In case we execute a goto ResumeExecution later on. */
922	pVM->hwaccm.s.svm.fResumeVM = true;
923	pVM->hwaccm.s.svm.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
924
925	Assert(sizeof(pVM->hwaccm.s.svm.pVMCBPhys) == 8);
926	Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
927	\| SVM_CTRL2_INTERCEPT_VMMCALL
928	\| SVM_CTRL2_INTERCEPT_VMLOAD
929	\| SVM_CTRL2_INTERCEPT_VMSAVE
930	\| SVM_CTRL2_INTERCEPT_STGI
931	\| SVM_CTRL2_INTERCEPT_CLGI
932	\| SVM_CTRL2_INTERCEPT_SKINIT
933	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
934	\| SVM_CTRL2_INTERCEPT_WBINVD
935	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
936	));
937	Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
938	Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
939	Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
940	Assert(pVMCB->ctrl.u64LBRVirt == 0);
941
942	pVM->hwaccm.s.svm.pfnVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);
943	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
944
945	/**
946	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
947	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
948	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
949	*/
950
951	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
952
953	/* Reason for the VM exit */
954	exitCode = pVMCB->ctrl.u64ExitCode;
955
956	if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
957	{
958	HWACCMDumpRegs(pCtx);
959	#ifdef DEBUG
960	Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
961	Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
962	Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
963	Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
964	Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
965	Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
966	Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
967	Log(("ctrl.u64IOPMPhysAddr %VX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
968	Log(("ctrl.u64MSRPMPhysAddr %VX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
969	Log(("ctrl.u64TSCOffset %VX64\n", pVMCB->ctrl.u64TSCOffset));
970
971	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
972	Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
973	Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
974	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
975
976	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
977	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
978	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
979	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
980	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
981	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
982	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
983	Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
984	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
985	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
986
987	Log(("ctrl.u64IntShadow %VX64\n", pVMCB->ctrl.u64IntShadow));
988	Log(("ctrl.u64ExitCode %VX64\n", pVMCB->ctrl.u64ExitCode));
989	Log(("ctrl.u64ExitInfo1 %VX64\n", pVMCB->ctrl.u64ExitInfo1));
990	Log(("ctrl.u64ExitInfo2 %VX64\n", pVMCB->ctrl.u64ExitInfo2));
991	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
992	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
993	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
994	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
995	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
996	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
997	Log(("ctrl.NestedPaging %VX64\n", pVMCB->ctrl.NestedPaging.au64));
998	Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
999	Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
1000	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
1001	Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
1002	Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
1003	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
1004
1005	Log(("ctrl.u64NestedPagingCR3 %VX64\n", pVMCB->ctrl.u64NestedPagingCR3));
1006	Log(("ctrl.u64LBRVirt %VX64\n", pVMCB->ctrl.u64LBRVirt));
1007
1008	Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
1009	Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1010	Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1011	Log(("guest.CS.u64Base %VX64\n", pVMCB->guest.CS.u64Base));
1012	Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1013	Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1014	Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1015	Log(("guest.DS.u64Base %VX64\n", pVMCB->guest.DS.u64Base));
1016	Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1017	Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1018	Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1019	Log(("guest.ES.u64Base %VX64\n", pVMCB->guest.ES.u64Base));
1020	Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1021	Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1022	Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1023	Log(("guest.FS.u64Base %VX64\n", pVMCB->guest.FS.u64Base));
1024	Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1025	Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1026	Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1027	Log(("guest.GS.u64Base %VX64\n", pVMCB->guest.GS.u64Base));
1028
1029	Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1030	Log(("guest.GDTR.u64Base %VX64\n", pVMCB->guest.GDTR.u64Base));
1031
1032	Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1033	Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1034	Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1035	Log(("guest.LDTR.u64Base %VX64\n", pVMCB->guest.LDTR.u64Base));
1036
1037	Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1038	Log(("guest.IDTR.u64Base %VX64\n", pVMCB->guest.IDTR.u64Base));
1039
1040	Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1041	Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1042	Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1043	Log(("guest.TR.u64Base %VX64\n", pVMCB->guest.TR.u64Base));
1044
1045	Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1046	Log(("guest.u64CR0 %VX64\n", pVMCB->guest.u64CR0));
1047	Log(("guest.u64CR2 %VX64\n", pVMCB->guest.u64CR2));
1048	Log(("guest.u64CR3 %VX64\n", pVMCB->guest.u64CR3));
1049	Log(("guest.u64CR4 %VX64\n", pVMCB->guest.u64CR4));
1050	Log(("guest.u64DR6 %VX64\n", pVMCB->guest.u64DR6));
1051	Log(("guest.u64DR7 %VX64\n", pVMCB->guest.u64DR7));
1052
1053	Log(("guest.u64RIP %VX64\n", pVMCB->guest.u64RIP));
1054	Log(("guest.u64RSP %VX64\n", pVMCB->guest.u64RSP));
1055	Log(("guest.u64RAX %VX64\n", pVMCB->guest.u64RAX));
1056	Log(("guest.u64RFlags %VX64\n", pVMCB->guest.u64RFlags));
1057
1058	Log(("guest.u64SysEnterCS %VX64\n", pVMCB->guest.u64SysEnterCS));
1059	Log(("guest.u64SysEnterEIP %VX64\n", pVMCB->guest.u64SysEnterEIP));
1060	Log(("guest.u64SysEnterESP %VX64\n", pVMCB->guest.u64SysEnterESP));
1061
1062	Log(("guest.u64EFER %VX64\n", pVMCB->guest.u64EFER));
1063	Log(("guest.u64STAR %VX64\n", pVMCB->guest.u64STAR));
1064	Log(("guest.u64LSTAR %VX64\n", pVMCB->guest.u64LSTAR));
1065	Log(("guest.u64CSTAR %VX64\n", pVMCB->guest.u64CSTAR));
1066	Log(("guest.u64SFMASK %VX64\n", pVMCB->guest.u64SFMASK));
1067	Log(("guest.u64KernelGSBase %VX64\n", pVMCB->guest.u64KernelGSBase));
1068	Log(("guest.u64GPAT %VX64\n", pVMCB->guest.u64GPAT));
1069	Log(("guest.u64DBGCTL %VX64\n", pVMCB->guest.u64DBGCTL));
1070	Log(("guest.u64BR_FROM %VX64\n", pVMCB->guest.u64BR_FROM));
1071	Log(("guest.u64BR_TO %VX64\n", pVMCB->guest.u64BR_TO));
1072	Log(("guest.u64LASTEXCPFROM %VX64\n", pVMCB->guest.u64LASTEXCPFROM));
1073	Log(("guest.u64LASTEXCPTO %VX64\n", pVMCB->guest.u64LASTEXCPTO));
1074
1075	#endif
1076	rc = VERR_SVM_UNABLE_TO_START_VM;
1077	goto end;
1078	}
1079
1080	/* Let's first sync back eip, esp, and eflags. */
1081	pCtx->rip = pVMCB->guest.u64RIP;
1082	pCtx->rsp = pVMCB->guest.u64RSP;
1083	pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1084	/* eax is saved/restore across the vmrun instruction */
1085	pCtx->rax = pVMCB->guest.u64RAX;
1086
1087	pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
1088
1089	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1090	SVM_READ_SELREG(SS, ss);
1091	SVM_READ_SELREG(CS, cs);
1092	SVM_READ_SELREG(DS, ds);
1093	SVM_READ_SELREG(ES, es);
1094	SVM_READ_SELREG(FS, fs);
1095	SVM_READ_SELREG(GS, gs);
1096
1097	/* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1098	/* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1099	if ( pVM->hwaccm.s.fNestedPaging
1100	&& pCtx->cr3 != pVMCB->guest.u64CR3)
1101	{
1102	CPUMSetGuestCR3(pVM, pVMCB->guest.u64CR3);
1103	PGMUpdateCR3(pVM, pVMCB->guest.u64CR3);
1104	}
1105
1106	/** @note NOW IT'S SAFE FOR LOGGING! */
1107
1108	/* Take care of instruction fusing (sti, mov ss) */
1109	if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1110	{
1111	Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->rip));
1112	EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1113	}
1114	else
1115	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1116
1117	Log2(("exitCode = %x\n", exitCode));
1118
1119	/* Sync back the debug registers. */
1120	/** @todo Implement debug registers correctly. */
1121	pCtx->dr6 = pVMCB->guest.u64DR6;
1122	pCtx->dr7 = pVMCB->guest.u64DR7;
1123
1124	/* Update the APIC if the cached TPR value has changed. */
1125	if (pVMCB->ctrl.IntCtrl.n.u8VTPR != pCtx->cr8)
1126	{
1127	rc = PDMApicSetTPR(pVM, pVMCB->ctrl.IntCtrl.n.u8VTPR);
1128	AssertRC(rc);
1129	pCtx->cr8 = pVMCB->ctrl.IntCtrl.n.u8VTPR;
1130	}
1131	pVMCB->ctrl.IntCtrl.n.u8VTPR = pCtx->cr8;
1132
1133	/* Check if an injected event was interrupted prematurely. */
1134	pVM->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1135	if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1136	&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1137	{
1138	Log(("Pending inject %VX64 at %VGv exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitCode));
1139
1140	#ifdef LOG_ENABLED
1141	SVM_EVENT Event;
1142	Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
1143
1144	if ( exitCode == SVM_EXIT_EXCEPTION_E
1145	&& Event.n.u8Vector == 0xE)
1146	{
1147	Log(("Double fault!\n"));
1148	}
1149	#endif
1150
1151	pVM->hwaccm.s.Event.fPending = true;
1152	/* Error code present? (redundant) */
1153	if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1154	{
1155	pVM->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1156	}
1157	else
1158	pVM->hwaccm.s.Event.errCode = 0;
1159	}
1160	#ifdef VBOX_WITH_STATISTICS
1161	if (exitCode == SVM_EXIT_NPF)
1162	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitReasonNPF);
1163	else
1164	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1165	#endif
1166
1167	/* Deal with the reason of the VM-exit. */
1168	switch (exitCode)
1169	{
1170	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1171	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1172	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1173	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1174	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1175	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1176	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1177	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1178	{
1179	/* Pending trap. */
1180	SVM_EVENT Event;
1181	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1182
1183	Log2(("Hardware/software interrupt %d\n", vector));
1184	switch (vector)
1185	{
1186	#ifdef DEBUG
1187	case X86_XCPT_DB:
1188	rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), pVMCB->guest.u64DR6);
1189	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
1190	break;
1191	#endif
1192
1193	case X86_XCPT_NM:
1194	{
1195	uint32_t oldCR0;
1196
1197	Log(("#NM fault at %VGv\n", pCtx->rip));
1198
1199	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1200	oldCR0 = ASMGetCR0();
1201	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1202	rc = CPUMHandleLazyFPU(pVM);
1203	if (rc == VINF_SUCCESS)
1204	{
1205	Assert(CPUMIsGuestFPUStateActive(pVM));
1206
1207	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
1208	ASMSetCR0(oldCR0);
1209
1210	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1211
1212	/* Continue execution. */
1213	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1214	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1215
1216	goto ResumeExecution;
1217	}
1218
1219	Log(("Forward #NM fault to the guest\n"));
1220	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1221
1222	Event.au64[0] = 0;
1223	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1224	Event.n.u1Valid = 1;
1225	Event.n.u8Vector = X86_XCPT_NM;
1226
1227	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1228	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1229	goto ResumeExecution;
1230	}
1231
1232	case X86_XCPT_PF: /* Page fault */
1233	{
1234	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1235	RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1236
1237	#ifdef DEBUG
1238	if (pVM->hwaccm.s.fNestedPaging)
1239	{ /* A genuine pagefault.
1240	* Forward the trap to the guest by injecting the exception and resuming execution.
1241	*/
1242	Log(("Guest page fault at %VGv cr2=%VGv error code %x rsp=%VGv\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
1243	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1244
1245	/* Now we must update CR2. */
1246	pCtx->cr2 = uFaultAddress;
1247
1248	Event.au64[0] = 0;
1249	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1250	Event.n.u1Valid = 1;
1251	Event.n.u8Vector = X86_XCPT_PF;
1252	Event.n.u1ErrorCodeValid = 1;
1253	Event.n.u32ErrorCode = errCode;
1254
1255	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1256
1257	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1258	goto ResumeExecution;
1259	}
1260	#endif
1261	Assert(!pVM->hwaccm.s.fNestedPaging);
1262
1263	Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, uFaultAddress, errCode));
1264	/* Exit qualification contains the linear address of the page fault. */
1265	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1266	TRPMSetErrorCode(pVM, errCode);
1267	TRPMSetFaultAddress(pVM, uFaultAddress);
1268
1269	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1270	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1271	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
1272	if (rc == VINF_SUCCESS)
1273	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1274	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, uFaultAddress, errCode));
1275	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1276
1277	TRPMResetTrap(pVM);
1278
1279	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1280	goto ResumeExecution;
1281	}
1282	else
1283	if (rc == VINF_EM_RAW_GUEST_TRAP)
1284	{ /* A genuine pagefault.
1285	* Forward the trap to the guest by injecting the exception and resuming execution.
1286	*/
1287	Log2(("Forward page fault to the guest\n"));
1288	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1289	/* The error code might have been changed. */
1290	errCode = TRPMGetErrorCode(pVM);
1291
1292	TRPMResetTrap(pVM);
1293
1294	/* Now we must update CR2. */
1295	pCtx->cr2 = uFaultAddress;
1296
1297	Event.au64[0] = 0;
1298	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1299	Event.n.u1Valid = 1;
1300	Event.n.u8Vector = X86_XCPT_PF;
1301	Event.n.u1ErrorCodeValid = 1;
1302	Event.n.u32ErrorCode = errCode;
1303
1304	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1305
1306	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1307	goto ResumeExecution;
1308	}
1309	#ifdef VBOX_STRICT
1310	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1311	LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
1312	#endif
1313	/* Need to go back to the recompiler to emulate the instruction. */
1314	TRPMResetTrap(pVM);
1315	break;
1316	}
1317
1318	case X86_XCPT_MF: /* Floating point exception. */
1319	{
1320	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1321	if (!(pCtx->cr0 & X86_CR0_NE))
1322	{
1323	/* old style FPU error reporting needs some extra work. */
1324	/** @todo don't fall back to the recompiler, but do it manually. */
1325	rc = VINF_EM_RAW_EMULATE_INSTR;
1326	break;
1327	}
1328	Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1329
1330	Event.au64[0] = 0;
1331	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1332	Event.n.u1Valid = 1;
1333	Event.n.u8Vector = X86_XCPT_MF;
1334
1335	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1336
1337	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1338	goto ResumeExecution;
1339	}
1340
1341	#ifdef VBOX_STRICT
1342	case X86_XCPT_GP: /* General protection failure exception.*/
1343	case X86_XCPT_UD: /* Unknown opcode exception. */
1344	case X86_XCPT_DE: /* Debug exception. */
1345	case X86_XCPT_SS: /* Stack segment exception. */
1346	case X86_XCPT_NP: /* Segment not present exception. */
1347	{
1348	Event.au64[0] = 0;
1349	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1350	Event.n.u1Valid = 1;
1351	Event.n.u8Vector = vector;
1352
1353	switch(vector)
1354	{
1355	case X86_XCPT_GP:
1356	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1357	Event.n.u1ErrorCodeValid = 1;
1358	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1359	break;
1360	case X86_XCPT_DE:
1361	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1362	break;
1363	case X86_XCPT_UD:
1364	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1365	break;
1366	case X86_XCPT_SS:
1367	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1368	Event.n.u1ErrorCodeValid = 1;
1369	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1370	break;
1371	case X86_XCPT_NP:
1372	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1373	Event.n.u1ErrorCodeValid = 1;
1374	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1375	break;
1376	}
1377	Log(("Trap %x at %VGv esi=%x\n", vector, pCtx->rip, pCtx->esi));
1378	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1379
1380	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1381	goto ResumeExecution;
1382	}
1383	#endif
1384	default:
1385	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1386	rc = VERR_EM_INTERNAL_ERROR;
1387	break;
1388
1389	} /* switch (vector) */
1390	break;
1391	}
1392
1393	case SVM_EXIT_NPF:
1394	{
1395	/* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1396	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1397	RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1398
1399	Assert(pVM->hwaccm.s.fNestedPaging);
1400	Log(("Nested page fault at %VGv cr2=%VGp error code %x\n", pCtx->rip, uFaultAddress, errCode));
1401	/* Exit qualification contains the linear address of the page fault. */
1402	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1403	TRPMSetErrorCode(pVM, errCode);
1404	TRPMSetFaultAddress(pVM, uFaultAddress);
1405
1406	/* Handle the pagefault trap for the nested shadow table. */
1407	rc = PGMR0Trap0eHandlerNestedPaging(pVM, PGMGetHostMode(pVM), errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1408	Log2(("PGMR0Trap0eHandlerNestedPaging %VGv returned %Vrc\n", pCtx->rip, rc));
1409	if (rc == VINF_SUCCESS)
1410	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1411	Log2(("Shadow page fault at %VGv cr2=%VGp error code %x\n", pCtx->rip, uFaultAddress, errCode));
1412	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1413
1414	TRPMResetTrap(pVM);
1415
1416	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1417	goto ResumeExecution;
1418	}
1419
1420	#ifdef VBOX_STRICT
1421	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1422	LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
1423	#endif
1424	/* Need to go back to the recompiler to emulate the instruction. */
1425	TRPMResetTrap(pVM);
1426	break;
1427	}
1428
1429	case SVM_EXIT_VINTR:
1430	/* A virtual interrupt is about to be delivered, which means IF=1. */
1431	Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1432	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1433	pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 0;
1434	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1435	goto ResumeExecution;
1436
1437	case SVM_EXIT_FERR_FREEZE:
1438	case SVM_EXIT_INTR:
1439	case SVM_EXIT_NMI:
1440	case SVM_EXIT_SMI:
1441	case SVM_EXIT_INIT:
1442	/* External interrupt; leave to allow it to be dispatched again. */
1443	rc = VINF_EM_RAW_INTERRUPT;
1444	break;
1445
1446	case SVM_EXIT_WBINVD:
1447	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1448	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1449	/* Skip instruction and continue directly. */
1450	pCtx->rip += 2; /** @note hardcoded opcode size! */
1451	/* Continue execution.*/
1452	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1453	goto ResumeExecution;
1454
1455	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1456	{
1457	Log2(("SVM: Cpuid at %VGv for %x\n", pCtx->rip, pCtx->eax));
1458	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1459	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1460	if (rc == VINF_SUCCESS)
1461	{
1462	/* Update EIP and continue execution. */
1463	pCtx->rip += 2; /** @note hardcoded opcode size! */
1464	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1465	goto ResumeExecution;
1466	}
1467	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1468	rc = VINF_EM_RAW_EMULATE_INSTR;
1469	break;
1470	}
1471
1472	case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1473	{
1474	Log2(("SVM: Rdtsc\n"));
1475	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1476	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1477	if (rc == VINF_SUCCESS)
1478	{
1479	/* Update EIP and continue execution. */
1480	pCtx->rip += 2; /** @note hardcoded opcode size! */
1481	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1482	goto ResumeExecution;
1483	}
1484	AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1485	rc = VINF_EM_RAW_EMULATE_INSTR;
1486	break;
1487	}
1488
1489	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1490	{
1491	Log2(("SVM: invlpg\n"));
1492	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1493
1494	Assert(!pVM->hwaccm.s.fNestedPaging);
1495
1496	/* Truly a pita. Why can't SVM give the same information as VT-x? */
1497	rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1498	if (rc == VINF_SUCCESS)
1499	{
1500	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageInvlpg);
1501	goto ResumeExecution; /* eip already updated */
1502	}
1503	break;
1504	}
1505
1506	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1507	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1508	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1509	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1510	{
1511	uint32_t cbSize;
1512
1513	Log2(("SVM: %VGv mov cr%d, \n", pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
1514	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1515	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1516
1517	switch (exitCode - SVM_EXIT_WRITE_CR0)
1518	{
1519	case 0:
1520	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1521	break;
1522	case 2:
1523	break;
1524	case 3:
1525	Assert(!pVM->hwaccm.s.fNestedPaging);
1526	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1527	break;
1528	case 4:
1529	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1530	break;
1531	case 8:
1532	AssertFailed(); /* shouldn't come here anymore */
1533	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR8;
1534	break;
1535	default:
1536	AssertFailed();
1537	}
1538	/* Check if a sync operation is pending. */
1539	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1540	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1541	{
1542	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1543	AssertRC(rc);
1544
1545	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBCRxChange);
1546
1547	/* Must be set by PGMSyncCR3 */
1548	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PROTECTED \|\| pVM->hwaccm.s.svm.fForceTLBFlush);
1549	}
1550	if (rc == VINF_SUCCESS)
1551	{
1552	/* EIP has been updated already. */
1553
1554	/* Only resume if successful. */
1555	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1556	goto ResumeExecution;
1557	}
1558	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1559	break;
1560	}
1561
1562	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1563	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1564	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1565	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1566	{
1567	uint32_t cbSize;
1568
1569	Log2(("SVM: %VGv mov x, cr%d\n", pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
1570	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1571	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1572	if (rc == VINF_SUCCESS)
1573	{
1574	/* EIP has been updated already. */
1575
1576	/* Only resume if successful. */
1577	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1578	goto ResumeExecution;
1579	}
1580	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1581	break;
1582	}
1583
1584	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1585	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1586	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1587	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1588	{
1589	uint32_t cbSize;
1590
1591	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
1592	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1593	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1594	if (rc == VINF_SUCCESS)
1595	{
1596	/* EIP has been updated already. */
1597
1598	/* Only resume if successful. */
1599	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1600	goto ResumeExecution;
1601	}
1602	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1603	break;
1604	}
1605
1606	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1607	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1608	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1609	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1610	{
1611	uint32_t cbSize;
1612
1613	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
1614	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1615	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1616	if (rc == VINF_SUCCESS)
1617	{
1618	/* EIP has been updated already. */
1619
1620	/* Only resume if successful. */
1621	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1622	goto ResumeExecution;
1623	}
1624	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1625	break;
1626	}
1627
1628	/* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1629	case SVM_EXIT_IOIO: /* I/O instruction. */
1630	{
1631	SVM_IOIO_EXIT IoExitInfo;
1632	uint32_t uIOSize, uAndVal;
1633
1634	IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1635
1636	/** @todo could use a lookup table here */
1637	if (IoExitInfo.n.u1OP8)
1638	{
1639	uIOSize = 1;
1640	uAndVal = 0xff;
1641	}
1642	else
1643	if (IoExitInfo.n.u1OP16)
1644	{
1645	uIOSize = 2;
1646	uAndVal = 0xffff;
1647	}
1648	else
1649	if (IoExitInfo.n.u1OP32)
1650	{
1651	uIOSize = 4;
1652	uAndVal = 0xffffffff;
1653	}
1654	else
1655	{
1656	AssertFailed(); /* should be fatal. */
1657	rc = VINF_EM_RAW_EMULATE_INSTR;
1658	break;
1659	}
1660
1661	if (IoExitInfo.n.u1STR)
1662	{
1663	/* ins/outs */
1664	uint32_t prefix = 0;
1665	if (IoExitInfo.n.u1REP)
1666	prefix \|= PREFIX_REP;
1667
1668	if (IoExitInfo.n.u1Type == 0)
1669	{
1670	Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1671	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1672	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1673	}
1674	else
1675	{
1676	Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1677	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1678	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1679	}
1680	}
1681	else
1682	{
1683	/* normal in/out */
1684	Assert(!IoExitInfo.n.u1REP);
1685
1686	if (IoExitInfo.n.u1Type == 0)
1687	{
1688	Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1689	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1690	rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1691	}
1692	else
1693	{
1694	uint32_t u32Val = 0;
1695
1696	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1697	rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1698	if (IOM_SUCCESS(rc))
1699	{
1700	/* Write back to the EAX register. */
1701	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1702	Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1703	}
1704	}
1705	}
1706	/*
1707	* Handled the I/O return codes.
1708	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1709	*/
1710	if (IOM_SUCCESS(rc))
1711	{
1712	/* Update EIP and continue execution. */
1713	pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1714	if (RT_LIKELY(rc == VINF_SUCCESS))
1715	{
1716	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1717	goto ResumeExecution;
1718	}
1719	Log2(("EM status from IO at %VGv %x size %d: %Vrc\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
1720	break;
1721	}
1722
1723	#ifdef VBOX_STRICT
1724	if (rc == VINF_IOM_HC_IOPORT_READ)
1725	Assert(IoExitInfo.n.u1Type != 0);
1726	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1727	Assert(IoExitInfo.n.u1Type == 0);
1728	else
1729	AssertMsg(VBOX_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1730	#endif
1731	Log2(("Failed IO at %VGv %x size %d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1732	break;
1733	}
1734
1735	case SVM_EXIT_HLT:
1736	/** Check if external interrupts are pending; if so, don't switch back. */
1737	if ( pCtx->eflags.Bits.u1IF
1738	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1739	{
1740	pCtx->rip++; /* skip hlt */
1741	goto ResumeExecution;
1742	}
1743
1744	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1745	break;
1746
1747	case SVM_EXIT_RSM:
1748	case SVM_EXIT_INVLPGA:
1749	case SVM_EXIT_VMRUN:
1750	case SVM_EXIT_VMMCALL:
1751	case SVM_EXIT_VMLOAD:
1752	case SVM_EXIT_VMSAVE:
1753	case SVM_EXIT_STGI:
1754	case SVM_EXIT_CLGI:
1755	case SVM_EXIT_SKINIT:
1756	case SVM_EXIT_RDTSCP:
1757	{
1758	/* Unsupported instructions. */
1759	SVM_EVENT Event;
1760
1761	Event.au64[0] = 0;
1762	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1763	Event.n.u1Valid = 1;
1764	Event.n.u8Vector = X86_XCPT_UD;
1765
1766	Log(("Forced #UD trap at %VGv\n", pCtx->rip));
1767	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1768
1769	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1770	goto ResumeExecution;
1771	}
1772
1773	/* Emulate in ring 3. */
1774	case SVM_EXIT_MSR:
1775	{
1776	uint32_t cbSize;
1777
1778	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
1779	Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
1780	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1781	if (rc == VINF_SUCCESS)
1782	{
1783	/* EIP has been updated already. */
1784
1785	/* Only resume if successful. */
1786	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1787	goto ResumeExecution;
1788	}
1789	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Vrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
1790	break;
1791	}
1792
1793	case SVM_EXIT_MONITOR:
1794	case SVM_EXIT_RDPMC:
1795	case SVM_EXIT_PAUSE:
1796	case SVM_EXIT_MWAIT_UNCOND:
1797	case SVM_EXIT_MWAIT_ARMED:
1798	case SVM_EXIT_TASK_SWITCH: /* can change CR3; emulate */
1799	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1800	break;
1801
1802	case SVM_EXIT_SHUTDOWN:
1803	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1804	break;
1805
1806	case SVM_EXIT_IDTR_READ:
1807	case SVM_EXIT_GDTR_READ:
1808	case SVM_EXIT_LDTR_READ:
1809	case SVM_EXIT_TR_READ:
1810	case SVM_EXIT_IDTR_WRITE:
1811	case SVM_EXIT_GDTR_WRITE:
1812	case SVM_EXIT_LDTR_WRITE:
1813	case SVM_EXIT_TR_WRITE:
1814	case SVM_EXIT_CR0_SEL_WRITE:
1815	default:
1816	/* Unexpected exit codes. */
1817	rc = VERR_EM_INTERNAL_ERROR;
1818	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
1819	break;
1820	}
1821
1822	end:
1823	if (fGuestStateSynced)
1824	{
1825	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1826	SVM_READ_SELREG(LDTR, ldtr);
1827	SVM_READ_SELREG(TR, tr);
1828
1829	pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1830	pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1831
1832	pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1833	pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1834
1835	/*
1836	* System MSRs
1837	*/
1838	pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1839	pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1840	pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1841	}
1842
1843	/* Signal changes for the recompiler. */
1844	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
1845
1846	/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
1847	if (exitCode == SVM_EXIT_INTR)
1848	{
1849	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1850	/* On the next entry we'll only sync the host context. */
1851	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
1852	}
1853	else
1854	{
1855	/* On the next entry we'll sync everything. */
1856	/** @todo we can do better than this */
1857	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
1858	}
1859
1860	/* translate into a less severe return code */
1861	if (rc == VERR_EM_INTERPRETER)
1862	rc = VINF_EM_RAW_EMULATE_INSTR;
1863
1864	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1865	return rc;
1866	}
1867
1868	/**
1869	* Enters the AMD-V session
1870	*
1871	* @returns VBox status code.
1872	* @param pVM The VM to operate on.
1873	* @param pCpu CPU info struct
1874	*/
1875	HWACCMR0DECL(int) SVMR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
1876	{
1877	Assert(pVM->hwaccm.s.svm.fSupported);
1878
1879	LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVM->hwaccm.s.svm.idLastCpu, pCpu->uCurrentASID));
1880	pVM->hwaccm.s.svm.fResumeVM = false;
1881
1882	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
1883	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_LDTR;
1884
1885	return VINF_SUCCESS;
1886	}
1887
1888
1889	/**
1890	* Leaves the AMD-V session
1891	*
1892	* @returns VBox status code.
1893	* @param pVM The VM to operate on.
1894	*/
1895	HWACCMR0DECL(int) SVMR0Leave(PVM pVM)
1896	{
1897	Assert(pVM->hwaccm.s.svm.fSupported);
1898	return VINF_SUCCESS;
1899	}
1900
1901
1902	static int svmInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1903	{
1904	OP_PARAMVAL param1;
1905	RTGCPTR addr;
1906
1907	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1908	if(VBOX_FAILURE(rc))
1909	return VERR_EM_INTERPRETER;
1910
1911	switch(param1.type)
1912	{
1913	case PARMTYPE_IMMEDIATE:
1914	case PARMTYPE_ADDRESS:
1915	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1916	return VERR_EM_INTERPRETER;
1917	addr = param1.val.val64;
1918	break;
1919
1920	default:
1921	return VERR_EM_INTERPRETER;
1922	}
1923
1924	/** @todo is addr always a flat linear address or ds based
1925	* (in absence of segment override prefixes)????
1926	*/
1927	rc = PGMInvalidatePage(pVM, addr);
1928	if (VBOX_SUCCESS(rc))
1929	{
1930	/* Manually invalidate the page for the VM's TLB. */
1931	Log(("SVMInvlpgA %VGv ASID=%d\n", addr, uASID));
1932	SVMInvlpgA(addr, uASID);
1933	return VINF_SUCCESS;
1934	}
1935	Assert(rc == VERR_REM_FLUSHED_PAGES_OVERFLOW);
1936	return rc;
1937	}
1938
1939	/**
1940	* Interprets INVLPG
1941	*
1942	* @returns VBox status code.
1943	* @retval VINF_* Scheduling instructions.
1944	* @retval VERR_EM_INTERPRETER Something we can't cope with.
1945	* @retval VERR_* Fatal errors.
1946	*
1947	* @param pVM The VM handle.
1948	* @param pRegFrame The register frame.
1949	* @param ASID Tagged TLB id for the guest
1950	*
1951	* Updates the EIP if an instruction was executed successfully.
1952	*/
1953	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1954	{
1955	/*
1956	* Only allow 32 & 64 bits code.
1957	*/
1958	DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
1959	if (enmMode != CPUMODE_16BIT)
1960	{
1961	RTGCPTR pbCode;
1962	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
1963	if (VBOX_SUCCESS(rc))
1964	{
1965	uint32_t cbOp;
1966	DISCPUSTATE Cpu;
1967
1968	Cpu.mode = enmMode;
1969	rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
1970	Assert(VBOX_FAILURE(rc) \|\| Cpu.pCurInstr->opcode == OP_INVLPG);
1971	if (VBOX_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
1972	{
1973	Assert(cbOp == Cpu.opsize);
1974	rc = svmInterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
1975	if (VBOX_SUCCESS(rc))
1976	{
1977	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
1978	}
1979	return rc;
1980	}
1981	}
1982	}
1983	return VERR_EM_INTERPRETER;
1984	}
1985
1986
1987	/**
1988	* Invalidates a guest page
1989	*
1990	* @returns VBox status code.
1991	* @param pVM The VM to operate on.
1992	* @param GCVirt Page to invalidate
1993	*/
1994	HWACCMR0DECL(int) SVMR0InvalidatePage(PVM pVM, RTGCPTR GCVirt)
1995	{
1996	bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB \| pVM->hwaccm.s.svm.fForceTLBFlush;
1997
1998	/* Skip it if a TLB flush is already pending. */
1999	if (!fFlushPending)
2000	{
2001	SVM_VMCB *pVMCB;
2002
2003	Log2(("SVMR0InvalidatePage %VGv\n", GCVirt));
2004	AssertReturn(pVM, VERR_INVALID_PARAMETER);
2005	Assert(pVM->hwaccm.s.svm.fSupported);
2006
2007	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
2008	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2009
2010	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageManual);
2011	SVMInvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2012	}
2013	return VINF_SUCCESS;
2014	}
2015
2016
2017	/**
2018	* Invalidates a guest page by physical address
2019	*
2020	* NOTE: Assumes the current instruction references this physical page though a virtual address!!
2021	*
2022	* @returns VBox status code.
2023	* @param pVM The VM to operate on.
2024	* @param GCPhys Page to invalidate
2025	*/
2026	HWACCMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys)
2027	{
2028	bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB \| pVM->hwaccm.s.svm.fForceTLBFlush;
2029
2030	Assert(pVM->hwaccm.s.fNestedPaging);
2031
2032	/* Skip it if a TLB flush is already pending. */
2033	if (!fFlushPending)
2034	{
2035	CPUMCTX *pCtx;
2036	int rc;
2037	SVM_VMCB *pVMCB;
2038
2039	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
2040	AssertRCReturn(rc, rc);
2041
2042	Log2(("SVMR0InvalidatePhysPage %VGp\n", GCPhys));
2043	AssertReturn(pVM, VERR_INVALID_PARAMETER);
2044	Assert(pVM->hwaccm.s.svm.fSupported);
2045
2046	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
2047	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2048
2049	/*
2050	* Only allow 32 & 64 bits code.
2051	*/
2052	DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid);
2053	if (enmMode != CPUMODE_16BIT)
2054	{
2055	RTGCPTR pbCode;
2056	int rc = SELMValidateAndConvertCSAddr(pVM, pCtx->eflags, pCtx->ss, pCtx->cs, &pCtx->csHid, (RTGCPTR)pCtx->rip, &pbCode);
2057	if (VBOX_SUCCESS(rc))
2058	{
2059	uint32_t cbOp;
2060	DISCPUSTATE Cpu;
2061	OP_PARAMVAL param1;
2062	RTGCPTR addr;
2063
2064	Cpu.mode = enmMode;
2065	rc = EMInterpretDisasOneEx(pVM, pbCode, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);
2066	AssertRCReturn(rc, rc);
2067	Assert(cbOp == Cpu.opsize);
2068
2069	int rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param1, &param1, PARAM_SOURCE);
2070	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2071
2072	switch(param1.type)
2073	{
2074	case PARMTYPE_IMMEDIATE:
2075	case PARMTYPE_ADDRESS:
2076	AssertReturn((param1.flags & (PARAM_VAL32\|PARAM_VAL64)), VERR_EM_INTERPRETER);
2077
2078	addr = param1.val.val64;
2079	break;
2080
2081	default:
2082	AssertFailed();
2083	return VERR_EM_INTERPRETER;
2084	}
2085
2086	/* Manually invalidate the page for the VM's TLB. */
2087	Log(("SVMR0InvalidatePhysPage Phys=%VGp Virt=%VGv ASID=%d\n", GCPhys, addr, pVMCB->ctrl.TLBCtrl.n.u32ASID));
2088	SVMInvlpgA(addr, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2089	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPhysPageManual);
2090
2091	return VINF_SUCCESS;
2092	}
2093	}
2094	AssertFailed();
2095	return VERR_EM_INTERPRETER;
2096	}
2097	return VINF_SUCCESS;
2098	}

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 10331

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