HWSVMR0.cpp@ 10354

Last change on this file since 10354 was 10354, checked in by vboxsync, 16 years ago
Extra assertion
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1	/* $Id: HWSVMR0.cpp 10354 2008-07-08 11:14:24Z vboxsync $ */
2	/** @file
3	* HWACCM SVM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_svm.h>
32	#include <VBox/pgm.h>
33	#include <VBox/pdm.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <VBox/selm.h>
37	#include <VBox/iom.h>
38	#include <VBox/dis.h>
39	#include <VBox/dbgf.h>
40	#include <VBox/disopcode.h>
41	#include <iprt/param.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm.h>
44	#include <iprt/cpuset.h>
45	#include <iprt/mp.h>
46	#include "HWSVMR0.h"
47
48	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
49
50	/**
51	* Sets up and activates AMD-V on the current CPU
52	*
53	* @returns VBox status code.
54	* @param pCpu CPU info struct
55	* @param pVM The VM to operate on.
56	* @param pvPageCpu Pointer to the global cpu page
57	* @param pPageCpuPhys Physical address of the global cpu page
58	*/
59	HWACCMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
60	{
61	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
62	AssertReturn(pVM, VERR_INVALID_PARAMETER);
63	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
64
65	/* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
66
67	#ifdef LOG_ENABLED
68	SUPR0Printf("SVMR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
69	#endif
70
71	/* Turn on AMD-V in the EFER MSR. */
72	uint64_t val = ASMRdMsr(MSR_K6_EFER);
73	if (!(val & MSR_K6_EFER_SVME))
74	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
75
76	/* Write the physical page address where the CPU will store the host state while executing the VM. */
77	ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
78
79	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
80	pCpu->cTLBFlushes = 0;
81	return VINF_SUCCESS;
82	}
83
84	/**
85	* Deactivates AMD-V on the current CPU
86	*
87	* @returns VBox status code.
88	* @param pCpu CPU info struct
89	* @param pvPageCpu Pointer to the global cpu page
90	* @param pPageCpuPhys Physical address of the global cpu page
91	*/
92	HWACCMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
93	{
94	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
95	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
96
97	#ifdef LOG_ENABLED
98	SUPR0Printf("SVMR0DisableCpu cpu %d\n", pCpu->idCpu);
99	#endif
100
101	/* Turn off AMD-V in the EFER MSR. */
102	uint64_t val = ASMRdMsr(MSR_K6_EFER);
103	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
104
105	/* Invalidate host state physical address. */
106	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
107	pCpu->uCurrentASID = 0;
108
109	return VINF_SUCCESS;
110	}
111
112	/**
113	* Does Ring-0 per VM AMD-V init.
114	*
115	* @returns VBox status code.
116	* @param pVM The VM to operate on.
117	*/
118	HWACCMR0DECL(int) SVMR0InitVM(PVM pVM)
119	{
120	int rc;
121
122	/* Allocate one page for the VM control block (VMCB). */
123	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
124	if (RT_FAILURE(rc))
125	return rc;
126
127	pVM->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCB);
128	pVM->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCB, 0);
129	ASMMemZero32(pVM->hwaccm.s.svm.pVMCB, PAGE_SIZE);
130
131	/* Allocate one page for the host context */
132	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
133	if (RT_FAILURE(rc))
134	return rc;
135
136	pVM->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCBHost);
137	pVM->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCBHost, 0);
138	ASMMemZero32(pVM->hwaccm.s.svm.pVMCBHost, PAGE_SIZE);
139
140	/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
141	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
142	if (RT_FAILURE(rc))
143	return rc;
144
145	pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
146	pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
147	/* Set all bits to intercept all IO accesses. */
148	ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
149
150	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
151	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
152	if (RT_FAILURE(rc))
153	return rc;
154
155	pVM->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
156	pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
157	/* Set all bits to intercept all MSR accesses. */
158	ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
159
160	/* Erratum 170 which requires a forced TLB flush for each world switch:
161	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
162	*
163	* All BH-G1/2 and DH-G1/2 models include a fix:
164	* Athlon X2: 0x6b 1/2
165	* 0x68 1/2
166	* Athlon 64: 0x7f 1
167	* 0x6f 2
168	* Sempron: 0x7f 1/2
169	* 0x6f 2
170	* 0x6c 2
171	* 0x7c 2
172	* Turion 64: 0x68 2
173	*
174	*/
175	uint32_t u32Dummy;
176	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
177	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
178	u32BaseFamily= (u32Version >> 8) & 0xf;
179	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
180	u32Model = ((u32Version >> 4) & 0xf);
181	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
182	u32Stepping = u32Version & 0xf;
183	if ( u32Family == 0xf
184	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
185	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
186	{
187	Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
188	pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
189	}
190
191	/* Invalidate the last cpu we were running on. */
192	pVM->hwaccm.s.svm.idLastCpu = NIL_RTCPUID;
193	return VINF_SUCCESS;
194	}
195
196	/**
197	* Does Ring-0 per VM AMD-V termination.
198	*
199	* @returns VBox status code.
200	* @param pVM The VM to operate on.
201	*/
202	HWACCMR0DECL(int) SVMR0TermVM(PVM pVM)
203	{
204	if (pVM->hwaccm.s.svm.pMemObjVMCB)
205	{
206	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCB, false);
207	pVM->hwaccm.s.svm.pVMCB = 0;
208	pVM->hwaccm.s.svm.pVMCBPhys = 0;
209	pVM->hwaccm.s.svm.pMemObjVMCB = 0;
210	}
211	if (pVM->hwaccm.s.svm.pMemObjVMCBHost)
212	{
213	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCBHost, false);
214	pVM->hwaccm.s.svm.pVMCBHost = 0;
215	pVM->hwaccm.s.svm.pVMCBHostPhys = 0;
216	pVM->hwaccm.s.svm.pMemObjVMCBHost = 0;
217	}
218	if (pVM->hwaccm.s.svm.pMemObjIOBitmap)
219	{
220	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
221	pVM->hwaccm.s.svm.pIOBitmap = 0;
222	pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
223	pVM->hwaccm.s.svm.pMemObjIOBitmap = 0;
224	}
225	if (pVM->hwaccm.s.svm.pMemObjMSRBitmap)
226	{
227	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
228	pVM->hwaccm.s.svm.pMSRBitmap = 0;
229	pVM->hwaccm.s.svm.pMSRBitmapPhys = 0;
230	pVM->hwaccm.s.svm.pMemObjMSRBitmap = 0;
231	}
232	return VINF_SUCCESS;
233	}
234
235	/**
236	* Sets up AMD-V for the specified VM
237	*
238	* @returns VBox status code.
239	* @param pVM The VM to operate on.
240	*/
241	HWACCMR0DECL(int) SVMR0SetupVM(PVM pVM)
242	{
243	int rc = VINF_SUCCESS;
244	SVM_VMCB *pVMCB;
245
246	AssertReturn(pVM, VERR_INVALID_PARAMETER);
247
248	Assert(pVM->hwaccm.s.svm.fSupported);
249
250	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
251	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
252
253	/* Program the control fields. Most of them never have to be changed again. */
254	/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
255	/** @note CR0 & CR4 can be safely read when guest and shadow copies are identical. */
256	if (!pVM->hwaccm.s.fNestedPaging)
257	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
258	else
259	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
260
261	/*
262	* CR0/3/4 writes must be intercepted for obvious reasons.
263	*/
264	if (!pVM->hwaccm.s.fNestedPaging)
265	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
266	else
267	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
268
269	/* Intercept all DRx reads and writes. */
270	pVMCB->ctrl.u16InterceptRdDRx = RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7);
271	pVMCB->ctrl.u16InterceptWrDRx = RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7);
272
273	/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
274	* All breakpoints are automatically cleared when the VM exits.
275	*/
276
277	pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
278	#ifndef DEBUG
279	if (pVM->hwaccm.s.fNestedPaging)
280	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(14); /* no longer need to intercept #PF. */
281	#endif
282
283	pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
284	\| SVM_CTRL1_INTERCEPT_VINTR
285	\| SVM_CTRL1_INTERCEPT_NMI
286	\| SVM_CTRL1_INTERCEPT_SMI
287	\| SVM_CTRL1_INTERCEPT_INIT
288	\| SVM_CTRL1_INTERCEPT_RDPMC
289	\| SVM_CTRL1_INTERCEPT_CPUID
290	\| SVM_CTRL1_INTERCEPT_RSM
291	\| SVM_CTRL1_INTERCEPT_HLT
292	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
293	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
294	\| SVM_CTRL1_INTERCEPT_INVLPG
295	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
296	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH
297	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
298	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
299	;
300	/* With nested paging we don't care about invlpg anymore. */
301	if (pVM->hwaccm.s.fNestedPaging)
302	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
303
304	pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
305	\| SVM_CTRL2_INTERCEPT_VMMCALL
306	\| SVM_CTRL2_INTERCEPT_VMLOAD
307	\| SVM_CTRL2_INTERCEPT_VMSAVE
308	\| SVM_CTRL2_INTERCEPT_STGI
309	\| SVM_CTRL2_INTERCEPT_CLGI
310	\| SVM_CTRL2_INTERCEPT_SKINIT
311	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
312	\| SVM_CTRL2_INTERCEPT_WBINVD
313	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
314	;
315	Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
316	Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
317	Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
318
319	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
320	pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
321
322	/* Set IO and MSR bitmap addresses. */
323	pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
324	pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
325
326	/* No LBR virtualization. */
327	pVMCB->ctrl.u64LBRVirt = 0;
328
329	/** The ASID must start at 1; the host uses 0. */
330	pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
331
332	/** Setup the PAT msr (nested paging only) */
333	pVMCB->guest.u64GPAT = 0x0007040600070406ULL;
334	return rc;
335	}
336
337
338	/**
339	* Injects an event (trap or external interrupt)
340	*
341	* @param pVM The VM to operate on.
342	* @param pVMCB SVM control block
343	* @param pCtx CPU Context
344	* @param pIntInfo SVM interrupt info
345	*/
346	inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx, SVM_EVENT* pEvent)
347	{
348	#ifdef VBOX_STRICT
349	if (pEvent->n.u8Vector == 0xE)
350	Log(("SVM: Inject int %d at %VGv error code=%02x CR2=%VGv intInfo=%08x\n", pEvent->n.u8Vector, pCtx->rip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
351	else
352	if (pEvent->n.u8Vector < 0x20)
353	Log(("SVM: Inject int %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->rip, pEvent->n.u32ErrorCode));
354	else
355	{
356	Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->rip));
357	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
358	Assert(pCtx->eflags.u32 & X86_EFL_IF);
359	}
360	#endif
361
362	/* Set event injection state. */
363	pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
364	}
365
366
367	/**
368	* Checks for pending guest interrupts and injects them
369	*
370	* @returns VBox status code.
371	* @param pVM The VM to operate on.
372	* @param pVMCB SVM control block
373	* @param pCtx CPU Context
374	*/
375	static int SVMR0CheckPendingInterrupt(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx)
376	{
377	int rc;
378
379	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
380	if (pVM->hwaccm.s.Event.fPending)
381	{
382	SVM_EVENT Event;
383
384	Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip));
385	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
386	Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
387	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
388
389	pVM->hwaccm.s.Event.fPending = false;
390	return VINF_SUCCESS;
391	}
392
393	/* When external interrupts are pending, we should exit the VM when IF is set. */
394	if ( !TRPMHasTrap(pVM)
395	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
396	{
397	if (!(pCtx->eflags.u32 & X86_EFL_IF))
398	{
399	if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
400	{
401	LogFlow(("Enable irq window exit!\n"));
402	/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
403	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
404	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
405	pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1; /* ignore the priority in the TPR; just deliver it */
406	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
407	}
408	}
409	else
410	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
411	{
412	uint8_t u8Interrupt;
413
414	rc = PDMGetInterrupt(pVM, &u8Interrupt);
415	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
416	if (VBOX_SUCCESS(rc))
417	{
418	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
419	AssertRC(rc);
420	}
421	else
422	{
423	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
424	Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)));
425	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
426	/* Just continue */
427	}
428	}
429	else
430	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->rip));
431	}
432
433	#ifdef VBOX_STRICT
434	if (TRPMHasTrap(pVM))
435	{
436	uint8_t u8Vector;
437	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
438	AssertRC(rc);
439	}
440	#endif
441
442	if ( pCtx->eflags.u32 & X86_EFL_IF
443	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
444	&& TRPMHasTrap(pVM)
445	)
446	{
447	uint8_t u8Vector;
448	int rc;
449	TRPMEVENT enmType;
450	SVM_EVENT Event;
451	RTGCUINT u32ErrorCode;
452
453	Event.au64[0] = 0;
454
455	/* If a new event is pending, then dispatch it now. */
456	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &u32ErrorCode, 0);
457	AssertRC(rc);
458	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
459	Assert(enmType != TRPM_SOFTWARE_INT);
460
461	/* Clear the pending trap. */
462	rc = TRPMResetTrap(pVM);
463	AssertRC(rc);
464
465	Event.n.u8Vector = u8Vector;
466	Event.n.u1Valid = 1;
467	Event.n.u32ErrorCode = u32ErrorCode;
468
469	if (enmType == TRPM_TRAP)
470	{
471	switch (u8Vector) {
472	case 8:
473	case 10:
474	case 11:
475	case 12:
476	case 13:
477	case 14:
478	case 17:
479	/* Valid error codes. */
480	Event.n.u1ErrorCodeValid = 1;
481	break;
482	default:
483	break;
484	}
485	if (u8Vector == X86_XCPT_NMI)
486	Event.n.u3Type = SVM_EVENT_NMI;
487	else
488	Event.n.u3Type = SVM_EVENT_EXCEPTION;
489	}
490	else
491	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
492
493	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
494	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
495	} /* if (interrupts can be dispatched) */
496
497	return VINF_SUCCESS;
498	}
499
500	/**
501	* Save the host state
502	*
503	* @returns VBox status code.
504	* @param pVM The VM to operate on.
505	*/
506	HWACCMR0DECL(int) SVMR0SaveHostState(PVM pVM)
507	{
508	/* Nothing to do here. */
509	return VINF_SUCCESS;
510	}
511
512	/**
513	* Loads the guest state
514	*
515	* NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
516	*
517	* @returns VBox status code.
518	* @param pVM The VM to operate on.
519	* @param pCtx Guest context
520	*/
521	HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
522	{
523	RTGCUINTPTR val;
524	SVM_VMCB *pVMCB;
525
526	if (pVM == NULL)
527	return VERR_INVALID_PARAMETER;
528
529	/* Setup AMD SVM. */
530	Assert(pVM->hwaccm.s.svm.fSupported);
531
532	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
533	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
534
535	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
536	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
537	{
538	SVM_WRITE_SELREG(CS, cs);
539	SVM_WRITE_SELREG(SS, ss);
540	SVM_WRITE_SELREG(DS, ds);
541	SVM_WRITE_SELREG(ES, es);
542	SVM_WRITE_SELREG(FS, fs);
543	SVM_WRITE_SELREG(GS, gs);
544	}
545
546	/* Guest CPU context: LDTR. */
547	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
548	{
549	SVM_WRITE_SELREG(LDTR, ldtr);
550	}
551
552	/* Guest CPU context: TR. */
553	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
554	{
555	SVM_WRITE_SELREG(TR, tr);
556	}
557
558	/* Guest CPU context: GDTR. */
559	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
560	{
561	pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
562	pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
563	}
564
565	/* Guest CPU context: IDTR. */
566	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
567	{
568	pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
569	pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
570	}
571
572	/*
573	* Sysenter MSRs (unconditional)
574	*/
575	pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
576	pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
577	pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
578
579	/* Control registers */
580	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
581	{
582	val = pCtx->cr0;
583	if (!CPUMIsGuestFPUStateActive(pVM))
584	{
585	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
586	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
587	}
588	else
589	{
590	/** @todo check if we support the old style mess correctly. */
591	if (!(val & X86_CR0_NE))
592	{
593	Log(("Forcing X86_CR0_NE!!!\n"));
594
595	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
596	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
597	{
598	pVMCB->ctrl.u32InterceptException \|= RT_BIT(16);
599	pVM->hwaccm.s.fFPUOldStyleOverride = true;
600	}
601	}
602	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
603	}
604	/* Always enable caching. */
605	val &= ~(X86_CR0_CD\|X86_CR0_NW);
606
607	/* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
608	/* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
609	if (!pVM->hwaccm.s.fNestedPaging)
610	{
611	val \|= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
612	val \|= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
613	}
614	pVMCB->guest.u64CR0 = val;
615	}
616	/* CR2 as well */
617	pVMCB->guest.u64CR2 = pCtx->cr2;
618
619	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
620	{
621	/* Save our shadow CR3 register. */
622	if (pVM->hwaccm.s.fNestedPaging)
623	{
624	pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVM, PGMGetHostMode(pVM));
625	Assert(pVMCB->ctrl.u64NestedPagingCR3);
626	pVMCB->guest.u64CR3 = pCtx->cr3;
627	}
628	else
629	{
630	pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
631	Assert(pVMCB->guest.u64CR3);
632	}
633	}
634
635	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
636	{
637	val = pCtx->cr4;
638	if (!pVM->hwaccm.s.fNestedPaging)
639	{
640	switch(pVM->hwaccm.s.enmShadowMode)
641	{
642	case PGMMODE_REAL:
643	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
644	AssertFailed();
645	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
646
647	case PGMMODE_32_BIT: /* 32-bit paging. */
648	break;
649
650	case PGMMODE_PAE: /* PAE paging. */
651	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
652	/** @todo use normal 32 bits paging */
653	val \|= X86_CR4_PAE;
654	break;
655
656	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
657	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
658	#ifdef VBOX_ENABLE_64_BITS_GUESTS
659	break;
660	#else
661	AssertFailed();
662	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
663	#endif
664
665	default: /* shut up gcc */
666	AssertFailed();
667	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
668	}
669	}
670	pVMCB->guest.u64CR4 = val;
671	}
672
673	/* Debug registers. */
674	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
675	{
676	/** @todo DR0-6 */
677	val = pCtx->dr7;
678	val &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
679	val \|= 0x400; /* must be one */
680	#ifdef VBOX_STRICT
681	val = 0x400;
682	#endif
683	pVMCB->guest.u64DR7 = val;
684
685	pVMCB->guest.u64DR6 = pCtx->dr6;
686	}
687
688	/* EIP, ESP and EFLAGS */
689	pVMCB->guest.u64RIP = pCtx->rip;
690	pVMCB->guest.u64RSP = pCtx->rsp;
691	pVMCB->guest.u64RFlags = pCtx->eflags.u32;
692
693	/* Set CPL */
694	pVMCB->guest.u8CPL = pCtx->csHid.Attr.n.u2Dpl;
695
696	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
697	pVMCB->guest.u64RAX = pCtx->rax;
698
699	/* vmrun will fail without MSR_K6_EFER_SVME. */
700	pVMCB->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
701
702	/* 64 bits guest mode? */
703	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
704	{
705	#if !defined(VBOX_WITH_64_BITS_GUESTS) \|\| HC_ARCH_BITS != 64
706	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
707	#else
708	pVM->hwaccm.s.svm.pfnVMRun = SVMVMRun64;
709	#endif
710	/* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
711	pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
712	pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
713	}
714	else
715	{
716	/* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
717	pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
718
719	pVM->hwaccm.s.svm.pfnVMRun = SVMVMRun;
720	}
721
722	/** TSC offset. */
723	if (TMCpuTickCanUseRealTSC(pVM, &pVMCB->ctrl.u64TSCOffset))
724	{
725	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
726	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
727	}
728	else
729	{
730	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
731	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
732	}
733
734	/* Sync the various msrs for 64 bits mode. */
735	pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
736	pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
737	pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
738	pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
739	pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
740
741	#ifdef DEBUG
742	/* Intercept X86_XCPT_DB if stepping is enabled */
743	if (DBGFIsStepping(pVM))
744	pVMCB->ctrl.u32InterceptException \|= RT_BIT(1);
745	else
746	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(1);
747	#endif
748
749	/* Done. */
750	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
751
752	return VINF_SUCCESS;
753	}
754
755
756	/**
757	* Runs guest code in an SVM VM.
758	*
759	* @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
760	*
761	* @returns VBox status code.
762	* @param pVM The VM to operate on.
763	* @param pCtx Guest context
764	* @param pCpu CPU info struct
765	*/
766	HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx, PHWACCM_CPUINFO pCpu)
767	{
768	int rc = VINF_SUCCESS;
769	uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
770	SVM_VMCB *pVMCB;
771	bool fGuestStateSynced = false;
772	unsigned cResume = 0;
773	uint8_t u8LastVTPR;
774
775	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
776
777	AssertReturn(pCpu->fConfigured, VERR_EM_INTERNAL_ERROR);
778
779	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
780	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
781
782	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
783	*/
784	ResumeExecution:
785	/* Safety precaution; looping for too long here can have a very bad effect on the host */
786	if (++cResume > HWACCM_MAX_RESUME_LOOPS)
787	{
788	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
789	rc = VINF_EM_RAW_INTERRUPT;
790	goto end;
791	}
792
793	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
794	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
795	{
796	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
797	if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
798	{
799	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
800	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
801	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
802	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
803	*/
804	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
805	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
806	pVMCB->ctrl.u64IntShadow = 0;
807	}
808	}
809	else
810	{
811	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
812	pVMCB->ctrl.u64IntShadow = 0;
813	}
814
815	/* Check for pending actions that force us to go back to ring 3. */
816	#ifdef DEBUG
817	/* Intercept X86_XCPT_DB if stepping is enabled */
818	if (!DBGFIsStepping(pVM))
819	#endif
820	{
821	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
822	{
823	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
824	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
825	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
826	rc = VINF_EM_RAW_TO_R3;
827	goto end;
828	}
829	}
830
831	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
832	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
833	{
834	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
835	rc = VINF_EM_PENDING_REQUEST;
836	goto end;
837	}
838
839	/* When external interrupts are pending, we should exit the VM when IF is set. */
840	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
841	rc = SVMR0CheckPendingInterrupt(pVM, pVMCB, pCtx);
842	if (VBOX_FAILURE(rc))
843	{
844	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
845	goto end;
846	}
847
848	/* Load the guest state */
849	rc = SVMR0LoadGuestState(pVM, pCtx);
850	if (rc != VINF_SUCCESS)
851	{
852	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
853	goto end;
854	}
855	fGuestStateSynced = true;
856
857	/* TPR caching using CR8 is only available in 64 bits mode */
858	/* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
859	/* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock). */
860	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
861	{
862	/* TPR caching in CR8 */
863	int rc = PDMApicGetTPR(pVM, &u8LastVTPR);
864	AssertRC(rc);
865	pVMCB->ctrl.IntCtrl.n.u8VTPR = u8LastVTPR;
866	}
867
868	/* All done! Let's start VM execution. */
869	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
870
871	/* Enable nested paging if necessary (disabled each time after #VMEXIT). */
872	pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
873
874	/* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
875	if (!pVM->hwaccm.s.svm.fResumeVM)
876	{
877	if ( pVM->hwaccm.s.svm.idLastCpu != pCpu->idCpu
878	/* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
879	\|\| pVM->hwaccm.s.svm.cTLBFlushes != pCpu->cTLBFlushes)
880	{
881	/* Force a TLB flush on VM entry. */
882	pVM->hwaccm.s.svm.fForceTLBFlush = true;
883	}
884	pVM->hwaccm.s.svm.idLastCpu = pCpu->idCpu;
885	}
886	else
887	Assert(pVM->hwaccm.s.svm.idLastCpu == pCpu->idCpu);
888
889	/* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
890	if ( pVM->hwaccm.s.svm.fForceTLBFlush
891	&& !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
892	{
893	if (++pCpu->uCurrentASID >= pVM->hwaccm.s.svm.u32MaxASID)
894	{
895	pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
896	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
897	pCpu->cTLBFlushes++;
898	}
899	else
900	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushASID);
901
902	pVM->hwaccm.s.svm.cTLBFlushes = pCpu->cTLBFlushes;
903	}
904	else
905	{
906	/* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
907	if (!pCpu->uCurrentASID)
908	pCpu->uCurrentASID = 1;
909
910	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVM->hwaccm.s.svm.fForceTLBFlush;
911	}
912
913	AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.svm.u32MaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
914	pVMCB->ctrl.TLBCtrl.n.u32ASID = pCpu->uCurrentASID;
915
916	#ifdef VBOX_WITH_STATISTICS
917	if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
918	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBWorldSwitch);
919	else
920	STAM_COUNTER_INC(&pVM->hwaccm.s.StatNoFlushTLBWorldSwitch);
921	#endif
922
923	/* In case we execute a goto ResumeExecution later on. */
924	pVM->hwaccm.s.svm.fResumeVM = true;
925	pVM->hwaccm.s.svm.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
926
927	Assert(sizeof(pVM->hwaccm.s.svm.pVMCBPhys) == 8);
928	Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
929	\| SVM_CTRL2_INTERCEPT_VMMCALL
930	\| SVM_CTRL2_INTERCEPT_VMLOAD
931	\| SVM_CTRL2_INTERCEPT_VMSAVE
932	\| SVM_CTRL2_INTERCEPT_STGI
933	\| SVM_CTRL2_INTERCEPT_CLGI
934	\| SVM_CTRL2_INTERCEPT_SKINIT
935	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
936	\| SVM_CTRL2_INTERCEPT_WBINVD
937	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
938	));
939	Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
940	Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
941	Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
942	Assert(pVMCB->ctrl.u64LBRVirt == 0);
943
944	pVM->hwaccm.s.svm.pfnVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);
945	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
946
947	/**
948	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
949	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
950	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
951	*/
952
953	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
954
955	/* Reason for the VM exit */
956	exitCode = pVMCB->ctrl.u64ExitCode;
957
958	if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
959	{
960	HWACCMDumpRegs(pCtx);
961	#ifdef DEBUG
962	Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
963	Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
964	Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
965	Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
966	Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
967	Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
968	Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
969	Log(("ctrl.u64IOPMPhysAddr %VX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
970	Log(("ctrl.u64MSRPMPhysAddr %VX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
971	Log(("ctrl.u64TSCOffset %VX64\n", pVMCB->ctrl.u64TSCOffset));
972
973	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
974	Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
975	Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
976	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
977
978	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
979	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
980	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
981	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
982	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
983	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
984	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
985	Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
986	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
987	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
988
989	Log(("ctrl.u64IntShadow %VX64\n", pVMCB->ctrl.u64IntShadow));
990	Log(("ctrl.u64ExitCode %VX64\n", pVMCB->ctrl.u64ExitCode));
991	Log(("ctrl.u64ExitInfo1 %VX64\n", pVMCB->ctrl.u64ExitInfo1));
992	Log(("ctrl.u64ExitInfo2 %VX64\n", pVMCB->ctrl.u64ExitInfo2));
993	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
994	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
995	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
996	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
997	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
998	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
999	Log(("ctrl.NestedPaging %VX64\n", pVMCB->ctrl.NestedPaging.au64));
1000	Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
1001	Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
1002	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
1003	Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
1004	Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
1005	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
1006
1007	Log(("ctrl.u64NestedPagingCR3 %VX64\n", pVMCB->ctrl.u64NestedPagingCR3));
1008	Log(("ctrl.u64LBRVirt %VX64\n", pVMCB->ctrl.u64LBRVirt));
1009
1010	Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
1011	Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1012	Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1013	Log(("guest.CS.u64Base %VX64\n", pVMCB->guest.CS.u64Base));
1014	Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1015	Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1016	Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1017	Log(("guest.DS.u64Base %VX64\n", pVMCB->guest.DS.u64Base));
1018	Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1019	Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1020	Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1021	Log(("guest.ES.u64Base %VX64\n", pVMCB->guest.ES.u64Base));
1022	Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1023	Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1024	Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1025	Log(("guest.FS.u64Base %VX64\n", pVMCB->guest.FS.u64Base));
1026	Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1027	Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1028	Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1029	Log(("guest.GS.u64Base %VX64\n", pVMCB->guest.GS.u64Base));
1030
1031	Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1032	Log(("guest.GDTR.u64Base %VX64\n", pVMCB->guest.GDTR.u64Base));
1033
1034	Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1035	Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1036	Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1037	Log(("guest.LDTR.u64Base %VX64\n", pVMCB->guest.LDTR.u64Base));
1038
1039	Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1040	Log(("guest.IDTR.u64Base %VX64\n", pVMCB->guest.IDTR.u64Base));
1041
1042	Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1043	Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1044	Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1045	Log(("guest.TR.u64Base %VX64\n", pVMCB->guest.TR.u64Base));
1046
1047	Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1048	Log(("guest.u64CR0 %VX64\n", pVMCB->guest.u64CR0));
1049	Log(("guest.u64CR2 %VX64\n", pVMCB->guest.u64CR2));
1050	Log(("guest.u64CR3 %VX64\n", pVMCB->guest.u64CR3));
1051	Log(("guest.u64CR4 %VX64\n", pVMCB->guest.u64CR4));
1052	Log(("guest.u64DR6 %VX64\n", pVMCB->guest.u64DR6));
1053	Log(("guest.u64DR7 %VX64\n", pVMCB->guest.u64DR7));
1054
1055	Log(("guest.u64RIP %VX64\n", pVMCB->guest.u64RIP));
1056	Log(("guest.u64RSP %VX64\n", pVMCB->guest.u64RSP));
1057	Log(("guest.u64RAX %VX64\n", pVMCB->guest.u64RAX));
1058	Log(("guest.u64RFlags %VX64\n", pVMCB->guest.u64RFlags));
1059
1060	Log(("guest.u64SysEnterCS %VX64\n", pVMCB->guest.u64SysEnterCS));
1061	Log(("guest.u64SysEnterEIP %VX64\n", pVMCB->guest.u64SysEnterEIP));
1062	Log(("guest.u64SysEnterESP %VX64\n", pVMCB->guest.u64SysEnterESP));
1063
1064	Log(("guest.u64EFER %VX64\n", pVMCB->guest.u64EFER));
1065	Log(("guest.u64STAR %VX64\n", pVMCB->guest.u64STAR));
1066	Log(("guest.u64LSTAR %VX64\n", pVMCB->guest.u64LSTAR));
1067	Log(("guest.u64CSTAR %VX64\n", pVMCB->guest.u64CSTAR));
1068	Log(("guest.u64SFMASK %VX64\n", pVMCB->guest.u64SFMASK));
1069	Log(("guest.u64KernelGSBase %VX64\n", pVMCB->guest.u64KernelGSBase));
1070	Log(("guest.u64GPAT %VX64\n", pVMCB->guest.u64GPAT));
1071	Log(("guest.u64DBGCTL %VX64\n", pVMCB->guest.u64DBGCTL));
1072	Log(("guest.u64BR_FROM %VX64\n", pVMCB->guest.u64BR_FROM));
1073	Log(("guest.u64BR_TO %VX64\n", pVMCB->guest.u64BR_TO));
1074	Log(("guest.u64LASTEXCPFROM %VX64\n", pVMCB->guest.u64LASTEXCPFROM));
1075	Log(("guest.u64LASTEXCPTO %VX64\n", pVMCB->guest.u64LASTEXCPTO));
1076
1077	#endif
1078	rc = VERR_SVM_UNABLE_TO_START_VM;
1079	goto end;
1080	}
1081
1082	/* Let's first sync back eip, esp, and eflags. */
1083	pCtx->rip = pVMCB->guest.u64RIP;
1084	pCtx->rsp = pVMCB->guest.u64RSP;
1085	pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1086	/* eax is saved/restore across the vmrun instruction */
1087	pCtx->rax = pVMCB->guest.u64RAX;
1088
1089	pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
1090
1091	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1092	SVM_READ_SELREG(SS, ss);
1093	SVM_READ_SELREG(CS, cs);
1094	SVM_READ_SELREG(DS, ds);
1095	SVM_READ_SELREG(ES, es);
1096	SVM_READ_SELREG(FS, fs);
1097	SVM_READ_SELREG(GS, gs);
1098
1099	/* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1100	/* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1101	if ( pVM->hwaccm.s.fNestedPaging
1102	&& pCtx->cr3 != pVMCB->guest.u64CR3)
1103	{
1104	CPUMSetGuestCR3(pVM, pVMCB->guest.u64CR3);
1105	PGMUpdateCR3(pVM, pVMCB->guest.u64CR3);
1106	}
1107
1108	/** @note NOW IT'S SAFE FOR LOGGING! */
1109
1110	/* Take care of instruction fusing (sti, mov ss) */
1111	if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1112	{
1113	Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->rip));
1114	EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1115	}
1116	else
1117	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1118
1119	Log2(("exitCode = %x\n", exitCode));
1120
1121	/* Sync back the debug registers. */
1122	/** @todo Implement debug registers correctly. */
1123	pCtx->dr6 = pVMCB->guest.u64DR6;
1124	pCtx->dr7 = pVMCB->guest.u64DR7;
1125
1126	/* Update the APIC if the cached TPR value has changed. */
1127	if ( (pCtx->msrEFER & MSR_K6_EFER_LMA)
1128	&& pVMCB->ctrl.IntCtrl.n.u8VTPR != u8LastVTPR)
1129	{
1130	rc = PDMApicSetTPR(pVM, pVMCB->ctrl.IntCtrl.n.u8VTPR);
1131	AssertRC(rc);
1132	u8LastVTPR = pVMCB->ctrl.IntCtrl.n.u8VTPR;
1133	}
1134
1135	/* Check if an injected event was interrupted prematurely. */
1136	pVM->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1137	if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1138	&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1139	{
1140	Log(("Pending inject %VX64 at %VGv exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitCode));
1141
1142	#ifdef LOG_ENABLED
1143	SVM_EVENT Event;
1144	Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
1145
1146	if ( exitCode == SVM_EXIT_EXCEPTION_E
1147	&& Event.n.u8Vector == 0xE)
1148	{
1149	Log(("Double fault!\n"));
1150	}
1151	#endif
1152
1153	pVM->hwaccm.s.Event.fPending = true;
1154	/* Error code present? (redundant) */
1155	if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1156	{
1157	pVM->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1158	}
1159	else
1160	pVM->hwaccm.s.Event.errCode = 0;
1161	}
1162	#ifdef VBOX_WITH_STATISTICS
1163	if (exitCode == SVM_EXIT_NPF)
1164	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitReasonNPF);
1165	else
1166	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1167	#endif
1168
1169	/* Deal with the reason of the VM-exit. */
1170	switch (exitCode)
1171	{
1172	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1173	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1174	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1175	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1176	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1177	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1178	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1179	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1180	{
1181	/* Pending trap. */
1182	SVM_EVENT Event;
1183	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1184
1185	Log2(("Hardware/software interrupt %d\n", vector));
1186	switch (vector)
1187	{
1188	#ifdef DEBUG
1189	case X86_XCPT_DB:
1190	rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), pVMCB->guest.u64DR6);
1191	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
1192	break;
1193	#endif
1194
1195	case X86_XCPT_NM:
1196	{
1197	uint32_t oldCR0;
1198
1199	Log(("#NM fault at %VGv\n", pCtx->rip));
1200
1201	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1202	oldCR0 = ASMGetCR0();
1203	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1204	rc = CPUMHandleLazyFPU(pVM);
1205	if (rc == VINF_SUCCESS)
1206	{
1207	Assert(CPUMIsGuestFPUStateActive(pVM));
1208
1209	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
1210	ASMSetCR0(oldCR0);
1211
1212	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1213
1214	/* Continue execution. */
1215	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1216	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1217
1218	goto ResumeExecution;
1219	}
1220
1221	Log(("Forward #NM fault to the guest\n"));
1222	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1223
1224	Event.au64[0] = 0;
1225	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1226	Event.n.u1Valid = 1;
1227	Event.n.u8Vector = X86_XCPT_NM;
1228
1229	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1230	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1231	goto ResumeExecution;
1232	}
1233
1234	case X86_XCPT_PF: /* Page fault */
1235	{
1236	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1237	RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1238
1239	#ifdef DEBUG
1240	if (pVM->hwaccm.s.fNestedPaging)
1241	{ /* A genuine pagefault.
1242	* Forward the trap to the guest by injecting the exception and resuming execution.
1243	*/
1244	Log(("Guest page fault at %VGv cr2=%VGv error code %x rsp=%VGv\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
1245	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1246
1247	/* Now we must update CR2. */
1248	pCtx->cr2 = uFaultAddress;
1249
1250	Event.au64[0] = 0;
1251	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1252	Event.n.u1Valid = 1;
1253	Event.n.u8Vector = X86_XCPT_PF;
1254	Event.n.u1ErrorCodeValid = 1;
1255	Event.n.u32ErrorCode = errCode;
1256
1257	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1258
1259	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1260	goto ResumeExecution;
1261	}
1262	#endif
1263	Assert(!pVM->hwaccm.s.fNestedPaging);
1264
1265	Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, uFaultAddress, errCode));
1266	/* Exit qualification contains the linear address of the page fault. */
1267	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1268	TRPMSetErrorCode(pVM, errCode);
1269	TRPMSetFaultAddress(pVM, uFaultAddress);
1270
1271	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1272	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1273	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
1274	if (rc == VINF_SUCCESS)
1275	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1276	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, uFaultAddress, errCode));
1277	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1278
1279	TRPMResetTrap(pVM);
1280
1281	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1282	goto ResumeExecution;
1283	}
1284	else
1285	if (rc == VINF_EM_RAW_GUEST_TRAP)
1286	{ /* A genuine pagefault.
1287	* Forward the trap to the guest by injecting the exception and resuming execution.
1288	*/
1289	Log2(("Forward page fault to the guest\n"));
1290	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1291	/* The error code might have been changed. */
1292	errCode = TRPMGetErrorCode(pVM);
1293
1294	TRPMResetTrap(pVM);
1295
1296	/* Now we must update CR2. */
1297	pCtx->cr2 = uFaultAddress;
1298
1299	Event.au64[0] = 0;
1300	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1301	Event.n.u1Valid = 1;
1302	Event.n.u8Vector = X86_XCPT_PF;
1303	Event.n.u1ErrorCodeValid = 1;
1304	Event.n.u32ErrorCode = errCode;
1305
1306	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1307
1308	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1309	goto ResumeExecution;
1310	}
1311	#ifdef VBOX_STRICT
1312	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1313	LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
1314	#endif
1315	/* Need to go back to the recompiler to emulate the instruction. */
1316	TRPMResetTrap(pVM);
1317	break;
1318	}
1319
1320	case X86_XCPT_MF: /* Floating point exception. */
1321	{
1322	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1323	if (!(pCtx->cr0 & X86_CR0_NE))
1324	{
1325	/* old style FPU error reporting needs some extra work. */
1326	/** @todo don't fall back to the recompiler, but do it manually. */
1327	rc = VINF_EM_RAW_EMULATE_INSTR;
1328	break;
1329	}
1330	Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1331
1332	Event.au64[0] = 0;
1333	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1334	Event.n.u1Valid = 1;
1335	Event.n.u8Vector = X86_XCPT_MF;
1336
1337	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1338
1339	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1340	goto ResumeExecution;
1341	}
1342
1343	#ifdef VBOX_STRICT
1344	case X86_XCPT_GP: /* General protection failure exception.*/
1345	case X86_XCPT_UD: /* Unknown opcode exception. */
1346	case X86_XCPT_DE: /* Debug exception. */
1347	case X86_XCPT_SS: /* Stack segment exception. */
1348	case X86_XCPT_NP: /* Segment not present exception. */
1349	{
1350	Event.au64[0] = 0;
1351	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1352	Event.n.u1Valid = 1;
1353	Event.n.u8Vector = vector;
1354
1355	switch(vector)
1356	{
1357	case X86_XCPT_GP:
1358	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1359	Event.n.u1ErrorCodeValid = 1;
1360	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1361	break;
1362	case X86_XCPT_DE:
1363	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1364	break;
1365	case X86_XCPT_UD:
1366	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1367	break;
1368	case X86_XCPT_SS:
1369	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1370	Event.n.u1ErrorCodeValid = 1;
1371	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1372	break;
1373	case X86_XCPT_NP:
1374	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1375	Event.n.u1ErrorCodeValid = 1;
1376	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1377	break;
1378	}
1379	Log(("Trap %x at %VGv esi=%x\n", vector, pCtx->rip, pCtx->esi));
1380	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1381
1382	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1383	goto ResumeExecution;
1384	}
1385	#endif
1386	default:
1387	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1388	rc = VERR_EM_INTERNAL_ERROR;
1389	break;
1390
1391	} /* switch (vector) */
1392	break;
1393	}
1394
1395	case SVM_EXIT_NPF:
1396	{
1397	/* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1398	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1399	RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1400
1401	Assert(pVM->hwaccm.s.fNestedPaging);
1402	Log(("Nested page fault at %VGv cr2=%VGp error code %x\n", pCtx->rip, uFaultAddress, errCode));
1403	/* Exit qualification contains the linear address of the page fault. */
1404	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1405	TRPMSetErrorCode(pVM, errCode);
1406	TRPMSetFaultAddress(pVM, uFaultAddress);
1407
1408	/* Handle the pagefault trap for the nested shadow table. */
1409	rc = PGMR0Trap0eHandlerNestedPaging(pVM, PGMGetHostMode(pVM), errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1410	Log2(("PGMR0Trap0eHandlerNestedPaging %VGv returned %Vrc\n", pCtx->rip, rc));
1411	if (rc == VINF_SUCCESS)
1412	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1413	Log2(("Shadow page fault at %VGv cr2=%VGp error code %x\n", pCtx->rip, uFaultAddress, errCode));
1414	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1415
1416	TRPMResetTrap(pVM);
1417
1418	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1419	goto ResumeExecution;
1420	}
1421
1422	#ifdef VBOX_STRICT
1423	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1424	LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
1425	#endif
1426	/* Need to go back to the recompiler to emulate the instruction. */
1427	TRPMResetTrap(pVM);
1428	break;
1429	}
1430
1431	case SVM_EXIT_VINTR:
1432	/* A virtual interrupt is about to be delivered, which means IF=1. */
1433	Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1434	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1435	pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 0;
1436	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1437	goto ResumeExecution;
1438
1439	case SVM_EXIT_FERR_FREEZE:
1440	case SVM_EXIT_INTR:
1441	case SVM_EXIT_NMI:
1442	case SVM_EXIT_SMI:
1443	case SVM_EXIT_INIT:
1444	/* External interrupt; leave to allow it to be dispatched again. */
1445	rc = VINF_EM_RAW_INTERRUPT;
1446	break;
1447
1448	case SVM_EXIT_WBINVD:
1449	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1450	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1451	/* Skip instruction and continue directly. */
1452	pCtx->rip += 2; /** @note hardcoded opcode size! */
1453	/* Continue execution.*/
1454	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1455	goto ResumeExecution;
1456
1457	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1458	{
1459	Log2(("SVM: Cpuid at %VGv for %x\n", pCtx->rip, pCtx->eax));
1460	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1461	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1462	if (rc == VINF_SUCCESS)
1463	{
1464	/* Update EIP and continue execution. */
1465	pCtx->rip += 2; /** @note hardcoded opcode size! */
1466	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1467	goto ResumeExecution;
1468	}
1469	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1470	rc = VINF_EM_RAW_EMULATE_INSTR;
1471	break;
1472	}
1473
1474	case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1475	{
1476	Log2(("SVM: Rdtsc\n"));
1477	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1478	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1479	if (rc == VINF_SUCCESS)
1480	{
1481	/* Update EIP and continue execution. */
1482	pCtx->rip += 2; /** @note hardcoded opcode size! */
1483	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1484	goto ResumeExecution;
1485	}
1486	AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1487	rc = VINF_EM_RAW_EMULATE_INSTR;
1488	break;
1489	}
1490
1491	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1492	{
1493	Log2(("SVM: invlpg\n"));
1494	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1495
1496	Assert(!pVM->hwaccm.s.fNestedPaging);
1497
1498	/* Truly a pita. Why can't SVM give the same information as VT-x? */
1499	rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1500	if (rc == VINF_SUCCESS)
1501	{
1502	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageInvlpg);
1503	goto ResumeExecution; /* eip already updated */
1504	}
1505	break;
1506	}
1507
1508	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1509	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1510	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1511	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1512	{
1513	uint32_t cbSize;
1514
1515	Log2(("SVM: %VGv mov cr%d, \n", pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
1516	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1517	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1518
1519	switch (exitCode - SVM_EXIT_WRITE_CR0)
1520	{
1521	case 0:
1522	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1523	break;
1524	case 2:
1525	break;
1526	case 3:
1527	Assert(!pVM->hwaccm.s.fNestedPaging);
1528	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1529	break;
1530	case 4:
1531	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1532	break;
1533	default:
1534	AssertFailed();
1535	}
1536	/* Check if a sync operation is pending. */
1537	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1538	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1539	{
1540	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1541	AssertRC(rc);
1542
1543	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBCRxChange);
1544
1545	/* Must be set by PGMSyncCR3 */
1546	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PROTECTED \|\| pVM->hwaccm.s.svm.fForceTLBFlush);
1547	}
1548	if (rc == VINF_SUCCESS)
1549	{
1550	/* EIP has been updated already. */
1551
1552	/* Only resume if successful. */
1553	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1554	goto ResumeExecution;
1555	}
1556	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1557	break;
1558	}
1559
1560	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1561	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1562	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1563	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1564	{
1565	uint32_t cbSize;
1566
1567	Log2(("SVM: %VGv mov x, cr%d\n", pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
1568	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1569	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1570	if (rc == VINF_SUCCESS)
1571	{
1572	/* EIP has been updated already. */
1573
1574	/* Only resume if successful. */
1575	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1576	goto ResumeExecution;
1577	}
1578	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1579	break;
1580	}
1581
1582	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1583	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1584	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1585	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1586	{
1587	uint32_t cbSize;
1588
1589	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
1590	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1591	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1592	if (rc == VINF_SUCCESS)
1593	{
1594	/* EIP has been updated already. */
1595
1596	/* Only resume if successful. */
1597	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1598	goto ResumeExecution;
1599	}
1600	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1601	break;
1602	}
1603
1604	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1605	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1606	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1607	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1608	{
1609	uint32_t cbSize;
1610
1611	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
1612	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1613	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1614	if (rc == VINF_SUCCESS)
1615	{
1616	/* EIP has been updated already. */
1617
1618	/* Only resume if successful. */
1619	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1620	goto ResumeExecution;
1621	}
1622	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1623	break;
1624	}
1625
1626	/* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1627	case SVM_EXIT_IOIO: /* I/O instruction. */
1628	{
1629	SVM_IOIO_EXIT IoExitInfo;
1630	uint32_t uIOSize, uAndVal;
1631
1632	IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1633
1634	/** @todo could use a lookup table here */
1635	if (IoExitInfo.n.u1OP8)
1636	{
1637	uIOSize = 1;
1638	uAndVal = 0xff;
1639	}
1640	else
1641	if (IoExitInfo.n.u1OP16)
1642	{
1643	uIOSize = 2;
1644	uAndVal = 0xffff;
1645	}
1646	else
1647	if (IoExitInfo.n.u1OP32)
1648	{
1649	uIOSize = 4;
1650	uAndVal = 0xffffffff;
1651	}
1652	else
1653	{
1654	AssertFailed(); /* should be fatal. */
1655	rc = VINF_EM_RAW_EMULATE_INSTR;
1656	break;
1657	}
1658
1659	if (IoExitInfo.n.u1STR)
1660	{
1661	/* ins/outs */
1662	uint32_t prefix = 0;
1663	if (IoExitInfo.n.u1REP)
1664	prefix \|= PREFIX_REP;
1665
1666	if (IoExitInfo.n.u1Type == 0)
1667	{
1668	Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1669	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1670	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1671	}
1672	else
1673	{
1674	Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1675	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1676	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1677	}
1678	}
1679	else
1680	{
1681	/* normal in/out */
1682	Assert(!IoExitInfo.n.u1REP);
1683
1684	if (IoExitInfo.n.u1Type == 0)
1685	{
1686	Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1687	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1688	rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1689	}
1690	else
1691	{
1692	uint32_t u32Val = 0;
1693
1694	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1695	rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1696	if (IOM_SUCCESS(rc))
1697	{
1698	/* Write back to the EAX register. */
1699	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1700	Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1701	}
1702	}
1703	}
1704	/*
1705	* Handled the I/O return codes.
1706	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1707	*/
1708	if (IOM_SUCCESS(rc))
1709	{
1710	/* Update EIP and continue execution. */
1711	pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1712	if (RT_LIKELY(rc == VINF_SUCCESS))
1713	{
1714	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1715	goto ResumeExecution;
1716	}
1717	Log2(("EM status from IO at %VGv %x size %d: %Vrc\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
1718	break;
1719	}
1720
1721	#ifdef VBOX_STRICT
1722	if (rc == VINF_IOM_HC_IOPORT_READ)
1723	Assert(IoExitInfo.n.u1Type != 0);
1724	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1725	Assert(IoExitInfo.n.u1Type == 0);
1726	else
1727	AssertMsg(VBOX_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1728	#endif
1729	Log2(("Failed IO at %VGv %x size %d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1730	break;
1731	}
1732
1733	case SVM_EXIT_HLT:
1734	/** Check if external interrupts are pending; if so, don't switch back. */
1735	if ( pCtx->eflags.Bits.u1IF
1736	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1737	{
1738	pCtx->rip++; /* skip hlt */
1739	goto ResumeExecution;
1740	}
1741
1742	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1743	break;
1744
1745	case SVM_EXIT_RSM:
1746	case SVM_EXIT_INVLPGA:
1747	case SVM_EXIT_VMRUN:
1748	case SVM_EXIT_VMMCALL:
1749	case SVM_EXIT_VMLOAD:
1750	case SVM_EXIT_VMSAVE:
1751	case SVM_EXIT_STGI:
1752	case SVM_EXIT_CLGI:
1753	case SVM_EXIT_SKINIT:
1754	case SVM_EXIT_RDTSCP:
1755	{
1756	/* Unsupported instructions. */
1757	SVM_EVENT Event;
1758
1759	Event.au64[0] = 0;
1760	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1761	Event.n.u1Valid = 1;
1762	Event.n.u8Vector = X86_XCPT_UD;
1763
1764	Log(("Forced #UD trap at %VGv\n", pCtx->rip));
1765	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1766
1767	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1768	goto ResumeExecution;
1769	}
1770
1771	/* Emulate in ring 3. */
1772	case SVM_EXIT_MSR:
1773	{
1774	uint32_t cbSize;
1775
1776	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
1777	Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
1778	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1779	if (rc == VINF_SUCCESS)
1780	{
1781	/* EIP has been updated already. */
1782
1783	/* Only resume if successful. */
1784	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1785	goto ResumeExecution;
1786	}
1787	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Vrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
1788	break;
1789	}
1790
1791	case SVM_EXIT_MONITOR:
1792	case SVM_EXIT_RDPMC:
1793	case SVM_EXIT_PAUSE:
1794	case SVM_EXIT_MWAIT_UNCOND:
1795	case SVM_EXIT_MWAIT_ARMED:
1796	case SVM_EXIT_TASK_SWITCH: /* can change CR3; emulate */
1797	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1798	break;
1799
1800	case SVM_EXIT_SHUTDOWN:
1801	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1802	break;
1803
1804	case SVM_EXIT_IDTR_READ:
1805	case SVM_EXIT_GDTR_READ:
1806	case SVM_EXIT_LDTR_READ:
1807	case SVM_EXIT_TR_READ:
1808	case SVM_EXIT_IDTR_WRITE:
1809	case SVM_EXIT_GDTR_WRITE:
1810	case SVM_EXIT_LDTR_WRITE:
1811	case SVM_EXIT_TR_WRITE:
1812	case SVM_EXIT_CR0_SEL_WRITE:
1813	default:
1814	/* Unexpected exit codes. */
1815	rc = VERR_EM_INTERNAL_ERROR;
1816	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
1817	break;
1818	}
1819
1820	end:
1821	if (fGuestStateSynced)
1822	{
1823	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1824	SVM_READ_SELREG(LDTR, ldtr);
1825	SVM_READ_SELREG(TR, tr);
1826
1827	pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1828	pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1829
1830	pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1831	pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1832
1833	/*
1834	* System MSRs
1835	*/
1836	pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1837	pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1838	pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1839	}
1840
1841	/* Signal changes for the recompiler. */
1842	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
1843
1844	/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
1845	if (exitCode == SVM_EXIT_INTR)
1846	{
1847	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1848	/* On the next entry we'll only sync the host context. */
1849	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
1850	}
1851	else
1852	{
1853	/* On the next entry we'll sync everything. */
1854	/** @todo we can do better than this */
1855	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
1856	}
1857
1858	/* translate into a less severe return code */
1859	if (rc == VERR_EM_INTERPRETER)
1860	rc = VINF_EM_RAW_EMULATE_INSTR;
1861
1862	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1863	return rc;
1864	}
1865
1866	/**
1867	* Enters the AMD-V session
1868	*
1869	* @returns VBox status code.
1870	* @param pVM The VM to operate on.
1871	* @param pCpu CPU info struct
1872	*/
1873	HWACCMR0DECL(int) SVMR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
1874	{
1875	Assert(pVM->hwaccm.s.svm.fSupported);
1876
1877	LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVM->hwaccm.s.svm.idLastCpu, pCpu->uCurrentASID));
1878	pVM->hwaccm.s.svm.fResumeVM = false;
1879
1880	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
1881	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_LDTR;
1882
1883	return VINF_SUCCESS;
1884	}
1885
1886
1887	/**
1888	* Leaves the AMD-V session
1889	*
1890	* @returns VBox status code.
1891	* @param pVM The VM to operate on.
1892	*/
1893	HWACCMR0DECL(int) SVMR0Leave(PVM pVM)
1894	{
1895	Assert(pVM->hwaccm.s.svm.fSupported);
1896	return VINF_SUCCESS;
1897	}
1898
1899
1900	static int svmInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1901	{
1902	OP_PARAMVAL param1;
1903	RTGCPTR addr;
1904
1905	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1906	if(VBOX_FAILURE(rc))
1907	return VERR_EM_INTERPRETER;
1908
1909	switch(param1.type)
1910	{
1911	case PARMTYPE_IMMEDIATE:
1912	case PARMTYPE_ADDRESS:
1913	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1914	return VERR_EM_INTERPRETER;
1915	addr = param1.val.val64;
1916	break;
1917
1918	default:
1919	return VERR_EM_INTERPRETER;
1920	}
1921
1922	/** @todo is addr always a flat linear address or ds based
1923	* (in absence of segment override prefixes)????
1924	*/
1925	rc = PGMInvalidatePage(pVM, addr);
1926	if (VBOX_SUCCESS(rc))
1927	{
1928	/* Manually invalidate the page for the VM's TLB. */
1929	Log(("SVMInvlpgA %VGv ASID=%d\n", addr, uASID));
1930	SVMInvlpgA(addr, uASID);
1931	return VINF_SUCCESS;
1932	}
1933	Assert(rc == VERR_REM_FLUSHED_PAGES_OVERFLOW);
1934	return rc;
1935	}
1936
1937	/**
1938	* Interprets INVLPG
1939	*
1940	* @returns VBox status code.
1941	* @retval VINF_* Scheduling instructions.
1942	* @retval VERR_EM_INTERPRETER Something we can't cope with.
1943	* @retval VERR_* Fatal errors.
1944	*
1945	* @param pVM The VM handle.
1946	* @param pRegFrame The register frame.
1947	* @param ASID Tagged TLB id for the guest
1948	*
1949	* Updates the EIP if an instruction was executed successfully.
1950	*/
1951	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1952	{
1953	/*
1954	* Only allow 32 & 64 bits code.
1955	*/
1956	DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
1957	if (enmMode != CPUMODE_16BIT)
1958	{
1959	RTGCPTR pbCode;
1960	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
1961	if (VBOX_SUCCESS(rc))
1962	{
1963	uint32_t cbOp;
1964	DISCPUSTATE Cpu;
1965
1966	Cpu.mode = enmMode;
1967	rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
1968	Assert(VBOX_FAILURE(rc) \|\| Cpu.pCurInstr->opcode == OP_INVLPG);
1969	if (VBOX_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
1970	{
1971	Assert(cbOp == Cpu.opsize);
1972	rc = svmInterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
1973	if (VBOX_SUCCESS(rc))
1974	{
1975	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
1976	}
1977	return rc;
1978	}
1979	}
1980	}
1981	return VERR_EM_INTERPRETER;
1982	}
1983
1984
1985	/**
1986	* Invalidates a guest page
1987	*
1988	* @returns VBox status code.
1989	* @param pVM The VM to operate on.
1990	* @param GCVirt Page to invalidate
1991	*/
1992	HWACCMR0DECL(int) SVMR0InvalidatePage(PVM pVM, RTGCPTR GCVirt)
1993	{
1994	bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB \| pVM->hwaccm.s.svm.fForceTLBFlush;
1995
1996	/* Skip it if a TLB flush is already pending. */
1997	if (!fFlushPending)
1998	{
1999	SVM_VMCB *pVMCB;
2000
2001	Log2(("SVMR0InvalidatePage %VGv\n", GCVirt));
2002	AssertReturn(pVM, VERR_INVALID_PARAMETER);
2003	Assert(pVM->hwaccm.s.svm.fSupported);
2004
2005	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
2006	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2007
2008	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageManual);
2009	SVMInvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2010	}
2011	return VINF_SUCCESS;
2012	}
2013
2014
2015	/**
2016	* Invalidates a guest page by physical address
2017	*
2018	* NOTE: Assumes the current instruction references this physical page though a virtual address!!
2019	*
2020	* @returns VBox status code.
2021	* @param pVM The VM to operate on.
2022	* @param GCPhys Page to invalidate
2023	*/
2024	HWACCMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys)
2025	{
2026	bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB \| pVM->hwaccm.s.svm.fForceTLBFlush;
2027
2028	Assert(pVM->hwaccm.s.fNestedPaging);
2029
2030	/* Skip it if a TLB flush is already pending. */
2031	if (!fFlushPending)
2032	{
2033	CPUMCTX *pCtx;
2034	int rc;
2035	SVM_VMCB *pVMCB;
2036
2037	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
2038	AssertRCReturn(rc, rc);
2039
2040	Log2(("SVMR0InvalidatePhysPage %VGp\n", GCPhys));
2041	AssertReturn(pVM, VERR_INVALID_PARAMETER);
2042	Assert(pVM->hwaccm.s.svm.fSupported);
2043
2044	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
2045	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2046
2047	/*
2048	* Only allow 32 & 64 bits code.
2049	*/
2050	DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid);
2051	if (enmMode != CPUMODE_16BIT)
2052	{
2053	RTGCPTR pbCode;
2054	int rc = SELMValidateAndConvertCSAddr(pVM, pCtx->eflags, pCtx->ss, pCtx->cs, &pCtx->csHid, (RTGCPTR)pCtx->rip, &pbCode);
2055	if (VBOX_SUCCESS(rc))
2056	{
2057	uint32_t cbOp;
2058	DISCPUSTATE Cpu;
2059	OP_PARAMVAL param1;
2060	RTGCPTR addr;
2061
2062	Cpu.mode = enmMode;
2063	rc = EMInterpretDisasOneEx(pVM, pbCode, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);
2064	AssertRCReturn(rc, rc);
2065	Assert(cbOp == Cpu.opsize);
2066
2067	int rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param1, &param1, PARAM_SOURCE);
2068	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2069
2070	switch(param1.type)
2071	{
2072	case PARMTYPE_IMMEDIATE:
2073	case PARMTYPE_ADDRESS:
2074	AssertReturn((param1.flags & (PARAM_VAL32\|PARAM_VAL64)), VERR_EM_INTERPRETER);
2075
2076	addr = param1.val.val64;
2077	break;
2078
2079	default:
2080	AssertFailed();
2081	return VERR_EM_INTERPRETER;
2082	}
2083
2084	/* Manually invalidate the page for the VM's TLB. */
2085	Log(("SVMR0InvalidatePhysPage Phys=%VGp Virt=%VGv ASID=%d\n", GCPhys, addr, pVMCB->ctrl.TLBCtrl.n.u32ASID));
2086	SVMInvlpgA(addr, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2087	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPhysPageManual);
2088
2089	return VINF_SUCCESS;
2090	}
2091	}
2092	AssertFailed();
2093	return VERR_EM_INTERPRETER;
2094	}
2095	return VINF_SUCCESS;
2096	}

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 10354

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