HWSVMR0.cpp@ 10509

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1	/* $Id: HWSVMR0.cpp 10509 2008-07-11 10:00:24Z vboxsync $ */
2	/** @file
3	* HWACCM SVM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_svm.h>
32	#include <VBox/pgm.h>
33	#include <VBox/pdm.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <VBox/selm.h>
37	#include <VBox/iom.h>
38	#include <VBox/dis.h>
39	#include <VBox/dbgf.h>
40	#include <VBox/disopcode.h>
41	#include <iprt/param.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm.h>
44	#include <iprt/cpuset.h>
45	#include <iprt/mp.h>
46	#include "HWSVMR0.h"
47
48	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
49
50	/**
51	* Sets up and activates AMD-V on the current CPU
52	*
53	* @returns VBox status code.
54	* @param pCpu CPU info struct
55	* @param pVM The VM to operate on.
56	* @param pvPageCpu Pointer to the global cpu page
57	* @param pPageCpuPhys Physical address of the global cpu page
58	*/
59	HWACCMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
60	{
61	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
62	AssertReturn(pVM, VERR_INVALID_PARAMETER);
63	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
64
65	/* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
66
67	#ifdef LOG_ENABLED
68	SUPR0Printf("SVMR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
69	#endif
70
71	/* Turn on AMD-V in the EFER MSR. */
72	uint64_t val = ASMRdMsr(MSR_K6_EFER);
73	if (!(val & MSR_K6_EFER_SVME))
74	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
75
76	/* Write the physical page address where the CPU will store the host state while executing the VM. */
77	ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
78
79	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
80	pCpu->cTLBFlushes = 0;
81	return VINF_SUCCESS;
82	}
83
84	/**
85	* Deactivates AMD-V on the current CPU
86	*
87	* @returns VBox status code.
88	* @param pCpu CPU info struct
89	* @param pvPageCpu Pointer to the global cpu page
90	* @param pPageCpuPhys Physical address of the global cpu page
91	*/
92	HWACCMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
93	{
94	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
95	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
96
97	#ifdef LOG_ENABLED
98	SUPR0Printf("SVMR0DisableCpu cpu %d\n", pCpu->idCpu);
99	#endif
100
101	/* Turn off AMD-V in the EFER MSR. */
102	uint64_t val = ASMRdMsr(MSR_K6_EFER);
103	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
104
105	/* Invalidate host state physical address. */
106	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
107	pCpu->uCurrentASID = 0;
108
109	return VINF_SUCCESS;
110	}
111
112	/**
113	* Does Ring-0 per VM AMD-V init.
114	*
115	* @returns VBox status code.
116	* @param pVM The VM to operate on.
117	*/
118	HWACCMR0DECL(int) SVMR0InitVM(PVM pVM)
119	{
120	int rc;
121
122	/* Allocate one page for the VM control block (VMCB). */
123	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
124	if (RT_FAILURE(rc))
125	return rc;
126
127	pVM->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCB);
128	pVM->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCB, 0);
129	ASMMemZero32(pVM->hwaccm.s.svm.pVMCB, PAGE_SIZE);
130
131	/* Allocate one page for the host context */
132	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
133	if (RT_FAILURE(rc))
134	return rc;
135
136	pVM->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCBHost);
137	pVM->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCBHost, 0);
138	ASMMemZero32(pVM->hwaccm.s.svm.pVMCBHost, PAGE_SIZE);
139
140	/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
141	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
142	if (RT_FAILURE(rc))
143	return rc;
144
145	pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
146	pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
147	/* Set all bits to intercept all IO accesses. */
148	ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
149
150	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
151	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
152	if (RT_FAILURE(rc))
153	return rc;
154
155	pVM->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
156	pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
157	/* Set all bits to intercept all MSR accesses. */
158	ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
159
160	/* Erratum 170 which requires a forced TLB flush for each world switch:
161	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
162	*
163	* All BH-G1/2 and DH-G1/2 models include a fix:
164	* Athlon X2: 0x6b 1/2
165	* 0x68 1/2
166	* Athlon 64: 0x7f 1
167	* 0x6f 2
168	* Sempron: 0x7f 1/2
169	* 0x6f 2
170	* 0x6c 2
171	* 0x7c 2
172	* Turion 64: 0x68 2
173	*
174	*/
175	uint32_t u32Dummy;
176	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
177	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
178	u32BaseFamily= (u32Version >> 8) & 0xf;
179	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
180	u32Model = ((u32Version >> 4) & 0xf);
181	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
182	u32Stepping = u32Version & 0xf;
183	if ( u32Family == 0xf
184	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
185	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
186	{
187	Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
188	pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
189	}
190
191	/* Invalidate the last cpu we were running on. */
192	pVM->hwaccm.s.svm.idLastCpu = NIL_RTCPUID;
193	return VINF_SUCCESS;
194	}
195
196	/**
197	* Does Ring-0 per VM AMD-V termination.
198	*
199	* @returns VBox status code.
200	* @param pVM The VM to operate on.
201	*/
202	HWACCMR0DECL(int) SVMR0TermVM(PVM pVM)
203	{
204	if (pVM->hwaccm.s.svm.pMemObjVMCB)
205	{
206	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCB, false);
207	pVM->hwaccm.s.svm.pVMCB = 0;
208	pVM->hwaccm.s.svm.pVMCBPhys = 0;
209	pVM->hwaccm.s.svm.pMemObjVMCB = 0;
210	}
211	if (pVM->hwaccm.s.svm.pMemObjVMCBHost)
212	{
213	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCBHost, false);
214	pVM->hwaccm.s.svm.pVMCBHost = 0;
215	pVM->hwaccm.s.svm.pVMCBHostPhys = 0;
216	pVM->hwaccm.s.svm.pMemObjVMCBHost = 0;
217	}
218	if (pVM->hwaccm.s.svm.pMemObjIOBitmap)
219	{
220	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
221	pVM->hwaccm.s.svm.pIOBitmap = 0;
222	pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
223	pVM->hwaccm.s.svm.pMemObjIOBitmap = 0;
224	}
225	if (pVM->hwaccm.s.svm.pMemObjMSRBitmap)
226	{
227	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
228	pVM->hwaccm.s.svm.pMSRBitmap = 0;
229	pVM->hwaccm.s.svm.pMSRBitmapPhys = 0;
230	pVM->hwaccm.s.svm.pMemObjMSRBitmap = 0;
231	}
232	return VINF_SUCCESS;
233	}
234
235	/**
236	* Sets up AMD-V for the specified VM
237	*
238	* @returns VBox status code.
239	* @param pVM The VM to operate on.
240	*/
241	HWACCMR0DECL(int) SVMR0SetupVM(PVM pVM)
242	{
243	int rc = VINF_SUCCESS;
244	SVM_VMCB *pVMCB;
245
246	AssertReturn(pVM, VERR_INVALID_PARAMETER);
247
248	Assert(pVM->hwaccm.s.svm.fSupported);
249
250	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
251	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
252
253	/* Program the control fields. Most of them never have to be changed again. */
254	/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
255	/** @note CR0 & CR4 can be safely read when guest and shadow copies are identical. */
256	if (!pVM->hwaccm.s.fNestedPaging)
257	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
258	else
259	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
260
261	/*
262	* CR0/3/4 writes must be intercepted for obvious reasons.
263	*/
264	if (!pVM->hwaccm.s.fNestedPaging)
265	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(8);
266	else
267	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4) \| RT_BIT(8);
268
269	/* Intercept all DRx reads and writes. */
270	pVMCB->ctrl.u16InterceptRdDRx = RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7);
271	pVMCB->ctrl.u16InterceptWrDRx = RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7);
272
273	/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
274	* All breakpoints are automatically cleared when the VM exits.
275	*/
276
277	pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
278	#ifndef DEBUG
279	if (pVM->hwaccm.s.fNestedPaging)
280	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(14); /* no longer need to intercept #PF. */
281	#endif
282
283	pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
284	\| SVM_CTRL1_INTERCEPT_VINTR
285	\| SVM_CTRL1_INTERCEPT_NMI
286	\| SVM_CTRL1_INTERCEPT_SMI
287	\| SVM_CTRL1_INTERCEPT_INIT
288	\| SVM_CTRL1_INTERCEPT_RDPMC
289	\| SVM_CTRL1_INTERCEPT_CPUID
290	\| SVM_CTRL1_INTERCEPT_RSM
291	\| SVM_CTRL1_INTERCEPT_HLT
292	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
293	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
294	\| SVM_CTRL1_INTERCEPT_INVLPG
295	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
296	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH
297	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
298	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
299	;
300	/* With nested paging we don't care about invlpg anymore. */
301	if (pVM->hwaccm.s.fNestedPaging)
302	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
303
304	pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
305	\| SVM_CTRL2_INTERCEPT_VMMCALL
306	\| SVM_CTRL2_INTERCEPT_VMLOAD
307	\| SVM_CTRL2_INTERCEPT_VMSAVE
308	\| SVM_CTRL2_INTERCEPT_STGI
309	\| SVM_CTRL2_INTERCEPT_CLGI
310	\| SVM_CTRL2_INTERCEPT_SKINIT
311	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
312	\| SVM_CTRL2_INTERCEPT_WBINVD
313	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
314	;
315	Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
316	Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
317	Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
318
319	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
320	pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
321	/* Ignore the priority in the TPR; just deliver it when we tell it to. */
322	pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
323
324	/* Set IO and MSR bitmap addresses. */
325	pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
326	pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
327
328	/* No LBR virtualization. */
329	pVMCB->ctrl.u64LBRVirt = 0;
330
331	/** The ASID must start at 1; the host uses 0. */
332	pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
333
334	/** Setup the PAT msr (nested paging only) */
335	pVMCB->guest.u64GPAT = 0x0007040600070406ULL;
336	return rc;
337	}
338
339
340	/**
341	* Injects an event (trap or external interrupt)
342	*
343	* @param pVM The VM to operate on.
344	* @param pVMCB SVM control block
345	* @param pCtx CPU Context
346	* @param pIntInfo SVM interrupt info
347	*/
348	inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx, SVM_EVENT* pEvent)
349	{
350	#ifdef VBOX_STRICT
351	if (pEvent->n.u8Vector == 0xE)
352	Log(("SVM: Inject int %d at %VGv error code=%02x CR2=%VGv intInfo=%08x\n", pEvent->n.u8Vector, pCtx->rip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
353	else
354	if (pEvent->n.u8Vector < 0x20)
355	Log(("SVM: Inject int %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->rip, pEvent->n.u32ErrorCode));
356	else
357	{
358	Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->rip));
359	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
360	Assert(pCtx->eflags.u32 & X86_EFL_IF);
361	}
362	#endif
363
364	/* Set event injection state. */
365	pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
366	}
367
368
369	/**
370	* Checks for pending guest interrupts and injects them
371	*
372	* @returns VBox status code.
373	* @param pVM The VM to operate on.
374	* @param pVMCB SVM control block
375	* @param pCtx CPU Context
376	*/
377	static int SVMR0CheckPendingInterrupt(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx)
378	{
379	int rc;
380
381	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
382	if (pVM->hwaccm.s.Event.fPending)
383	{
384	SVM_EVENT Event;
385
386	Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip));
387	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
388	Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
389	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
390
391	pVM->hwaccm.s.Event.fPending = false;
392	return VINF_SUCCESS;
393	}
394
395	/* When external interrupts are pending, we should exit the VM when IF is set. */
396	if ( !TRPMHasTrap(pVM)
397	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
398	{
399	if ( !(pCtx->eflags.u32 & X86_EFL_IF)
400	\|\| VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
401	{
402	if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
403	{
404	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
405	LogFlow(("Enable irq window exit!\n"));
406	else
407	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", pCtx->rip));
408
409	/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
410	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
411	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
412	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
413	}
414	}
415	else
416	{
417	uint8_t u8Interrupt;
418
419	rc = PDMGetInterrupt(pVM, &u8Interrupt);
420	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
421	if (VBOX_SUCCESS(rc))
422	{
423	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
424	AssertRC(rc);
425	}
426	else
427	{
428	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
429	Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)));
430	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
431	/* Just continue */
432	}
433	}
434	}
435
436	#ifdef VBOX_STRICT
437	if (TRPMHasTrap(pVM))
438	{
439	uint8_t u8Vector;
440	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
441	AssertRC(rc);
442	}
443	#endif
444
445	if ( pCtx->eflags.u32 & X86_EFL_IF
446	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
447	&& TRPMHasTrap(pVM)
448	)
449	{
450	uint8_t u8Vector;
451	int rc;
452	TRPMEVENT enmType;
453	SVM_EVENT Event;
454	RTGCUINT u32ErrorCode;
455
456	Event.au64[0] = 0;
457
458	/* If a new event is pending, then dispatch it now. */
459	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &u32ErrorCode, 0);
460	AssertRC(rc);
461	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
462	Assert(enmType != TRPM_SOFTWARE_INT);
463
464	/* Clear the pending trap. */
465	rc = TRPMResetTrap(pVM);
466	AssertRC(rc);
467
468	Event.n.u8Vector = u8Vector;
469	Event.n.u1Valid = 1;
470	Event.n.u32ErrorCode = u32ErrorCode;
471
472	if (enmType == TRPM_TRAP)
473	{
474	switch (u8Vector) {
475	case 8:
476	case 10:
477	case 11:
478	case 12:
479	case 13:
480	case 14:
481	case 17:
482	/* Valid error codes. */
483	Event.n.u1ErrorCodeValid = 1;
484	break;
485	default:
486	break;
487	}
488	if (u8Vector == X86_XCPT_NMI)
489	Event.n.u3Type = SVM_EVENT_NMI;
490	else
491	Event.n.u3Type = SVM_EVENT_EXCEPTION;
492	}
493	else
494	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
495
496	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
497	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
498	} /* if (interrupts can be dispatched) */
499
500	return VINF_SUCCESS;
501	}
502
503	/**
504	* Save the host state
505	*
506	* @returns VBox status code.
507	* @param pVM The VM to operate on.
508	*/
509	HWACCMR0DECL(int) SVMR0SaveHostState(PVM pVM)
510	{
511	/* Nothing to do here. */
512	return VINF_SUCCESS;
513	}
514
515	/**
516	* Loads the guest state
517	*
518	* NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
519	*
520	* @returns VBox status code.
521	* @param pVM The VM to operate on.
522	* @param pCtx Guest context
523	*/
524	HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
525	{
526	RTGCUINTPTR val;
527	SVM_VMCB *pVMCB;
528
529	if (pVM == NULL)
530	return VERR_INVALID_PARAMETER;
531
532	/* Setup AMD SVM. */
533	Assert(pVM->hwaccm.s.svm.fSupported);
534
535	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
536	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
537
538	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
539	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
540	{
541	SVM_WRITE_SELREG(CS, cs);
542	SVM_WRITE_SELREG(SS, ss);
543	SVM_WRITE_SELREG(DS, ds);
544	SVM_WRITE_SELREG(ES, es);
545	SVM_WRITE_SELREG(FS, fs);
546	SVM_WRITE_SELREG(GS, gs);
547	}
548
549	/* Guest CPU context: LDTR. */
550	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
551	{
552	SVM_WRITE_SELREG(LDTR, ldtr);
553	}
554
555	/* Guest CPU context: TR. */
556	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
557	{
558	SVM_WRITE_SELREG(TR, tr);
559	}
560
561	/* Guest CPU context: GDTR. */
562	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
563	{
564	pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
565	pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
566	}
567
568	/* Guest CPU context: IDTR. */
569	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
570	{
571	pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
572	pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
573	}
574
575	/*
576	* Sysenter MSRs (unconditional)
577	*/
578	pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
579	pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
580	pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
581
582	/* Control registers */
583	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
584	{
585	val = pCtx->cr0;
586	if (!CPUMIsGuestFPUStateActive(pVM))
587	{
588	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
589	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
590	}
591	else
592	{
593	/** @todo check if we support the old style mess correctly. */
594	if (!(val & X86_CR0_NE))
595	{
596	Log(("Forcing X86_CR0_NE!!!\n"));
597
598	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
599	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
600	{
601	pVMCB->ctrl.u32InterceptException \|= RT_BIT(16);
602	pVM->hwaccm.s.fFPUOldStyleOverride = true;
603	}
604	}
605	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
606	}
607	/* Always enable caching. */
608	val &= ~(X86_CR0_CD\|X86_CR0_NW);
609
610	/* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
611	/* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
612	if (!pVM->hwaccm.s.fNestedPaging)
613	{
614	val \|= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
615	val \|= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
616	}
617	pVMCB->guest.u64CR0 = val;
618	}
619	/* CR2 as well */
620	pVMCB->guest.u64CR2 = pCtx->cr2;
621
622	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
623	{
624	/* Save our shadow CR3 register. */
625	if (pVM->hwaccm.s.fNestedPaging)
626	{
627	pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVM, PGMGetHostMode(pVM));
628	Assert(pVMCB->ctrl.u64NestedPagingCR3);
629	pVMCB->guest.u64CR3 = pCtx->cr3;
630	}
631	else
632	{
633	pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
634	Assert(pVMCB->guest.u64CR3);
635	}
636	}
637
638	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
639	{
640	val = pCtx->cr4;
641	if (!pVM->hwaccm.s.fNestedPaging)
642	{
643	switch(pVM->hwaccm.s.enmShadowMode)
644	{
645	case PGMMODE_REAL:
646	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
647	AssertFailed();
648	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
649
650	case PGMMODE_32_BIT: /* 32-bit paging. */
651	break;
652
653	case PGMMODE_PAE: /* PAE paging. */
654	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
655	/** @todo use normal 32 bits paging */
656	val \|= X86_CR4_PAE;
657	break;
658
659	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
660	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
661	#ifdef VBOX_ENABLE_64_BITS_GUESTS
662	break;
663	#else
664	AssertFailed();
665	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
666	#endif
667
668	default: /* shut up gcc */
669	AssertFailed();
670	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
671	}
672	}
673	pVMCB->guest.u64CR4 = val;
674	}
675
676	/* Debug registers. */
677	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
678	{
679	/** @todo DR0-6 */
680	val = pCtx->dr7;
681	val &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
682	val \|= 0x400; /* must be one */
683	#ifdef VBOX_STRICT
684	val = 0x400;
685	#endif
686	pVMCB->guest.u64DR7 = val;
687
688	pVMCB->guest.u64DR6 = pCtx->dr6;
689	}
690
691	/* EIP, ESP and EFLAGS */
692	pVMCB->guest.u64RIP = pCtx->rip;
693	pVMCB->guest.u64RSP = pCtx->rsp;
694	pVMCB->guest.u64RFlags = pCtx->eflags.u32;
695
696	/* Set CPL */
697	pVMCB->guest.u8CPL = pCtx->csHid.Attr.n.u2Dpl;
698
699	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
700	pVMCB->guest.u64RAX = pCtx->rax;
701
702	/* vmrun will fail without MSR_K6_EFER_SVME. */
703	pVMCB->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
704
705	/* 64 bits guest mode? */
706	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
707	{
708	#if !defined(VBOX_WITH_64_BITS_GUESTS) \|\| HC_ARCH_BITS != 64
709	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
710	#else
711	pVM->hwaccm.s.svm.pfnVMRun = SVMVMRun64;
712	#endif
713	/* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
714	pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
715	pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
716	}
717	else
718	{
719	/* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
720	pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
721
722	pVM->hwaccm.s.svm.pfnVMRun = SVMVMRun;
723	}
724
725	/** TSC offset. */
726	if (TMCpuTickCanUseRealTSC(pVM, &pVMCB->ctrl.u64TSCOffset))
727	{
728	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
729	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
730	}
731	else
732	{
733	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
734	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
735	}
736
737	/* Sync the various msrs for 64 bits mode. */
738	pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
739	pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
740	pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
741	pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
742	pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
743
744	#ifdef DEBUG
745	/* Intercept X86_XCPT_DB if stepping is enabled */
746	if (DBGFIsStepping(pVM))
747	pVMCB->ctrl.u32InterceptException \|= RT_BIT(1);
748	else
749	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(1);
750	#endif
751
752	/* Done. */
753	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
754
755	return VINF_SUCCESS;
756	}
757
758
759	/**
760	* Runs guest code in an SVM VM.
761	*
762	* @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
763	*
764	* @returns VBox status code.
765	* @param pVM The VM to operate on.
766	* @param pCtx Guest context
767	*/
768	HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
769	{
770	int rc = VINF_SUCCESS;
771	uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
772	SVM_VMCB *pVMCB;
773	bool fGuestStateSynced = false;
774	unsigned cResume = 0;
775	uint8_t u8LastVTPR;
776	PHWACCM_CPUINFO pCpu = 0;
777
778	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
779
780	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
781	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
782
783	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
784	*/
785	ResumeExecution:
786	/* Safety precaution; looping for too long here can have a very bad effect on the host */
787	if (++cResume > HWACCM_MAX_RESUME_LOOPS)
788	{
789	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
790	rc = VINF_EM_RAW_INTERRUPT;
791	goto end;
792	}
793
794	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
795	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
796	{
797	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
798	if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
799	{
800	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
801	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
802	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
803	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
804	*/
805	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
806	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
807	pVMCB->ctrl.u64IntShadow = 0;
808	}
809	}
810	else
811	{
812	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
813	pVMCB->ctrl.u64IntShadow = 0;
814	}
815
816	/* Check for pending actions that force us to go back to ring 3. */
817	#ifdef DEBUG
818	/* Intercept X86_XCPT_DB if stepping is enabled */
819	if (!DBGFIsStepping(pVM))
820	#endif
821	{
822	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
823	{
824	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
825	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
826	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
827	rc = VINF_EM_RAW_TO_R3;
828	goto end;
829	}
830	}
831
832	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
833	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
834	{
835	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
836	rc = VINF_EM_PENDING_REQUEST;
837	goto end;
838	}
839
840	/* When external interrupts are pending, we should exit the VM when IF is set. */
841	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
842	rc = SVMR0CheckPendingInterrupt(pVM, pVMCB, pCtx);
843	if (VBOX_FAILURE(rc))
844	{
845	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
846	goto end;
847	}
848
849	/* Load the guest state */
850	rc = SVMR0LoadGuestState(pVM, pCtx);
851	if (rc != VINF_SUCCESS)
852	{
853	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
854	goto end;
855	}
856	fGuestStateSynced = true;
857
858	/* TPR caching using CR8 is only available in 64 bits mode */
859	/* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
860	/* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock). */
861	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
862	{
863	/* TPR caching in CR8 */
864	int rc = PDMApicGetTPR(pVM, &u8LastVTPR);
865	AssertRC(rc);
866	pVMCB->ctrl.IntCtrl.n.u8VTPR = u8LastVTPR;
867	}
868
869	/* All done! Let's start VM execution. */
870	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
871
872	/* Enable nested paging if necessary (disabled each time after #VMEXIT). */
873	pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
874
875	#ifdef LOG_ENABLED
876	pCpu = HWACCMR0GetCurrentCpu();
877	if ( pVM->hwaccm.s.svm.idLastCpu != pCpu->idCpu
878	\|\| pVM->hwaccm.s.svm.cTLBFlushes != pCpu->cTLBFlushes)
879	{
880	if (pVM->hwaccm.s.svm.idLastCpu != pCpu->idCpu)
881	Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVM->hwaccm.s.svm.idLastCpu, pCpu->idCpu));
882	else
883	Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVM->hwaccm.s.svm.cTLBFlushes, pCpu->cTLBFlushes));
884	}
885	if (pCpu->fFlushTLB)
886	Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
887	#endif
888
889	/*
890	* NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
891	* (until the actual world switch)
892	*/
893	pCpu = HWACCMR0GetCurrentCpu();
894	/* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
895	/* Note that this can happen both for start and resume due to long jumps back to ring 3. */
896	if ( pVM->hwaccm.s.svm.idLastCpu != pCpu->idCpu
897	/* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
898	\|\| pVM->hwaccm.s.svm.cTLBFlushes != pCpu->cTLBFlushes)
899	{
900	/* Force a TLB flush on VM entry. */
901	pVM->hwaccm.s.svm.fForceTLBFlush = true;
902	}
903	else
904	Assert(!pCpu->fFlushTLB);
905
906	pVM->hwaccm.s.svm.idLastCpu = pCpu->idCpu;
907
908	/* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
909	if ( pVM->hwaccm.s.svm.fForceTLBFlush
910	&& !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
911	{
912	if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.svm.u32MaxASID
913	\|\| pCpu->fFlushTLB)
914	{
915	pCpu->fFlushTLB = false;
916	pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
917	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
918	pCpu->cTLBFlushes++;
919	}
920	else
921	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushASID);
922
923	pVM->hwaccm.s.svm.cTLBFlushes = pCpu->cTLBFlushes;
924	}
925	else
926	{
927	Assert(!pCpu->fFlushTLB \|\| pVM->hwaccm.s.svm.fAlwaysFlushTLB);
928
929	/* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
930	if (!pCpu->uCurrentASID)
931	pCpu->uCurrentASID = 1;
932
933	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVM->hwaccm.s.svm.fForceTLBFlush;
934	}
935	AssertMsg(pVM->hwaccm.s.svm.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVM->hwaccm.s.svm.cTLBFlushes, pCpu->cTLBFlushes));
936	AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.svm.u32MaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
937	pVMCB->ctrl.TLBCtrl.n.u32ASID = pCpu->uCurrentASID;
938
939	#ifdef VBOX_WITH_STATISTICS
940	if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
941	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBWorldSwitch);
942	else
943	STAM_COUNTER_INC(&pVM->hwaccm.s.StatNoFlushTLBWorldSwitch);
944	#endif
945
946	/* In case we execute a goto ResumeExecution later on. */
947	pVM->hwaccm.s.svm.fResumeVM = true;
948	pVM->hwaccm.s.svm.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
949
950	Assert(sizeof(pVM->hwaccm.s.svm.pVMCBPhys) == 8);
951	Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
952	\| SVM_CTRL2_INTERCEPT_VMMCALL
953	\| SVM_CTRL2_INTERCEPT_VMLOAD
954	\| SVM_CTRL2_INTERCEPT_VMSAVE
955	\| SVM_CTRL2_INTERCEPT_STGI
956	\| SVM_CTRL2_INTERCEPT_CLGI
957	\| SVM_CTRL2_INTERCEPT_SKINIT
958	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
959	\| SVM_CTRL2_INTERCEPT_WBINVD
960	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
961	));
962	Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
963	Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
964	Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
965	Assert(pVMCB->ctrl.u64LBRVirt == 0);
966
967	pVM->hwaccm.s.svm.pfnVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);
968	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
969
970	/**
971	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
972	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
973	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
974	*/
975
976	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
977
978	/* Reason for the VM exit */
979	exitCode = pVMCB->ctrl.u64ExitCode;
980
981	if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
982	{
983	HWACCMDumpRegs(pCtx);
984	#ifdef DEBUG
985	Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
986	Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
987	Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
988	Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
989	Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
990	Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
991	Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
992	Log(("ctrl.u64IOPMPhysAddr %VX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
993	Log(("ctrl.u64MSRPMPhysAddr %VX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
994	Log(("ctrl.u64TSCOffset %VX64\n", pVMCB->ctrl.u64TSCOffset));
995
996	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
997	Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
998	Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
999	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
1000
1001	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
1002	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
1003	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
1004	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
1005	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
1006	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
1007	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
1008	Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
1009	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
1010	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
1011
1012	Log(("ctrl.u64IntShadow %VX64\n", pVMCB->ctrl.u64IntShadow));
1013	Log(("ctrl.u64ExitCode %VX64\n", pVMCB->ctrl.u64ExitCode));
1014	Log(("ctrl.u64ExitInfo1 %VX64\n", pVMCB->ctrl.u64ExitInfo1));
1015	Log(("ctrl.u64ExitInfo2 %VX64\n", pVMCB->ctrl.u64ExitInfo2));
1016	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
1017	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
1018	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
1019	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
1020	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
1021	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
1022	Log(("ctrl.NestedPaging %VX64\n", pVMCB->ctrl.NestedPaging.au64));
1023	Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
1024	Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
1025	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
1026	Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
1027	Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
1028	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
1029
1030	Log(("ctrl.u64NestedPagingCR3 %VX64\n", pVMCB->ctrl.u64NestedPagingCR3));
1031	Log(("ctrl.u64LBRVirt %VX64\n", pVMCB->ctrl.u64LBRVirt));
1032
1033	Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
1034	Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1035	Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1036	Log(("guest.CS.u64Base %VX64\n", pVMCB->guest.CS.u64Base));
1037	Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1038	Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1039	Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1040	Log(("guest.DS.u64Base %VX64\n", pVMCB->guest.DS.u64Base));
1041	Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1042	Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1043	Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1044	Log(("guest.ES.u64Base %VX64\n", pVMCB->guest.ES.u64Base));
1045	Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1046	Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1047	Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1048	Log(("guest.FS.u64Base %VX64\n", pVMCB->guest.FS.u64Base));
1049	Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1050	Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1051	Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1052	Log(("guest.GS.u64Base %VX64\n", pVMCB->guest.GS.u64Base));
1053
1054	Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1055	Log(("guest.GDTR.u64Base %VX64\n", pVMCB->guest.GDTR.u64Base));
1056
1057	Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1058	Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1059	Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1060	Log(("guest.LDTR.u64Base %VX64\n", pVMCB->guest.LDTR.u64Base));
1061
1062	Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1063	Log(("guest.IDTR.u64Base %VX64\n", pVMCB->guest.IDTR.u64Base));
1064
1065	Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1066	Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1067	Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1068	Log(("guest.TR.u64Base %VX64\n", pVMCB->guest.TR.u64Base));
1069
1070	Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1071	Log(("guest.u64CR0 %VX64\n", pVMCB->guest.u64CR0));
1072	Log(("guest.u64CR2 %VX64\n", pVMCB->guest.u64CR2));
1073	Log(("guest.u64CR3 %VX64\n", pVMCB->guest.u64CR3));
1074	Log(("guest.u64CR4 %VX64\n", pVMCB->guest.u64CR4));
1075	Log(("guest.u64DR6 %VX64\n", pVMCB->guest.u64DR6));
1076	Log(("guest.u64DR7 %VX64\n", pVMCB->guest.u64DR7));
1077
1078	Log(("guest.u64RIP %VX64\n", pVMCB->guest.u64RIP));
1079	Log(("guest.u64RSP %VX64\n", pVMCB->guest.u64RSP));
1080	Log(("guest.u64RAX %VX64\n", pVMCB->guest.u64RAX));
1081	Log(("guest.u64RFlags %VX64\n", pVMCB->guest.u64RFlags));
1082
1083	Log(("guest.u64SysEnterCS %VX64\n", pVMCB->guest.u64SysEnterCS));
1084	Log(("guest.u64SysEnterEIP %VX64\n", pVMCB->guest.u64SysEnterEIP));
1085	Log(("guest.u64SysEnterESP %VX64\n", pVMCB->guest.u64SysEnterESP));
1086
1087	Log(("guest.u64EFER %VX64\n", pVMCB->guest.u64EFER));
1088	Log(("guest.u64STAR %VX64\n", pVMCB->guest.u64STAR));
1089	Log(("guest.u64LSTAR %VX64\n", pVMCB->guest.u64LSTAR));
1090	Log(("guest.u64CSTAR %VX64\n", pVMCB->guest.u64CSTAR));
1091	Log(("guest.u64SFMASK %VX64\n", pVMCB->guest.u64SFMASK));
1092	Log(("guest.u64KernelGSBase %VX64\n", pVMCB->guest.u64KernelGSBase));
1093	Log(("guest.u64GPAT %VX64\n", pVMCB->guest.u64GPAT));
1094	Log(("guest.u64DBGCTL %VX64\n", pVMCB->guest.u64DBGCTL));
1095	Log(("guest.u64BR_FROM %VX64\n", pVMCB->guest.u64BR_FROM));
1096	Log(("guest.u64BR_TO %VX64\n", pVMCB->guest.u64BR_TO));
1097	Log(("guest.u64LASTEXCPFROM %VX64\n", pVMCB->guest.u64LASTEXCPFROM));
1098	Log(("guest.u64LASTEXCPTO %VX64\n", pVMCB->guest.u64LASTEXCPTO));
1099
1100	#endif
1101	rc = VERR_SVM_UNABLE_TO_START_VM;
1102	goto end;
1103	}
1104
1105	/* Let's first sync back eip, esp, and eflags. */
1106	pCtx->rip = pVMCB->guest.u64RIP;
1107	pCtx->rsp = pVMCB->guest.u64RSP;
1108	pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1109	/* eax is saved/restore across the vmrun instruction */
1110	pCtx->rax = pVMCB->guest.u64RAX;
1111
1112	pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
1113
1114	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1115	SVM_READ_SELREG(SS, ss);
1116	SVM_READ_SELREG(CS, cs);
1117	SVM_READ_SELREG(DS, ds);
1118	SVM_READ_SELREG(ES, es);
1119	SVM_READ_SELREG(FS, fs);
1120	SVM_READ_SELREG(GS, gs);
1121
1122	/* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1123	/* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1124	if ( pVM->hwaccm.s.fNestedPaging
1125	&& pCtx->cr3 != pVMCB->guest.u64CR3)
1126	{
1127	CPUMSetGuestCR3(pVM, pVMCB->guest.u64CR3);
1128	PGMUpdateCR3(pVM, pVMCB->guest.u64CR3);
1129	}
1130
1131	/** @note NOW IT'S SAFE FOR LOGGING! */
1132
1133	/* Take care of instruction fusing (sti, mov ss) */
1134	if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1135	{
1136	Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->rip));
1137	EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1138	}
1139	else
1140	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1141
1142	Log2(("exitCode = %x\n", exitCode));
1143
1144	/* Sync back the debug registers. */
1145	/** @todo Implement debug registers correctly. */
1146	pCtx->dr6 = pVMCB->guest.u64DR6;
1147	pCtx->dr7 = pVMCB->guest.u64DR7;
1148
1149	/* Check if an injected event was interrupted prematurely. */
1150	pVM->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1151	if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1152	&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1153	{
1154	Log(("Pending inject %VX64 at %VGv exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitCode));
1155
1156	#ifdef LOG_ENABLED
1157	SVM_EVENT Event;
1158	Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
1159
1160	if ( exitCode == SVM_EXIT_EXCEPTION_E
1161	&& Event.n.u8Vector == 0xE)
1162	{
1163	Log(("Double fault!\n"));
1164	}
1165	#endif
1166
1167	pVM->hwaccm.s.Event.fPending = true;
1168	/* Error code present? (redundant) */
1169	if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1170	{
1171	pVM->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1172	}
1173	else
1174	pVM->hwaccm.s.Event.errCode = 0;
1175	}
1176	#ifdef VBOX_WITH_STATISTICS
1177	if (exitCode == SVM_EXIT_NPF)
1178	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitReasonNPF);
1179	else
1180	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1181	#endif
1182
1183	/* Deal with the reason of the VM-exit. */
1184	switch (exitCode)
1185	{
1186	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1187	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1188	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1189	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1190	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1191	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1192	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1193	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1194	{
1195	/* Pending trap. */
1196	SVM_EVENT Event;
1197	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1198
1199	Log2(("Hardware/software interrupt %d\n", vector));
1200	switch (vector)
1201	{
1202	#ifdef DEBUG
1203	case X86_XCPT_DB:
1204	rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), pVMCB->guest.u64DR6);
1205	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
1206	break;
1207	#endif
1208
1209	case X86_XCPT_NM:
1210	{
1211	uint32_t oldCR0;
1212
1213	Log(("#NM fault at %VGv\n", pCtx->rip));
1214
1215	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1216	oldCR0 = ASMGetCR0();
1217	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1218	rc = CPUMHandleLazyFPU(pVM);
1219	if (rc == VINF_SUCCESS)
1220	{
1221	Assert(CPUMIsGuestFPUStateActive(pVM));
1222
1223	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
1224	ASMSetCR0(oldCR0);
1225
1226	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1227
1228	/* Continue execution. */
1229	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1230	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1231
1232	goto ResumeExecution;
1233	}
1234
1235	Log(("Forward #NM fault to the guest\n"));
1236	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1237
1238	Event.au64[0] = 0;
1239	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1240	Event.n.u1Valid = 1;
1241	Event.n.u8Vector = X86_XCPT_NM;
1242
1243	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1244	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1245	goto ResumeExecution;
1246	}
1247
1248	case X86_XCPT_PF: /* Page fault */
1249	{
1250	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1251	RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1252
1253	#ifdef DEBUG
1254	if (pVM->hwaccm.s.fNestedPaging)
1255	{ /* A genuine pagefault.
1256	* Forward the trap to the guest by injecting the exception and resuming execution.
1257	*/
1258	Log(("Guest page fault at %VGv cr2=%VGv error code %x rsp=%VGv\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
1259	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1260
1261	/* Now we must update CR2. */
1262	pCtx->cr2 = uFaultAddress;
1263
1264	Event.au64[0] = 0;
1265	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1266	Event.n.u1Valid = 1;
1267	Event.n.u8Vector = X86_XCPT_PF;
1268	Event.n.u1ErrorCodeValid = 1;
1269	Event.n.u32ErrorCode = errCode;
1270
1271	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1272
1273	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1274	goto ResumeExecution;
1275	}
1276	#endif
1277	Assert(!pVM->hwaccm.s.fNestedPaging);
1278
1279	Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, uFaultAddress, errCode));
1280	/* Exit qualification contains the linear address of the page fault. */
1281	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1282	TRPMSetErrorCode(pVM, errCode);
1283	TRPMSetFaultAddress(pVM, uFaultAddress);
1284
1285	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1286	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1287	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
1288	if (rc == VINF_SUCCESS)
1289	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1290	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, uFaultAddress, errCode));
1291	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1292
1293	TRPMResetTrap(pVM);
1294
1295	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1296	goto ResumeExecution;
1297	}
1298	else
1299	if (rc == VINF_EM_RAW_GUEST_TRAP)
1300	{ /* A genuine pagefault.
1301	* Forward the trap to the guest by injecting the exception and resuming execution.
1302	*/
1303	Log2(("Forward page fault to the guest\n"));
1304	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1305	/* The error code might have been changed. */
1306	errCode = TRPMGetErrorCode(pVM);
1307
1308	TRPMResetTrap(pVM);
1309
1310	/* Now we must update CR2. */
1311	pCtx->cr2 = uFaultAddress;
1312
1313	Event.au64[0] = 0;
1314	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1315	Event.n.u1Valid = 1;
1316	Event.n.u8Vector = X86_XCPT_PF;
1317	Event.n.u1ErrorCodeValid = 1;
1318	Event.n.u32ErrorCode = errCode;
1319
1320	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1321
1322	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1323	goto ResumeExecution;
1324	}
1325	#ifdef VBOX_STRICT
1326	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1327	LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
1328	#endif
1329	/* Need to go back to the recompiler to emulate the instruction. */
1330	TRPMResetTrap(pVM);
1331	break;
1332	}
1333
1334	case X86_XCPT_MF: /* Floating point exception. */
1335	{
1336	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1337	if (!(pCtx->cr0 & X86_CR0_NE))
1338	{
1339	/* old style FPU error reporting needs some extra work. */
1340	/** @todo don't fall back to the recompiler, but do it manually. */
1341	rc = VINF_EM_RAW_EMULATE_INSTR;
1342	break;
1343	}
1344	Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1345
1346	Event.au64[0] = 0;
1347	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1348	Event.n.u1Valid = 1;
1349	Event.n.u8Vector = X86_XCPT_MF;
1350
1351	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1352
1353	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1354	goto ResumeExecution;
1355	}
1356
1357	#ifdef VBOX_STRICT
1358	case X86_XCPT_GP: /* General protection failure exception.*/
1359	case X86_XCPT_UD: /* Unknown opcode exception. */
1360	case X86_XCPT_DE: /* Debug exception. */
1361	case X86_XCPT_SS: /* Stack segment exception. */
1362	case X86_XCPT_NP: /* Segment not present exception. */
1363	{
1364	Event.au64[0] = 0;
1365	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1366	Event.n.u1Valid = 1;
1367	Event.n.u8Vector = vector;
1368
1369	switch(vector)
1370	{
1371	case X86_XCPT_GP:
1372	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1373	Event.n.u1ErrorCodeValid = 1;
1374	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1375	break;
1376	case X86_XCPT_DE:
1377	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1378	break;
1379	case X86_XCPT_UD:
1380	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1381	break;
1382	case X86_XCPT_SS:
1383	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1384	Event.n.u1ErrorCodeValid = 1;
1385	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1386	break;
1387	case X86_XCPT_NP:
1388	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1389	Event.n.u1ErrorCodeValid = 1;
1390	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1391	break;
1392	}
1393	Log(("Trap %x at %VGv esi=%x\n", vector, pCtx->rip, pCtx->esi));
1394	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1395
1396	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1397	goto ResumeExecution;
1398	}
1399	#endif
1400	default:
1401	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1402	rc = VERR_EM_INTERNAL_ERROR;
1403	break;
1404
1405	} /* switch (vector) */
1406	break;
1407	}
1408
1409	case SVM_EXIT_NPF:
1410	{
1411	/* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1412	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1413	RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1414
1415	Assert(pVM->hwaccm.s.fNestedPaging);
1416	Log(("Nested page fault at %VGv cr2=%VGp error code %x\n", pCtx->rip, uFaultAddress, errCode));
1417	/* Exit qualification contains the linear address of the page fault. */
1418	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1419	TRPMSetErrorCode(pVM, errCode);
1420	TRPMSetFaultAddress(pVM, uFaultAddress);
1421
1422	/* Handle the pagefault trap for the nested shadow table. */
1423	rc = PGMR0Trap0eHandlerNestedPaging(pVM, PGMGetHostMode(pVM), errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1424	Log2(("PGMR0Trap0eHandlerNestedPaging %VGv returned %Vrc\n", pCtx->rip, rc));
1425	if (rc == VINF_SUCCESS)
1426	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1427	Log2(("Shadow page fault at %VGv cr2=%VGp error code %x\n", pCtx->rip, uFaultAddress, errCode));
1428	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1429
1430	TRPMResetTrap(pVM);
1431
1432	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1433	goto ResumeExecution;
1434	}
1435
1436	#ifdef VBOX_STRICT
1437	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1438	LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
1439	#endif
1440	/* Need to go back to the recompiler to emulate the instruction. */
1441	TRPMResetTrap(pVM);
1442	break;
1443	}
1444
1445	case SVM_EXIT_VINTR:
1446	/* A virtual interrupt is about to be delivered, which means IF=1. */
1447	Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1448	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1449	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1450	goto ResumeExecution;
1451
1452	case SVM_EXIT_FERR_FREEZE:
1453	case SVM_EXIT_INTR:
1454	case SVM_EXIT_NMI:
1455	case SVM_EXIT_SMI:
1456	case SVM_EXIT_INIT:
1457	/* External interrupt; leave to allow it to be dispatched again. */
1458	rc = VINF_EM_RAW_INTERRUPT;
1459	break;
1460
1461	case SVM_EXIT_WBINVD:
1462	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1463	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1464	/* Skip instruction and continue directly. */
1465	pCtx->rip += 2; /** @note hardcoded opcode size! */
1466	/* Continue execution.*/
1467	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1468	goto ResumeExecution;
1469
1470	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1471	{
1472	Log2(("SVM: Cpuid at %VGv for %x\n", pCtx->rip, pCtx->eax));
1473	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1474	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1475	if (rc == VINF_SUCCESS)
1476	{
1477	/* Update EIP and continue execution. */
1478	pCtx->rip += 2; /** @note hardcoded opcode size! */
1479	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1480	goto ResumeExecution;
1481	}
1482	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1483	rc = VINF_EM_RAW_EMULATE_INSTR;
1484	break;
1485	}
1486
1487	case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1488	{
1489	Log2(("SVM: Rdtsc\n"));
1490	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1491	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1492	if (rc == VINF_SUCCESS)
1493	{
1494	/* Update EIP and continue execution. */
1495	pCtx->rip += 2; /** @note hardcoded opcode size! */
1496	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1497	goto ResumeExecution;
1498	}
1499	AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1500	rc = VINF_EM_RAW_EMULATE_INSTR;
1501	break;
1502	}
1503
1504	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1505	{
1506	Log2(("SVM: invlpg\n"));
1507	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1508
1509	Assert(!pVM->hwaccm.s.fNestedPaging);
1510
1511	/* Truly a pita. Why can't SVM give the same information as VT-x? */
1512	rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1513	if (rc == VINF_SUCCESS)
1514	{
1515	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageInvlpg);
1516	goto ResumeExecution; /* eip already updated */
1517	}
1518	break;
1519	}
1520
1521	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1522	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1523	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1524	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1525	{
1526	uint32_t cbSize;
1527
1528	Log2(("SVM: %VGv mov cr%d, \n", pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
1529	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1530	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1531
1532	switch (exitCode - SVM_EXIT_WRITE_CR0)
1533	{
1534	case 0:
1535	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1536	break;
1537	case 2:
1538	break;
1539	case 3:
1540	Assert(!pVM->hwaccm.s.fNestedPaging);
1541	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1542	break;
1543	case 4:
1544	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1545	break;
1546	case 8:
1547	break;
1548	default:
1549	AssertFailed();
1550	}
1551	/* Check if a sync operation is pending. */
1552	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1553	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1554	{
1555	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1556	AssertRC(rc);
1557
1558	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBCRxChange);
1559
1560	/* Must be set by PGMSyncCR3 */
1561	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PROTECTED \|\| pVM->hwaccm.s.svm.fForceTLBFlush);
1562	}
1563	if (rc == VINF_SUCCESS)
1564	{
1565	/* EIP has been updated already. */
1566
1567	/* Only resume if successful. */
1568	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1569	goto ResumeExecution;
1570	}
1571	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1572	break;
1573	}
1574
1575	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1576	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1577	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1578	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1579	{
1580	uint32_t cbSize;
1581
1582	Log2(("SVM: %VGv mov x, cr%d\n", pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
1583	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1584	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1585	if (rc == VINF_SUCCESS)
1586	{
1587	/* EIP has been updated already. */
1588
1589	/* Only resume if successful. */
1590	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1591	goto ResumeExecution;
1592	}
1593	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1594	break;
1595	}
1596
1597	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1598	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1599	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1600	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1601	{
1602	uint32_t cbSize;
1603
1604	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
1605	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1606	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1607	if (rc == VINF_SUCCESS)
1608	{
1609	/* EIP has been updated already. */
1610
1611	/* Only resume if successful. */
1612	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1613	goto ResumeExecution;
1614	}
1615	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1616	break;
1617	}
1618
1619	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1620	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1621	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1622	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1623	{
1624	uint32_t cbSize;
1625
1626	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
1627	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1628	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1629	if (rc == VINF_SUCCESS)
1630	{
1631	/* EIP has been updated already. */
1632
1633	/* Only resume if successful. */
1634	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1635	goto ResumeExecution;
1636	}
1637	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1638	break;
1639	}
1640
1641	/* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1642	case SVM_EXIT_IOIO: /* I/O instruction. */
1643	{
1644	SVM_IOIO_EXIT IoExitInfo;
1645	uint32_t uIOSize, uAndVal;
1646
1647	IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1648
1649	/** @todo could use a lookup table here */
1650	if (IoExitInfo.n.u1OP8)
1651	{
1652	uIOSize = 1;
1653	uAndVal = 0xff;
1654	}
1655	else
1656	if (IoExitInfo.n.u1OP16)
1657	{
1658	uIOSize = 2;
1659	uAndVal = 0xffff;
1660	}
1661	else
1662	if (IoExitInfo.n.u1OP32)
1663	{
1664	uIOSize = 4;
1665	uAndVal = 0xffffffff;
1666	}
1667	else
1668	{
1669	AssertFailed(); /* should be fatal. */
1670	rc = VINF_EM_RAW_EMULATE_INSTR;
1671	break;
1672	}
1673
1674	if (IoExitInfo.n.u1STR)
1675	{
1676	/* ins/outs */
1677	uint32_t prefix = 0;
1678	if (IoExitInfo.n.u1REP)
1679	prefix \|= PREFIX_REP;
1680
1681	if (IoExitInfo.n.u1Type == 0)
1682	{
1683	Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1684	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1685	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1686	}
1687	else
1688	{
1689	Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1690	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1691	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1692	}
1693	}
1694	else
1695	{
1696	/* normal in/out */
1697	Assert(!IoExitInfo.n.u1REP);
1698
1699	if (IoExitInfo.n.u1Type == 0)
1700	{
1701	Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1702	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1703	rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1704	}
1705	else
1706	{
1707	uint32_t u32Val = 0;
1708
1709	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1710	rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1711	if (IOM_SUCCESS(rc))
1712	{
1713	/* Write back to the EAX register. */
1714	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1715	Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1716	}
1717	}
1718	}
1719	/*
1720	* Handled the I/O return codes.
1721	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1722	*/
1723	if (IOM_SUCCESS(rc))
1724	{
1725	/* Update EIP and continue execution. */
1726	pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1727	if (RT_LIKELY(rc == VINF_SUCCESS))
1728	{
1729	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1730	goto ResumeExecution;
1731	}
1732	Log2(("EM status from IO at %VGv %x size %d: %Vrc\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
1733	break;
1734	}
1735
1736	#ifdef VBOX_STRICT
1737	if (rc == VINF_IOM_HC_IOPORT_READ)
1738	Assert(IoExitInfo.n.u1Type != 0);
1739	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1740	Assert(IoExitInfo.n.u1Type == 0);
1741	else
1742	AssertMsg(VBOX_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1743	#endif
1744	Log2(("Failed IO at %VGv %x size %d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1745	break;
1746	}
1747
1748	case SVM_EXIT_HLT:
1749	/** Check if external interrupts are pending; if so, don't switch back. */
1750	if ( pCtx->eflags.Bits.u1IF
1751	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1752	{
1753	pCtx->rip++; /* skip hlt */
1754	goto ResumeExecution;
1755	}
1756
1757	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1758	break;
1759
1760	case SVM_EXIT_RSM:
1761	case SVM_EXIT_INVLPGA:
1762	case SVM_EXIT_VMRUN:
1763	case SVM_EXIT_VMMCALL:
1764	case SVM_EXIT_VMLOAD:
1765	case SVM_EXIT_VMSAVE:
1766	case SVM_EXIT_STGI:
1767	case SVM_EXIT_CLGI:
1768	case SVM_EXIT_SKINIT:
1769	case SVM_EXIT_RDTSCP:
1770	{
1771	/* Unsupported instructions. */
1772	SVM_EVENT Event;
1773
1774	Event.au64[0] = 0;
1775	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1776	Event.n.u1Valid = 1;
1777	Event.n.u8Vector = X86_XCPT_UD;
1778
1779	Log(("Forced #UD trap at %VGv\n", pCtx->rip));
1780	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1781
1782	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1783	goto ResumeExecution;
1784	}
1785
1786	/* Emulate in ring 3. */
1787	case SVM_EXIT_MSR:
1788	{
1789	uint32_t cbSize;
1790
1791	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
1792	Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
1793	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1794	if (rc == VINF_SUCCESS)
1795	{
1796	/* EIP has been updated already. */
1797
1798	/* Only resume if successful. */
1799	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1800	goto ResumeExecution;
1801	}
1802	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Vrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
1803	break;
1804	}
1805
1806	case SVM_EXIT_MONITOR:
1807	case SVM_EXIT_RDPMC:
1808	case SVM_EXIT_PAUSE:
1809	case SVM_EXIT_MWAIT_UNCOND:
1810	case SVM_EXIT_MWAIT_ARMED:
1811	case SVM_EXIT_TASK_SWITCH: /* can change CR3; emulate */
1812	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1813	break;
1814
1815	case SVM_EXIT_SHUTDOWN:
1816	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1817	break;
1818
1819	case SVM_EXIT_IDTR_READ:
1820	case SVM_EXIT_GDTR_READ:
1821	case SVM_EXIT_LDTR_READ:
1822	case SVM_EXIT_TR_READ:
1823	case SVM_EXIT_IDTR_WRITE:
1824	case SVM_EXIT_GDTR_WRITE:
1825	case SVM_EXIT_LDTR_WRITE:
1826	case SVM_EXIT_TR_WRITE:
1827	case SVM_EXIT_CR0_SEL_WRITE:
1828	default:
1829	/* Unexpected exit codes. */
1830	rc = VERR_EM_INTERNAL_ERROR;
1831	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
1832	break;
1833	}
1834
1835	end:
1836	if (fGuestStateSynced)
1837	{
1838	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1839	SVM_READ_SELREG(LDTR, ldtr);
1840	SVM_READ_SELREG(TR, tr);
1841
1842	pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1843	pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1844
1845	pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1846	pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1847
1848	/*
1849	* System MSRs
1850	*/
1851	pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1852	pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1853	pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1854	}
1855
1856	/* Signal changes for the recompiler. */
1857	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
1858
1859	/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
1860	if (exitCode == SVM_EXIT_INTR)
1861	{
1862	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1863	/* On the next entry we'll only sync the host context. */
1864	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
1865	}
1866	else
1867	{
1868	/* On the next entry we'll sync everything. */
1869	/** @todo we can do better than this */
1870	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
1871	}
1872
1873	/* translate into a less severe return code */
1874	if (rc == VERR_EM_INTERPRETER)
1875	rc = VINF_EM_RAW_EMULATE_INSTR;
1876
1877	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1878	return rc;
1879	}
1880
1881	/**
1882	* Enters the AMD-V session
1883	*
1884	* @returns VBox status code.
1885	* @param pVM The VM to operate on.
1886	* @param pCpu CPU info struct
1887	*/
1888	HWACCMR0DECL(int) SVMR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
1889	{
1890	Assert(pVM->hwaccm.s.svm.fSupported);
1891
1892	LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVM->hwaccm.s.svm.idLastCpu, pCpu->uCurrentASID));
1893	pVM->hwaccm.s.svm.fResumeVM = false;
1894
1895	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
1896	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_LDTR;
1897
1898	return VINF_SUCCESS;
1899	}
1900
1901
1902	/**
1903	* Leaves the AMD-V session
1904	*
1905	* @returns VBox status code.
1906	* @param pVM The VM to operate on.
1907	*/
1908	HWACCMR0DECL(int) SVMR0Leave(PVM pVM)
1909	{
1910	Assert(pVM->hwaccm.s.svm.fSupported);
1911	return VINF_SUCCESS;
1912	}
1913
1914
1915	static int svmInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1916	{
1917	OP_PARAMVAL param1;
1918	RTGCPTR addr;
1919
1920	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1921	if(VBOX_FAILURE(rc))
1922	return VERR_EM_INTERPRETER;
1923
1924	switch(param1.type)
1925	{
1926	case PARMTYPE_IMMEDIATE:
1927	case PARMTYPE_ADDRESS:
1928	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1929	return VERR_EM_INTERPRETER;
1930	addr = param1.val.val64;
1931	break;
1932
1933	default:
1934	return VERR_EM_INTERPRETER;
1935	}
1936
1937	/** @todo is addr always a flat linear address or ds based
1938	* (in absence of segment override prefixes)????
1939	*/
1940	rc = PGMInvalidatePage(pVM, addr);
1941	if (VBOX_SUCCESS(rc))
1942	{
1943	/* Manually invalidate the page for the VM's TLB. */
1944	Log(("SVMInvlpgA %VGv ASID=%d\n", addr, uASID));
1945	SVMInvlpgA(addr, uASID);
1946	return VINF_SUCCESS;
1947	}
1948	Assert(rc == VERR_REM_FLUSHED_PAGES_OVERFLOW);
1949	return rc;
1950	}
1951
1952	/**
1953	* Interprets INVLPG
1954	*
1955	* @returns VBox status code.
1956	* @retval VINF_* Scheduling instructions.
1957	* @retval VERR_EM_INTERPRETER Something we can't cope with.
1958	* @retval VERR_* Fatal errors.
1959	*
1960	* @param pVM The VM handle.
1961	* @param pRegFrame The register frame.
1962	* @param ASID Tagged TLB id for the guest
1963	*
1964	* Updates the EIP if an instruction was executed successfully.
1965	*/
1966	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1967	{
1968	/*
1969	* Only allow 32 & 64 bits code.
1970	*/
1971	DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
1972	if (enmMode != CPUMODE_16BIT)
1973	{
1974	RTGCPTR pbCode;
1975	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
1976	if (VBOX_SUCCESS(rc))
1977	{
1978	uint32_t cbOp;
1979	DISCPUSTATE Cpu;
1980
1981	Cpu.mode = enmMode;
1982	rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
1983	Assert(VBOX_FAILURE(rc) \|\| Cpu.pCurInstr->opcode == OP_INVLPG);
1984	if (VBOX_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
1985	{
1986	Assert(cbOp == Cpu.opsize);
1987	rc = svmInterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
1988	if (VBOX_SUCCESS(rc))
1989	{
1990	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
1991	}
1992	return rc;
1993	}
1994	}
1995	}
1996	return VERR_EM_INTERPRETER;
1997	}
1998
1999
2000	/**
2001	* Invalidates a guest page
2002	*
2003	* @returns VBox status code.
2004	* @param pVM The VM to operate on.
2005	* @param GCVirt Page to invalidate
2006	*/
2007	HWACCMR0DECL(int) SVMR0InvalidatePage(PVM pVM, RTGCPTR GCVirt)
2008	{
2009	bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB \| pVM->hwaccm.s.svm.fForceTLBFlush;
2010
2011	/* Skip it if a TLB flush is already pending. */
2012	if (!fFlushPending)
2013	{
2014	SVM_VMCB *pVMCB;
2015
2016	Log2(("SVMR0InvalidatePage %VGv\n", GCVirt));
2017	AssertReturn(pVM, VERR_INVALID_PARAMETER);
2018	Assert(pVM->hwaccm.s.svm.fSupported);
2019
2020	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
2021	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2022
2023	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageManual);
2024	SVMInvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2025	}
2026	return VINF_SUCCESS;
2027	}
2028
2029
2030	/**
2031	* Invalidates a guest page by physical address
2032	*
2033	* NOTE: Assumes the current instruction references this physical page though a virtual address!!
2034	*
2035	* @returns VBox status code.
2036	* @param pVM The VM to operate on.
2037	* @param GCPhys Page to invalidate
2038	*/
2039	HWACCMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys)
2040	{
2041	bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB \| pVM->hwaccm.s.svm.fForceTLBFlush;
2042
2043	Assert(pVM->hwaccm.s.fNestedPaging);
2044
2045	/* Skip it if a TLB flush is already pending. */
2046	if (!fFlushPending)
2047	{
2048	CPUMCTX *pCtx;
2049	int rc;
2050	SVM_VMCB *pVMCB;
2051
2052	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
2053	AssertRCReturn(rc, rc);
2054
2055	Log2(("SVMR0InvalidatePhysPage %VGp\n", GCPhys));
2056	AssertReturn(pVM, VERR_INVALID_PARAMETER);
2057	Assert(pVM->hwaccm.s.svm.fSupported);
2058
2059	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
2060	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2061
2062	/*
2063	* Only allow 32 & 64 bits code.
2064	*/
2065	DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid);
2066	if (enmMode != CPUMODE_16BIT)
2067	{
2068	RTGCPTR pbCode;
2069	int rc = SELMValidateAndConvertCSAddr(pVM, pCtx->eflags, pCtx->ss, pCtx->cs, &pCtx->csHid, (RTGCPTR)pCtx->rip, &pbCode);
2070	if (VBOX_SUCCESS(rc))
2071	{
2072	uint32_t cbOp;
2073	DISCPUSTATE Cpu;
2074	OP_PARAMVAL param1;
2075	RTGCPTR addr;
2076
2077	Cpu.mode = enmMode;
2078	rc = EMInterpretDisasOneEx(pVM, pbCode, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);
2079	AssertRCReturn(rc, rc);
2080	Assert(cbOp == Cpu.opsize);
2081
2082	int rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param1, &param1, PARAM_SOURCE);
2083	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2084
2085	switch(param1.type)
2086	{
2087	case PARMTYPE_IMMEDIATE:
2088	case PARMTYPE_ADDRESS:
2089	AssertReturn((param1.flags & (PARAM_VAL32\|PARAM_VAL64)), VERR_EM_INTERPRETER);
2090
2091	addr = param1.val.val64;
2092	break;
2093
2094	default:
2095	AssertFailed();
2096	return VERR_EM_INTERPRETER;
2097	}
2098
2099	/* Manually invalidate the page for the VM's TLB. */
2100	Log(("SVMR0InvalidatePhysPage Phys=%VGp Virt=%VGv ASID=%d\n", GCPhys, addr, pVMCB->ctrl.TLBCtrl.n.u32ASID));
2101	SVMInvlpgA(addr, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2102	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPhysPageManual);
2103
2104	return VINF_SUCCESS;
2105	}
2106	}
2107	AssertFailed();
2108	return VERR_EM_INTERPRETER;
2109	}
2110	return VINF_SUCCESS;
2111	}

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 10509

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