HWSVMR0.cpp@ 12091

Last change on this file since 12091 was 12091, checked in by vboxsync, 16 years ago
Debug register support updates
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1	/* $Id: HWSVMR0.cpp 12091 2008-09-04 12:58:23Z vboxsync $ */
2	/** @file
3	* HWACCM SVM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_svm.h>
32	#include <VBox/pgm.h>
33	#include <VBox/pdm.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <VBox/selm.h>
37	#include <VBox/iom.h>
38	#include <VBox/dis.h>
39	#include <VBox/dbgf.h>
40	#include <VBox/disopcode.h>
41	#include <iprt/param.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm.h>
44	#include <iprt/cpuset.h>
45	#include <iprt/mp.h>
46	#include "HWSVMR0.h"
47
48	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
49
50	/**
51	* Sets up and activates AMD-V on the current CPU
52	*
53	* @returns VBox status code.
54	* @param pCpu CPU info struct
55	* @param pVM The VM to operate on.
56	* @param pvPageCpu Pointer to the global cpu page
57	* @param pPageCpuPhys Physical address of the global cpu page
58	*/
59	HWACCMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
60	{
61	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
62	AssertReturn(pVM, VERR_INVALID_PARAMETER);
63	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
64
65	/* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
66
67	#ifdef LOG_ENABLED
68	SUPR0Printf("SVMR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
69	#endif
70
71	/* Turn on AMD-V in the EFER MSR. */
72	uint64_t val = ASMRdMsr(MSR_K6_EFER);
73	if (!(val & MSR_K6_EFER_SVME))
74	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
75
76	/* Write the physical page address where the CPU will store the host state while executing the VM. */
77	ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
78
79	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
80	pCpu->cTLBFlushes = 0;
81	return VINF_SUCCESS;
82	}
83
84	/**
85	* Deactivates AMD-V on the current CPU
86	*
87	* @returns VBox status code.
88	* @param pCpu CPU info struct
89	* @param pvPageCpu Pointer to the global cpu page
90	* @param pPageCpuPhys Physical address of the global cpu page
91	*/
92	HWACCMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
93	{
94	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
95	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
96
97	#ifdef LOG_ENABLED
98	SUPR0Printf("SVMR0DisableCpu cpu %d\n", pCpu->idCpu);
99	#endif
100
101	/* Turn off AMD-V in the EFER MSR. */
102	uint64_t val = ASMRdMsr(MSR_K6_EFER);
103	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
104
105	/* Invalidate host state physical address. */
106	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
107	pCpu->uCurrentASID = 0;
108
109	return VINF_SUCCESS;
110	}
111
112	/**
113	* Does Ring-0 per VM AMD-V init.
114	*
115	* @returns VBox status code.
116	* @param pVM The VM to operate on.
117	*/
118	HWACCMR0DECL(int) SVMR0InitVM(PVM pVM)
119	{
120	int rc;
121
122	pVM->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
123	pVM->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
124	pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
125	pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
126
127
128	/* Allocate one page for the VM control block (VMCB). */
129	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
130	if (RT_FAILURE(rc))
131	return rc;
132
133	pVM->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCB);
134	pVM->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCB, 0);
135	ASMMemZeroPage(pVM->hwaccm.s.svm.pVMCB);
136
137	/* Allocate one page for the host context */
138	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
139	if (RT_FAILURE(rc))
140	return rc;
141
142	pVM->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCBHost);
143	pVM->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCBHost, 0);
144	ASMMemZeroPage(pVM->hwaccm.s.svm.pVMCBHost);
145
146	/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
147	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
148	if (RT_FAILURE(rc))
149	return rc;
150
151	pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
152	pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
153	/* Set all bits to intercept all IO accesses. */
154	ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
155
156	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
157	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
158	if (RT_FAILURE(rc))
159	return rc;
160
161	pVM->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
162	pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
163	/* Set all bits to intercept all MSR accesses. */
164	ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
165
166	/* Erratum 170 which requires a forced TLB flush for each world switch:
167	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
168	*
169	* All BH-G1/2 and DH-G1/2 models include a fix:
170	* Athlon X2: 0x6b 1/2
171	* 0x68 1/2
172	* Athlon 64: 0x7f 1
173	* 0x6f 2
174	* Sempron: 0x7f 1/2
175	* 0x6f 2
176	* 0x6c 2
177	* 0x7c 2
178	* Turion 64: 0x68 2
179	*
180	*/
181	uint32_t u32Dummy;
182	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
183	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
184	u32BaseFamily= (u32Version >> 8) & 0xf;
185	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
186	u32Model = ((u32Version >> 4) & 0xf);
187	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
188	u32Stepping = u32Version & 0xf;
189	if ( u32Family == 0xf
190	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
191	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
192	{
193	Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
194	pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
195	}
196
197	/* Invalidate the last cpu we were running on. */
198	pVM->hwaccm.s.svm.idLastCpu = NIL_RTCPUID;
199
200	/* we'll aways increment this the first time (host uses ASID 0) */
201	pVM->hwaccm.s.svm.uCurrentASID = 0;
202	return VINF_SUCCESS;
203	}
204
205	/**
206	* Does Ring-0 per VM AMD-V termination.
207	*
208	* @returns VBox status code.
209	* @param pVM The VM to operate on.
210	*/
211	HWACCMR0DECL(int) SVMR0TermVM(PVM pVM)
212	{
213	if (pVM->hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)
214	{
215	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCB, false);
216	pVM->hwaccm.s.svm.pVMCB = 0;
217	pVM->hwaccm.s.svm.pVMCBPhys = 0;
218	pVM->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
219	}
220	if (pVM->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ)
221	{
222	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCBHost, false);
223	pVM->hwaccm.s.svm.pVMCBHost = 0;
224	pVM->hwaccm.s.svm.pVMCBHostPhys = 0;
225	pVM->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
226	}
227	if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)
228	{
229	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
230	pVM->hwaccm.s.svm.pIOBitmap = 0;
231	pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
232	pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
233	}
234	if (pVM->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
235	{
236	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
237	pVM->hwaccm.s.svm.pMSRBitmap = 0;
238	pVM->hwaccm.s.svm.pMSRBitmapPhys = 0;
239	pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
240	}
241	return VINF_SUCCESS;
242	}
243
244	/**
245	* Sets up AMD-V for the specified VM
246	*
247	* @returns VBox status code.
248	* @param pVM The VM to operate on.
249	*/
250	HWACCMR0DECL(int) SVMR0SetupVM(PVM pVM)
251	{
252	int rc = VINF_SUCCESS;
253	SVM_VMCB *pVMCB;
254
255	AssertReturn(pVM, VERR_INVALID_PARAMETER);
256
257	Assert(pVM->hwaccm.s.svm.fSupported);
258
259	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
260	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
261
262	/* Program the control fields. Most of them never have to be changed again. */
263	/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
264	/** @note CR0 & CR4 can be safely read when guest and shadow copies are identical. */
265	if (!pVM->hwaccm.s.fNestedPaging)
266	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
267	else
268	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
269
270	/*
271	* CR0/3/4 writes must be intercepted for obvious reasons.
272	*/
273	if (!pVM->hwaccm.s.fNestedPaging)
274	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
275	else
276	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4) \| RT_BIT(8);
277
278	/* Intercept all DRx reads and writes. */
279	pVMCB->ctrl.u16InterceptRdDRx = RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7);
280	pVMCB->ctrl.u16InterceptWrDRx = RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7);
281
282	/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
283	* All breakpoints are automatically cleared when the VM exits.
284	*/
285
286	pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
287	#ifndef DEBUG
288	if (pVM->hwaccm.s.fNestedPaging)
289	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
290	#endif
291
292	pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
293	\| SVM_CTRL1_INTERCEPT_VINTR
294	\| SVM_CTRL1_INTERCEPT_NMI
295	\| SVM_CTRL1_INTERCEPT_SMI
296	\| SVM_CTRL1_INTERCEPT_INIT
297	\| SVM_CTRL1_INTERCEPT_RDPMC
298	\| SVM_CTRL1_INTERCEPT_CPUID
299	\| SVM_CTRL1_INTERCEPT_RSM
300	\| SVM_CTRL1_INTERCEPT_HLT
301	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
302	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
303	\| SVM_CTRL1_INTERCEPT_INVLPG
304	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
305	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH
306	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
307	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
308	;
309	/* With nested paging we don't care about invlpg anymore. */
310	if (pVM->hwaccm.s.fNestedPaging)
311	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
312
313	pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
314	\| SVM_CTRL2_INTERCEPT_VMMCALL
315	\| SVM_CTRL2_INTERCEPT_VMLOAD
316	\| SVM_CTRL2_INTERCEPT_VMSAVE
317	\| SVM_CTRL2_INTERCEPT_STGI
318	\| SVM_CTRL2_INTERCEPT_CLGI
319	\| SVM_CTRL2_INTERCEPT_SKINIT
320	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
321	\| SVM_CTRL2_INTERCEPT_WBINVD
322	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
323	;
324	Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
325	Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
326	Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
327
328	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
329	pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
330	/* Ignore the priority in the TPR; just deliver it when we tell it to. */
331	pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
332
333	/* Set IO and MSR bitmap addresses. */
334	pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
335	pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
336
337	/* No LBR virtualization. */
338	pVMCB->ctrl.u64LBRVirt = 0;
339
340	/** The ASID must start at 1; the host uses 0. */
341	pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
342
343	/** Setup the PAT msr (nested paging only) */
344	pVMCB->guest.u64GPAT = 0x0007040600070406ULL;
345	return rc;
346	}
347
348
349	/**
350	* Injects an event (trap or external interrupt)
351	*
352	* @param pVM The VM to operate on.
353	* @param pVMCB SVM control block
354	* @param pCtx CPU Context
355	* @param pIntInfo SVM interrupt info
356	*/
357	inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx, SVM_EVENT* pEvent)
358	{
359	#ifdef VBOX_STRICT
360	if (pEvent->n.u8Vector == 0xE)
361	Log(("SVM: Inject int %d at %VGv error code=%02x CR2=%VGv intInfo=%08x\n", pEvent->n.u8Vector, pCtx->rip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
362	else
363	if (pEvent->n.u8Vector < 0x20)
364	Log(("SVM: Inject int %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->rip, pEvent->n.u32ErrorCode));
365	else
366	{
367	Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->rip));
368	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
369	Assert(pCtx->eflags.u32 & X86_EFL_IF);
370	}
371	#endif
372
373	/* Set event injection state. */
374	pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
375	}
376
377
378	/**
379	* Checks for pending guest interrupts and injects them
380	*
381	* @returns VBox status code.
382	* @param pVM The VM to operate on.
383	* @param pVMCB SVM control block
384	* @param pCtx CPU Context
385	*/
386	static int SVMR0CheckPendingInterrupt(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx)
387	{
388	int rc;
389
390	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
391	if (pVM->hwaccm.s.Event.fPending)
392	{
393	SVM_EVENT Event;
394
395	Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip));
396	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
397	Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
398	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
399
400	pVM->hwaccm.s.Event.fPending = false;
401	return VINF_SUCCESS;
402	}
403
404	/* When external interrupts are pending, we should exit the VM when IF is set. */
405	if ( !TRPMHasTrap(pVM)
406	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
407	{
408	if ( !(pCtx->eflags.u32 & X86_EFL_IF)
409	\|\| VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
410	{
411	if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
412	{
413	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
414	LogFlow(("Enable irq window exit!\n"));
415	else
416	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", pCtx->rip));
417
418	/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
419	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
420	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
421	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
422	}
423	}
424	else
425	{
426	uint8_t u8Interrupt;
427
428	rc = PDMGetInterrupt(pVM, &u8Interrupt);
429	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
430	if (VBOX_SUCCESS(rc))
431	{
432	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
433	AssertRC(rc);
434	}
435	else
436	{
437	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
438	Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)));
439	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
440	/* Just continue */
441	}
442	}
443	}
444
445	#ifdef VBOX_STRICT
446	if (TRPMHasTrap(pVM))
447	{
448	uint8_t u8Vector;
449	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
450	AssertRC(rc);
451	}
452	#endif
453
454	if ( pCtx->eflags.u32 & X86_EFL_IF
455	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
456	&& TRPMHasTrap(pVM)
457	)
458	{
459	uint8_t u8Vector;
460	int rc;
461	TRPMEVENT enmType;
462	SVM_EVENT Event;
463	RTGCUINT u32ErrorCode;
464
465	Event.au64[0] = 0;
466
467	/* If a new event is pending, then dispatch it now. */
468	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &u32ErrorCode, 0);
469	AssertRC(rc);
470	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
471	Assert(enmType != TRPM_SOFTWARE_INT);
472
473	/* Clear the pending trap. */
474	rc = TRPMResetTrap(pVM);
475	AssertRC(rc);
476
477	Event.n.u8Vector = u8Vector;
478	Event.n.u1Valid = 1;
479	Event.n.u32ErrorCode = u32ErrorCode;
480
481	if (enmType == TRPM_TRAP)
482	{
483	switch (u8Vector) {
484	case 8:
485	case 10:
486	case 11:
487	case 12:
488	case 13:
489	case 14:
490	case 17:
491	/* Valid error codes. */
492	Event.n.u1ErrorCodeValid = 1;
493	break;
494	default:
495	break;
496	}
497	if (u8Vector == X86_XCPT_NMI)
498	Event.n.u3Type = SVM_EVENT_NMI;
499	else
500	Event.n.u3Type = SVM_EVENT_EXCEPTION;
501	}
502	else
503	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
504
505	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
506	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
507	} /* if (interrupts can be dispatched) */
508
509	return VINF_SUCCESS;
510	}
511
512	/**
513	* Save the host state
514	*
515	* @returns VBox status code.
516	* @param pVM The VM to operate on.
517	*/
518	HWACCMR0DECL(int) SVMR0SaveHostState(PVM pVM)
519	{
520	/* Nothing to do here. */
521	return VINF_SUCCESS;
522	}
523
524	/**
525	* Loads the guest state
526	*
527	* NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
528	*
529	* @returns VBox status code.
530	* @param pVM The VM to operate on.
531	* @param pCtx Guest context
532	*/
533	HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
534	{
535	RTGCUINTPTR val;
536	SVM_VMCB *pVMCB;
537
538	if (pVM == NULL)
539	return VERR_INVALID_PARAMETER;
540
541	/* Setup AMD SVM. */
542	Assert(pVM->hwaccm.s.svm.fSupported);
543
544	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
545	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
546
547	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
548	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
549	{
550	SVM_WRITE_SELREG(CS, cs);
551	SVM_WRITE_SELREG(SS, ss);
552	SVM_WRITE_SELREG(DS, ds);
553	SVM_WRITE_SELREG(ES, es);
554	SVM_WRITE_SELREG(FS, fs);
555	SVM_WRITE_SELREG(GS, gs);
556	}
557
558	/* Guest CPU context: LDTR. */
559	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
560	{
561	SVM_WRITE_SELREG(LDTR, ldtr);
562	}
563
564	/* Guest CPU context: TR. */
565	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
566	{
567	SVM_WRITE_SELREG(TR, tr);
568	}
569
570	/* Guest CPU context: GDTR. */
571	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
572	{
573	pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
574	pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
575	}
576
577	/* Guest CPU context: IDTR. */
578	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
579	{
580	pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
581	pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
582	}
583
584	/*
585	* Sysenter MSRs (unconditional)
586	*/
587	pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
588	pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
589	pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
590
591	/* Control registers */
592	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
593	{
594	val = pCtx->cr0;
595	if (!CPUMIsGuestFPUStateActive(pVM))
596	{
597	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
598	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
599	}
600	else
601	{
602	/** @todo check if we support the old style mess correctly. */
603	if (!(val & X86_CR0_NE))
604	{
605	Log(("Forcing X86_CR0_NE!!!\n"));
606
607	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
608	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
609	{
610	pVMCB->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_MF);
611	pVM->hwaccm.s.fFPUOldStyleOverride = true;
612	}
613	}
614	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
615	}
616	/* Always enable caching. */
617	val &= ~(X86_CR0_CD\|X86_CR0_NW);
618
619	/* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
620	/* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
621	if (!pVM->hwaccm.s.fNestedPaging)
622	{
623	val \|= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
624	val \|= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
625	}
626	pVMCB->guest.u64CR0 = val;
627	}
628	/* CR2 as well */
629	pVMCB->guest.u64CR2 = pCtx->cr2;
630
631	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
632	{
633	/* Save our shadow CR3 register. */
634	if (pVM->hwaccm.s.fNestedPaging)
635	{
636	pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVM, PGMGetHostMode(pVM));
637	Assert(pVMCB->ctrl.u64NestedPagingCR3);
638	pVMCB->guest.u64CR3 = pCtx->cr3;
639	}
640	else
641	{
642	pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
643	Assert(pVMCB->guest.u64CR3);
644	}
645	}
646
647	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
648	{
649	val = pCtx->cr4;
650	if (!pVM->hwaccm.s.fNestedPaging)
651	{
652	switch(pVM->hwaccm.s.enmShadowMode)
653	{
654	case PGMMODE_REAL:
655	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
656	AssertFailed();
657	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
658
659	case PGMMODE_32_BIT: /* 32-bit paging. */
660	break;
661
662	case PGMMODE_PAE: /* PAE paging. */
663	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
664	/** @todo use normal 32 bits paging */
665	val \|= X86_CR4_PAE;
666	break;
667
668	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
669	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
670	#ifdef VBOX_ENABLE_64_BITS_GUESTS
671	break;
672	#else
673	AssertFailed();
674	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
675	#endif
676
677	default: /* shut up gcc */
678	AssertFailed();
679	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
680	}
681	}
682	pVMCB->guest.u64CR4 = val;
683	}
684
685	/* Debug registers. */
686	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
687	{
688	val = pCtx->dr7;
689	val &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
690	val \|= 0x400; /* must be one */
691	#ifndef VBOX_WITH_DEBUG_REGISTER_SUPPORT
692	val = 0x400;
693	#endif
694	pVMCB->guest.u64DR7 = val;
695
696	pVMCB->guest.u64DR6 = pCtx->dr6;
697	}
698
699	/* EIP, ESP and EFLAGS */
700	pVMCB->guest.u64RIP = pCtx->rip;
701	pVMCB->guest.u64RSP = pCtx->rsp;
702	pVMCB->guest.u64RFlags = pCtx->eflags.u32;
703
704	/* Set CPL */
705	pVMCB->guest.u8CPL = pCtx->csHid.Attr.n.u2Dpl;
706
707	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
708	pVMCB->guest.u64RAX = pCtx->rax;
709
710	/* vmrun will fail without MSR_K6_EFER_SVME. */
711	pVMCB->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
712
713	/* 64 bits guest mode? */
714	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
715	{
716	#if !defined(VBOX_WITH_64_BITS_GUESTS) \|\| HC_ARCH_BITS != 64
717	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
718	#else
719	pVM->hwaccm.s.svm.pfnVMRun = SVMVMRun64;
720	#endif
721	/* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
722	pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
723	pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
724	}
725	else
726	{
727	/* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
728	pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
729
730	pVM->hwaccm.s.svm.pfnVMRun = SVMVMRun;
731	}
732
733	/** TSC offset. */
734	if (TMCpuTickCanUseRealTSC(pVM, &pVMCB->ctrl.u64TSCOffset))
735	{
736	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
737	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
738	}
739	else
740	{
741	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
742	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
743	}
744
745	/* Sync the various msrs for 64 bits mode. */
746	pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
747	pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
748	pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
749	pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
750	pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
751
752	#ifdef DEBUG
753	/* Intercept X86_XCPT_DB if stepping is enabled */
754	if (DBGFIsStepping(pVM))
755	pVMCB->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_DB);
756	else
757	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_DB);
758	#endif
759
760	/* Done. */
761	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
762
763	return VINF_SUCCESS;
764	}
765
766
767	/**
768	* Runs guest code in an SVM VM.
769	*
770	* @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
771	*
772	* @returns VBox status code.
773	* @param pVM The VM to operate on.
774	* @param pCtx Guest context
775	*/
776	HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
777	{
778	int rc = VINF_SUCCESS;
779	uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
780	SVM_VMCB *pVMCB;
781	bool fGuestStateSynced = false;
782	bool fSyncTPR = false;
783	unsigned cResume = 0;
784	uint8_t u8LastVTPR;
785	PHWACCM_CPUINFO pCpu = 0;
786	#ifdef VBOX_STRICT
787	RTCPUID idCpuCheck;
788	#endif
789
790	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
791
792	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
793	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
794
795	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
796	*/
797	ResumeExecution:
798	/* Safety precaution; looping for too long here can have a very bad effect on the host */
799	if (++cResume > HWACCM_MAX_RESUME_LOOPS)
800	{
801	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
802	rc = VINF_EM_RAW_INTERRUPT;
803	goto end;
804	}
805
806	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
807	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
808	{
809	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
810	if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
811	{
812	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
813	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
814	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
815	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
816	*/
817	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
818	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
819	pVMCB->ctrl.u64IntShadow = 0;
820	}
821	}
822	else
823	{
824	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
825	pVMCB->ctrl.u64IntShadow = 0;
826	}
827
828	/* Check for pending actions that force us to go back to ring 3. */
829	#ifdef DEBUG
830	/* Intercept X86_XCPT_DB if stepping is enabled */
831	if (!DBGFIsStepping(pVM))
832	#endif
833	{
834	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
835	{
836	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
837	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
838	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
839	rc = VINF_EM_RAW_TO_R3;
840	goto end;
841	}
842	}
843
844	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
845	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
846	{
847	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
848	rc = VINF_EM_PENDING_REQUEST;
849	goto end;
850	}
851
852	/* When external interrupts are pending, we should exit the VM when IF is set. */
853	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
854	rc = SVMR0CheckPendingInterrupt(pVM, pVMCB, pCtx);
855	if (VBOX_FAILURE(rc))
856	{
857	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
858	goto end;
859	}
860
861	/* TPR caching using CR8 is only available in 64 bits mode */
862	/* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
863	/* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! */
864	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
865	{
866	bool fPending;
867
868	/* TPR caching in CR8 */
869	int rc = PDMApicGetTPR(pVM, &u8LastVTPR, &fPending);
870	AssertRC(rc);
871	pVMCB->ctrl.IntCtrl.n.u8VTPR = u8LastVTPR;
872
873	if (fPending)
874	{
875	/* A TPR change could activate a pending interrupt, so catch cr8 writes. */
876	pVMCB->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
877	}
878	else
879	/* No interrupts are pending, so we don't need to be explicitely notified.
880	* There are enough world switches for detecting pending interrupts.
881	*/
882	pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
883
884	fSyncTPR = !fPending;
885	}
886
887	/* All done! Let's start VM execution. */
888	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
889
890	/* Enable nested paging if necessary (disabled each time after #VMEXIT). */
891	pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
892
893	#ifdef LOG_ENABLED
894	pCpu = HWACCMR0GetCurrentCpu();
895	if ( pVM->hwaccm.s.svm.idLastCpu != pCpu->idCpu
896	\|\| pVM->hwaccm.s.svm.cTLBFlushes != pCpu->cTLBFlushes)
897	{
898	if (pVM->hwaccm.s.svm.idLastCpu != pCpu->idCpu)
899	Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVM->hwaccm.s.svm.idLastCpu, pCpu->idCpu));
900	else
901	Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVM->hwaccm.s.svm.cTLBFlushes, pCpu->cTLBFlushes));
902	}
903	if (pCpu->fFlushTLB)
904	Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
905	#endif
906
907	/*
908	* NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
909	* (until the actual world switch)
910	*/
911
912	#ifdef VBOX_STRICT
913	idCpuCheck = RTMpCpuId();
914	#endif
915
916	/* Load the guest state; must be here as it sets up the shadow cr0 for lazy fpu syncing! */
917	rc = SVMR0LoadGuestState(pVM, pCtx);
918	if (rc != VINF_SUCCESS)
919	{
920	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
921	goto end;
922	}
923	fGuestStateSynced = true;
924
925	pCpu = HWACCMR0GetCurrentCpu();
926	/* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
927	/* Note that this can happen both for start and resume due to long jumps back to ring 3. */
928	if ( pVM->hwaccm.s.svm.idLastCpu != pCpu->idCpu
929	/* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
930	\|\| pVM->hwaccm.s.svm.cTLBFlushes != pCpu->cTLBFlushes)
931	{
932	/* Force a TLB flush on VM entry. */
933	pVM->hwaccm.s.svm.fForceTLBFlush = true;
934	}
935	else
936	Assert(!pCpu->fFlushTLB \|\| pVM->hwaccm.s.svm.fAlwaysFlushTLB);
937
938	pVM->hwaccm.s.svm.idLastCpu = pCpu->idCpu;
939
940	/* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
941	if ( pVM->hwaccm.s.svm.fForceTLBFlush
942	&& !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
943	{
944	if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.svm.u32MaxASID
945	\|\| pCpu->fFlushTLB)
946	{
947	pCpu->fFlushTLB = false;
948	pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
949	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
950	pCpu->cTLBFlushes++;
951	}
952	else
953	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushASID);
954
955	pVM->hwaccm.s.svm.cTLBFlushes = pCpu->cTLBFlushes;
956	pVM->hwaccm.s.svm.uCurrentASID = pCpu->uCurrentASID;
957	}
958	else
959	{
960	Assert(!pCpu->fFlushTLB \|\| pVM->hwaccm.s.svm.fAlwaysFlushTLB);
961
962	/* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
963	if (!pCpu->uCurrentASID)
964	pVM->hwaccm.s.svm.uCurrentASID = pCpu->uCurrentASID = 1;
965
966	Assert(!pVM->hwaccm.s.svm.fAlwaysFlushTLB \|\| pVM->hwaccm.s.svm.fForceTLBFlush);
967	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVM->hwaccm.s.svm.fForceTLBFlush;
968	}
969	AssertMsg(pVM->hwaccm.s.svm.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVM->hwaccm.s.svm.cTLBFlushes, pCpu->cTLBFlushes));
970	AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.svm.u32MaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
971	AssertMsg(pVM->hwaccm.s.svm.uCurrentASID >= 1 && pVM->hwaccm.s.svm.uCurrentASID < pVM->hwaccm.s.svm.u32MaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVM->hwaccm.s.svm.uCurrentASID));
972	pVMCB->ctrl.TLBCtrl.n.u32ASID = pVM->hwaccm.s.svm.uCurrentASID;
973
974	#ifdef VBOX_WITH_STATISTICS
975	if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
976	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBWorldSwitch);
977	else
978	STAM_COUNTER_INC(&pVM->hwaccm.s.StatNoFlushTLBWorldSwitch);
979	#endif
980
981	/* In case we execute a goto ResumeExecution later on. */
982	pVM->hwaccm.s.svm.fResumeVM = true;
983	pVM->hwaccm.s.svm.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
984
985	Assert(sizeof(pVM->hwaccm.s.svm.pVMCBPhys) == 8);
986	Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
987	\| SVM_CTRL2_INTERCEPT_VMMCALL
988	\| SVM_CTRL2_INTERCEPT_VMLOAD
989	\| SVM_CTRL2_INTERCEPT_VMSAVE
990	\| SVM_CTRL2_INTERCEPT_STGI
991	\| SVM_CTRL2_INTERCEPT_CLGI
992	\| SVM_CTRL2_INTERCEPT_SKINIT
993	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
994	\| SVM_CTRL2_INTERCEPT_WBINVD
995	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
996	));
997	Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
998	Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
999	Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
1000	Assert(pVMCB->ctrl.u64LBRVirt == 0);
1001
1002	#ifdef VBOX_STRICT
1003	Assert(idCpuCheck == RTMpCpuId());
1004	#endif
1005	pVM->hwaccm.s.svm.pfnVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);
1006	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
1007
1008	/**
1009	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1010	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1011	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1012	*/
1013
1014	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
1015
1016	/* Reason for the VM exit */
1017	exitCode = pVMCB->ctrl.u64ExitCode;
1018
1019	if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
1020	{
1021	HWACCMDumpRegs(pVM, pCtx);
1022	#ifdef DEBUG
1023	Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
1024	Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
1025	Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
1026	Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
1027	Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
1028	Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
1029	Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
1030	Log(("ctrl.u64IOPMPhysAddr %VX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
1031	Log(("ctrl.u64MSRPMPhysAddr %VX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
1032	Log(("ctrl.u64TSCOffset %VX64\n", pVMCB->ctrl.u64TSCOffset));
1033
1034	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
1035	Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
1036	Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
1037	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
1038
1039	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
1040	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
1041	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
1042	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
1043	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
1044	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
1045	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
1046	Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
1047	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
1048	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
1049
1050	Log(("ctrl.u64IntShadow %VX64\n", pVMCB->ctrl.u64IntShadow));
1051	Log(("ctrl.u64ExitCode %VX64\n", pVMCB->ctrl.u64ExitCode));
1052	Log(("ctrl.u64ExitInfo1 %VX64\n", pVMCB->ctrl.u64ExitInfo1));
1053	Log(("ctrl.u64ExitInfo2 %VX64\n", pVMCB->ctrl.u64ExitInfo2));
1054	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
1055	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
1056	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
1057	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
1058	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
1059	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
1060	Log(("ctrl.NestedPaging %VX64\n", pVMCB->ctrl.NestedPaging.au64));
1061	Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
1062	Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
1063	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
1064	Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
1065	Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
1066	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
1067
1068	Log(("ctrl.u64NestedPagingCR3 %VX64\n", pVMCB->ctrl.u64NestedPagingCR3));
1069	Log(("ctrl.u64LBRVirt %VX64\n", pVMCB->ctrl.u64LBRVirt));
1070
1071	Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
1072	Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1073	Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1074	Log(("guest.CS.u64Base %VX64\n", pVMCB->guest.CS.u64Base));
1075	Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1076	Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1077	Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1078	Log(("guest.DS.u64Base %VX64\n", pVMCB->guest.DS.u64Base));
1079	Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1080	Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1081	Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1082	Log(("guest.ES.u64Base %VX64\n", pVMCB->guest.ES.u64Base));
1083	Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1084	Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1085	Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1086	Log(("guest.FS.u64Base %VX64\n", pVMCB->guest.FS.u64Base));
1087	Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1088	Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1089	Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1090	Log(("guest.GS.u64Base %VX64\n", pVMCB->guest.GS.u64Base));
1091
1092	Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1093	Log(("guest.GDTR.u64Base %VX64\n", pVMCB->guest.GDTR.u64Base));
1094
1095	Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1096	Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1097	Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1098	Log(("guest.LDTR.u64Base %VX64\n", pVMCB->guest.LDTR.u64Base));
1099
1100	Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1101	Log(("guest.IDTR.u64Base %VX64\n", pVMCB->guest.IDTR.u64Base));
1102
1103	Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1104	Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1105	Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1106	Log(("guest.TR.u64Base %VX64\n", pVMCB->guest.TR.u64Base));
1107
1108	Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1109	Log(("guest.u64CR0 %VX64\n", pVMCB->guest.u64CR0));
1110	Log(("guest.u64CR2 %VX64\n", pVMCB->guest.u64CR2));
1111	Log(("guest.u64CR3 %VX64\n", pVMCB->guest.u64CR3));
1112	Log(("guest.u64CR4 %VX64\n", pVMCB->guest.u64CR4));
1113	Log(("guest.u64DR6 %VX64\n", pVMCB->guest.u64DR6));
1114	Log(("guest.u64DR7 %VX64\n", pVMCB->guest.u64DR7));
1115
1116	Log(("guest.u64RIP %VX64\n", pVMCB->guest.u64RIP));
1117	Log(("guest.u64RSP %VX64\n", pVMCB->guest.u64RSP));
1118	Log(("guest.u64RAX %VX64\n", pVMCB->guest.u64RAX));
1119	Log(("guest.u64RFlags %VX64\n", pVMCB->guest.u64RFlags));
1120
1121	Log(("guest.u64SysEnterCS %VX64\n", pVMCB->guest.u64SysEnterCS));
1122	Log(("guest.u64SysEnterEIP %VX64\n", pVMCB->guest.u64SysEnterEIP));
1123	Log(("guest.u64SysEnterESP %VX64\n", pVMCB->guest.u64SysEnterESP));
1124
1125	Log(("guest.u64EFER %VX64\n", pVMCB->guest.u64EFER));
1126	Log(("guest.u64STAR %VX64\n", pVMCB->guest.u64STAR));
1127	Log(("guest.u64LSTAR %VX64\n", pVMCB->guest.u64LSTAR));
1128	Log(("guest.u64CSTAR %VX64\n", pVMCB->guest.u64CSTAR));
1129	Log(("guest.u64SFMASK %VX64\n", pVMCB->guest.u64SFMASK));
1130	Log(("guest.u64KernelGSBase %VX64\n", pVMCB->guest.u64KernelGSBase));
1131	Log(("guest.u64GPAT %VX64\n", pVMCB->guest.u64GPAT));
1132	Log(("guest.u64DBGCTL %VX64\n", pVMCB->guest.u64DBGCTL));
1133	Log(("guest.u64BR_FROM %VX64\n", pVMCB->guest.u64BR_FROM));
1134	Log(("guest.u64BR_TO %VX64\n", pVMCB->guest.u64BR_TO));
1135	Log(("guest.u64LASTEXCPFROM %VX64\n", pVMCB->guest.u64LASTEXCPFROM));
1136	Log(("guest.u64LASTEXCPTO %VX64\n", pVMCB->guest.u64LASTEXCPTO));
1137
1138	#endif
1139	rc = VERR_SVM_UNABLE_TO_START_VM;
1140	goto end;
1141	}
1142
1143	/* Let's first sync back eip, esp, and eflags. */
1144	pCtx->rip = pVMCB->guest.u64RIP;
1145	pCtx->rsp = pVMCB->guest.u64RSP;
1146	pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1147	/* eax is saved/restore across the vmrun instruction */
1148	pCtx->rax = pVMCB->guest.u64RAX;
1149
1150	pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
1151
1152	/* Can be updated behind our back in the nested paging case. */
1153	pCtx->cr2 = pVMCB->guest.u64CR2;
1154
1155	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1156	SVM_READ_SELREG(SS, ss);
1157	SVM_READ_SELREG(CS, cs);
1158	SVM_READ_SELREG(DS, ds);
1159	SVM_READ_SELREG(ES, es);
1160	SVM_READ_SELREG(FS, fs);
1161	SVM_READ_SELREG(GS, gs);
1162
1163	/*
1164	* System MSRs
1165	*/
1166	pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1167	pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1168	pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1169
1170	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1171	SVM_READ_SELREG(LDTR, ldtr);
1172	SVM_READ_SELREG(TR, tr);
1173
1174	pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1175	pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1176
1177	pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1178	pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1179
1180	/* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1181	/* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1182	if ( pVM->hwaccm.s.fNestedPaging
1183	&& pCtx->cr3 != pVMCB->guest.u64CR3)
1184	{
1185	CPUMSetGuestCR3(pVM, pVMCB->guest.u64CR3);
1186	PGMUpdateCR3(pVM, pVMCB->guest.u64CR3);
1187	}
1188
1189	/** @note NOW IT'S SAFE FOR LOGGING! */
1190
1191	/* Take care of instruction fusing (sti, mov ss) (see 15.20.5 Interrupt Shadows) */
1192	if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1193	{
1194	Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->rip));
1195	EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1196	}
1197	else
1198	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1199
1200	Log2(("exitCode = %x\n", exitCode));
1201
1202	/* Sync back the debug registers. */
1203	pCtx->dr6 = pVMCB->guest.u64DR6;
1204	pCtx->dr7 = pVMCB->guest.u64DR7;
1205
1206	/* Check if an injected event was interrupted prematurely. */
1207	pVM->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1208	if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1209	&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1210	{
1211	Log(("Pending inject %VX64 at %VGv exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitCode));
1212
1213	#ifdef LOG_ENABLED
1214	SVM_EVENT Event;
1215	Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
1216
1217	if ( exitCode == SVM_EXIT_EXCEPTION_E
1218	&& Event.n.u8Vector == 0xE)
1219	{
1220	Log(("Double fault!\n"));
1221	}
1222	#endif
1223
1224	pVM->hwaccm.s.Event.fPending = true;
1225	/* Error code present? (redundant) */
1226	if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1227	{
1228	pVM->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1229	}
1230	else
1231	pVM->hwaccm.s.Event.errCode = 0;
1232	}
1233	#ifdef VBOX_WITH_STATISTICS
1234	if (exitCode == SVM_EXIT_NPF)
1235	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitReasonNPF);
1236	else
1237	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1238	#endif
1239
1240	if (fSyncTPR)
1241	{
1242	rc = PDMApicSetTPR(pVM, pVMCB->ctrl.IntCtrl.n.u8VTPR);
1243	AssertRC(rc);
1244	}
1245
1246	/* Deal with the reason of the VM-exit. */
1247	switch (exitCode)
1248	{
1249	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1250	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1251	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1252	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1253	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1254	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1255	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1256	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1257	{
1258	/* Pending trap. */
1259	SVM_EVENT Event;
1260	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1261
1262	Log2(("Hardware/software interrupt %d\n", vector));
1263	switch (vector)
1264	{
1265	#ifdef DEBUG
1266	case X86_XCPT_DB:
1267	rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), pVMCB->guest.u64DR6);
1268	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
1269	break;
1270	#endif
1271
1272	case X86_XCPT_NM:
1273	{
1274	Log(("#NM fault at %VGv\n", pCtx->rip));
1275
1276	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1277	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1278	rc = CPUMR0LoadGuestFPU(pVM, pCtx);
1279	if (rc == VINF_SUCCESS)
1280	{
1281	Assert(CPUMIsGuestFPUStateActive(pVM));
1282	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1283
1284	/* Continue execution. */
1285	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1286	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1287
1288	goto ResumeExecution;
1289	}
1290
1291	Log(("Forward #NM fault to the guest\n"));
1292	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1293
1294	Event.au64[0] = 0;
1295	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1296	Event.n.u1Valid = 1;
1297	Event.n.u8Vector = X86_XCPT_NM;
1298
1299	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1300	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1301	goto ResumeExecution;
1302	}
1303
1304	case X86_XCPT_PF: /* Page fault */
1305	{
1306	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1307	RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1308
1309	#ifdef DEBUG
1310	if (pVM->hwaccm.s.fNestedPaging)
1311	{ /* A genuine pagefault.
1312	* Forward the trap to the guest by injecting the exception and resuming execution.
1313	*/
1314	Log(("Guest page fault at %VGv cr2=%VGv error code %x rsp=%VGv\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
1315	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1316
1317	/* Now we must update CR2. */
1318	pCtx->cr2 = uFaultAddress;
1319
1320	Event.au64[0] = 0;
1321	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1322	Event.n.u1Valid = 1;
1323	Event.n.u8Vector = X86_XCPT_PF;
1324	Event.n.u1ErrorCodeValid = 1;
1325	Event.n.u32ErrorCode = errCode;
1326
1327	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1328
1329	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1330	goto ResumeExecution;
1331	}
1332	#endif
1333	Assert(!pVM->hwaccm.s.fNestedPaging);
1334
1335	Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, uFaultAddress, errCode));
1336	/* Exit qualification contains the linear address of the page fault. */
1337	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1338	TRPMSetErrorCode(pVM, errCode);
1339	TRPMSetFaultAddress(pVM, uFaultAddress);
1340
1341	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1342	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1343	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
1344	if (rc == VINF_SUCCESS)
1345	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1346	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, uFaultAddress, errCode));
1347	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1348
1349	TRPMResetTrap(pVM);
1350
1351	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1352	goto ResumeExecution;
1353	}
1354	else
1355	if (rc == VINF_EM_RAW_GUEST_TRAP)
1356	{ /* A genuine pagefault.
1357	* Forward the trap to the guest by injecting the exception and resuming execution.
1358	*/
1359	Log2(("Forward page fault to the guest\n"));
1360	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1361	/* The error code might have been changed. */
1362	errCode = TRPMGetErrorCode(pVM);
1363
1364	TRPMResetTrap(pVM);
1365
1366	/* Now we must update CR2. */
1367	pCtx->cr2 = uFaultAddress;
1368
1369	Event.au64[0] = 0;
1370	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1371	Event.n.u1Valid = 1;
1372	Event.n.u8Vector = X86_XCPT_PF;
1373	Event.n.u1ErrorCodeValid = 1;
1374	Event.n.u32ErrorCode = errCode;
1375
1376	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1377
1378	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1379	goto ResumeExecution;
1380	}
1381	#ifdef VBOX_STRICT
1382	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1383	LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
1384	#endif
1385	/* Need to go back to the recompiler to emulate the instruction. */
1386	TRPMResetTrap(pVM);
1387	break;
1388	}
1389
1390	case X86_XCPT_MF: /* Floating point exception. */
1391	{
1392	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1393	if (!(pCtx->cr0 & X86_CR0_NE))
1394	{
1395	/* old style FPU error reporting needs some extra work. */
1396	/** @todo don't fall back to the recompiler, but do it manually. */
1397	rc = VINF_EM_RAW_EMULATE_INSTR;
1398	break;
1399	}
1400	Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1401
1402	Event.au64[0] = 0;
1403	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1404	Event.n.u1Valid = 1;
1405	Event.n.u8Vector = X86_XCPT_MF;
1406
1407	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1408
1409	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1410	goto ResumeExecution;
1411	}
1412
1413	#ifdef VBOX_STRICT
1414	case X86_XCPT_GP: /* General protection failure exception.*/
1415	case X86_XCPT_UD: /* Unknown opcode exception. */
1416	case X86_XCPT_DE: /* Debug exception. */
1417	case X86_XCPT_SS: /* Stack segment exception. */
1418	case X86_XCPT_NP: /* Segment not present exception. */
1419	{
1420	Event.au64[0] = 0;
1421	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1422	Event.n.u1Valid = 1;
1423	Event.n.u8Vector = vector;
1424
1425	switch(vector)
1426	{
1427	case X86_XCPT_GP:
1428	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1429	Event.n.u1ErrorCodeValid = 1;
1430	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1431	break;
1432	case X86_XCPT_DE:
1433	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1434	break;
1435	case X86_XCPT_UD:
1436	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1437	break;
1438	case X86_XCPT_SS:
1439	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1440	Event.n.u1ErrorCodeValid = 1;
1441	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1442	break;
1443	case X86_XCPT_NP:
1444	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1445	Event.n.u1ErrorCodeValid = 1;
1446	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1447	break;
1448	}
1449	Log(("Trap %x at %VGv esi=%x\n", vector, pCtx->rip, pCtx->esi));
1450	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1451
1452	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1453	goto ResumeExecution;
1454	}
1455	#endif
1456	default:
1457	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1458	rc = VERR_EM_INTERNAL_ERROR;
1459	break;
1460
1461	} /* switch (vector) */
1462	break;
1463	}
1464
1465	case SVM_EXIT_NPF:
1466	{
1467	/* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1468	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1469	RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1470
1471	Assert(pVM->hwaccm.s.fNestedPaging);
1472	Log(("Nested page fault at %VGv cr2=%VGp error code %x\n", pCtx->rip, uFaultAddress, errCode));
1473	/* Exit qualification contains the linear address of the page fault. */
1474	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1475	TRPMSetErrorCode(pVM, errCode);
1476	TRPMSetFaultAddress(pVM, uFaultAddress);
1477
1478	/* Handle the pagefault trap for the nested shadow table. */
1479	rc = PGMR0Trap0eHandlerNestedPaging(pVM, PGMGetHostMode(pVM), errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1480	Log2(("PGMR0Trap0eHandlerNestedPaging %VGv returned %Vrc\n", pCtx->rip, rc));
1481	if (rc == VINF_SUCCESS)
1482	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1483	Log2(("Shadow page fault at %VGv cr2=%VGp error code %x\n", pCtx->rip, uFaultAddress, errCode));
1484	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1485
1486	TRPMResetTrap(pVM);
1487
1488	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1489	goto ResumeExecution;
1490	}
1491
1492	#ifdef VBOX_STRICT
1493	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1494	LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
1495	#endif
1496	/* Need to go back to the recompiler to emulate the instruction. */
1497	TRPMResetTrap(pVM);
1498	break;
1499	}
1500
1501	case SVM_EXIT_VINTR:
1502	/* A virtual interrupt is about to be delivered, which means IF=1. */
1503	Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1504	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1505	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1506	goto ResumeExecution;
1507
1508	case SVM_EXIT_FERR_FREEZE:
1509	case SVM_EXIT_INTR:
1510	case SVM_EXIT_NMI:
1511	case SVM_EXIT_SMI:
1512	case SVM_EXIT_INIT:
1513	/* External interrupt; leave to allow it to be dispatched again. */
1514	rc = VINF_EM_RAW_INTERRUPT;
1515	break;
1516
1517	case SVM_EXIT_WBINVD:
1518	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1519	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1520	/* Skip instruction and continue directly. */
1521	pCtx->rip += 2; /** @note hardcoded opcode size! */
1522	/* Continue execution.*/
1523	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1524	goto ResumeExecution;
1525
1526	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1527	{
1528	Log2(("SVM: Cpuid at %VGv for %x\n", pCtx->rip, pCtx->eax));
1529	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1530	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1531	if (rc == VINF_SUCCESS)
1532	{
1533	/* Update EIP and continue execution. */
1534	pCtx->rip += 2; /** @note hardcoded opcode size! */
1535	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1536	goto ResumeExecution;
1537	}
1538	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1539	rc = VINF_EM_RAW_EMULATE_INSTR;
1540	break;
1541	}
1542
1543	case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1544	{
1545	Log2(("SVM: Rdtsc\n"));
1546	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1547	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1548	if (rc == VINF_SUCCESS)
1549	{
1550	/* Update EIP and continue execution. */
1551	pCtx->rip += 2; /** @note hardcoded opcode size! */
1552	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1553	goto ResumeExecution;
1554	}
1555	AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1556	rc = VINF_EM_RAW_EMULATE_INSTR;
1557	break;
1558	}
1559
1560	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1561	{
1562	Log2(("SVM: invlpg\n"));
1563	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1564
1565	Assert(!pVM->hwaccm.s.fNestedPaging);
1566
1567	/* Truly a pita. Why can't SVM give the same information as VT-x? */
1568	rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1569	if (rc == VINF_SUCCESS)
1570	{
1571	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageInvlpg);
1572	goto ResumeExecution; /* eip already updated */
1573	}
1574	break;
1575	}
1576
1577	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1578	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1579	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1580	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1581	{
1582	uint32_t cbSize;
1583
1584	Log2(("SVM: %VGv mov cr%d, \n", pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
1585	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1586	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1587
1588	switch (exitCode - SVM_EXIT_WRITE_CR0)
1589	{
1590	case 0:
1591	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1592	break;
1593	case 2:
1594	break;
1595	case 3:
1596	Assert(!pVM->hwaccm.s.fNestedPaging);
1597	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1598	break;
1599	case 4:
1600	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1601	break;
1602	case 8:
1603	break;
1604	default:
1605	AssertFailed();
1606	}
1607	/* Check if a sync operation is pending. */
1608	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1609	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1610	{
1611	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1612	AssertRC(rc);
1613
1614	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBCRxChange);
1615
1616	/* Must be set by PGMSyncCR3 */
1617	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PROTECTED \|\| pVM->hwaccm.s.svm.fForceTLBFlush);
1618	}
1619	if (rc == VINF_SUCCESS)
1620	{
1621	/* EIP has been updated already. */
1622
1623	/* Only resume if successful. */
1624	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1625	goto ResumeExecution;
1626	}
1627	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1628	break;
1629	}
1630
1631	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1632	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1633	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1634	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1635	{
1636	uint32_t cbSize;
1637
1638	Log2(("SVM: %VGv mov x, cr%d\n", pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
1639	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1640	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1641	if (rc == VINF_SUCCESS)
1642	{
1643	/* EIP has been updated already. */
1644
1645	/* Only resume if successful. */
1646	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1647	goto ResumeExecution;
1648	}
1649	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1650	break;
1651	}
1652
1653	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1654	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1655	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1656	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1657	{
1658	uint32_t cbSize;
1659
1660	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
1661	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1662	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1663	if (rc == VINF_SUCCESS)
1664	{
1665	/* EIP has been updated already. */
1666	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_DEBUG;
1667
1668	/* Only resume if successful. */
1669	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1670	goto ResumeExecution;
1671	}
1672	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1673	break;
1674	}
1675
1676	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1677	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1678	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1679	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1680	{
1681	uint32_t cbSize;
1682
1683	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
1684	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1685	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1686	if (rc == VINF_SUCCESS)
1687	{
1688	/* EIP has been updated already. */
1689
1690	/* Only resume if successful. */
1691	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1692	goto ResumeExecution;
1693	}
1694	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1695	break;
1696	}
1697
1698	/* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1699	case SVM_EXIT_IOIO: /* I/O instruction. */
1700	{
1701	SVM_IOIO_EXIT IoExitInfo;
1702	uint32_t uIOSize, uAndVal;
1703
1704	IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1705
1706	/** @todo could use a lookup table here */
1707	if (IoExitInfo.n.u1OP8)
1708	{
1709	uIOSize = 1;
1710	uAndVal = 0xff;
1711	}
1712	else
1713	if (IoExitInfo.n.u1OP16)
1714	{
1715	uIOSize = 2;
1716	uAndVal = 0xffff;
1717	}
1718	else
1719	if (IoExitInfo.n.u1OP32)
1720	{
1721	uIOSize = 4;
1722	uAndVal = 0xffffffff;
1723	}
1724	else
1725	{
1726	AssertFailed(); /* should be fatal. */
1727	rc = VINF_EM_RAW_EMULATE_INSTR;
1728	break;
1729	}
1730
1731	if (IoExitInfo.n.u1STR)
1732	{
1733	/* ins/outs */
1734	uint32_t prefix = 0;
1735	if (IoExitInfo.n.u1REP)
1736	prefix \|= PREFIX_REP;
1737
1738	if (IoExitInfo.n.u1Type == 0)
1739	{
1740	Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1741	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1742	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1743	}
1744	else
1745	{
1746	Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1747	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1748	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1749	}
1750	}
1751	else
1752	{
1753	/* normal in/out */
1754	Assert(!IoExitInfo.n.u1REP);
1755
1756	if (IoExitInfo.n.u1Type == 0)
1757	{
1758	Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1759	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1760	rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1761	}
1762	else
1763	{
1764	uint32_t u32Val = 0;
1765
1766	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1767	rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1768	if (IOM_SUCCESS(rc))
1769	{
1770	/* Write back to the EAX register. */
1771	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1772	Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1773	}
1774	}
1775	}
1776	/*
1777	* Handled the I/O return codes.
1778	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1779	*/
1780	if (IOM_SUCCESS(rc))
1781	{
1782	/* Update EIP and continue execution. */
1783	pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1784	if (RT_LIKELY(rc == VINF_SUCCESS))
1785	{
1786	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1787	goto ResumeExecution;
1788	}
1789	Log2(("EM status from IO at %VGv %x size %d: %Vrc\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
1790	break;
1791	}
1792
1793	#ifdef VBOX_STRICT
1794	if (rc == VINF_IOM_HC_IOPORT_READ)
1795	Assert(IoExitInfo.n.u1Type != 0);
1796	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1797	Assert(IoExitInfo.n.u1Type == 0);
1798	else
1799	AssertMsg(VBOX_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1800	#endif
1801	Log2(("Failed IO at %VGv %x size %d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1802	break;
1803	}
1804
1805	case SVM_EXIT_HLT:
1806	/** Check if external interrupts are pending; if so, don't switch back. */
1807	pCtx->rip++; /* skip hlt */
1808	if ( pCtx->eflags.Bits.u1IF
1809	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1810	goto ResumeExecution;
1811
1812	rc = VINF_EM_HALT;
1813	break;
1814
1815	case SVM_EXIT_RSM:
1816	case SVM_EXIT_INVLPGA:
1817	case SVM_EXIT_VMRUN:
1818	case SVM_EXIT_VMMCALL:
1819	case SVM_EXIT_VMLOAD:
1820	case SVM_EXIT_VMSAVE:
1821	case SVM_EXIT_STGI:
1822	case SVM_EXIT_CLGI:
1823	case SVM_EXIT_SKINIT:
1824	case SVM_EXIT_RDTSCP:
1825	{
1826	/* Unsupported instructions. */
1827	SVM_EVENT Event;
1828
1829	Event.au64[0] = 0;
1830	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1831	Event.n.u1Valid = 1;
1832	Event.n.u8Vector = X86_XCPT_UD;
1833
1834	Log(("Forced #UD trap at %VGv\n", pCtx->rip));
1835	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1836
1837	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1838	goto ResumeExecution;
1839	}
1840
1841	/* Emulate in ring 3. */
1842	case SVM_EXIT_MSR:
1843	{
1844	uint32_t cbSize;
1845
1846	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
1847	Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
1848	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1849	if (rc == VINF_SUCCESS)
1850	{
1851	/* EIP has been updated already. */
1852
1853	/* Only resume if successful. */
1854	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1855	goto ResumeExecution;
1856	}
1857	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Vrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
1858	break;
1859	}
1860
1861	case SVM_EXIT_MONITOR:
1862	case SVM_EXIT_RDPMC:
1863	case SVM_EXIT_PAUSE:
1864	case SVM_EXIT_MWAIT_UNCOND:
1865	case SVM_EXIT_MWAIT_ARMED:
1866	case SVM_EXIT_TASK_SWITCH: /* can change CR3; emulate */
1867	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1868	break;
1869
1870	case SVM_EXIT_SHUTDOWN:
1871	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1872	break;
1873
1874	case SVM_EXIT_IDTR_READ:
1875	case SVM_EXIT_GDTR_READ:
1876	case SVM_EXIT_LDTR_READ:
1877	case SVM_EXIT_TR_READ:
1878	case SVM_EXIT_IDTR_WRITE:
1879	case SVM_EXIT_GDTR_WRITE:
1880	case SVM_EXIT_LDTR_WRITE:
1881	case SVM_EXIT_TR_WRITE:
1882	case SVM_EXIT_CR0_SEL_WRITE:
1883	default:
1884	/* Unexpected exit codes. */
1885	rc = VERR_EM_INTERNAL_ERROR;
1886	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
1887	break;
1888	}
1889
1890	end:
1891
1892	/* Signal changes for the recompiler. */
1893	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
1894
1895	/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
1896	if (exitCode == SVM_EXIT_INTR)
1897	{
1898	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1899	/* On the next entry we'll only sync the host context. */
1900	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
1901	}
1902	else
1903	{
1904	/* On the next entry we'll sync everything. */
1905	/** @todo we can do better than this */
1906	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
1907	}
1908
1909	/* translate into a less severe return code */
1910	if (rc == VERR_EM_INTERPRETER)
1911	rc = VINF_EM_RAW_EMULATE_INSTR;
1912
1913	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1914	return rc;
1915	}
1916
1917	/**
1918	* Enters the AMD-V session
1919	*
1920	* @returns VBox status code.
1921	* @param pVM The VM to operate on.
1922	* @param pCpu CPU info struct
1923	*/
1924	HWACCMR0DECL(int) SVMR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
1925	{
1926	Assert(pVM->hwaccm.s.svm.fSupported);
1927
1928	LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVM->hwaccm.s.svm.idLastCpu, pVM->hwaccm.s.svm.uCurrentASID));
1929	pVM->hwaccm.s.svm.fResumeVM = false;
1930
1931	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
1932	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_LDTR;
1933
1934	return VINF_SUCCESS;
1935	}
1936
1937
1938	/**
1939	* Leaves the AMD-V session
1940	*
1941	* @returns VBox status code.
1942	* @param pVM The VM to operate on.
1943	*/
1944	HWACCMR0DECL(int) SVMR0Leave(PVM pVM)
1945	{
1946	Assert(pVM->hwaccm.s.svm.fSupported);
1947	return VINF_SUCCESS;
1948	}
1949
1950
1951	static int svmInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1952	{
1953	OP_PARAMVAL param1;
1954	RTGCPTR addr;
1955
1956	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1957	if(VBOX_FAILURE(rc))
1958	return VERR_EM_INTERPRETER;
1959
1960	switch(param1.type)
1961	{
1962	case PARMTYPE_IMMEDIATE:
1963	case PARMTYPE_ADDRESS:
1964	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1965	return VERR_EM_INTERPRETER;
1966	addr = param1.val.val64;
1967	break;
1968
1969	default:
1970	return VERR_EM_INTERPRETER;
1971	}
1972
1973	/** @todo is addr always a flat linear address or ds based
1974	* (in absence of segment override prefixes)????
1975	*/
1976	rc = PGMInvalidatePage(pVM, addr);
1977	if (VBOX_SUCCESS(rc))
1978	{
1979	/* Manually invalidate the page for the VM's TLB. */
1980	Log(("SVMInvlpgA %VGv ASID=%d\n", addr, uASID));
1981	SVMInvlpgA(addr, uASID);
1982	return VINF_SUCCESS;
1983	}
1984	Assert(rc == VERR_REM_FLUSHED_PAGES_OVERFLOW);
1985	return rc;
1986	}
1987
1988	/**
1989	* Interprets INVLPG
1990	*
1991	* @returns VBox status code.
1992	* @retval VINF_* Scheduling instructions.
1993	* @retval VERR_EM_INTERPRETER Something we can't cope with.
1994	* @retval VERR_* Fatal errors.
1995	*
1996	* @param pVM The VM handle.
1997	* @param pRegFrame The register frame.
1998	* @param ASID Tagged TLB id for the guest
1999	*
2000	* Updates the EIP if an instruction was executed successfully.
2001	*/
2002	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2003	{
2004	/*
2005	* Only allow 32 & 64 bits code.
2006	*/
2007	DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
2008	if (enmMode != CPUMODE_16BIT)
2009	{
2010	RTGCPTR pbCode;
2011	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
2012	if (VBOX_SUCCESS(rc))
2013	{
2014	uint32_t cbOp;
2015	DISCPUSTATE Cpu;
2016
2017	Cpu.mode = enmMode;
2018	rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
2019	Assert(VBOX_FAILURE(rc) \|\| Cpu.pCurInstr->opcode == OP_INVLPG);
2020	if (VBOX_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
2021	{
2022	Assert(cbOp == Cpu.opsize);
2023	rc = svmInterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
2024	if (VBOX_SUCCESS(rc))
2025	{
2026	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
2027	}
2028	return rc;
2029	}
2030	}
2031	}
2032	return VERR_EM_INTERPRETER;
2033	}
2034
2035
2036	/**
2037	* Invalidates a guest page
2038	*
2039	* @returns VBox status code.
2040	* @param pVM The VM to operate on.
2041	* @param GCVirt Page to invalidate
2042	*/
2043	HWACCMR0DECL(int) SVMR0InvalidatePage(PVM pVM, RTGCPTR GCVirt)
2044	{
2045	bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB \| pVM->hwaccm.s.svm.fForceTLBFlush;
2046
2047	/* Skip it if a TLB flush is already pending. */
2048	if (!fFlushPending)
2049	{
2050	SVM_VMCB *pVMCB;
2051
2052	Log2(("SVMR0InvalidatePage %VGv\n", GCVirt));
2053	AssertReturn(pVM, VERR_INVALID_PARAMETER);
2054	Assert(pVM->hwaccm.s.svm.fSupported);
2055
2056	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
2057	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2058
2059	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageManual);
2060	SVMInvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2061	}
2062	return VINF_SUCCESS;
2063	}
2064
2065
2066	/**
2067	* Invalidates a guest page by physical address
2068	*
2069	* NOTE: Assumes the current instruction references this physical page though a virtual address!!
2070	*
2071	* @returns VBox status code.
2072	* @param pVM The VM to operate on.
2073	* @param GCPhys Page to invalidate
2074	*/
2075	HWACCMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys)
2076	{
2077	bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB \| pVM->hwaccm.s.svm.fForceTLBFlush;
2078
2079	Assert(pVM->hwaccm.s.fNestedPaging);
2080
2081	/* Skip it if a TLB flush is already pending. */
2082	if (!fFlushPending)
2083	{
2084	CPUMCTX *pCtx;
2085	int rc;
2086	SVM_VMCB *pVMCB;
2087
2088	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
2089	AssertRCReturn(rc, rc);
2090
2091	Log2(("SVMR0InvalidatePhysPage %VGp\n", GCPhys));
2092	AssertReturn(pVM, VERR_INVALID_PARAMETER);
2093	Assert(pVM->hwaccm.s.svm.fSupported);
2094
2095	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
2096	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2097
2098	/*
2099	* Only allow 32 & 64 bits code.
2100	*/
2101	DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid);
2102	if (enmMode != CPUMODE_16BIT)
2103	{
2104	RTGCPTR pbCode;
2105	int rc = SELMValidateAndConvertCSAddr(pVM, pCtx->eflags, pCtx->ss, pCtx->cs, &pCtx->csHid, (RTGCPTR)pCtx->rip, &pbCode);
2106	if (VBOX_SUCCESS(rc))
2107	{
2108	uint32_t cbOp;
2109	DISCPUSTATE Cpu;
2110	OP_PARAMVAL param1;
2111	RTGCPTR addr;
2112
2113	Cpu.mode = enmMode;
2114	rc = EMInterpretDisasOneEx(pVM, pbCode, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);
2115	AssertRCReturn(rc, rc);
2116	Assert(cbOp == Cpu.opsize);
2117
2118	int rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param1, &param1, PARAM_SOURCE);
2119	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2120
2121	switch(param1.type)
2122	{
2123	case PARMTYPE_IMMEDIATE:
2124	case PARMTYPE_ADDRESS:
2125	AssertReturn((param1.flags & (PARAM_VAL32\|PARAM_VAL64)), VERR_EM_INTERPRETER);
2126
2127	addr = param1.val.val64;
2128	break;
2129
2130	default:
2131	AssertFailed();
2132	return VERR_EM_INTERPRETER;
2133	}
2134
2135	/* Manually invalidate the page for the VM's TLB. */
2136	Log(("SVMR0InvalidatePhysPage Phys=%VGp Virt=%VGv ASID=%d\n", GCPhys, addr, pVMCB->ctrl.TLBCtrl.n.u32ASID));
2137	SVMInvlpgA(addr, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2138	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPhysPageManual);
2139
2140	return VINF_SUCCESS;
2141	}
2142	}
2143	AssertFailed();
2144	return VERR_EM_INTERPRETER;
2145	}
2146	return VINF_SUCCESS;
2147	}

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 12091

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