HWSVMR0.cpp@ 1241

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1	/* $Id: HWSVMR0.cpp 1225 2007-03-05 15:30:47Z vboxsync $ */
2	/** @file
3	* HWACCM SVM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_svm.h>
32	#include <VBox/pgm.h>
33	#include <VBox/pdm.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <VBox/selm.h>
37	#include <VBox/iom.h>
38	#include <VBox/dis.h>
39	#include <VBox/disopcode.h>
40	#include <iprt/param.h>
41	#include <iprt/assert.h>
42	#include <iprt/asm.h>
43	#include "HWSVMR0.h"
44
45	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
46
47	/**
48	* Sets up and activates SVM
49	*
50	* @returns VBox status code.
51	* @param pVM The VM to operate on.
52	*/
53	HWACCMR0DECL(int) SVMR0Setup(PVM pVM)
54	{
55	int rc = VINF_SUCCESS;
56	SVM_VMCB *pVMCB;
57
58	if (pVM == NULL)
59	return VERR_INVALID_PARAMETER;
60
61	/* Setup AMD SVM. */
62	Assert(pVM->hwaccm.s.svm.fSupported);
63
64	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
65	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
66
67	/* Program the control fields. Most of them never have to be changed again. */
68	/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
69	/** @note CR0 & CR4 can be safely read when guest and shadow copies are identical. */
70	pVMCB->ctrl.u16InterceptRdCRx = BIT(0) \| BIT(3) \| BIT(4) \| BIT(8);
71
72	/*
73	* CR0/3/4 writes must be intercepted for obvious reasons.
74	*/
75	pVMCB->ctrl.u16InterceptWrCRx = BIT(0) \| BIT(3) \| BIT(4) \| BIT(8);
76
77	/* Intercept all DRx reads and writes. */
78	pVMCB->ctrl.u16InterceptRdDRx = BIT(0) \| BIT(1) \| BIT(2) \| BIT(3) \| BIT(4) \| BIT(5) \| BIT(6) \| BIT(7);
79	pVMCB->ctrl.u16InterceptWrDRx = BIT(0) \| BIT(1) \| BIT(2) \| BIT(3) \| BIT(4) \| BIT(5) \| BIT(6) \| BIT(7);
80
81	/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
82	* All breakpoints are automatically cleared when the VM exits.
83	*/
84
85	/** @todo nested paging */
86	/* Intercept #NM only; #PF is not relevant due to nested paging (we get a seperate exit code (SVM_EXIT_NPF) for
87	* pagefaults that need our attention).
88	*/
89	pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
90
91	pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
92	\| SVM_CTRL1_INTERCEPT_VINTR
93	\| SVM_CTRL1_INTERCEPT_NMI
94	\| SVM_CTRL1_INTERCEPT_SMI
95	\| SVM_CTRL1_INTERCEPT_INIT
96	\| SVM_CTRL1_INTERCEPT_CR0 /** @todo redundant? */
97	\| SVM_CTRL1_INTERCEPT_RDPMC
98	\| SVM_CTRL1_INTERCEPT_CPUID
99	\| SVM_CTRL1_INTERCEPT_RSM
100	\| SVM_CTRL1_INTERCEPT_HLT
101	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
102	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
103	\| SVM_CTRL1_INTERCEPT_INVLPG
104	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
105	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
106	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
107	;
108	pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
109	\| SVM_CTRL2_INTERCEPT_VMMCALL
110	\| SVM_CTRL2_INTERCEPT_VMLOAD
111	\| SVM_CTRL2_INTERCEPT_VMSAVE
112	\| SVM_CTRL2_INTERCEPT_STGI
113	\| SVM_CTRL2_INTERCEPT_CLGI
114	\| SVM_CTRL2_INTERCEPT_SKINIT
115	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
116	;
117	Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
118	Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
119	Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
120
121	/* Virtualize masking of INTR interrupts. */
122	pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
123
124	/* Set IO and MSR bitmap addresses. */
125	pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
126	pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
127
128	/* Enable nested paging. */
129	/** @todo how to detect support for this?? */
130	pVMCB->ctrl.u64NestedPaging = 0; /** @todo SVM_NESTED_PAGING_ENABLE; */
131
132	/* No LBR virtualization. */
133	pVMCB->ctrl.u64LBRVirt = 0;
134
135	return rc;
136	}
137
138
139	/**
140	* Injects an event (trap or external interrupt)
141	*
142	* @param pVM The VM to operate on.
143	* @param pVMCB SVM control block
144	* @param pCtx CPU Context
145	* @param pIntInfo SVM interrupt info
146	*/
147	inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx, SVM_EVENT* pEvent)
148	{
149	#ifdef VBOX_STRICT
150	if (pEvent->n.u8Vector == 0xE)
151	Log(("SVMR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
152	else
153	if (pEvent->n.u8Vector < 0x20)
154	Log(("SVMR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode));
155	else
156	{
157	Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->eip));
158	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
159	Assert(pCtx->eflags.u32 & X86_EFL_IF);
160	}
161	#endif
162
163	/* Set event injection state. */
164	pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
165	}
166
167
168	/**
169	* Checks for pending guest interrupts and injects them
170	*
171	* @returns VBox status code.
172	* @param pVM The VM to operate on.
173	* @param pVMCB SVM control block
174	* @param pCtx CPU Context
175	*/
176	static int SVMR0CheckPendingInterrupt(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx)
177	{
178	int rc;
179
180	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
181	if (pVM->hwaccm.s.Event.fPending)
182	{
183	SVM_EVENT Event;
184
185	Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
186	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
187	Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
188	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
189
190	pVM->hwaccm.s.Event.fPending = false;
191	return VINF_SUCCESS;
192	}
193
194	/* When external interrupts are pending, we should exit the VM when IF is set. */
195	if ( !TRPMHasTrap(pVM)
196	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
197	{
198	if (!(pCtx->eflags.u32 & X86_EFL_IF))
199	{
200	Log2(("Enable irq window exit!\n"));
201	/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
202	//// pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
203	//// AssertRC(rc);
204	}
205	else
206	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
207	{
208	uint8_t u8Interrupt;
209
210	rc = PDMGetInterrupt(pVM, &u8Interrupt);
211	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
212	if (VBOX_SUCCESS(rc))
213	{
214	rc = TRPMAssertTrap(pVM, u8Interrupt, false);
215	AssertRC(rc);
216	}
217	else
218	{
219	/* can't happen... */
220	AssertFailed();
221	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
222	return VINF_EM_RAW_INTERRUPT_PENDING;
223	}
224	}
225	else
226	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
227	}
228
229	#ifdef VBOX_STRICT
230	if (TRPMHasTrap(pVM))
231	{
232	uint8_t u8Vector;
233	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
234	AssertRC(rc);
235	Assert(u8Vector >= 0x20);
236	}
237	#endif
238
239	if ( pCtx->eflags.u32 & X86_EFL_IF
240	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
241	&& TRPMHasTrap(pVM)
242	)
243	{
244	uint8_t u8Vector;
245	int rc;
246	bool fSoftwareInt;
247	SVM_EVENT Event;
248	uint32_t u32ErrorCode;
249
250	Event.au64[0] = 0;
251
252	/* If a new event is pending, then dispatch it now. */
253	rc = TRPMQueryTrapAll(pVM, &u8Vector, &fSoftwareInt, &u32ErrorCode, 0);
254	AssertRC(rc);
255	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| u8Vector < 0x20);
256	Assert(fSoftwareInt == false);
257
258	/* Clear the pending trap. */
259	rc = TRPMResetTrap(pVM);
260	AssertRC(rc);
261
262	Event.n.u8Vector = u8Vector;
263	Event.n.u1Valid = 1;
264	Event.n.u32ErrorCode = u32ErrorCode;
265
266	switch (u8Vector) {
267	case 8:
268	case 10:
269	case 11:
270	case 12:
271	case 13:
272	case 14:
273	case 17:
274	/* Valid error codes. */
275	Event.n.u1ErrorCodeValid = 1;
276	break;
277	default:
278	break;
279	}
280
281	if (u8Vector == X86_XCPT_NMI)
282	Event.n.u3Type = SVM_EVENT_NMI;
283	else
284	if (u8Vector < 0x20)
285	Event.n.u3Type = SVM_EVENT_EXCEPTION;
286	else
287	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
288
289	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
290	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
291	} /* if (interrupts can be dispatched) */
292
293	return VINF_SUCCESS;
294	}
295
296
297	/**
298	* Loads the guest state
299	*
300	* @returns VBox status code.
301	* @param pVM The VM to operate on.
302	* @param pCtx Guest context
303	*/
304	HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
305	{
306	int rc = VINF_SUCCESS;
307	RTGCUINTPTR val;
308	SVM_VMCB *pVMCB;
309
310	if (pVM == NULL)
311	return VERR_INVALID_PARAMETER;
312
313	/* Setup AMD SVM. */
314	Assert(pVM->hwaccm.s.svm.fSupported);
315
316	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
317	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
318
319	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
320	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
321	{
322	SVM_WRITE_SELREG(CS, cs);
323	Assert(pVMCB->guest.CS.u16Sel \|\| !pVMCB->guest.CS.u16Attr);
324
325	SVM_WRITE_SELREG(SS, ss);
326	Assert(pVMCB->guest.SS.u16Sel \|\| !pVMCB->guest.SS.u16Attr);
327
328	SVM_WRITE_SELREG(DS, ds);
329	Assert(pVMCB->guest.DS.u16Sel \|\| !pVMCB->guest.DS.u16Attr);
330
331	SVM_WRITE_SELREG(ES, es);
332	Assert(pVMCB->guest.ES.u16Sel \|\| !pVMCB->guest.ES.u16Attr);
333
334	SVM_WRITE_SELREG(FS, fs);
335	Assert(pVMCB->guest.FS.u16Sel \|\| !pVMCB->guest.FS.u16Attr);
336
337	SVM_WRITE_SELREG(GS, gs);
338	Assert(pVMCB->guest.GS.u16Sel \|\| !pVMCB->guest.GS.u16Attr);
339	}
340
341	/* Guest CPU context: LDTR. */
342	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
343	{
344	SVM_WRITE_SELREG(LDTR, ldtr);
345	}
346
347	/* Guest CPU context: TR. */
348	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
349	{
350	SVM_WRITE_SELREG(TR, tr);
351	}
352
353	/* Guest CPU context: GDTR. */
354	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
355	{
356	pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
357	pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
358	}
359
360	/* Guest CPU context: IDTR. */
361	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
362	{
363	pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
364	pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
365	}
366
367	/*
368	* Sysenter MSRs
369	*/
370	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
371	{
372	pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
373	pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
374	pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
375	}
376
377	/* Control registers */
378	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
379	{
380	val = pCtx->cr0;
381	if (CPUMIsGuestFPUStateActive(pVM) == false)
382	{
383	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
384	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
385	}
386	else
387	{
388	Assert(pVM->hwaccm.s.svm.fResumeVM == true);
389	/** @todo check if we support the old style mess correctly. */
390	if (!(val & X86_CR0_NE))
391	{
392	Log(("Forcing X86_CR0_NE!!!\n"));
393
394	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
395	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
396	{
397	pVMCB->ctrl.u32InterceptException \|= BIT(16);
398	pVM->hwaccm.s.fFPUOldStyleOverride = true;
399	}
400	}
401	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
402	}
403	/* Illegal when cache is turned on. */
404	val &= ~X86_CR0_NW;
405
406	pVMCB->guest.u64CR0 = val;
407	}
408	/* CR2 as well */
409	pVMCB->guest.u64CR2 = pCtx->cr2;
410
411	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
412	{
413	/* Save our shadow CR3 register. */
414	pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
415	}
416
417	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
418	{
419	val = pCtx->cr4;
420	switch(pVM->hwaccm.s.enmShadowMode)
421	{
422	case PGMMODE_REAL:
423	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
424	AssertFailed();
425	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
426
427	case PGMMODE_32_BIT: /* 32-bit paging. */
428	break;
429
430	case PGMMODE_PAE: /* PAE paging. */
431	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
432	/** @todo use normal 32 bits paging */
433	val \|= X86_CR4_PAE;
434	break;
435
436	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
437	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
438	AssertFailed();
439	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
440
441	default: /* shut up gcc */
442	AssertFailed();
443	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
444	}
445	pVMCB->guest.u64CR4 = val;
446	}
447
448	/* Debug registers. */
449	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
450	{
451	/** @todo DR0-6 */
452	val = pCtx->dr7;
453	val &= ~(BIT(11) \| BIT(12) \| BIT(14) \| BIT(15)); /* must be zero */
454	val \|= 0x400; /* must be one */
455	#ifdef VBOX_STRICT
456	val = 0x400;
457	#endif
458	pVMCB->guest.u64DR7 = val;
459
460	pVMCB->guest.u64DR6 = pCtx->dr6;
461	}
462
463	/* EIP, ESP and EFLAGS */
464	pVMCB->guest.u64RIP = pCtx->eip;
465	pVMCB->guest.u64RSP = pCtx->esp;
466	pVMCB->guest.u64RFlags = pCtx->eflags.u32;
467
468	/* Set CPL */
469	if (!(pCtx->cr0 & X86_CR0_PE))
470	pVMCB->guest.u8CPL = 0;
471	else
472	if (pCtx->eflags.Bits.u1VM)
473	pVMCB->guest.u8CPL = 3;
474	else
475	pVMCB->guest.u8CPL = (pCtx->ss & X86_SEL_RPL);
476
477	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
478	pVMCB->guest.u64RAX = pCtx->eax;
479
480	/* vmrun will fail otherwise. */
481	pVMCB->guest.u64EFER = MSR_K6_EFER_SVME;
482
483	/** @note We can do more complex things with tagged TLBs. */
484	pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
485
486	/** @todo TSC offset. */
487	/** @todo 64 bits stuff (?):
488	* - STAR
489	* - LSTAR
490	* - CSTAR
491	* - SFMASK
492	* - KernelGSBase
493	*/
494
495	/* Done. */
496	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
497
498	return rc;
499	}
500
501
502	/**
503	* Runs guest code in an SVM VM.
504	*
505	* @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
506	*
507	* @returns VBox status code.
508	* @param pVM The VM to operate on.
509	* @param pCtx Guest context
510	*/
511	HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
512	{
513	int rc = VINF_SUCCESS;
514	uint64_t exitCode;
515	SVM_VMCB *pVMCB;
516	bool fForceTLBFlush = false;
517	int cResume = 0;
518
519	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
520
521	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
522	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
523
524	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
525	*/
526	ResumeExecution:
527	cResume++;
528
529	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
530	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
531	{
532	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
533	if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
534	{
535	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
536	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
537	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
538	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
539	*/
540	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
541	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
542	pVMCB->ctrl.u64IntShadow = 0;
543	}
544	}
545	else
546	{
547	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
548	pVMCB->ctrl.u64IntShadow = 0;
549	}
550
551	/* Check for pending actions that force us to go back to ring 3. */
552	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
553	{
554	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
555	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
556	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
557	rc = VINF_EM_RAW_TO_R3;
558	goto end;
559	}
560	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
561	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
562	{
563	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
564	rc = VINF_EM_PENDING_REQUEST;
565	goto end;
566	}
567
568	/* When external interrupts are pending, we should exit the VM when IF is set. */
569	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
570	rc = SVMR0CheckPendingInterrupt(pVM, pVMCB, pCtx);
571	if (VBOX_FAILURE(rc))
572	{
573	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
574	goto end;
575	}
576
577	/** @todo check timers?? */
578
579	/* Load the guest state */
580	rc = SVMR0LoadGuestState(pVM, pCtx);
581	if (rc != VINF_SUCCESS)
582	{
583	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
584	goto end;
585	}
586
587	/* All done! Let's start VM execution. */
588	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
589
590	/** Erratum #170 -> must force a TLB flush */
591	/** @todo supposed to be fixed in future by AMD */
592	fForceTLBFlush = true;
593
594	if ( pVM->hwaccm.s.svm.fResumeVM == false
595	\|\| fForceTLBFlush)
596	{
597	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1;
598	}
599	else
600	{
601	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 0;
602	}
603	/* In case we execute a goto ResumeExecution later on. */
604	pVM->hwaccm.s.svm.fResumeVM = true;
605	fForceTLBFlush = false;
606
607	Assert(sizeof(pVM->hwaccm.s.svm.pVMCBPhys) == 8);
608	Assert(pVMCB->ctrl.u32InterceptCtrl1 == ( SVM_CTRL1_INTERCEPT_INTR
609	\| SVM_CTRL1_INTERCEPT_VINTR
610	\| SVM_CTRL1_INTERCEPT_NMI
611	\| SVM_CTRL1_INTERCEPT_SMI
612	\| SVM_CTRL1_INTERCEPT_INIT
613	\| SVM_CTRL1_INTERCEPT_CR0 /** @todo redundant? */
614	\| SVM_CTRL1_INTERCEPT_RDPMC
615	\| SVM_CTRL1_INTERCEPT_CPUID
616	\| SVM_CTRL1_INTERCEPT_RSM
617	\| SVM_CTRL1_INTERCEPT_HLT
618	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
619	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
620	\| SVM_CTRL1_INTERCEPT_INVLPG
621	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
622	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
623	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE /* Legacy FPU FERR handling. */
624	));
625	Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
626	\| SVM_CTRL2_INTERCEPT_VMMCALL
627	\| SVM_CTRL2_INTERCEPT_VMLOAD
628	\| SVM_CTRL2_INTERCEPT_VMSAVE
629	\| SVM_CTRL2_INTERCEPT_STGI
630	\| SVM_CTRL2_INTERCEPT_CLGI
631	\| SVM_CTRL2_INTERCEPT_SKINIT
632	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
633	));
634	Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
635	Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
636	Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
637	Assert(pVMCB->ctrl.u64NestedPaging == 0);
638	Assert(pVMCB->ctrl.u64LBRVirt == 0);
639
640	SVMVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);
641	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
642
643	/**
644	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
645	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
646	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
647	*/
648
649	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
650
651	/* Reason for the VM exit */
652	exitCode = pVMCB->ctrl.u64ExitCode;
653
654	if (exitCode == SVM_EXIT_INVALID) /* Invalid guest state. */
655	{
656	HWACCMDumpRegs(pCtx);
657	#ifdef DEBUG
658	Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
659	Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
660	Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
661	Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
662	Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
663	Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
664	Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
665	Log(("ctrl.u64IOPMPhysAddr %VX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
666	Log(("ctrl.u64MSRPMPhysAddr %VX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
667	Log(("ctrl.u64TSCOffset %VX64\n", pVMCB->ctrl.u64TSCOffset));
668
669	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
670	Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
671	Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
672	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
673
674	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
675	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
676	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
677	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
678	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
679	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
680	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
681	Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
682	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
683	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
684
685	Log(("ctrl.u64IntShadow %VX64\n", pVMCB->ctrl.u64IntShadow));
686	Log(("ctrl.u64ExitCode %VX64\n", pVMCB->ctrl.u64ExitCode));
687	Log(("ctrl.u64ExitInfo1 %VX64\n", pVMCB->ctrl.u64ExitInfo1));
688	Log(("ctrl.u64ExitInfo2 %VX64\n", pVMCB->ctrl.u64ExitInfo2));
689	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
690	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
691	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
692	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
693	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
694	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
695	Log(("ctrl.u64NestedPaging %VX64\n", pVMCB->ctrl.u64NestedPaging));
696	Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
697	Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
698	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
699	Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
700	Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
701	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
702
703	Log(("ctrl.u64HostCR3 %VX64\n", pVMCB->ctrl.u64HostCR3));
704	Log(("ctrl.u64LBRVirt %VX64\n", pVMCB->ctrl.u64LBRVirt));
705
706	Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
707	Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
708	Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
709	Log(("guest.CS.u64Base %VX64\n", pVMCB->guest.CS.u64Base));
710	Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
711	Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
712	Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
713	Log(("guest.DS.u64Base %VX64\n", pVMCB->guest.DS.u64Base));
714	Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
715	Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
716	Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
717	Log(("guest.ES.u64Base %VX64\n", pVMCB->guest.ES.u64Base));
718	Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
719	Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
720	Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
721	Log(("guest.FS.u64Base %VX64\n", pVMCB->guest.FS.u64Base));
722	Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
723	Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
724	Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
725	Log(("guest.GS.u64Base %VX64\n", pVMCB->guest.GS.u64Base));
726
727	Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
728	Log(("guest.GDTR.u64Base %VX64\n", pVMCB->guest.GDTR.u64Base));
729
730	Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
731	Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
732	Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
733	Log(("guest.LDTR.u64Base %VX64\n", pVMCB->guest.LDTR.u64Base));
734
735	Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
736	Log(("guest.IDTR.u64Base %VX64\n", pVMCB->guest.IDTR.u64Base));
737
738	Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
739	Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
740	Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
741	Log(("guest.TR.u64Base %VX64\n", pVMCB->guest.TR.u64Base));
742
743	Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
744	Log(("guest.u64CR0 %VX64\n", pVMCB->guest.u64CR0));
745	Log(("guest.u64CR2 %VX64\n", pVMCB->guest.u64CR2));
746	Log(("guest.u64CR3 %VX64\n", pVMCB->guest.u64CR3));
747	Log(("guest.u64CR4 %VX64\n", pVMCB->guest.u64CR4));
748	Log(("guest.u64DR6 %VX64\n", pVMCB->guest.u64DR6));
749	Log(("guest.u64DR7 %VX64\n", pVMCB->guest.u64DR7));
750
751	Log(("guest.u64RIP %VX64\n", pVMCB->guest.u64RIP));
752	Log(("guest.u64RSP %VX64\n", pVMCB->guest.u64RSP));
753	Log(("guest.u64RAX %VX64\n", pVMCB->guest.u64RAX));
754	Log(("guest.u64RFlags %VX64\n", pVMCB->guest.u64RFlags));
755
756	Log(("guest.u64SysEnterCS %VX64\n", pVMCB->guest.u64SysEnterCS));
757	Log(("guest.u64SysEnterEIP %VX64\n", pVMCB->guest.u64SysEnterEIP));
758	Log(("guest.u64SysEnterESP %VX64\n", pVMCB->guest.u64SysEnterESP));
759
760	Log(("guest.u64EFER %VX64\n", pVMCB->guest.u64EFER));
761	Log(("guest.u64STAR %VX64\n", pVMCB->guest.u64STAR));
762	Log(("guest.u64LSTAR %VX64\n", pVMCB->guest.u64LSTAR));
763	Log(("guest.u64CSTAR %VX64\n", pVMCB->guest.u64CSTAR));
764	Log(("guest.u64SFMASK %VX64\n", pVMCB->guest.u64SFMASK));
765	Log(("guest.u64KernelGSBase %VX64\n", pVMCB->guest.u64KernelGSBase));
766	Log(("guest.u64GPAT %VX64\n", pVMCB->guest.u64GPAT));
767	Log(("guest.u64DBGCTL %VX64\n", pVMCB->guest.u64DBGCTL));
768	Log(("guest.u64BR_FROM %VX64\n", pVMCB->guest.u64BR_FROM));
769	Log(("guest.u64BR_TO %VX64\n", pVMCB->guest.u64BR_TO));
770	Log(("guest.u64LASTEXCPFROM %VX64\n", pVMCB->guest.u64LASTEXCPFROM));
771	Log(("guest.u64LASTEXCPTO %VX64\n", pVMCB->guest.u64LASTEXCPTO));
772
773	#endif
774	rc = VERR_SVM_UNABLE_TO_START_VM;
775	goto end;
776	}
777
778	/* Let's first sync back eip, esp, and eflags. */
779	pCtx->eip = pVMCB->guest.u64RIP;
780	pCtx->esp = pVMCB->guest.u64RSP;
781	pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
782	/* eax is saved/restore across the vmrun instruction */
783	pCtx->eax = pVMCB->guest.u64RAX;
784
785	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
786	SVM_READ_SELREG(SS, ss);
787	SVM_READ_SELREG(CS, cs);
788	SVM_READ_SELREG(DS, ds);
789	SVM_READ_SELREG(ES, es);
790	SVM_READ_SELREG(FS, fs);
791	SVM_READ_SELREG(GS, gs);
792
793	/** @note no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
794
795	/** @note NOW IT'S SAFE FOR LOGGING! */
796
797	/* Take care of instruction fusing (sti, mov ss) */
798	if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
799	{
800	Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->eip));
801	EMSetInhibitInterruptsPC(pVM, pCtx->eip);
802	}
803	else
804	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
805
806	Log2(("exitCode = %x\n", exitCode));
807
808	/* Check if an injected event was interrupted prematurely. */
809	pVM->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
810	if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
811	&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
812	{
813	Log(("Pending inject %VX64 at %08x exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitCode));
814	pVM->hwaccm.s.Event.fPending = true;
815	/* Error code present? (redundant) */
816	if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
817	{
818	pVM->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
819	}
820	else
821	pVM->hwaccm.s.Event.errCode = 0;
822	}
823	/** @note Safety precaution; frequent loops have been observed even though external interrupts were pending. */
824	if (cResume > 32 /* low limit, but anything higher risks a hanging host due to interrupts left pending for too long */)
825	{
826	exitCode = SVM_EXIT_INTR;
827	}
828
829	/* Deal with the reason of the VM-exit. */
830	switch (exitCode)
831	{
832	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
833	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
834	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
835	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
836	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
837	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
838	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
839	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
840	{
841	/* Pending trap. */
842	SVM_EVENT Event;
843	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
844
845	Log2(("Hardware/software interrupt %d\n", vector));
846	switch (vector)
847	{
848	case X86_XCPT_NM:
849	{
850	uint32_t oldCR0;
851
852	Log(("#NM fault at %VGv\n", pCtx->eip));
853
854	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
855	oldCR0 = ASMGetCR0();
856	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
857	rc = CPUMHandleLazyFPU(pVM);
858	if (rc == VINF_SUCCESS)
859	{
860	Assert(CPUMIsGuestFPUStateActive(pVM));
861
862	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
863	ASMSetCR0(oldCR0);
864
865	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
866
867	/* Continue execution. */
868	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
869	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
870
871	goto ResumeExecution;
872	}
873
874	Log(("Forward #NM fault to the guest\n"));
875	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
876
877	Event.au64[0] = 0;
878	Event.n.u3Type = SVM_EVENT_EXCEPTION;
879	Event.n.u1Valid = 1;
880	Event.n.u8Vector = X86_XCPT_NM;
881
882	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
883	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
884	goto ResumeExecution;
885	}
886
887	case X86_XCPT_PF: /* Page fault */
888	{
889	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
890	RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
891
892	Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
893	/* Exit qualification contains the linear address of the page fault. */
894	TRPMAssertTrap(pVM, X86_XCPT_PF, false);
895	TRPMSetErrorCode(pVM, errCode);
896	TRPMSetFaultAddress(pVM, uFaultAddress);
897
898	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
899	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
900	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
901	if (rc == VINF_SUCCESS)
902	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
903	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
904	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
905
906	TRPMResetTrap(pVM);
907
908	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
909	goto ResumeExecution;
910	}
911	else
912	if (rc == VINF_EM_RAW_GUEST_TRAP)
913	{ /* A genuine pagefault.
914	* Forward the trap to the guest by injecting the exception and resuming execution.
915	*/
916	Log2(("Forward page fault to the guest\n"));
917	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
918	/* The error code might have been changed. */
919	errCode = TRPMGetErrorCode(pVM);
920
921	TRPMResetTrap(pVM);
922
923	/* Now we must update CR2. */
924	pCtx->cr2 = uFaultAddress;
925
926	Event.au64[0] = 0;
927	Event.n.u3Type = SVM_EVENT_EXCEPTION;
928	Event.n.u1Valid = 1;
929	Event.n.u8Vector = X86_XCPT_PF;
930	Event.n.u1ErrorCodeValid = 1;
931	Event.n.u32ErrorCode = errCode;
932
933	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
934
935	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
936	goto ResumeExecution;
937	}
938	#ifdef VBOX_STRICT
939	if (rc != VINF_EM_RAW_EMULATE_INSTR)
940	Log(("PGMTrap0eHandler failed with %d\n", rc));
941	#endif
942	/* Need to go back to the recompiler to emulate the instruction. */
943	TRPMResetTrap(pVM);
944	break;
945	}
946
947	case X86_XCPT_MF: /* Floating point exception. */
948	{
949	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
950	if (!(pCtx->cr0 & X86_CR0_NE))
951	{
952	/* old style FPU error reporting needs some extra work. */
953	/** @todo don't fall back to the recompiler, but do it manually. */
954	rc = VINF_EM_RAW_EMULATE_INSTR;
955	break;
956	}
957	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
958
959	Event.au64[0] = 0;
960	Event.n.u3Type = SVM_EVENT_EXCEPTION;
961	Event.n.u1Valid = 1;
962	Event.n.u8Vector = X86_XCPT_MF;
963
964	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
965
966	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
967	goto ResumeExecution;
968	}
969
970	case X86_XCPT_GP: /* General protection failure exception.*/
971	{
972	if (pCtx->eflags.Bits.u1VM == 1)
973	{
974	Log(("#GP in V86 mode -> fall back\n"));
975	/** @note workaround for #GP loop; looks like an SVM bug */
976	rc = VINF_EM_RAW_EMULATE_INSTR;
977	break;
978	}
979	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
980
981	Event.au64[0] = 0;
982	Event.n.u3Type = SVM_EVENT_EXCEPTION;
983	Event.n.u1Valid = 1;
984	Event.n.u8Vector = X86_XCPT_GP;
985	Event.n.u1ErrorCodeValid= 1;
986	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
987	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
988	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
989
990	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
991	goto ResumeExecution;
992	}
993
994	#ifdef VBOX_STRICT
995	case X86_XCPT_UD: /* Unknown opcode exception. */
996	case X86_XCPT_DE: /* Debug exception. */
997	case X86_XCPT_SS: /* Stack segment exception. */
998	case X86_XCPT_NP: /* Segment not present exception. */
999	{
1000	Event.au64[0] = 0;
1001	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1002	Event.n.u1Valid = 1;
1003	Event.n.u8Vector = vector;
1004
1005	switch(vector)
1006	{
1007	case X86_XCPT_DE:
1008	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1009	break;
1010	case X86_XCPT_UD:
1011	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1012	break;
1013	case X86_XCPT_SS:
1014	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1015	Event.n.u1ErrorCodeValid = 1;
1016	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1017	break;
1018	case X86_XCPT_NP:
1019	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1020	Event.n.u1ErrorCodeValid = 1;
1021	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1022	break;
1023	}
1024
1025	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1026	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1027
1028	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1029	goto ResumeExecution;
1030	}
1031	#endif
1032	default:
1033	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1034	rc = VERR_EM_INTERNAL_ERROR;
1035	break;
1036
1037	} /* switch (vector) */
1038	break;
1039	}
1040
1041	case SVM_EXIT_FERR_FREEZE:
1042	case SVM_EXIT_INTR:
1043	case SVM_EXIT_NMI:
1044	case SVM_EXIT_SMI:
1045	case SVM_EXIT_INIT:
1046	case SVM_EXIT_VINTR:
1047	/* External interrupt; leave to allow it to be dispatched again. */
1048	rc = VINF_EM_RAW_INTERRUPT;
1049	break;
1050
1051	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1052	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1053	/* Skip instruction and continue directly. */
1054	pCtx->eip += 2; /** @note hardcoded opcode size! */
1055	/* Continue execution.*/
1056	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1057	goto ResumeExecution;
1058
1059	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1060	{
1061	Log2(("SVM: Cpuid %x\n", pCtx->eax));
1062	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1063	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1064	if (rc == VINF_SUCCESS)
1065	{
1066	/* Update EIP and continue execution. */
1067	pCtx->eip += 2; /** @note hardcoded opcode size! */
1068	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1069	goto ResumeExecution;
1070	}
1071	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1072	rc = VINF_EM_RAW_EMULATE_INSTR;
1073	break;
1074	}
1075
1076	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1077	{
1078	Log2(("VMX: invlpg\n"));
1079	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1080
1081	/* Truly a pita. Why can't SVM give the same information as VMX? */
1082	rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1083	break;
1084	}
1085
1086	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1087	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1088	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1089	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1090	{
1091	uint32_t cbSize;
1092
1093	Log2(("VMX: %VGv mov cr%d, \n", pCtx->eip, exitCode - SVM_EXIT_WRITE_CR0));
1094	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1095	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1096
1097	switch (exitCode - SVM_EXIT_WRITE_CR0)
1098	{
1099	case 0:
1100	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1101	break;
1102	case 2:
1103	break;
1104	case 3:
1105	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1106	break;
1107	case 4:
1108	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1109	break;
1110	default:
1111	AssertFailed();
1112	}
1113	/* Check if a sync operation is pending. */
1114	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1115	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1116	{
1117	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1118	AssertRC(rc);
1119
1120	/** @note Force a TLB flush. SVM requires us to do it manually. */
1121	fForceTLBFlush = true;
1122	}
1123	if (rc == VINF_SUCCESS)
1124	{
1125	/* EIP has been updated already. */
1126
1127	/* Only resume if successful. */
1128	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1129	goto ResumeExecution;
1130	}
1131	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1132	if (rc == VERR_EM_INTERPRETER)
1133	rc = VINF_EM_RAW_EMULATE_INSTR;
1134	break;
1135	}
1136
1137	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1138	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1139	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1140	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1141	{
1142	uint32_t cbSize;
1143
1144	Log2(("VMX: %VGv mov x, cr%d\n", pCtx->eip, exitCode - SVM_EXIT_READ_CR0));
1145	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1146	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1147	if (rc == VINF_SUCCESS)
1148	{
1149	/* EIP has been updated already. */
1150
1151	/* Only resume if successful. */
1152	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1153	goto ResumeExecution;
1154	}
1155	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1156	if (rc == VERR_EM_INTERPRETER)
1157	rc = VINF_EM_RAW_EMULATE_INSTR;
1158	break;
1159	}
1160
1161	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1162	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1163	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1164	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1165	{
1166	uint32_t cbSize;
1167
1168	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_WRITE_DR0));
1169	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1170	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1171	if (rc == VINF_SUCCESS)
1172	{
1173	/* EIP has been updated already. */
1174
1175	/* Only resume if successful. */
1176	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1177	goto ResumeExecution;
1178	}
1179	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1180	if (rc == VERR_EM_INTERPRETER)
1181	rc = VINF_EM_RAW_EMULATE_INSTR;
1182	break;
1183	}
1184
1185	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1186	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1187	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1188	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1189	{
1190	uint32_t cbSize;
1191
1192	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_READ_DR0));
1193	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1194	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1195	if (rc == VINF_SUCCESS)
1196	{
1197	/* EIP has been updated already. */
1198
1199	/* Only resume if successful. */
1200	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1201	goto ResumeExecution;
1202	}
1203	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1204	if (rc == VERR_EM_INTERPRETER)
1205	rc = VINF_EM_RAW_EMULATE_INSTR;
1206	break;
1207	}
1208
1209	/** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1210	case SVM_EXIT_IOIO: /* I/O instruction. */
1211	{
1212	SVM_IOIO_EXIT IoExitInfo;
1213	uint32_t uIOSize, uAndVal;
1214
1215	IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1216
1217	/** @todo could use a lookup table here */
1218	if (IoExitInfo.n.u1OP8)
1219	{
1220	uIOSize = 1;
1221	uAndVal = 0xff;
1222	}
1223	else
1224	if (IoExitInfo.n.u1OP16)
1225	{
1226	uIOSize = 2;
1227	uAndVal = 0xffff;
1228	}
1229	else
1230	if (IoExitInfo.n.u1OP32)
1231	{
1232	uIOSize = 4;
1233	uAndVal = 0xffffffff;
1234	}
1235	else
1236	{
1237	AssertFailed(); /* should be fatal. */
1238	rc = VINF_EM_RAW_EMULATE_INSTR;
1239	break;
1240	}
1241
1242	/* First simple in and out instructions. */
1243	/** @todo str & rep */
1244	if ( !IoExitInfo.n.u1REP
1245	&& !IoExitInfo.n.u1STR
1246	)
1247	{
1248	if (IoExitInfo.n.u1Type == 0)
1249	{
1250	Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1251	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1252	rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1253	}
1254	else
1255	{
1256	uint32_t u32Val = 0;
1257
1258	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1259	rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1260	if (rc == VINF_SUCCESS)
1261	{
1262	/* Write back to the EAX register. */
1263	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1264	Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1265	}
1266	}
1267	if (rc == VINF_SUCCESS)
1268	{
1269	/* Update EIP and continue execution. */
1270	pCtx->eip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1271	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1272	goto ResumeExecution;
1273	}
1274	Assert(rc == VINF_IOM_HC_IOPORT_READ \|\| rc == VINF_IOM_HC_IOPORT_WRITE);
1275	rc = (IoExitInfo.n.u1Type == 0) ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1276	}
1277	else
1278	rc = VINF_IOM_HC_IOPORT_READWRITE;
1279
1280	Log2(("Failed IO at %VGv %x size %d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1281
1282	break;
1283	}
1284
1285	case SVM_EXIT_HLT:
1286	/** Check if external interrupts are pending; if so, don't switch back. */
1287	if (VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1288	{
1289	pCtx->eip++; /* skip hlt */
1290	goto ResumeExecution;
1291	}
1292
1293	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1294	break;
1295
1296	case SVM_EXIT_RDPMC:
1297	case SVM_EXIT_RSM:
1298	case SVM_EXIT_INVLPGA:
1299	case SVM_EXIT_VMRUN:
1300	case SVM_EXIT_VMMCALL:
1301	case SVM_EXIT_VMLOAD:
1302	case SVM_EXIT_VMSAVE:
1303	case SVM_EXIT_STGI:
1304	case SVM_EXIT_CLGI:
1305	case SVM_EXIT_SKINIT:
1306	case SVM_EXIT_RDTSCP:
1307	{
1308	/* Unsupported instructions. */
1309	SVM_EVENT Event;
1310
1311	Event.au64[0] = 0;
1312	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1313	Event.n.u1Valid = 1;
1314	Event.n.u8Vector = X86_XCPT_UD;
1315
1316	Log(("Forced #UD trap at %VGv\n", pCtx->eip));
1317	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1318
1319	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1320	goto ResumeExecution;
1321	}
1322
1323	/* Emulate RDMSR & WRMSR in ring 3. */
1324	case SVM_EXIT_MSR:
1325	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1326	break;
1327
1328	case SVM_EXIT_NPF:
1329	AssertFailed(); /* unexpected */
1330	break;
1331
1332	case SVM_EXIT_SHUTDOWN:
1333	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1334	break;
1335
1336	case SVM_EXIT_PAUSE:
1337	case SVM_EXIT_IDTR_READ:
1338	case SVM_EXIT_GDTR_READ:
1339	case SVM_EXIT_LDTR_READ:
1340	case SVM_EXIT_TR_READ:
1341	case SVM_EXIT_IDTR_WRITE:
1342	case SVM_EXIT_GDTR_WRITE:
1343	case SVM_EXIT_LDTR_WRITE:
1344	case SVM_EXIT_TR_WRITE:
1345	case SVM_EXIT_CR0_SEL_WRITE:
1346	default:
1347	/* Unexpected exit codes. */
1348	rc = VERR_EM_INTERNAL_ERROR;
1349	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
1350	break;
1351	}
1352
1353	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1354	SVM_READ_SELREG(LDTR, ldtr);
1355	SVM_READ_SELREG(TR, tr);
1356
1357	pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1358	pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1359
1360	pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1361	pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1362
1363	/*
1364	* System MSRs
1365	*/
1366	pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1367	pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1368	pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1369
1370	/* Signal changes for the recompiler. */
1371	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
1372
1373	end:
1374
1375	/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
1376	if (exitCode == SVM_EXIT_INTR)
1377	{
1378	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1379	/* On the next entry we'll only sync the host context. */
1380	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
1381	}
1382	else
1383	{
1384	/* On the next entry we'll sync everything. */
1385	/** @todo we can do better than this */
1386	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
1387	}
1388
1389	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1390	return rc;
1391	}
1392
1393	/**
1394	* Enable SVM
1395	*
1396	* @returns VBox status code.
1397	* @param pVM The VM to operate on.
1398	*/
1399	HWACCMR0DECL(int) SVMR0Enable(PVM pVM)
1400	{
1401	uint64_t val;
1402
1403	Assert(pVM->hwaccm.s.svm.fSupported);
1404
1405	/* We must turn on SVM and setup the host state physical address, as those MSRs are per-cpu/core. */
1406
1407	/* Turn on SVM in the EFER MSR. */
1408	val = ASMRdMsr(MSR_K6_EFER);
1409	if (!(val & MSR_K6_EFER_SVME))
1410	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
1411
1412	/* Write the physical page address where the CPU will store the host state while executing the VM. */
1413	ASMWrMsr(MSR_K8_VM_HSAVE_PA, pVM->hwaccm.s.svm.pHStatePhys);
1414
1415	/* Force a TLB flush on VM entry. */
1416	pVM->hwaccm.s.svm.fResumeVM = false;
1417
1418	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
1419	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_LDTR;
1420
1421	return VINF_SUCCESS;
1422	}
1423
1424
1425	/**
1426	* Disable SVM
1427	*
1428	* @returns VBox status code.
1429	* @param pVM The VM to operate on.
1430	*/
1431	HWACCMR0DECL(int) SVMR0Disable(PVM pVM)
1432	{
1433	/** @todo hopefully this is not very expensive. */
1434
1435	/* Turn off SVM in the EFER MSR. */
1436	uint64_t val = ASMRdMsr(MSR_K6_EFER);
1437	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
1438
1439	/* Invalidate host state physical address. */
1440	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
1441
1442	Assert(pVM->hwaccm.s.svm.fSupported);
1443	return VINF_SUCCESS;
1444	}
1445
1446
1447	static int svmInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1448	{
1449	OP_PARAMVAL param1;
1450	RTGCPTR addr;
1451
1452	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1453	if(VBOX_FAILURE(rc))
1454	return VERR_EM_INTERPRETER;
1455
1456	switch(param1.type)
1457	{
1458	case PARMTYPE_IMMEDIATE:
1459	case PARMTYPE_ADDRESS:
1460	if(!(param1.flags & PARAM_VAL32))
1461	return VERR_EM_INTERPRETER;
1462	addr = (RTGCPTR)param1.val.val32;
1463	break;
1464
1465	default:
1466	return VERR_EM_INTERPRETER;
1467	}
1468
1469	/** @todo is addr always a flat linear address or ds based
1470	* (in absence of segment override prefixes)????
1471	*/
1472	rc = PGMInvalidatePage(pVM, addr);
1473	if (VBOX_SUCCESS(rc))
1474	{
1475	/* Manually invalidate the page for the VM's TLB. */
1476	SVMInvlpgA(addr, uASID);
1477	return VINF_SUCCESS;
1478	}
1479	/** @todo r=bird: we shouldn't ignore returns codes like this... I'm 99% sure the error is fatal. */
1480	return VERR_EM_INTERPRETER;
1481	}
1482
1483	/**
1484	* Interprets INVLPG
1485	*
1486	* @returns VBox status code.
1487	* @retval VINF_* Scheduling instructions.
1488	* @retval VERR_EM_INTERPRETER Something we can't cope with.
1489	* @retval VERR_* Fatal errors.
1490	*
1491	* @param pVM The VM handle.
1492	* @param pRegFrame The register frame.
1493	* @param ASID Tagged TLB id for the guest
1494	*
1495	* Updates the EIP if an instruction was executed successfully.
1496	*/
1497	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1498	{
1499	/*
1500	* Only allow 32-bit code.
1501	*/
1502	if (SELMIsSelector32Bit(pVM, pRegFrame->cs, &pRegFrame->csHid))
1503	{
1504	RTGCPTR pbCode;
1505	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pbCode);
1506	if (VBOX_SUCCESS(rc))
1507	{
1508	uint32_t cbOp;
1509	DISCPUSTATE Cpu;
1510
1511	Cpu.mode = CPUMODE_32BIT;
1512	rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
1513	Assert(VBOX_FAILURE(rc) \|\| Cpu.pCurInstr->opcode == OP_INVLPG);
1514	if (VBOX_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
1515	{
1516	Assert(cbOp == Cpu.opsize);
1517	rc = svmInterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
1518	if (VBOX_SUCCESS(rc))
1519	{
1520	pRegFrame->eip += cbOp; /* Move on to the next instruction. */
1521	}
1522	return rc;
1523	}
1524	}
1525	}
1526	return VERR_EM_INTERPRETER;
1527	}
1528

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 1241

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