HWSVMR0.cpp@ 13972

Last change on this file since 13972 was 13960, checked in by vboxsync, 16 years ago
Moved guest and host CPU contexts into per-VCPU array.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 90.1 KB

Line
1	/* $Id: HWSVMR0.cpp 13960 2008-11-07 13:04:45Z vboxsync $ */
2	/** @file
3	* HWACCM SVM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_svm.h>
32	#include <VBox/pgm.h>
33	#include <VBox/pdm.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <VBox/selm.h>
37	#include <VBox/iom.h>
38	#include <VBox/dis.h>
39	#include <VBox/dbgf.h>
40	#include <VBox/disopcode.h>
41	#include <iprt/param.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm.h>
44	#include <iprt/cpuset.h>
45	#include <iprt/mp.h>
46	#include "HWSVMR0.h"
47
48	/*******************************************************************************
49	* Internal Functions *
50	*******************************************************************************/
51	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
52
53	/*******************************************************************************
54	* Global Variables *
55	*******************************************************************************/
56	/* IO operation lookup arrays. */
57	static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
58
59	/**
60	* Sets up and activates AMD-V on the current CPU
61	*
62	* @returns VBox status code.
63	* @param pCpu CPU info struct
64	* @param pVM The VM to operate on. (can be NULL after a resume!!)
65	* @param pvPageCpu Pointer to the global cpu page
66	* @param pPageCpuPhys Physical address of the global cpu page
67	*/
68	VMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
69	{
70	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
71	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
72
73	/* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
74
75	#ifdef LOG_ENABLED
76	SUPR0Printf("SVMR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
77	#endif
78
79	/* Turn on AMD-V in the EFER MSR. */
80	uint64_t val = ASMRdMsr(MSR_K6_EFER);
81	if (!(val & MSR_K6_EFER_SVME))
82	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
83
84	/* Write the physical page address where the CPU will store the host state while executing the VM. */
85	ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
86
87	return VINF_SUCCESS;
88	}
89
90	/**
91	* Deactivates AMD-V on the current CPU
92	*
93	* @returns VBox status code.
94	* @param pCpu CPU info struct
95	* @param pvPageCpu Pointer to the global cpu page
96	* @param pPageCpuPhys Physical address of the global cpu page
97	*/
98	VMMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
99	{
100	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
101	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
102
103	#ifdef LOG_ENABLED
104	SUPR0Printf("SVMR0DisableCpu cpu %d\n", pCpu->idCpu);
105	#endif
106
107	/* Turn off AMD-V in the EFER MSR. */
108	uint64_t val = ASMRdMsr(MSR_K6_EFER);
109	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
110
111	/* Invalidate host state physical address. */
112	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
113
114	return VINF_SUCCESS;
115	}
116
117	/**
118	* Does Ring-0 per VM AMD-V init.
119	*
120	* @returns VBox status code.
121	* @param pVM The VM to operate on.
122	*/
123	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
124	{
125	int rc;
126
127	pVM->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
128	pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
129	pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
130
131	/* Allocate one page for the host context */
132	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
133	if (RT_FAILURE(rc))
134	return rc;
135
136	pVM->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCBHost);
137	pVM->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCBHost, 0);
138	ASMMemZeroPage(pVM->hwaccm.s.svm.pVMCBHost);
139
140	/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
141	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
142	if (RT_FAILURE(rc))
143	return rc;
144
145	pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
146	pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
147	/* Set all bits to intercept all IO accesses. */
148	ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
149
150	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
151	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
152	if (RT_FAILURE(rc))
153	return rc;
154
155	pVM->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
156	pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
157	/* Set all bits to intercept all MSR accesses. */
158	ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
159
160	/* Erratum 170 which requires a forced TLB flush for each world switch:
161	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
162	*
163	* All BH-G1/2 and DH-G1/2 models include a fix:
164	* Athlon X2: 0x6b 1/2
165	* 0x68 1/2
166	* Athlon 64: 0x7f 1
167	* 0x6f 2
168	* Sempron: 0x7f 1/2
169	* 0x6f 2
170	* 0x6c 2
171	* 0x7c 2
172	* Turion 64: 0x68 2
173	*
174	*/
175	uint32_t u32Dummy;
176	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
177	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
178	u32BaseFamily= (u32Version >> 8) & 0xf;
179	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
180	u32Model = ((u32Version >> 4) & 0xf);
181	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
182	u32Stepping = u32Version & 0xf;
183	if ( u32Family == 0xf
184	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
185	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
186	{
187	Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
188	pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
189	}
190
191	/* Allocate VMCBs for all guest CPUs. */
192	for (unsigned i=0;i<pVM->cCPUs;i++)
193	{
194	pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
195
196	/* Allocate one page for the VM control block (VMCB). */
197	rc = RTR0MemObjAllocCont(&pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
198	if (RT_FAILURE(rc))
199	return rc;
200
201	pVM->aCpus[i].hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB);
202	pVM->aCpus[i].hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB, 0);
203	ASMMemZeroPage(pVM->aCpus[i].hwaccm.s.svm.pVMCB);
204	}
205
206	return VINF_SUCCESS;
207	}
208
209	/**
210	* Does Ring-0 per VM AMD-V termination.
211	*
212	* @returns VBox status code.
213	* @param pVM The VM to operate on.
214	*/
215	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
216	{
217	for (unsigned i=0;i<pVM->cCPUs;i++)
218	{
219	if (pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)
220	{
221	RTR0MemObjFree(pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB, false);
222	pVM->aCpus[i].hwaccm.s.svm.pVMCB = 0;
223	pVM->aCpus[i].hwaccm.s.svm.pVMCBPhys = 0;
224	pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
225	}
226	}
227	if (pVM->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ)
228	{
229	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCBHost, false);
230	pVM->hwaccm.s.svm.pVMCBHost = 0;
231	pVM->hwaccm.s.svm.pVMCBHostPhys = 0;
232	pVM->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
233	}
234	if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)
235	{
236	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
237	pVM->hwaccm.s.svm.pIOBitmap = 0;
238	pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
239	pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
240	}
241	if (pVM->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
242	{
243	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
244	pVM->hwaccm.s.svm.pMSRBitmap = 0;
245	pVM->hwaccm.s.svm.pMSRBitmapPhys = 0;
246	pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
247	}
248	return VINF_SUCCESS;
249	}
250
251	/**
252	* Sets up AMD-V for the specified VM
253	*
254	* @returns VBox status code.
255	* @param pVM The VM to operate on.
256	*/
257	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
258	{
259	int rc = VINF_SUCCESS;
260	SVM_VMCB *pVMCB;
261
262	AssertReturn(pVM, VERR_INVALID_PARAMETER);
263
264	Assert(pVM->hwaccm.s.svm.fSupported);
265
266	for (unsigned i=0;i<pVM->cCPUs;i++)
267	{
268	pVMCB = (SVM_VMCB *)pVM->aCpus[i].hwaccm.s.svm.pVMCB;
269	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
270
271	/* Program the control fields. Most of them never have to be changed again. */
272	/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
273	/* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical. */
274	if (!pVM->hwaccm.s.fNestedPaging)
275	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
276	else
277	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
278
279	/*
280	* CR0/3/4 writes must be intercepted for obvious reasons.
281	*/
282	if (!pVM->hwaccm.s.fNestedPaging)
283	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
284	else
285	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4) \| RT_BIT(8);
286
287	/* Intercept all DRx reads and writes by default. Changed later on. */
288	pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
289	pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
290
291	/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
292	* All breakpoints are automatically cleared when the VM exits.
293	*/
294
295	pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
296	#ifndef DEBUG
297	if (pVM->hwaccm.s.fNestedPaging)
298	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
299	#endif
300
301	pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
302	\| SVM_CTRL1_INTERCEPT_VINTR
303	\| SVM_CTRL1_INTERCEPT_NMI
304	\| SVM_CTRL1_INTERCEPT_SMI
305	\| SVM_CTRL1_INTERCEPT_INIT
306	\| SVM_CTRL1_INTERCEPT_RDPMC
307	\| SVM_CTRL1_INTERCEPT_CPUID
308	\| SVM_CTRL1_INTERCEPT_RSM
309	\| SVM_CTRL1_INTERCEPT_HLT
310	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
311	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
312	\| SVM_CTRL1_INTERCEPT_INVLPG
313	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
314	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH
315	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
316	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
317	;
318	/* With nested paging we don't care about invlpg anymore. */
319	if (pVM->hwaccm.s.fNestedPaging)
320	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
321
322	pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
323	\| SVM_CTRL2_INTERCEPT_VMMCALL
324	\| SVM_CTRL2_INTERCEPT_VMLOAD
325	\| SVM_CTRL2_INTERCEPT_VMSAVE
326	\| SVM_CTRL2_INTERCEPT_STGI
327	\| SVM_CTRL2_INTERCEPT_CLGI
328	\| SVM_CTRL2_INTERCEPT_SKINIT
329	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
330	\| SVM_CTRL2_INTERCEPT_WBINVD
331	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
332	;
333	Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
334	Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
335	Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
336
337	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
338	pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
339	/* Ignore the priority in the TPR; just deliver it when we tell it to. */
340	pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
341
342	/* Set IO and MSR bitmap addresses. */
343	pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
344	pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
345
346	/* No LBR virtualization. */
347	pVMCB->ctrl.u64LBRVirt = 0;
348
349	/** The ASID must start at 1; the host uses 0. */
350	pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
351
352	/** Setup the PAT msr (nested paging only) */
353	pVMCB->guest.u64GPAT = 0x0007040600070406ULL;
354	}
355	return rc;
356	}
357
358
359	/**
360	* Injects an event (trap or external interrupt)
361	*
362	* @param pVM The VM to operate on.
363	* @param pVMCB SVM control block
364	* @param pCtx CPU Context
365	* @param pIntInfo SVM interrupt info
366	*/
367	inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx, SVM_EVENT* pEvent)
368	{
369	#ifdef VBOX_STRICT
370	if (pEvent->n.u8Vector == 0xE)
371	Log(("SVM: Inject int %d at %RGv error code=%02x CR2=%RGv intInfo=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode, (RTGCPTR)pCtx->cr2, pEvent->au64[0]));
372	else
373	if (pEvent->n.u8Vector < 0x20)
374	Log(("SVM: Inject int %d at %RGv error code=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode));
375	else
376	{
377	Log(("INJ-EI: %x at %RGv\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip));
378	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
379	Assert(pCtx->eflags.u32 & X86_EFL_IF);
380	}
381	#endif
382
383	/* Set event injection state. */
384	pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
385	}
386
387
388	/**
389	* Checks for pending guest interrupts and injects them
390	*
391	* @returns VBox status code.
392	* @param pVM The VM to operate on.
393	* @param pVCpu The VM CPU to operate on.
394	* @param pVMCB SVM control block
395	* @param pCtx CPU Context
396	*/
397	static int SVMR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, SVM_VMCB pVMCB, CPUMCTX pCtx)
398	{
399	int rc;
400
401	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
402	if (pVCpu->hwaccm.s.Event.fPending)
403	{
404	SVM_EVENT Event;
405
406	Log(("Reinjecting event %08x %08x at %RGv\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip));
407	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
408	Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
409	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
410
411	pVCpu->hwaccm.s.Event.fPending = false;
412	return VINF_SUCCESS;
413	}
414
415	/* When external interrupts are pending, we should exit the VM when IF is set. */
416	if ( !TRPMHasTrap(pVM)
417	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
418	{
419	if ( !(pCtx->eflags.u32 & X86_EFL_IF)
420	\|\| VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
421	{
422	if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
423	{
424	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
425	LogFlow(("Enable irq window exit!\n"));
426	else
427	Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", (RTGCPTR)pCtx->rip));
428
429	/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
430	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
431	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
432	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
433	}
434	}
435	else
436	{
437	uint8_t u8Interrupt;
438
439	rc = PDMGetInterrupt(pVM, &u8Interrupt);
440	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
441	if (RT_SUCCESS(rc))
442	{
443	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
444	AssertRC(rc);
445	}
446	else
447	{
448	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
449	Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)));
450	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
451	/* Just continue */
452	}
453	}
454	}
455
456	#ifdef VBOX_STRICT
457	if (TRPMHasTrap(pVM))
458	{
459	uint8_t u8Vector;
460	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
461	AssertRC(rc);
462	}
463	#endif
464
465	if ( pCtx->eflags.u32 & X86_EFL_IF
466	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
467	&& TRPMHasTrap(pVM)
468	)
469	{
470	uint8_t u8Vector;
471	int rc;
472	TRPMEVENT enmType;
473	SVM_EVENT Event;
474	RTGCUINT u32ErrorCode;
475
476	Event.au64[0] = 0;
477
478	/* If a new event is pending, then dispatch it now. */
479	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &u32ErrorCode, 0);
480	AssertRC(rc);
481	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
482	Assert(enmType != TRPM_SOFTWARE_INT);
483
484	/* Clear the pending trap. */
485	rc = TRPMResetTrap(pVM);
486	AssertRC(rc);
487
488	Event.n.u8Vector = u8Vector;
489	Event.n.u1Valid = 1;
490	Event.n.u32ErrorCode = u32ErrorCode;
491
492	if (enmType == TRPM_TRAP)
493	{
494	switch (u8Vector) {
495	case 8:
496	case 10:
497	case 11:
498	case 12:
499	case 13:
500	case 14:
501	case 17:
502	/* Valid error codes. */
503	Event.n.u1ErrorCodeValid = 1;
504	break;
505	default:
506	break;
507	}
508	if (u8Vector == X86_XCPT_NMI)
509	Event.n.u3Type = SVM_EVENT_NMI;
510	else
511	Event.n.u3Type = SVM_EVENT_EXCEPTION;
512	}
513	else
514	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
515
516	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
517	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
518	} /* if (interrupts can be dispatched) */
519
520	return VINF_SUCCESS;
521	}
522
523	/**
524	* Save the host state
525	*
526	* @returns VBox status code.
527	* @param pVM The VM to operate on.
528	* @param pVCpu The VM CPU to operate on.
529	*/
530	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
531	{
532	NOREF(pVM);
533	NOREF(pVCpu);
534	/* Nothing to do here. */
535	return VINF_SUCCESS;
536	}
537
538	/**
539	* Loads the guest state
540	*
541	* NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
542	*
543	* @returns VBox status code.
544	* @param pVM The VM to operate on.
545	* @param pVCpu The VM CPU to operate on.
546	* @param pCtx Guest context
547	*/
548	VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
549	{
550	RTGCUINTPTR val;
551	SVM_VMCB *pVMCB;
552
553	if (pVM == NULL)
554	return VERR_INVALID_PARAMETER;
555
556	/* Setup AMD SVM. */
557	Assert(pVM->hwaccm.s.svm.fSupported);
558
559	pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
560	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
561
562	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
563	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
564	{
565	SVM_WRITE_SELREG(CS, cs);
566	SVM_WRITE_SELREG(SS, ss);
567	SVM_WRITE_SELREG(DS, ds);
568	SVM_WRITE_SELREG(ES, es);
569	SVM_WRITE_SELREG(FS, fs);
570	SVM_WRITE_SELREG(GS, gs);
571	}
572
573	/* Guest CPU context: LDTR. */
574	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
575	{
576	SVM_WRITE_SELREG(LDTR, ldtr);
577	}
578
579	/* Guest CPU context: TR. */
580	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
581	{
582	SVM_WRITE_SELREG(TR, tr);
583	}
584
585	/* Guest CPU context: GDTR. */
586	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
587	{
588	pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
589	pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
590	}
591
592	/* Guest CPU context: IDTR. */
593	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
594	{
595	pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
596	pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
597	}
598
599	/*
600	* Sysenter MSRs (unconditional)
601	*/
602	pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
603	pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
604	pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
605
606	/* Control registers */
607	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
608	{
609	val = pCtx->cr0;
610	if (!CPUMIsGuestFPUStateActive(pVCpu))
611	{
612	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
613	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
614	}
615	else
616	{
617	/** @todo check if we support the old style mess correctly. */
618	if (!(val & X86_CR0_NE))
619	{
620	Log(("Forcing X86_CR0_NE!!!\n"));
621
622	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
623	if (!pVCpu->hwaccm.s.fFPUOldStyleOverride)
624	{
625	pVMCB->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_MF);
626	pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
627	}
628	}
629	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
630	}
631	/* Always enable caching. */
632	val &= ~(X86_CR0_CD\|X86_CR0_NW);
633
634	/* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
635	/* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
636	if (!pVM->hwaccm.s.fNestedPaging)
637	{
638	val \|= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
639	val \|= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
640	}
641	pVMCB->guest.u64CR0 = val;
642	}
643	/* CR2 as well */
644	pVMCB->guest.u64CR2 = pCtx->cr2;
645
646	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
647	{
648	/* Save our shadow CR3 register. */
649	if (pVM->hwaccm.s.fNestedPaging)
650	{
651	pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVM, PGMGetHostMode(pVM));
652	Assert(pVMCB->ctrl.u64NestedPagingCR3);
653	pVMCB->guest.u64CR3 = pCtx->cr3;
654	}
655	else
656	{
657	pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
658	Assert(pVMCB->guest.u64CR3);
659	}
660	}
661
662	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
663	{
664	val = pCtx->cr4;
665	if (!pVM->hwaccm.s.fNestedPaging)
666	{
667	switch(pVCpu->hwaccm.s.enmShadowMode)
668	{
669	case PGMMODE_REAL:
670	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
671	AssertFailed();
672	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
673
674	case PGMMODE_32_BIT: /* 32-bit paging. */
675	break;
676
677	case PGMMODE_PAE: /* PAE paging. */
678	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
679	/** @todo use normal 32 bits paging */
680	val \|= X86_CR4_PAE;
681	break;
682
683	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
684	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
685	#ifdef VBOX_ENABLE_64_BITS_GUESTS
686	break;
687	#else
688	AssertFailed();
689	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
690	#endif
691
692	default: /* shut up gcc */
693	AssertFailed();
694	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
695	}
696	}
697	pVMCB->guest.u64CR4 = val;
698	}
699
700	/* Debug registers. */
701	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
702	{
703	pCtx->dr[6] \|= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
704	pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
705
706	pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
707	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
708	pCtx->dr[7] \|= 0x400; /* must be one */
709
710	pVMCB->guest.u64DR7 = pCtx->dr[7];
711	pVMCB->guest.u64DR6 = pCtx->dr[6];
712
713	/* Sync the debug state now if any breakpoint is armed. */
714	if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK\|X86_DR7_GD))
715	&& !CPUMIsGuestDebugStateActive(pVM)
716	&& !DBGFIsStepping(pVM))
717	{
718	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
719
720	/* Disable drx move intercepts. */
721	pVMCB->ctrl.u16InterceptRdDRx = 0;
722	pVMCB->ctrl.u16InterceptWrDRx = 0;
723
724	/* Save the host and load the guest debug state. */
725	int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
726	AssertRC(rc);
727	}
728	}
729
730	/* EIP, ESP and EFLAGS */
731	pVMCB->guest.u64RIP = pCtx->rip;
732	pVMCB->guest.u64RSP = pCtx->rsp;
733	pVMCB->guest.u64RFlags = pCtx->eflags.u32;
734
735	/* Set CPL */
736	pVMCB->guest.u8CPL = pCtx->csHid.Attr.n.u2Dpl;
737
738	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
739	pVMCB->guest.u64RAX = pCtx->rax;
740
741	/* vmrun will fail without MSR_K6_EFER_SVME. */
742	pVMCB->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
743
744	/* 64 bits guest mode? */
745	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
746	{
747	#if !defined(VBOX_WITH_64_BITS_GUESTS) \|\| HC_ARCH_BITS != 64
748	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
749	#else
750	pVCpu->hwaccm.s.svm.pfnVMRun = SVMVMRun64;
751	#endif
752	/* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
753	pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
754	pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
755	}
756	else
757	{
758	/* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
759	pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
760
761	pVCpu->hwaccm.s.svm.pfnVMRun = SVMVMRun;
762	}
763
764	/* TSC offset. */
765	if (TMCpuTickCanUseRealTSC(pVM, &pVMCB->ctrl.u64TSCOffset))
766	{
767	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
768	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
769	}
770	else
771	{
772	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
773	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
774	}
775
776	/* Sync the various msrs for 64 bits mode. */
777	pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
778	pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
779	pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
780	pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
781	pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
782
783	#ifdef DEBUG
784	/* Intercept X86_XCPT_DB if stepping is enabled */
785	if (DBGFIsStepping(pVM))
786	pVMCB->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_DB);
787	else
788	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_DB);
789	#endif
790
791	/* Done. */
792	pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
793
794	return VINF_SUCCESS;
795	}
796
797
798	/**
799	* Runs guest code in an AMD-V VM.
800	*
801	* @returns VBox status code.
802	* @param pVM The VM to operate on.
803	* @param pVCpu The VM CPU to operate on.
804	* @param pCtx Guest context
805	*/
806	VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
807	{
808	int rc = VINF_SUCCESS;
809	uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
810	SVM_VMCB *pVMCB;
811	bool fSyncTPR = false;
812	unsigned cResume = 0;
813	uint8_t u8LastVTPR;
814	PHWACCM_CPUINFO pCpu = 0;
815	#ifdef VBOX_STRICT
816	RTCPUID idCpuCheck;
817	#endif
818
819	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
820
821	pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
822	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
823
824	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
825	*/
826	ResumeExecution:
827	Assert(!HWACCMR0SuspendPending());
828
829	/* Safety precaution; looping for too long here can have a very bad effect on the host */
830	if (++cResume > HWACCM_MAX_RESUME_LOOPS)
831	{
832	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
833	rc = VINF_EM_RAW_INTERRUPT;
834	goto end;
835	}
836
837	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
838	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
839	{
840	Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
841	if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
842	{
843	/* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
844	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
845	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
846	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
847	*/
848	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
849	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
850	pVMCB->ctrl.u64IntShadow = 0;
851	}
852	}
853	else
854	{
855	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
856	pVMCB->ctrl.u64IntShadow = 0;
857	}
858
859	/* Check for pending actions that force us to go back to ring 3. */
860	#ifdef DEBUG
861	/* Intercept X86_XCPT_DB if stepping is enabled */
862	if (!DBGFIsStepping(pVM))
863	#endif
864	{
865	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
866	{
867	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
868	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
869	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
870	rc = VINF_EM_RAW_TO_R3;
871	goto end;
872	}
873	}
874
875	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
876	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
877	{
878	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
879	rc = VINF_EM_PENDING_REQUEST;
880	goto end;
881	}
882
883	/* When external interrupts are pending, we should exit the VM when IF is set. */
884	/* Note! After VM_FF_INHIBIT_INTERRUPTS check!!! */
885	rc = SVMR0CheckPendingInterrupt(pVM, pVCpu, pVMCB, pCtx);
886	if (RT_FAILURE(rc))
887	{
888	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
889	goto end;
890	}
891
892	/* TPR caching using CR8 is only available in 64 bits mode */
893	/* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
894	/* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! */
895	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
896	{
897	bool fPending;
898
899	/* TPR caching in CR8 */
900	int rc = PDMApicGetTPR(pVM, &u8LastVTPR, &fPending);
901	AssertRC(rc);
902	pVMCB->ctrl.IntCtrl.n.u8VTPR = u8LastVTPR;
903
904	if (fPending)
905	{
906	/* A TPR change could activate a pending interrupt, so catch cr8 writes. */
907	pVMCB->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
908	}
909	else
910	/* No interrupts are pending, so we don't need to be explicitely notified.
911	* There are enough world switches for detecting pending interrupts.
912	*/
913	pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
914
915	fSyncTPR = !fPending;
916	}
917
918	/* All done! Let's start VM execution. */
919	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, x);
920
921	/* Enable nested paging if necessary (disabled each time after #VMEXIT). */
922	pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
923
924	#ifdef LOG_ENABLED
925	pCpu = HWACCMR0GetCurrentCpu();
926	if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
927	\|\| pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
928	{
929	if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
930	Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
931	else
932	Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
933	}
934	if (pCpu->fFlushTLB)
935	Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
936	#endif
937
938	/*
939	* NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
940	* (until the actual world switch)
941	*/
942
943	#ifdef VBOX_STRICT
944	idCpuCheck = RTMpCpuId();
945	#endif
946
947	/* Load the guest state; must be here as it sets up the shadow cr0 for lazy fpu syncing! */
948	rc = SVMR0LoadGuestState(pVM, pVCpu, pCtx);
949	if (rc != VINF_SUCCESS)
950	{
951	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
952	goto end;
953	}
954
955	pCpu = HWACCMR0GetCurrentCpu();
956	/* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
957	/* Note that this can happen both for start and resume due to long jumps back to ring 3. */
958	if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
959	/* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
960	\|\| pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
961	{
962	/* Force a TLB flush on VM entry. */
963	pVCpu->hwaccm.s.fForceTLBFlush = true;
964	}
965	else
966	Assert(!pCpu->fFlushTLB \|\| pVM->hwaccm.s.svm.fAlwaysFlushTLB);
967
968	pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
969
970	/* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
971	if ( pVCpu->hwaccm.s.fForceTLBFlush
972	&& !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
973	{
974	if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
975	\|\| pCpu->fFlushTLB)
976	{
977	pCpu->fFlushTLB = false;
978	pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
979	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
980	pCpu->cTLBFlushes++;
981	}
982	else
983	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
984
985	pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
986	pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
987	}
988	else
989	{
990	Assert(!pCpu->fFlushTLB \|\| pVM->hwaccm.s.svm.fAlwaysFlushTLB);
991
992	/* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
993	if (!pCpu->uCurrentASID \|\| !pVCpu->hwaccm.s.uCurrentASID)
994	pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
995
996	Assert(!pVM->hwaccm.s.svm.fAlwaysFlushTLB \|\| pVCpu->hwaccm.s.fForceTLBFlush);
997	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVCpu->hwaccm.s.fForceTLBFlush;
998	}
999	AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1000	AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1001	AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1002	pVMCB->ctrl.TLBCtrl.n.u32ASID = pVCpu->hwaccm.s.uCurrentASID;
1003
1004	#ifdef VBOX_WITH_STATISTICS
1005	if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
1006	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1007	else
1008	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1009	#endif
1010
1011	/* In case we execute a goto ResumeExecution later on. */
1012	pVCpu->hwaccm.s.fResumeVM = true;
1013	pVCpu->hwaccm.s.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
1014
1015	Assert(sizeof(pVCpu->hwaccm.s.svm.pVMCBPhys) == 8);
1016	Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
1017	\| SVM_CTRL2_INTERCEPT_VMMCALL
1018	\| SVM_CTRL2_INTERCEPT_VMLOAD
1019	\| SVM_CTRL2_INTERCEPT_VMSAVE
1020	\| SVM_CTRL2_INTERCEPT_STGI
1021	\| SVM_CTRL2_INTERCEPT_CLGI
1022	\| SVM_CTRL2_INTERCEPT_SKINIT
1023	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
1024	\| SVM_CTRL2_INTERCEPT_WBINVD
1025	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
1026	));
1027	Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
1028	Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
1029	Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
1030	Assert(pVMCB->ctrl.u64LBRVirt == 0);
1031
1032	#ifdef VBOX_STRICT
1033	Assert(idCpuCheck == RTMpCpuId());
1034	#endif
1035	TMNotifyStartOfExecution(pVM);
1036	pVCpu->hwaccm.s.svm.pfnVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx);
1037	TMNotifyEndOfExecution(pVM);
1038	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, x);
1039
1040	/*
1041	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1042	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1043	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1044	*/
1045
1046	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit, x);
1047
1048	/* Reason for the VM exit */
1049	exitCode = pVMCB->ctrl.u64ExitCode;
1050
1051	if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
1052	{
1053	HWACCMDumpRegs(pVM, pCtx);
1054	#ifdef DEBUG
1055	Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
1056	Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
1057	Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
1058	Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
1059	Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
1060	Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
1061	Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
1062	Log(("ctrl.u64IOPMPhysAddr %RX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
1063	Log(("ctrl.u64MSRPMPhysAddr %RX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
1064	Log(("ctrl.u64TSCOffset %RX64\n", pVMCB->ctrl.u64TSCOffset));
1065
1066	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
1067	Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
1068	Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
1069	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
1070
1071	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
1072	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
1073	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
1074	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
1075	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
1076	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
1077	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
1078	Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
1079	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
1080	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
1081
1082	Log(("ctrl.u64IntShadow %RX64\n", pVMCB->ctrl.u64IntShadow));
1083	Log(("ctrl.u64ExitCode %RX64\n", pVMCB->ctrl.u64ExitCode));
1084	Log(("ctrl.u64ExitInfo1 %RX64\n", pVMCB->ctrl.u64ExitInfo1));
1085	Log(("ctrl.u64ExitInfo2 %RX64\n", pVMCB->ctrl.u64ExitInfo2));
1086	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
1087	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
1088	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
1089	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
1090	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
1091	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
1092	Log(("ctrl.NestedPaging %RX64\n", pVMCB->ctrl.NestedPaging.au64));
1093	Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
1094	Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
1095	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
1096	Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
1097	Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
1098	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
1099
1100	Log(("ctrl.u64NestedPagingCR3 %RX64\n", pVMCB->ctrl.u64NestedPagingCR3));
1101	Log(("ctrl.u64LBRVirt %RX64\n", pVMCB->ctrl.u64LBRVirt));
1102
1103	Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
1104	Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1105	Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1106	Log(("guest.CS.u64Base %RX64\n", pVMCB->guest.CS.u64Base));
1107	Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1108	Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1109	Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1110	Log(("guest.DS.u64Base %RX64\n", pVMCB->guest.DS.u64Base));
1111	Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1112	Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1113	Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1114	Log(("guest.ES.u64Base %RX64\n", pVMCB->guest.ES.u64Base));
1115	Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1116	Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1117	Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1118	Log(("guest.FS.u64Base %RX64\n", pVMCB->guest.FS.u64Base));
1119	Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1120	Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1121	Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1122	Log(("guest.GS.u64Base %RX64\n", pVMCB->guest.GS.u64Base));
1123
1124	Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1125	Log(("guest.GDTR.u64Base %RX64\n", pVMCB->guest.GDTR.u64Base));
1126
1127	Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1128	Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1129	Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1130	Log(("guest.LDTR.u64Base %RX64\n", pVMCB->guest.LDTR.u64Base));
1131
1132	Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1133	Log(("guest.IDTR.u64Base %RX64\n", pVMCB->guest.IDTR.u64Base));
1134
1135	Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1136	Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1137	Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1138	Log(("guest.TR.u64Base %RX64\n", pVMCB->guest.TR.u64Base));
1139
1140	Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1141	Log(("guest.u64CR0 %RX64\n", pVMCB->guest.u64CR0));
1142	Log(("guest.u64CR2 %RX64\n", pVMCB->guest.u64CR2));
1143	Log(("guest.u64CR3 %RX64\n", pVMCB->guest.u64CR3));
1144	Log(("guest.u64CR4 %RX64\n", pVMCB->guest.u64CR4));
1145	Log(("guest.u64DR6 %RX64\n", pVMCB->guest.u64DR6));
1146	Log(("guest.u64DR7 %RX64\n", pVMCB->guest.u64DR7));
1147
1148	Log(("guest.u64RIP %RX64\n", pVMCB->guest.u64RIP));
1149	Log(("guest.u64RSP %RX64\n", pVMCB->guest.u64RSP));
1150	Log(("guest.u64RAX %RX64\n", pVMCB->guest.u64RAX));
1151	Log(("guest.u64RFlags %RX64\n", pVMCB->guest.u64RFlags));
1152
1153	Log(("guest.u64SysEnterCS %RX64\n", pVMCB->guest.u64SysEnterCS));
1154	Log(("guest.u64SysEnterEIP %RX64\n", pVMCB->guest.u64SysEnterEIP));
1155	Log(("guest.u64SysEnterESP %RX64\n", pVMCB->guest.u64SysEnterESP));
1156
1157	Log(("guest.u64EFER %RX64\n", pVMCB->guest.u64EFER));
1158	Log(("guest.u64STAR %RX64\n", pVMCB->guest.u64STAR));
1159	Log(("guest.u64LSTAR %RX64\n", pVMCB->guest.u64LSTAR));
1160	Log(("guest.u64CSTAR %RX64\n", pVMCB->guest.u64CSTAR));
1161	Log(("guest.u64SFMASK %RX64\n", pVMCB->guest.u64SFMASK));
1162	Log(("guest.u64KernelGSBase %RX64\n", pVMCB->guest.u64KernelGSBase));
1163	Log(("guest.u64GPAT %RX64\n", pVMCB->guest.u64GPAT));
1164	Log(("guest.u64DBGCTL %RX64\n", pVMCB->guest.u64DBGCTL));
1165	Log(("guest.u64BR_FROM %RX64\n", pVMCB->guest.u64BR_FROM));
1166	Log(("guest.u64BR_TO %RX64\n", pVMCB->guest.u64BR_TO));
1167	Log(("guest.u64LASTEXCPFROM %RX64\n", pVMCB->guest.u64LASTEXCPFROM));
1168	Log(("guest.u64LASTEXCPTO %RX64\n", pVMCB->guest.u64LASTEXCPTO));
1169
1170	#endif
1171	rc = VERR_SVM_UNABLE_TO_START_VM;
1172	goto end;
1173	}
1174
1175	/* Let's first sync back eip, esp, and eflags. */
1176	pCtx->rip = pVMCB->guest.u64RIP;
1177	pCtx->rsp = pVMCB->guest.u64RSP;
1178	pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1179	/* eax is saved/restore across the vmrun instruction */
1180	pCtx->rax = pVMCB->guest.u64RAX;
1181
1182	pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
1183
1184	/* Can be updated behind our back in the nested paging case. */
1185	pCtx->cr2 = pVMCB->guest.u64CR2;
1186
1187	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1188	SVM_READ_SELREG(SS, ss);
1189	SVM_READ_SELREG(CS, cs);
1190	SVM_READ_SELREG(DS, ds);
1191	SVM_READ_SELREG(ES, es);
1192	SVM_READ_SELREG(FS, fs);
1193	SVM_READ_SELREG(GS, gs);
1194
1195	/*
1196	* System MSRs
1197	*/
1198	pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1199	pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1200	pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1201
1202	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1203	SVM_READ_SELREG(LDTR, ldtr);
1204	SVM_READ_SELREG(TR, tr);
1205
1206	pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1207	pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1208
1209	pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1210	pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1211
1212	/* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1213	/* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1214	if ( pVM->hwaccm.s.fNestedPaging
1215	&& pCtx->cr3 != pVMCB->guest.u64CR3)
1216	{
1217	CPUMSetGuestCR3(pVM, pVMCB->guest.u64CR3);
1218	PGMUpdateCR3(pVM, pVMCB->guest.u64CR3);
1219	}
1220
1221	/* Note! NOW IT'S SAFE FOR LOGGING! */
1222
1223	/* Take care of instruction fusing (sti, mov ss) (see 15.20.5 Interrupt Shadows) */
1224	if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1225	{
1226	Log(("uInterruptState %x rip=%RGv\n", pVMCB->ctrl.u64IntShadow, (RTGCPTR)pCtx->rip));
1227	EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1228	}
1229	else
1230	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1231
1232	Log2(("exitCode = %x\n", exitCode));
1233
1234	/* Sync back DR6 as it could have been changed by hitting breakpoints. */
1235	pCtx->dr[6] = pVMCB->guest.u64DR6;
1236	/* DR7.GD can be cleared by debug exceptions, so sync it back as well. */
1237	pCtx->dr[7] = pVMCB->guest.u64DR7;
1238
1239	/* Check if an injected event was interrupted prematurely. */
1240	pVCpu->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1241	if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1242	&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1243	{
1244	Log(("Pending inject %RX64 at %RGv exit=%08x\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitCode));
1245
1246	#ifdef LOG_ENABLED
1247	SVM_EVENT Event;
1248	Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
1249
1250	if ( exitCode == SVM_EXIT_EXCEPTION_E
1251	&& Event.n.u8Vector == 0xE)
1252	{
1253	Log(("Double fault!\n"));
1254	}
1255	#endif
1256
1257	pVCpu->hwaccm.s.Event.fPending = true;
1258	/* Error code present? (redundant) */
1259	if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1260	{
1261	pVCpu->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1262	}
1263	else
1264	pVCpu->hwaccm.s.Event.errCode = 0;
1265	}
1266	#ifdef VBOX_WITH_STATISTICS
1267	if (exitCode == SVM_EXIT_NPF)
1268	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
1269	else
1270	STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1271	#endif
1272
1273	if (fSyncTPR)
1274	{
1275	rc = PDMApicSetTPR(pVM, pVMCB->ctrl.IntCtrl.n.u8VTPR);
1276	AssertRC(rc);
1277	}
1278
1279	/* Deal with the reason of the VM-exit. */
1280	switch (exitCode)
1281	{
1282	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1283	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1284	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1285	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1286	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1287	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1288	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1289	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1290	{
1291	/* Pending trap. */
1292	SVM_EVENT Event;
1293	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1294
1295	Log2(("Hardware/software interrupt %d\n", vector));
1296	switch (vector)
1297	{
1298	case X86_XCPT_DB:
1299	{
1300	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
1301
1302	/* Note that we don't support guest and host-initiated debugging at the same time. */
1303	Assert(DBGFIsStepping(pVM));
1304
1305	rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
1306	if (rc == VINF_EM_RAW_GUEST_TRAP)
1307	{
1308	Log(("Trap %x (debug) at %016RX64\n", vector, pCtx->rip));
1309
1310	/* Reinject the exception. */
1311	Event.au64[0] = 0;
1312	Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
1313	Event.n.u1Valid = 1;
1314	Event.n.u8Vector = X86_XCPT_DB;
1315
1316	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1317
1318	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1319	goto ResumeExecution;
1320	}
1321	/* Return to ring 3 to deal with the debug exit code. */
1322	break;
1323	}
1324
1325	case X86_XCPT_NM:
1326	{
1327	Log(("#NM fault at %RGv\n", (RTGCPTR)pCtx->rip));
1328
1329	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1330	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1331	rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
1332	if (rc == VINF_SUCCESS)
1333	{
1334	Assert(CPUMIsGuestFPUStateActive(pVCpu));
1335	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
1336
1337	/* Continue execution. */
1338	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1339	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1340
1341	goto ResumeExecution;
1342	}
1343
1344	Log(("Forward #NM fault to the guest\n"));
1345	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
1346
1347	Event.au64[0] = 0;
1348	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1349	Event.n.u1Valid = 1;
1350	Event.n.u8Vector = X86_XCPT_NM;
1351
1352	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1353	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1354	goto ResumeExecution;
1355	}
1356
1357	case X86_XCPT_PF: /* Page fault */
1358	{
1359	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1360	RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1361
1362	#ifdef DEBUG
1363	if (pVM->hwaccm.s.fNestedPaging)
1364	{ /* A genuine pagefault.
1365	* Forward the trap to the guest by injecting the exception and resuming execution.
1366	*/
1367	Log(("Guest page fault at %RGv cr2=%RGv error code %x rsp=%RGv\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
1368	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1369
1370	/* Now we must update CR2. */
1371	pCtx->cr2 = uFaultAddress;
1372
1373	Event.au64[0] = 0;
1374	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1375	Event.n.u1Valid = 1;
1376	Event.n.u8Vector = X86_XCPT_PF;
1377	Event.n.u1ErrorCodeValid = 1;
1378	Event.n.u32ErrorCode = errCode;
1379
1380	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1381
1382	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1383	goto ResumeExecution;
1384	}
1385	#endif
1386	Assert(!pVM->hwaccm.s.fNestedPaging);
1387
1388	Log2(("Page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1389	/* Exit qualification contains the linear address of the page fault. */
1390	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1391	TRPMSetErrorCode(pVM, errCode);
1392	TRPMSetFaultAddress(pVM, uFaultAddress);
1393
1394	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1395	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1396	Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1397	if (rc == VINF_SUCCESS)
1398	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1399	Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1400	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1401
1402	TRPMResetTrap(pVM);
1403
1404	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1405	goto ResumeExecution;
1406	}
1407	else
1408	if (rc == VINF_EM_RAW_GUEST_TRAP)
1409	{ /* A genuine pagefault.
1410	* Forward the trap to the guest by injecting the exception and resuming execution.
1411	*/
1412	Log2(("Forward page fault to the guest\n"));
1413	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1414	/* The error code might have been changed. */
1415	errCode = TRPMGetErrorCode(pVM);
1416
1417	TRPMResetTrap(pVM);
1418
1419	/* Now we must update CR2. */
1420	pCtx->cr2 = uFaultAddress;
1421
1422	Event.au64[0] = 0;
1423	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1424	Event.n.u1Valid = 1;
1425	Event.n.u8Vector = X86_XCPT_PF;
1426	Event.n.u1ErrorCodeValid = 1;
1427	Event.n.u32ErrorCode = errCode;
1428
1429	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1430
1431	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1432	goto ResumeExecution;
1433	}
1434	#ifdef VBOX_STRICT
1435	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1436	LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
1437	#endif
1438	/* Need to go back to the recompiler to emulate the instruction. */
1439	TRPMResetTrap(pVM);
1440	break;
1441	}
1442
1443	case X86_XCPT_MF: /* Floating point exception. */
1444	{
1445	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
1446	if (!(pCtx->cr0 & X86_CR0_NE))
1447	{
1448	/* old style FPU error reporting needs some extra work. */
1449	/** @todo don't fall back to the recompiler, but do it manually. */
1450	rc = VINF_EM_RAW_EMULATE_INSTR;
1451	break;
1452	}
1453	Log(("Trap %x at %RGv\n", vector, (RTGCPTR)pCtx->rip));
1454
1455	Event.au64[0] = 0;
1456	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1457	Event.n.u1Valid = 1;
1458	Event.n.u8Vector = X86_XCPT_MF;
1459
1460	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1461
1462	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1463	goto ResumeExecution;
1464	}
1465
1466	#ifdef VBOX_STRICT
1467	case X86_XCPT_GP: /* General protection failure exception.*/
1468	case X86_XCPT_UD: /* Unknown opcode exception. */
1469	case X86_XCPT_DE: /* Divide error. */
1470	case X86_XCPT_SS: /* Stack segment exception. */
1471	case X86_XCPT_NP: /* Segment not present exception. */
1472	{
1473	Event.au64[0] = 0;
1474	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1475	Event.n.u1Valid = 1;
1476	Event.n.u8Vector = vector;
1477
1478	switch(vector)
1479	{
1480	case X86_XCPT_GP:
1481	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
1482	Event.n.u1ErrorCodeValid = 1;
1483	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1484	break;
1485	case X86_XCPT_DE:
1486	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
1487	break;
1488	case X86_XCPT_UD:
1489	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
1490	break;
1491	case X86_XCPT_SS:
1492	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
1493	Event.n.u1ErrorCodeValid = 1;
1494	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1495	break;
1496	case X86_XCPT_NP:
1497	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
1498	Event.n.u1ErrorCodeValid = 1;
1499	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1500	break;
1501	}
1502	Log(("Trap %x at %RGv esi=%x\n", vector, (RTGCPTR)pCtx->rip, pCtx->esi));
1503	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1504
1505	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1506	goto ResumeExecution;
1507	}
1508	#endif
1509	default:
1510	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1511	rc = VERR_EM_INTERNAL_ERROR;
1512	break;
1513
1514	} /* switch (vector) */
1515	break;
1516	}
1517
1518	case SVM_EXIT_NPF:
1519	{
1520	/* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1521	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1522	RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1523
1524	Assert(pVM->hwaccm.s.fNestedPaging);
1525	Log(("Nested page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1526	/* Exit qualification contains the linear address of the page fault. */
1527	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1528	TRPMSetErrorCode(pVM, errCode);
1529	TRPMSetFaultAddress(pVM, uFaultAddress);
1530
1531	/* Handle the pagefault trap for the nested shadow table. */
1532	rc = PGMR0Trap0eHandlerNestedPaging(pVM, PGMGetHostMode(pVM), errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1533	Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1534	if (rc == VINF_SUCCESS)
1535	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1536	Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1537	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1538
1539	TRPMResetTrap(pVM);
1540
1541	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1542	goto ResumeExecution;
1543	}
1544
1545	#ifdef VBOX_STRICT
1546	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1547	LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
1548	#endif
1549	/* Need to go back to the recompiler to emulate the instruction. */
1550	TRPMResetTrap(pVM);
1551	break;
1552	}
1553
1554	case SVM_EXIT_VINTR:
1555	/* A virtual interrupt is about to be delivered, which means IF=1. */
1556	Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1557	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1558	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1559	goto ResumeExecution;
1560
1561	case SVM_EXIT_FERR_FREEZE:
1562	case SVM_EXIT_INTR:
1563	case SVM_EXIT_NMI:
1564	case SVM_EXIT_SMI:
1565	case SVM_EXIT_INIT:
1566	/* External interrupt; leave to allow it to be dispatched again. */
1567	rc = VINF_EM_RAW_INTERRUPT;
1568	break;
1569
1570	case SVM_EXIT_WBINVD:
1571	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1572	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
1573	/* Skip instruction and continue directly. */
1574	pCtx->rip += 2; /* Note! hardcoded opcode size! */
1575	/* Continue execution.*/
1576	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1577	goto ResumeExecution;
1578
1579	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1580	{
1581	Log2(("SVM: Cpuid at %RGv for %x\n", (RTGCPTR)pCtx->rip, pCtx->eax));
1582	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
1583	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1584	if (rc == VINF_SUCCESS)
1585	{
1586	/* Update EIP and continue execution. */
1587	pCtx->rip += 2; /* Note! hardcoded opcode size! */
1588	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1589	goto ResumeExecution;
1590	}
1591	AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
1592	rc = VINF_EM_RAW_EMULATE_INSTR;
1593	break;
1594	}
1595
1596	case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1597	{
1598	Log2(("SVM: Rdtsc\n"));
1599	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1600	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1601	if (rc == VINF_SUCCESS)
1602	{
1603	/* Update EIP and continue execution. */
1604	pCtx->rip += 2; /* Note! hardcoded opcode size! */
1605	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1606	goto ResumeExecution;
1607	}
1608	AssertMsgFailed(("EMU: rdtsc failed with %Rrc\n", rc));
1609	rc = VINF_EM_RAW_EMULATE_INSTR;
1610	break;
1611	}
1612
1613	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1614	{
1615	Log2(("SVM: invlpg\n"));
1616	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
1617
1618	Assert(!pVM->hwaccm.s.fNestedPaging);
1619
1620	/* Truly a pita. Why can't SVM give the same information as VT-x? */
1621	rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1622	if (rc == VINF_SUCCESS)
1623	{
1624	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushPageInvlpg);
1625	goto ResumeExecution; /* eip already updated */
1626	}
1627	break;
1628	}
1629
1630	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1631	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1632	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1633	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1634	{
1635	uint32_t cbSize;
1636
1637	Log2(("SVM: %RGv mov cr%d, \n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
1638	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite);
1639	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1640
1641	switch (exitCode - SVM_EXIT_WRITE_CR0)
1642	{
1643	case 0:
1644	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1645	break;
1646	case 2:
1647	break;
1648	case 3:
1649	Assert(!pVM->hwaccm.s.fNestedPaging);
1650	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1651	break;
1652	case 4:
1653	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1654	break;
1655	case 8:
1656	break;
1657	default:
1658	AssertFailed();
1659	}
1660	/* Check if a sync operation is pending. */
1661	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1662	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1663	{
1664	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1665	AssertRC(rc);
1666
1667	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBCRxChange);
1668
1669	/* Must be set by PGMSyncCR3 */
1670	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PROTECTED \|\| pVCpu->hwaccm.s.fForceTLBFlush);
1671	}
1672	if (rc == VINF_SUCCESS)
1673	{
1674	/* EIP has been updated already. */
1675
1676	/* Only resume if successful. */
1677	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1678	goto ResumeExecution;
1679	}
1680	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1681	break;
1682	}
1683
1684	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1685	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1686	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1687	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1688	{
1689	uint32_t cbSize;
1690
1691	Log2(("SVM: %RGv mov x, cr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
1692	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead);
1693	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1694	if (rc == VINF_SUCCESS)
1695	{
1696	/* EIP has been updated already. */
1697
1698	/* Only resume if successful. */
1699	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1700	goto ResumeExecution;
1701	}
1702	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1703	break;
1704	}
1705
1706	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1707	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1708	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1709	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1710	{
1711	uint32_t cbSize;
1712
1713	Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
1714	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
1715
1716	if (!DBGFIsStepping(pVM))
1717	{
1718	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
1719
1720	/* Disable drx move intercepts. */
1721	pVMCB->ctrl.u16InterceptRdDRx = 0;
1722	pVMCB->ctrl.u16InterceptWrDRx = 0;
1723
1724	/* Save the host and load the guest debug state. */
1725	rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
1726	AssertRC(rc);
1727
1728	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1729	goto ResumeExecution;
1730	}
1731
1732	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1733	if (rc == VINF_SUCCESS)
1734	{
1735	/* EIP has been updated already. */
1736	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_DEBUG;
1737
1738	/* Only resume if successful. */
1739	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1740	goto ResumeExecution;
1741	}
1742	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1743	break;
1744	}
1745
1746	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1747	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1748	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1749	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1750	{
1751	uint32_t cbSize;
1752
1753	Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
1754	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
1755
1756	if (!DBGFIsStepping(pVM))
1757	{
1758	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
1759
1760	/* Disable drx move intercepts. */
1761	pVMCB->ctrl.u16InterceptRdDRx = 0;
1762	pVMCB->ctrl.u16InterceptWrDRx = 0;
1763
1764	/* Save the host and load the guest debug state. */
1765	rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
1766	AssertRC(rc);
1767
1768	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1769	goto ResumeExecution;
1770	}
1771
1772	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1773	if (rc == VINF_SUCCESS)
1774	{
1775	/* EIP has been updated already. */
1776
1777	/* Only resume if successful. */
1778	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1779	goto ResumeExecution;
1780	}
1781	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1782	break;
1783	}
1784
1785	/* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1786	case SVM_EXIT_IOIO: /* I/O instruction. */
1787	{
1788	SVM_IOIO_EXIT IoExitInfo;
1789	uint32_t uIOSize, uAndVal;
1790
1791	IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1792
1793	/** @todo could use a lookup table here */
1794	if (IoExitInfo.n.u1OP8)
1795	{
1796	uIOSize = 1;
1797	uAndVal = 0xff;
1798	}
1799	else
1800	if (IoExitInfo.n.u1OP16)
1801	{
1802	uIOSize = 2;
1803	uAndVal = 0xffff;
1804	}
1805	else
1806	if (IoExitInfo.n.u1OP32)
1807	{
1808	uIOSize = 4;
1809	uAndVal = 0xffffffff;
1810	}
1811	else
1812	{
1813	AssertFailed(); /* should be fatal. */
1814	rc = VINF_EM_RAW_EMULATE_INSTR;
1815	break;
1816	}
1817
1818	if (IoExitInfo.n.u1STR)
1819	{
1820	/* ins/outs */
1821	uint32_t prefix = 0;
1822	if (IoExitInfo.n.u1REP)
1823	prefix \|= PREFIX_REP;
1824
1825	if (IoExitInfo.n.u1Type == 0)
1826	{
1827	Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1828	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
1829	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1830	}
1831	else
1832	{
1833	Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1834	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
1835	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1836	}
1837	}
1838	else
1839	{
1840	/* normal in/out */
1841	Assert(!IoExitInfo.n.u1REP);
1842
1843	if (IoExitInfo.n.u1Type == 0)
1844	{
1845	Log2(("IOMIOPortWrite %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1846	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
1847	rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1848	}
1849	else
1850	{
1851	uint32_t u32Val = 0;
1852
1853	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
1854	rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1855	if (IOM_SUCCESS(rc))
1856	{
1857	/* Write back to the EAX register. */
1858	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1859	Log2(("IOMIOPortRead %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1860	}
1861	}
1862	}
1863	/*
1864	* Handled the I/O return codes.
1865	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1866	*/
1867	if (IOM_SUCCESS(rc))
1868	{
1869	/* Update EIP and continue execution. */
1870	pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1871	if (RT_LIKELY(rc == VINF_SUCCESS))
1872	{
1873	/* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
1874	if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
1875	{
1876	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
1877	for (unsigned i=0;i<4;i++)
1878	{
1879	unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
1880
1881	if ( (IoExitInfo.n.u16Port >= pCtx->dr[i] && IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen)
1882	&& (pCtx->dr[7] & (X86_DR7_L(i) \| X86_DR7_G(i)))
1883	&& (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
1884	{
1885	SVM_EVENT Event;
1886
1887	Assert(CPUMIsGuestDebugStateActive(pVM));
1888
1889	/* Clear all breakpoint status flags and set the one we just hit. */
1890	pCtx->dr[6] &= ~(X86_DR6_B0\|X86_DR6_B1\|X86_DR6_B2\|X86_DR6_B3);
1891	pCtx->dr[6] \|= (uint64_t)RT_BIT(i);
1892
1893	/* Note: AMD64 Architecture Programmer's Manual 13.1:
1894	* Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
1895	* the contents have been read.
1896	*/
1897	pVMCB->guest.u64DR6 = pCtx->dr[6];
1898
1899	/* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
1900	pCtx->dr[7] &= ~X86_DR7_GD;
1901
1902	/* Paranoia. */
1903	pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
1904	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
1905	pCtx->dr[7] \|= 0x400; /* must be one */
1906
1907	pVMCB->guest.u64DR7 = pCtx->dr[7];
1908
1909	/* Inject the exception. */
1910	Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
1911
1912	Event.au64[0] = 0;
1913	Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
1914	Event.n.u1Valid = 1;
1915	Event.n.u8Vector = X86_XCPT_DB;
1916
1917	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1918
1919	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1920	goto ResumeExecution;
1921	}
1922	}
1923	}
1924
1925	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1926	goto ResumeExecution;
1927	}
1928	Log2(("EM status from IO at %RGv %x size %d: %Rrc\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
1929	break;
1930	}
1931
1932	#ifdef VBOX_STRICT
1933	if (rc == VINF_IOM_HC_IOPORT_READ)
1934	Assert(IoExitInfo.n.u1Type != 0);
1935	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1936	Assert(IoExitInfo.n.u1Type == 0);
1937	else
1938	AssertMsg(RT_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
1939	#endif
1940	Log2(("Failed IO at %RGv %x size %d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1941	break;
1942	}
1943
1944	case SVM_EXIT_HLT:
1945	/** Check if external interrupts are pending; if so, don't switch back. */
1946	pCtx->rip++; /* skip hlt */
1947	if ( pCtx->eflags.Bits.u1IF
1948	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1949	goto ResumeExecution;
1950
1951	rc = VINF_EM_HALT;
1952	break;
1953
1954	case SVM_EXIT_RSM:
1955	case SVM_EXIT_INVLPGA:
1956	case SVM_EXIT_VMRUN:
1957	case SVM_EXIT_VMMCALL:
1958	case SVM_EXIT_VMLOAD:
1959	case SVM_EXIT_VMSAVE:
1960	case SVM_EXIT_STGI:
1961	case SVM_EXIT_CLGI:
1962	case SVM_EXIT_SKINIT:
1963	case SVM_EXIT_RDTSCP:
1964	{
1965	/* Unsupported instructions. */
1966	SVM_EVENT Event;
1967
1968	Event.au64[0] = 0;
1969	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1970	Event.n.u1Valid = 1;
1971	Event.n.u8Vector = X86_XCPT_UD;
1972
1973	Log(("Forced #UD trap at %RGv\n", (RTGCPTR)pCtx->rip));
1974	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1975
1976	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1977	goto ResumeExecution;
1978	}
1979
1980	/* Emulate in ring 3. */
1981	case SVM_EXIT_MSR:
1982	{
1983	uint32_t cbSize;
1984
1985	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
1986	Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
1987	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1988	if (rc == VINF_SUCCESS)
1989	{
1990	/* EIP has been updated already. */
1991
1992	/* Only resume if successful. */
1993	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1994	goto ResumeExecution;
1995	}
1996	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
1997	break;
1998	}
1999
2000	case SVM_EXIT_MONITOR:
2001	case SVM_EXIT_RDPMC:
2002	case SVM_EXIT_PAUSE:
2003	case SVM_EXIT_MWAIT_UNCOND:
2004	case SVM_EXIT_MWAIT_ARMED:
2005	case SVM_EXIT_TASK_SWITCH: /* can change CR3; emulate */
2006	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2007	break;
2008
2009	case SVM_EXIT_SHUTDOWN:
2010	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2011	break;
2012
2013	case SVM_EXIT_IDTR_READ:
2014	case SVM_EXIT_GDTR_READ:
2015	case SVM_EXIT_LDTR_READ:
2016	case SVM_EXIT_TR_READ:
2017	case SVM_EXIT_IDTR_WRITE:
2018	case SVM_EXIT_GDTR_WRITE:
2019	case SVM_EXIT_LDTR_WRITE:
2020	case SVM_EXIT_TR_WRITE:
2021	case SVM_EXIT_CR0_SEL_WRITE:
2022	default:
2023	/* Unexpected exit codes. */
2024	rc = VERR_EM_INTERNAL_ERROR;
2025	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
2026	break;
2027	}
2028
2029	end:
2030
2031	/* Signal changes for the recompiler. */
2032	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
2033
2034	/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
2035	if (exitCode == SVM_EXIT_INTR)
2036	{
2037	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
2038	/* On the next entry we'll only sync the host context. */
2039	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
2040	}
2041	else
2042	{
2043	/* On the next entry we'll sync everything. */
2044	/** @todo we can do better than this */
2045	/* Not in the VINF_PGM_CHANGE_MODE though! */
2046	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
2047	}
2048
2049	/* translate into a less severe return code */
2050	if (rc == VERR_EM_INTERPRETER)
2051	rc = VINF_EM_RAW_EMULATE_INSTR;
2052
2053	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
2054	return rc;
2055	}
2056
2057	/**
2058	* Enters the AMD-V session
2059	*
2060	* @returns VBox status code.
2061	* @param pVM The VM to operate on.
2062	* @param pVCpu The VM CPU to operate on.
2063	* @param pCpu CPU info struct
2064	*/
2065	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
2066	{
2067	Assert(pVM->hwaccm.s.svm.fSupported);
2068
2069	LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVCpu->hwaccm.s.idLastCpu, pVCpu->hwaccm.s.uCurrentASID));
2070	pVCpu->hwaccm.s.fResumeVM = false;
2071
2072	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
2073	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_LDTR;
2074
2075	return VINF_SUCCESS;
2076	}
2077
2078
2079	/**
2080	* Leaves the AMD-V session
2081	*
2082	* @returns VBox status code.
2083	* @param pVM The VM to operate on.
2084	* @param pVCpu The VM CPU to operate on.
2085	* @param pCtx CPU context
2086	*/
2087	VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2088	{
2089	SVM_VMCB pVMCB = (SVM_VMCB )pVCpu->hwaccm.s.svm.pVMCB;
2090
2091	Assert(pVM->hwaccm.s.svm.fSupported);
2092
2093	/* Save the guest debug state if necessary. */
2094	if (CPUMIsGuestDebugStateActive(pVM))
2095	{
2096	CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, false /* skip DR6 */);
2097
2098	/* Intercept all DRx reads and writes again. Changed later on. */
2099	pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
2100	pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
2101
2102	/* Resync the debug registers the next time. */
2103	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_DEBUG;
2104	}
2105	else
2106	Assert(pVMCB->ctrl.u16InterceptRdDRx == 0xFFFF && pVMCB->ctrl.u16InterceptWrDRx == 0xFFFF);
2107
2108	return VINF_SUCCESS;
2109	}
2110
2111
2112	static int svmR0InterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2113	{
2114	OP_PARAMVAL param1;
2115	RTGCPTR addr;
2116
2117	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2118	if(RT_FAILURE(rc))
2119	return VERR_EM_INTERPRETER;
2120
2121	switch(param1.type)
2122	{
2123	case PARMTYPE_IMMEDIATE:
2124	case PARMTYPE_ADDRESS:
2125	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
2126	return VERR_EM_INTERPRETER;
2127	addr = param1.val.val64;
2128	break;
2129
2130	default:
2131	return VERR_EM_INTERPRETER;
2132	}
2133
2134	/** @todo is addr always a flat linear address or ds based
2135	* (in absence of segment override prefixes)????
2136	*/
2137	rc = PGMInvalidatePage(pVM, addr);
2138	if (RT_SUCCESS(rc))
2139	{
2140	/* Manually invalidate the page for the VM's TLB. */
2141	Log(("SVMInvlpgA %RGv ASID=%d\n", addr, uASID));
2142	SVMInvlpgA(addr, uASID);
2143	return VINF_SUCCESS;
2144	}
2145	Assert(rc == VERR_REM_FLUSHED_PAGES_OVERFLOW);
2146	return rc;
2147	}
2148
2149	/**
2150	* Interprets INVLPG
2151	*
2152	* @returns VBox status code.
2153	* @retval VINF_* Scheduling instructions.
2154	* @retval VERR_EM_INTERPRETER Something we can't cope with.
2155	* @retval VERR_* Fatal errors.
2156	*
2157	* @param pVM The VM handle.
2158	* @param pRegFrame The register frame.
2159	* @param ASID Tagged TLB id for the guest
2160	*
2161	* Updates the EIP if an instruction was executed successfully.
2162	*/
2163	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2164	{
2165	/*
2166	* Only allow 32 & 64 bits code.
2167	*/
2168	DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
2169	if (enmMode != CPUMODE_16BIT)
2170	{
2171	RTGCPTR pbCode;
2172	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
2173	if (RT_SUCCESS(rc))
2174	{
2175	uint32_t cbOp;
2176	DISCPUSTATE Cpu;
2177
2178	Cpu.mode = enmMode;
2179	rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
2180	Assert(RT_FAILURE(rc) \|\| Cpu.pCurInstr->opcode == OP_INVLPG);
2181	if (RT_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
2182	{
2183	Assert(cbOp == Cpu.opsize);
2184	rc = svmR0InterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
2185	if (RT_SUCCESS(rc))
2186	{
2187	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
2188	}
2189	return rc;
2190	}
2191	}
2192	}
2193	return VERR_EM_INTERPRETER;
2194	}
2195
2196
2197	/**
2198	* Invalidates a guest page
2199	*
2200	* @returns VBox status code.
2201	* @param pVM The VM to operate on.
2202	* @param pVCpu The VM CPU to operate on.
2203	* @param GCVirt Page to invalidate
2204	*/
2205	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
2206	{
2207	bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB \| pVCpu->hwaccm.s.fForceTLBFlush;
2208
2209	/* Skip it if a TLB flush is already pending. */
2210	if (!fFlushPending)
2211	{
2212	SVM_VMCB *pVMCB;
2213
2214	Log2(("SVMR0InvalidatePage %RGv\n", GCVirt));
2215	AssertReturn(pVM, VERR_INVALID_PARAMETER);
2216	Assert(pVM->hwaccm.s.svm.fSupported);
2217
2218	/* @todo SMP */
2219	pVMCB = (SVM_VMCB *)pVM->aCpus[0].hwaccm.s.svm.pVMCB;
2220	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2221
2222	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushPageManual);
2223	SVMInvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2224	}
2225	return VINF_SUCCESS;
2226	}
2227
2228
2229	/**
2230	* Invalidates a guest page by physical address
2231	*
2232	* @returns VBox status code.
2233	* @param pVM The VM to operate on.
2234	* @param pVCpu The VM CPU to operate on.
2235	* @param GCPhys Page to invalidate
2236	*/
2237	VMMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
2238	{
2239	Assert(pVM->hwaccm.s.fNestedPaging);
2240	/* invlpga only invalidates TLB entries for guest virtual addresses; we have no choice but to force a TLB flush here. */
2241	pVCpu->hwaccm.s.fForceTLBFlush = true;
2242	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBInvlpga);
2243	return VINF_SUCCESS;
2244	}

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 13972

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