HWSVMR0.cpp@ 14366

Last change on this file since 14366 was 14366, checked in by vboxsync, 16 years ago
Cleaned up some more.
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1	/* $Id: HWSVMR0.cpp 14366 2008-11-19 17:20:49Z vboxsync $ */
2	/** @file
3	* HWACCM SVM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_svm.h>
32	#include <VBox/pgm.h>
33	#include <VBox/pdm.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <VBox/selm.h>
37	#include <VBox/iom.h>
38	#include <VBox/dis.h>
39	#include <VBox/dbgf.h>
40	#include <VBox/disopcode.h>
41	#include <iprt/param.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm.h>
44	#include <iprt/cpuset.h>
45	#include <iprt/mp.h>
46	#include "HWSVMR0.h"
47
48	/*******************************************************************************
49	* Internal Functions *
50	*******************************************************************************/
51	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
52
53	/*******************************************************************************
54	* Global Variables *
55	*******************************************************************************/
56	/* IO operation lookup arrays. */
57	static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
58
59	/**
60	* Sets up and activates AMD-V on the current CPU
61	*
62	* @returns VBox status code.
63	* @param pCpu CPU info struct
64	* @param pVM The VM to operate on. (can be NULL after a resume!!)
65	* @param pvPageCpu Pointer to the global cpu page
66	* @param pPageCpuPhys Physical address of the global cpu page
67	*/
68	VMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
69	{
70	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
71	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
72
73	/* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
74
75	#ifdef LOG_ENABLED
76	SUPR0Printf("SVMR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
77	#endif
78
79	/* Turn on AMD-V in the EFER MSR. */
80	uint64_t val = ASMRdMsr(MSR_K6_EFER);
81	if (!(val & MSR_K6_EFER_SVME))
82	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
83
84	/* Write the physical page address where the CPU will store the host state while executing the VM. */
85	ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
86
87	return VINF_SUCCESS;
88	}
89
90	/**
91	* Deactivates AMD-V on the current CPU
92	*
93	* @returns VBox status code.
94	* @param pCpu CPU info struct
95	* @param pvPageCpu Pointer to the global cpu page
96	* @param pPageCpuPhys Physical address of the global cpu page
97	*/
98	VMMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
99	{
100	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
101	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
102
103	#ifdef LOG_ENABLED
104	SUPR0Printf("SVMR0DisableCpu cpu %d\n", pCpu->idCpu);
105	#endif
106
107	/* Turn off AMD-V in the EFER MSR. */
108	uint64_t val = ASMRdMsr(MSR_K6_EFER);
109	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
110
111	/* Invalidate host state physical address. */
112	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
113
114	return VINF_SUCCESS;
115	}
116
117	/**
118	* Does Ring-0 per VM AMD-V init.
119	*
120	* @returns VBox status code.
121	* @param pVM The VM to operate on.
122	*/
123	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
124	{
125	int rc;
126
127	pVM->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
128	pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
129	pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
130
131	/* Allocate one page for the host context */
132	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
133	if (RT_FAILURE(rc))
134	return rc;
135
136	pVM->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCBHost);
137	pVM->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCBHost, 0);
138	ASMMemZeroPage(pVM->hwaccm.s.svm.pVMCBHost);
139
140	/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
141	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
142	if (RT_FAILURE(rc))
143	return rc;
144
145	pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
146	pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
147	/* Set all bits to intercept all IO accesses. */
148	ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
149
150	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
151	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
152	if (RT_FAILURE(rc))
153	return rc;
154
155	pVM->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
156	pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
157	/* Set all bits to intercept all MSR accesses. */
158	ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
159
160	/* Erratum 170 which requires a forced TLB flush for each world switch:
161	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
162	*
163	* All BH-G1/2 and DH-G1/2 models include a fix:
164	* Athlon X2: 0x6b 1/2
165	* 0x68 1/2
166	* Athlon 64: 0x7f 1
167	* 0x6f 2
168	* Sempron: 0x7f 1/2
169	* 0x6f 2
170	* 0x6c 2
171	* 0x7c 2
172	* Turion 64: 0x68 2
173	*
174	*/
175	uint32_t u32Dummy;
176	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
177	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
178	u32BaseFamily= (u32Version >> 8) & 0xf;
179	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
180	u32Model = ((u32Version >> 4) & 0xf);
181	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
182	u32Stepping = u32Version & 0xf;
183	if ( u32Family == 0xf
184	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
185	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
186	{
187	Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
188	pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
189	}
190
191	/* Allocate VMCBs for all guest CPUs. */
192	for (unsigned i=0;i<pVM->cCPUs;i++)
193	{
194	pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
195
196	/* Allocate one page for the VM control block (VMCB). */
197	rc = RTR0MemObjAllocCont(&pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
198	if (RT_FAILURE(rc))
199	return rc;
200
201	pVM->aCpus[i].hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB);
202	pVM->aCpus[i].hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB, 0);
203	ASMMemZeroPage(pVM->aCpus[i].hwaccm.s.svm.pVMCB);
204	}
205
206	return VINF_SUCCESS;
207	}
208
209	/**
210	* Does Ring-0 per VM AMD-V termination.
211	*
212	* @returns VBox status code.
213	* @param pVM The VM to operate on.
214	*/
215	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
216	{
217	for (unsigned i=0;i<pVM->cCPUs;i++)
218	{
219	if (pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)
220	{
221	RTR0MemObjFree(pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB, false);
222	pVM->aCpus[i].hwaccm.s.svm.pVMCB = 0;
223	pVM->aCpus[i].hwaccm.s.svm.pVMCBPhys = 0;
224	pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
225	}
226	}
227	if (pVM->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ)
228	{
229	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCBHost, false);
230	pVM->hwaccm.s.svm.pVMCBHost = 0;
231	pVM->hwaccm.s.svm.pVMCBHostPhys = 0;
232	pVM->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
233	}
234	if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)
235	{
236	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
237	pVM->hwaccm.s.svm.pIOBitmap = 0;
238	pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
239	pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
240	}
241	if (pVM->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
242	{
243	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
244	pVM->hwaccm.s.svm.pMSRBitmap = 0;
245	pVM->hwaccm.s.svm.pMSRBitmapPhys = 0;
246	pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
247	}
248	return VINF_SUCCESS;
249	}
250
251	/**
252	* Sets up AMD-V for the specified VM
253	*
254	* @returns VBox status code.
255	* @param pVM The VM to operate on.
256	*/
257	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
258	{
259	int rc = VINF_SUCCESS;
260	SVM_VMCB *pVMCB;
261
262	AssertReturn(pVM, VERR_INVALID_PARAMETER);
263
264	Assert(pVM->hwaccm.s.svm.fSupported);
265
266	for (unsigned i=0;i<pVM->cCPUs;i++)
267	{
268	pVMCB = (SVM_VMCB *)pVM->aCpus[i].hwaccm.s.svm.pVMCB;
269	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
270
271	/* Program the control fields. Most of them never have to be changed again. */
272	/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
273	/* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical. */
274	if (!pVM->hwaccm.s.fNestedPaging)
275	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
276	else
277	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
278
279	/*
280	* CR0/3/4 writes must be intercepted for obvious reasons.
281	*/
282	if (!pVM->hwaccm.s.fNestedPaging)
283	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
284	else
285	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4) \| RT_BIT(8);
286
287	/* Intercept all DRx reads and writes by default. Changed later on. */
288	pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
289	pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
290
291	/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
292	* All breakpoints are automatically cleared when the VM exits.
293	*/
294
295	pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
296	#ifndef DEBUG
297	if (pVM->hwaccm.s.fNestedPaging)
298	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
299	#endif
300
301	pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
302	\| SVM_CTRL1_INTERCEPT_VINTR
303	\| SVM_CTRL1_INTERCEPT_NMI
304	\| SVM_CTRL1_INTERCEPT_SMI
305	\| SVM_CTRL1_INTERCEPT_INIT
306	\| SVM_CTRL1_INTERCEPT_RDPMC
307	\| SVM_CTRL1_INTERCEPT_CPUID
308	\| SVM_CTRL1_INTERCEPT_RSM
309	\| SVM_CTRL1_INTERCEPT_HLT
310	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
311	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
312	\| SVM_CTRL1_INTERCEPT_INVLPG
313	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
314	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH
315	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
316	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
317	;
318	/* With nested paging we don't care about invlpg anymore. */
319	if (pVM->hwaccm.s.fNestedPaging)
320	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
321
322	pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
323	\| SVM_CTRL2_INTERCEPT_VMMCALL
324	\| SVM_CTRL2_INTERCEPT_VMLOAD
325	\| SVM_CTRL2_INTERCEPT_VMSAVE
326	\| SVM_CTRL2_INTERCEPT_STGI
327	\| SVM_CTRL2_INTERCEPT_CLGI
328	\| SVM_CTRL2_INTERCEPT_SKINIT
329	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
330	\| SVM_CTRL2_INTERCEPT_WBINVD
331	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
332	;
333	Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
334	Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
335	Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
336
337	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
338	pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
339	/* Ignore the priority in the TPR; just deliver it when we tell it to. */
340	pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
341
342	/* Set IO and MSR bitmap addresses. */
343	pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
344	pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
345
346	/* No LBR virtualization. */
347	pVMCB->ctrl.u64LBRVirt = 0;
348
349	/** The ASID must start at 1; the host uses 0. */
350	pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
351
352	/** Setup the PAT msr (nested paging only) */
353	pVMCB->guest.u64GPAT = 0x0007040600070406ULL;
354	}
355	return rc;
356	}
357
358
359	/**
360	* Injects an event (trap or external interrupt)
361	*
362	* @param pVM The VM to operate on.
363	* @param pVMCB SVM control block
364	* @param pCtx CPU Context
365	* @param pIntInfo SVM interrupt info
366	*/
367	inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx, SVM_EVENT* pEvent)
368	{
369	#ifdef VBOX_STRICT
370	if (pEvent->n.u8Vector == 0xE)
371	Log(("SVM: Inject int %d at %RGv error code=%02x CR2=%RGv intInfo=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode, (RTGCPTR)pCtx->cr2, pEvent->au64[0]));
372	else
373	if (pEvent->n.u8Vector < 0x20)
374	Log(("SVM: Inject int %d at %RGv error code=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode));
375	else
376	{
377	Log(("INJ-EI: %x at %RGv\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip));
378	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
379	Assert(pCtx->eflags.u32 & X86_EFL_IF);
380	}
381	#endif
382
383	/* Set event injection state. */
384	pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
385	}
386
387
388	/**
389	* Checks for pending guest interrupts and injects them
390	*
391	* @returns VBox status code.
392	* @param pVM The VM to operate on.
393	* @param pVCpu The VM CPU to operate on.
394	* @param pVMCB SVM control block
395	* @param pCtx CPU Context
396	*/
397	static int SVMR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, SVM_VMCB pVMCB, CPUMCTX pCtx)
398	{
399	int rc;
400
401	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
402	if (pVCpu->hwaccm.s.Event.fPending)
403	{
404	SVM_EVENT Event;
405
406	Log(("Reinjecting event %08x %08x at %RGv\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip));
407	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
408	Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
409	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
410
411	pVCpu->hwaccm.s.Event.fPending = false;
412	return VINF_SUCCESS;
413	}
414
415	if (pVM->hwaccm.s.fInjectNMI)
416	{
417	SVM_EVENT Event;
418
419	Event.n.u8Vector = X86_XCPT_NMI;
420	Event.n.u1Valid = 1;
421	Event.n.u32ErrorCode = 0;
422	Event.n.u3Type = SVM_EVENT_NMI;
423
424	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
425	pVM->hwaccm.s.fInjectNMI = false;
426	return VINF_SUCCESS;
427	}
428
429	/* When external interrupts are pending, we should exit the VM when IF is set. */
430	if ( !TRPMHasTrap(pVM)
431	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
432	{
433	if ( !(pCtx->eflags.u32 & X86_EFL_IF)
434	\|\| VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
435	{
436	if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
437	{
438	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
439	LogFlow(("Enable irq window exit!\n"));
440	else
441	Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", (RTGCPTR)pCtx->rip));
442
443	/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
444	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
445	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
446	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
447	}
448	}
449	else
450	{
451	uint8_t u8Interrupt;
452
453	rc = PDMGetInterrupt(pVM, &u8Interrupt);
454	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
455	if (RT_SUCCESS(rc))
456	{
457	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
458	AssertRC(rc);
459	}
460	else
461	{
462	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
463	Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)));
464	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
465	/* Just continue */
466	}
467	}
468	}
469
470	#ifdef VBOX_STRICT
471	if (TRPMHasTrap(pVM))
472	{
473	uint8_t u8Vector;
474	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
475	AssertRC(rc);
476	}
477	#endif
478
479	if ( pCtx->eflags.u32 & X86_EFL_IF
480	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
481	&& TRPMHasTrap(pVM)
482	)
483	{
484	uint8_t u8Vector;
485	int rc;
486	TRPMEVENT enmType;
487	SVM_EVENT Event;
488	RTGCUINT u32ErrorCode;
489
490	Event.au64[0] = 0;
491
492	/* If a new event is pending, then dispatch it now. */
493	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &u32ErrorCode, 0);
494	AssertRC(rc);
495	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
496	Assert(enmType != TRPM_SOFTWARE_INT);
497
498	/* Clear the pending trap. */
499	rc = TRPMResetTrap(pVM);
500	AssertRC(rc);
501
502	Event.n.u8Vector = u8Vector;
503	Event.n.u1Valid = 1;
504	Event.n.u32ErrorCode = u32ErrorCode;
505
506	if (enmType == TRPM_TRAP)
507	{
508	switch (u8Vector) {
509	case 8:
510	case 10:
511	case 11:
512	case 12:
513	case 13:
514	case 14:
515	case 17:
516	/* Valid error codes. */
517	Event.n.u1ErrorCodeValid = 1;
518	break;
519	default:
520	break;
521	}
522	if (u8Vector == X86_XCPT_NMI)
523	Event.n.u3Type = SVM_EVENT_NMI;
524	else
525	Event.n.u3Type = SVM_EVENT_EXCEPTION;
526	}
527	else
528	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
529
530	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
531	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
532	} /* if (interrupts can be dispatched) */
533
534	return VINF_SUCCESS;
535	}
536
537	/**
538	* Save the host state
539	*
540	* @returns VBox status code.
541	* @param pVM The VM to operate on.
542	* @param pVCpu The VM CPU to operate on.
543	*/
544	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
545	{
546	NOREF(pVM);
547	NOREF(pVCpu);
548	/* Nothing to do here. */
549	return VINF_SUCCESS;
550	}
551
552	/**
553	* Loads the guest state
554	*
555	* NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
556	*
557	* @returns VBox status code.
558	* @param pVM The VM to operate on.
559	* @param pVCpu The VM CPU to operate on.
560	* @param pCtx Guest context
561	*/
562	VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
563	{
564	RTGCUINTPTR val;
565	SVM_VMCB *pVMCB;
566
567	if (pVM == NULL)
568	return VERR_INVALID_PARAMETER;
569
570	/* Setup AMD SVM. */
571	Assert(pVM->hwaccm.s.svm.fSupported);
572
573	pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
574	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
575
576	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
577	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
578	{
579	SVM_WRITE_SELREG(CS, cs);
580	SVM_WRITE_SELREG(SS, ss);
581	SVM_WRITE_SELREG(DS, ds);
582	SVM_WRITE_SELREG(ES, es);
583	SVM_WRITE_SELREG(FS, fs);
584	SVM_WRITE_SELREG(GS, gs);
585	}
586
587	/* Guest CPU context: LDTR. */
588	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
589	{
590	SVM_WRITE_SELREG(LDTR, ldtr);
591	}
592
593	/* Guest CPU context: TR. */
594	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
595	{
596	SVM_WRITE_SELREG(TR, tr);
597	}
598
599	/* Guest CPU context: GDTR. */
600	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
601	{
602	pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
603	pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
604	}
605
606	/* Guest CPU context: IDTR. */
607	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
608	{
609	pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
610	pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
611	}
612
613	/*
614	* Sysenter MSRs (unconditional)
615	*/
616	pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
617	pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
618	pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
619
620	/* Control registers */
621	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
622	{
623	val = pCtx->cr0;
624	if (!CPUMIsGuestFPUStateActive(pVCpu))
625	{
626	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
627	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
628	}
629	else
630	{
631	/** @todo check if we support the old style mess correctly. */
632	if (!(val & X86_CR0_NE))
633	{
634	Log(("Forcing X86_CR0_NE!!!\n"));
635
636	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
637	if (!pVCpu->hwaccm.s.fFPUOldStyleOverride)
638	{
639	pVMCB->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_MF);
640	pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
641	}
642	}
643	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
644	}
645	/* Always enable caching. */
646	val &= ~(X86_CR0_CD\|X86_CR0_NW);
647
648	/* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
649	/* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
650	if (!pVM->hwaccm.s.fNestedPaging)
651	{
652	val \|= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
653	val \|= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
654	}
655	pVMCB->guest.u64CR0 = val;
656	}
657	/* CR2 as well */
658	pVMCB->guest.u64CR2 = pCtx->cr2;
659
660	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
661	{
662	/* Save our shadow CR3 register. */
663	if (pVM->hwaccm.s.fNestedPaging)
664	{
665	pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVM, PGMGetHostMode(pVM));
666	Assert(pVMCB->ctrl.u64NestedPagingCR3);
667	pVMCB->guest.u64CR3 = pCtx->cr3;
668	}
669	else
670	{
671	pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
672	Assert(pVMCB->guest.u64CR3);
673	}
674	}
675
676	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
677	{
678	val = pCtx->cr4;
679	if (!pVM->hwaccm.s.fNestedPaging)
680	{
681	switch(pVCpu->hwaccm.s.enmShadowMode)
682	{
683	case PGMMODE_REAL:
684	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
685	AssertFailed();
686	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
687
688	case PGMMODE_32_BIT: /* 32-bit paging. */
689	break;
690
691	case PGMMODE_PAE: /* PAE paging. */
692	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
693	/** @todo use normal 32 bits paging */
694	val \|= X86_CR4_PAE;
695	break;
696
697	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
698	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
699	#ifdef VBOX_ENABLE_64_BITS_GUESTS
700	break;
701	#else
702	AssertFailed();
703	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
704	#endif
705
706	default: /* shut up gcc */
707	AssertFailed();
708	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
709	}
710	}
711	pVMCB->guest.u64CR4 = val;
712	}
713
714	/* Debug registers. */
715	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
716	{
717	pCtx->dr[6] \|= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
718	pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
719
720	pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
721	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
722	pCtx->dr[7] \|= 0x400; /* must be one */
723
724	pVMCB->guest.u64DR7 = pCtx->dr[7];
725	pVMCB->guest.u64DR6 = pCtx->dr[6];
726
727	/* Sync the debug state now if any breakpoint is armed. */
728	if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK\|X86_DR7_GD))
729	&& !CPUMIsGuestDebugStateActive(pVM)
730	&& !DBGFIsStepping(pVM))
731	{
732	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
733
734	/* Disable drx move intercepts. */
735	pVMCB->ctrl.u16InterceptRdDRx = 0;
736	pVMCB->ctrl.u16InterceptWrDRx = 0;
737
738	/* Save the host and load the guest debug state. */
739	int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
740	AssertRC(rc);
741	}
742	}
743
744	/* EIP, ESP and EFLAGS */
745	pVMCB->guest.u64RIP = pCtx->rip;
746	pVMCB->guest.u64RSP = pCtx->rsp;
747	pVMCB->guest.u64RFlags = pCtx->eflags.u32;
748
749	/* Set CPL */
750	pVMCB->guest.u8CPL = pCtx->csHid.Attr.n.u2Dpl;
751
752	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
753	pVMCB->guest.u64RAX = pCtx->rax;
754
755	/* vmrun will fail without MSR_K6_EFER_SVME. */
756	pVMCB->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
757
758	/* 64 bits guest mode? */
759	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
760	{
761	#if !defined(VBOX_WITH_64_BITS_GUESTS)
762	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
763	#elif HC_ARCH_BITS == 32
764	pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
765	#else
766	pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun64;
767	#endif
768	/* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
769	pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
770	pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
771	}
772	else
773	{
774	/* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
775	pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
776
777	pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun;
778	}
779
780	/* TSC offset. */
781	if (TMCpuTickCanUseRealTSC(pVM, &pVMCB->ctrl.u64TSCOffset))
782	{
783	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
784	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
785	}
786	else
787	{
788	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
789	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
790	}
791
792	/* Sync the various msrs for 64 bits mode. */
793	pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
794	pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
795	pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
796	pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
797	pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
798
799	#ifdef DEBUG
800	/* Intercept X86_XCPT_DB if stepping is enabled */
801	if (DBGFIsStepping(pVM))
802	pVMCB->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_DB);
803	else
804	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_DB);
805	#endif
806
807	/* Done. */
808	pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
809
810	return VINF_SUCCESS;
811	}
812
813
814	/**
815	* Runs guest code in an AMD-V VM.
816	*
817	* @returns VBox status code.
818	* @param pVM The VM to operate on.
819	* @param pVCpu The VM CPU to operate on.
820	* @param pCtx Guest context
821	*/
822	VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
823	{
824	int rc = VINF_SUCCESS;
825	uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
826	SVM_VMCB *pVMCB;
827	bool fSyncTPR = false;
828	unsigned cResume = 0;
829	uint8_t u8LastVTPR;
830	PHWACCM_CPUINFO pCpu = 0;
831	#ifdef VBOX_STRICT
832	RTCPUID idCpuCheck;
833	#endif
834
835	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
836
837	pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
838	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
839
840	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
841	*/
842	ResumeExecution:
843	Assert(!HWACCMR0SuspendPending());
844
845	/* Safety precaution; looping for too long here can have a very bad effect on the host */
846	if (++cResume > HWACCM_MAX_RESUME_LOOPS)
847	{
848	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
849	rc = VINF_EM_RAW_INTERRUPT;
850	goto end;
851	}
852
853	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
854	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
855	{
856	Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
857	if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
858	{
859	/* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
860	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
861	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
862	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
863	*/
864	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
865	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
866	pVMCB->ctrl.u64IntShadow = 0;
867	}
868	}
869	else
870	{
871	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
872	pVMCB->ctrl.u64IntShadow = 0;
873	}
874
875	/* Check for pending actions that force us to go back to ring 3. */
876	#ifdef DEBUG
877	/* Intercept X86_XCPT_DB if stepping is enabled */
878	if (!DBGFIsStepping(pVM))
879	#endif
880	{
881	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
882	{
883	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
884	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
885	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
886	rc = VINF_EM_RAW_TO_R3;
887	goto end;
888	}
889	}
890
891	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
892	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
893	{
894	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
895	rc = VINF_EM_PENDING_REQUEST;
896	goto end;
897	}
898
899	/* When external interrupts are pending, we should exit the VM when IF is set. */
900	/* Note! After VM_FF_INHIBIT_INTERRUPTS check!!! */
901	rc = SVMR0CheckPendingInterrupt(pVM, pVCpu, pVMCB, pCtx);
902	if (RT_FAILURE(rc))
903	{
904	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
905	goto end;
906	}
907
908	/* TPR caching using CR8 is only available in 64 bits mode */
909	/* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
910	/* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! */
911	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
912	{
913	bool fPending;
914
915	/* TPR caching in CR8 */
916	int rc = PDMApicGetTPR(pVM, &u8LastVTPR, &fPending);
917	AssertRC(rc);
918	pVMCB->ctrl.IntCtrl.n.u8VTPR = u8LastVTPR;
919
920	if (fPending)
921	{
922	/* A TPR change could activate a pending interrupt, so catch cr8 writes. */
923	pVMCB->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
924	}
925	else
926	/* No interrupts are pending, so we don't need to be explicitely notified.
927	* There are enough world switches for detecting pending interrupts.
928	*/
929	pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
930
931	fSyncTPR = !fPending;
932	}
933
934	/* All done! Let's start VM execution. */
935	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, x);
936
937	/* Enable nested paging if necessary (disabled each time after #VMEXIT). */
938	pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
939
940	#ifdef LOG_ENABLED
941	pCpu = HWACCMR0GetCurrentCpu();
942	if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
943	\|\| pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
944	{
945	if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
946	Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
947	else
948	Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
949	}
950	if (pCpu->fFlushTLB)
951	Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
952	#endif
953
954	/*
955	* NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
956	* (until the actual world switch)
957	*/
958
959	#ifdef VBOX_STRICT
960	idCpuCheck = RTMpCpuId();
961	#endif
962
963	/* Load the guest state; must be here as it sets up the shadow cr0 for lazy fpu syncing! */
964	rc = SVMR0LoadGuestState(pVM, pVCpu, pCtx);
965	if (rc != VINF_SUCCESS)
966	{
967	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
968	goto end;
969	}
970
971	pCpu = HWACCMR0GetCurrentCpu();
972	/* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
973	/* Note that this can happen both for start and resume due to long jumps back to ring 3. */
974	if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
975	/* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
976	\|\| pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
977	{
978	/* Force a TLB flush on VM entry. */
979	pVCpu->hwaccm.s.fForceTLBFlush = true;
980	}
981	else
982	Assert(!pCpu->fFlushTLB \|\| pVM->hwaccm.s.svm.fAlwaysFlushTLB);
983
984	pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
985
986	/* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
987	if ( pVCpu->hwaccm.s.fForceTLBFlush
988	&& !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
989	{
990	if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
991	\|\| pCpu->fFlushTLB)
992	{
993	pCpu->fFlushTLB = false;
994	pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
995	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
996	pCpu->cTLBFlushes++;
997	}
998	else
999	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1000
1001	pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1002	pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1003	}
1004	else
1005	{
1006	Assert(!pCpu->fFlushTLB \|\| pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1007
1008	/* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
1009	if (!pCpu->uCurrentASID \|\| !pVCpu->hwaccm.s.uCurrentASID)
1010	pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
1011
1012	Assert(!pVM->hwaccm.s.svm.fAlwaysFlushTLB \|\| pVCpu->hwaccm.s.fForceTLBFlush);
1013	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVCpu->hwaccm.s.fForceTLBFlush;
1014	}
1015	AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1016	AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1017	AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1018	pVMCB->ctrl.TLBCtrl.n.u32ASID = pVCpu->hwaccm.s.uCurrentASID;
1019
1020	#ifdef VBOX_WITH_STATISTICS
1021	if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
1022	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1023	else
1024	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1025	#endif
1026
1027	/* In case we execute a goto ResumeExecution later on. */
1028	pVCpu->hwaccm.s.fResumeVM = true;
1029	pVCpu->hwaccm.s.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
1030
1031	Assert(sizeof(pVCpu->hwaccm.s.svm.pVMCBPhys) == 8);
1032	Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
1033	\| SVM_CTRL2_INTERCEPT_VMMCALL
1034	\| SVM_CTRL2_INTERCEPT_VMLOAD
1035	\| SVM_CTRL2_INTERCEPT_VMSAVE
1036	\| SVM_CTRL2_INTERCEPT_STGI
1037	\| SVM_CTRL2_INTERCEPT_CLGI
1038	\| SVM_CTRL2_INTERCEPT_SKINIT
1039	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
1040	\| SVM_CTRL2_INTERCEPT_WBINVD
1041	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
1042	));
1043	Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
1044	Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
1045	Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
1046	Assert(pVMCB->ctrl.u64LBRVirt == 0);
1047
1048	#ifdef VBOX_STRICT
1049	Assert(idCpuCheck == RTMpCpuId());
1050	#endif
1051	TMNotifyStartOfExecution(pVM);
1052	pVCpu->hwaccm.s.svm.pfnVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx);
1053	TMNotifyEndOfExecution(pVM);
1054	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, x);
1055
1056	/*
1057	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1058	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1059	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1060	*/
1061
1062	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit, x);
1063
1064	/* Reason for the VM exit */
1065	exitCode = pVMCB->ctrl.u64ExitCode;
1066
1067	if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
1068	{
1069	HWACCMDumpRegs(pVM, pCtx);
1070	#ifdef DEBUG
1071	Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
1072	Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
1073	Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
1074	Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
1075	Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
1076	Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
1077	Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
1078	Log(("ctrl.u64IOPMPhysAddr %RX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
1079	Log(("ctrl.u64MSRPMPhysAddr %RX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
1080	Log(("ctrl.u64TSCOffset %RX64\n", pVMCB->ctrl.u64TSCOffset));
1081
1082	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
1083	Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
1084	Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
1085	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
1086
1087	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
1088	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
1089	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
1090	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
1091	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
1092	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
1093	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
1094	Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
1095	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
1096	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
1097
1098	Log(("ctrl.u64IntShadow %RX64\n", pVMCB->ctrl.u64IntShadow));
1099	Log(("ctrl.u64ExitCode %RX64\n", pVMCB->ctrl.u64ExitCode));
1100	Log(("ctrl.u64ExitInfo1 %RX64\n", pVMCB->ctrl.u64ExitInfo1));
1101	Log(("ctrl.u64ExitInfo2 %RX64\n", pVMCB->ctrl.u64ExitInfo2));
1102	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
1103	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
1104	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
1105	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
1106	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
1107	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
1108	Log(("ctrl.NestedPaging %RX64\n", pVMCB->ctrl.NestedPaging.au64));
1109	Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
1110	Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
1111	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
1112	Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
1113	Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
1114	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
1115
1116	Log(("ctrl.u64NestedPagingCR3 %RX64\n", pVMCB->ctrl.u64NestedPagingCR3));
1117	Log(("ctrl.u64LBRVirt %RX64\n", pVMCB->ctrl.u64LBRVirt));
1118
1119	Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
1120	Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1121	Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1122	Log(("guest.CS.u64Base %RX64\n", pVMCB->guest.CS.u64Base));
1123	Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1124	Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1125	Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1126	Log(("guest.DS.u64Base %RX64\n", pVMCB->guest.DS.u64Base));
1127	Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1128	Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1129	Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1130	Log(("guest.ES.u64Base %RX64\n", pVMCB->guest.ES.u64Base));
1131	Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1132	Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1133	Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1134	Log(("guest.FS.u64Base %RX64\n", pVMCB->guest.FS.u64Base));
1135	Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1136	Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1137	Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1138	Log(("guest.GS.u64Base %RX64\n", pVMCB->guest.GS.u64Base));
1139
1140	Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1141	Log(("guest.GDTR.u64Base %RX64\n", pVMCB->guest.GDTR.u64Base));
1142
1143	Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1144	Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1145	Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1146	Log(("guest.LDTR.u64Base %RX64\n", pVMCB->guest.LDTR.u64Base));
1147
1148	Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1149	Log(("guest.IDTR.u64Base %RX64\n", pVMCB->guest.IDTR.u64Base));
1150
1151	Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1152	Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1153	Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1154	Log(("guest.TR.u64Base %RX64\n", pVMCB->guest.TR.u64Base));
1155
1156	Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1157	Log(("guest.u64CR0 %RX64\n", pVMCB->guest.u64CR0));
1158	Log(("guest.u64CR2 %RX64\n", pVMCB->guest.u64CR2));
1159	Log(("guest.u64CR3 %RX64\n", pVMCB->guest.u64CR3));
1160	Log(("guest.u64CR4 %RX64\n", pVMCB->guest.u64CR4));
1161	Log(("guest.u64DR6 %RX64\n", pVMCB->guest.u64DR6));
1162	Log(("guest.u64DR7 %RX64\n", pVMCB->guest.u64DR7));
1163
1164	Log(("guest.u64RIP %RX64\n", pVMCB->guest.u64RIP));
1165	Log(("guest.u64RSP %RX64\n", pVMCB->guest.u64RSP));
1166	Log(("guest.u64RAX %RX64\n", pVMCB->guest.u64RAX));
1167	Log(("guest.u64RFlags %RX64\n", pVMCB->guest.u64RFlags));
1168
1169	Log(("guest.u64SysEnterCS %RX64\n", pVMCB->guest.u64SysEnterCS));
1170	Log(("guest.u64SysEnterEIP %RX64\n", pVMCB->guest.u64SysEnterEIP));
1171	Log(("guest.u64SysEnterESP %RX64\n", pVMCB->guest.u64SysEnterESP));
1172
1173	Log(("guest.u64EFER %RX64\n", pVMCB->guest.u64EFER));
1174	Log(("guest.u64STAR %RX64\n", pVMCB->guest.u64STAR));
1175	Log(("guest.u64LSTAR %RX64\n", pVMCB->guest.u64LSTAR));
1176	Log(("guest.u64CSTAR %RX64\n", pVMCB->guest.u64CSTAR));
1177	Log(("guest.u64SFMASK %RX64\n", pVMCB->guest.u64SFMASK));
1178	Log(("guest.u64KernelGSBase %RX64\n", pVMCB->guest.u64KernelGSBase));
1179	Log(("guest.u64GPAT %RX64\n", pVMCB->guest.u64GPAT));
1180	Log(("guest.u64DBGCTL %RX64\n", pVMCB->guest.u64DBGCTL));
1181	Log(("guest.u64BR_FROM %RX64\n", pVMCB->guest.u64BR_FROM));
1182	Log(("guest.u64BR_TO %RX64\n", pVMCB->guest.u64BR_TO));
1183	Log(("guest.u64LASTEXCPFROM %RX64\n", pVMCB->guest.u64LASTEXCPFROM));
1184	Log(("guest.u64LASTEXCPTO %RX64\n", pVMCB->guest.u64LASTEXCPTO));
1185
1186	#endif
1187	rc = VERR_SVM_UNABLE_TO_START_VM;
1188	goto end;
1189	}
1190
1191	/* Let's first sync back eip, esp, and eflags. */
1192	pCtx->rip = pVMCB->guest.u64RIP;
1193	pCtx->rsp = pVMCB->guest.u64RSP;
1194	pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1195	/* eax is saved/restore across the vmrun instruction */
1196	pCtx->rax = pVMCB->guest.u64RAX;
1197
1198	pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
1199
1200	/* Can be updated behind our back in the nested paging case. */
1201	pCtx->cr2 = pVMCB->guest.u64CR2;
1202
1203	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1204	SVM_READ_SELREG(SS, ss);
1205	SVM_READ_SELREG(CS, cs);
1206	SVM_READ_SELREG(DS, ds);
1207	SVM_READ_SELREG(ES, es);
1208	SVM_READ_SELREG(FS, fs);
1209	SVM_READ_SELREG(GS, gs);
1210
1211	/*
1212	* System MSRs
1213	*/
1214	pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1215	pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1216	pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1217
1218	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1219	SVM_READ_SELREG(LDTR, ldtr);
1220	SVM_READ_SELREG(TR, tr);
1221
1222	pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1223	pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1224
1225	pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1226	pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1227
1228	/* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1229	/* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1230	if ( pVM->hwaccm.s.fNestedPaging
1231	&& pCtx->cr3 != pVMCB->guest.u64CR3)
1232	{
1233	CPUMSetGuestCR3(pVM, pVMCB->guest.u64CR3);
1234	PGMUpdateCR3(pVM, pVMCB->guest.u64CR3);
1235	}
1236
1237	/* Note! NOW IT'S SAFE FOR LOGGING! */
1238
1239	/* Take care of instruction fusing (sti, mov ss) (see 15.20.5 Interrupt Shadows) */
1240	if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1241	{
1242	Log(("uInterruptState %x rip=%RGv\n", pVMCB->ctrl.u64IntShadow, (RTGCPTR)pCtx->rip));
1243	EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1244	}
1245	else
1246	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1247
1248	Log2(("exitCode = %x\n", exitCode));
1249
1250	/* Sync back DR6 as it could have been changed by hitting breakpoints. */
1251	pCtx->dr[6] = pVMCB->guest.u64DR6;
1252	/* DR7.GD can be cleared by debug exceptions, so sync it back as well. */
1253	pCtx->dr[7] = pVMCB->guest.u64DR7;
1254
1255	/* Check if an injected event was interrupted prematurely. */
1256	pVCpu->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1257	if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1258	&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1259	{
1260	Log(("Pending inject %RX64 at %RGv exit=%08x\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitCode));
1261
1262	#ifdef LOG_ENABLED
1263	SVM_EVENT Event;
1264	Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
1265
1266	if ( exitCode == SVM_EXIT_EXCEPTION_E
1267	&& Event.n.u8Vector == 0xE)
1268	{
1269	Log(("Double fault!\n"));
1270	}
1271	#endif
1272
1273	pVCpu->hwaccm.s.Event.fPending = true;
1274	/* Error code present? (redundant) */
1275	if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1276	{
1277	pVCpu->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1278	}
1279	else
1280	pVCpu->hwaccm.s.Event.errCode = 0;
1281	}
1282	#ifdef VBOX_WITH_STATISTICS
1283	if (exitCode == SVM_EXIT_NPF)
1284	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
1285	else
1286	STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1287	#endif
1288
1289	if (fSyncTPR)
1290	{
1291	rc = PDMApicSetTPR(pVM, pVMCB->ctrl.IntCtrl.n.u8VTPR);
1292	AssertRC(rc);
1293	}
1294
1295	/* Deal with the reason of the VM-exit. */
1296	switch (exitCode)
1297	{
1298	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1299	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1300	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1301	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1302	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1303	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1304	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1305	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1306	{
1307	/* Pending trap. */
1308	SVM_EVENT Event;
1309	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1310
1311	Log2(("Hardware/software interrupt %d\n", vector));
1312	switch (vector)
1313	{
1314	case X86_XCPT_DB:
1315	{
1316	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
1317
1318	/* Note that we don't support guest and host-initiated debugging at the same time. */
1319	Assert(DBGFIsStepping(pVM));
1320
1321	rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
1322	if (rc == VINF_EM_RAW_GUEST_TRAP)
1323	{
1324	Log(("Trap %x (debug) at %016RX64\n", vector, pCtx->rip));
1325
1326	/* Reinject the exception. */
1327	Event.au64[0] = 0;
1328	Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
1329	Event.n.u1Valid = 1;
1330	Event.n.u8Vector = X86_XCPT_DB;
1331
1332	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1333
1334	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1335	goto ResumeExecution;
1336	}
1337	/* Return to ring 3 to deal with the debug exit code. */
1338	break;
1339	}
1340
1341	case X86_XCPT_NM:
1342	{
1343	Log(("#NM fault at %RGv\n", (RTGCPTR)pCtx->rip));
1344
1345	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1346	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1347	rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
1348	if (rc == VINF_SUCCESS)
1349	{
1350	Assert(CPUMIsGuestFPUStateActive(pVCpu));
1351	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
1352
1353	/* Continue execution. */
1354	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1355	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1356
1357	goto ResumeExecution;
1358	}
1359
1360	Log(("Forward #NM fault to the guest\n"));
1361	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
1362
1363	Event.au64[0] = 0;
1364	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1365	Event.n.u1Valid = 1;
1366	Event.n.u8Vector = X86_XCPT_NM;
1367
1368	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1369	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1370	goto ResumeExecution;
1371	}
1372
1373	case X86_XCPT_PF: /* Page fault */
1374	{
1375	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1376	RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1377
1378	#ifdef DEBUG
1379	if (pVM->hwaccm.s.fNestedPaging)
1380	{ /* A genuine pagefault.
1381	* Forward the trap to the guest by injecting the exception and resuming execution.
1382	*/
1383	Log(("Guest page fault at %RGv cr2=%RGv error code %x rsp=%RGv\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
1384	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1385
1386	/* Now we must update CR2. */
1387	pCtx->cr2 = uFaultAddress;
1388
1389	Event.au64[0] = 0;
1390	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1391	Event.n.u1Valid = 1;
1392	Event.n.u8Vector = X86_XCPT_PF;
1393	Event.n.u1ErrorCodeValid = 1;
1394	Event.n.u32ErrorCode = errCode;
1395
1396	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1397
1398	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1399	goto ResumeExecution;
1400	}
1401	#endif
1402	Assert(!pVM->hwaccm.s.fNestedPaging);
1403
1404	Log2(("Page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1405	/* Exit qualification contains the linear address of the page fault. */
1406	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1407	TRPMSetErrorCode(pVM, errCode);
1408	TRPMSetFaultAddress(pVM, uFaultAddress);
1409
1410	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1411	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1412	Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1413	if (rc == VINF_SUCCESS)
1414	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1415	Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1416	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1417
1418	TRPMResetTrap(pVM);
1419
1420	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1421	goto ResumeExecution;
1422	}
1423	else
1424	if (rc == VINF_EM_RAW_GUEST_TRAP)
1425	{ /* A genuine pagefault.
1426	* Forward the trap to the guest by injecting the exception and resuming execution.
1427	*/
1428	Log2(("Forward page fault to the guest\n"));
1429	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1430	/* The error code might have been changed. */
1431	errCode = TRPMGetErrorCode(pVM);
1432
1433	TRPMResetTrap(pVM);
1434
1435	/* Now we must update CR2. */
1436	pCtx->cr2 = uFaultAddress;
1437
1438	Event.au64[0] = 0;
1439	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1440	Event.n.u1Valid = 1;
1441	Event.n.u8Vector = X86_XCPT_PF;
1442	Event.n.u1ErrorCodeValid = 1;
1443	Event.n.u32ErrorCode = errCode;
1444
1445	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1446
1447	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1448	goto ResumeExecution;
1449	}
1450	#ifdef VBOX_STRICT
1451	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1452	LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
1453	#endif
1454	/* Need to go back to the recompiler to emulate the instruction. */
1455	TRPMResetTrap(pVM);
1456	break;
1457	}
1458
1459	case X86_XCPT_MF: /* Floating point exception. */
1460	{
1461	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
1462	if (!(pCtx->cr0 & X86_CR0_NE))
1463	{
1464	/* old style FPU error reporting needs some extra work. */
1465	/** @todo don't fall back to the recompiler, but do it manually. */
1466	rc = VINF_EM_RAW_EMULATE_INSTR;
1467	break;
1468	}
1469	Log(("Trap %x at %RGv\n", vector, (RTGCPTR)pCtx->rip));
1470
1471	Event.au64[0] = 0;
1472	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1473	Event.n.u1Valid = 1;
1474	Event.n.u8Vector = X86_XCPT_MF;
1475
1476	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1477
1478	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1479	goto ResumeExecution;
1480	}
1481
1482	#ifdef VBOX_STRICT
1483	case X86_XCPT_GP: /* General protection failure exception.*/
1484	case X86_XCPT_UD: /* Unknown opcode exception. */
1485	case X86_XCPT_DE: /* Divide error. */
1486	case X86_XCPT_SS: /* Stack segment exception. */
1487	case X86_XCPT_NP: /* Segment not present exception. */
1488	{
1489	Event.au64[0] = 0;
1490	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1491	Event.n.u1Valid = 1;
1492	Event.n.u8Vector = vector;
1493
1494	switch(vector)
1495	{
1496	case X86_XCPT_GP:
1497	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
1498	Event.n.u1ErrorCodeValid = 1;
1499	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1500	break;
1501	case X86_XCPT_DE:
1502	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
1503	break;
1504	case X86_XCPT_UD:
1505	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
1506	break;
1507	case X86_XCPT_SS:
1508	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
1509	Event.n.u1ErrorCodeValid = 1;
1510	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1511	break;
1512	case X86_XCPT_NP:
1513	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
1514	Event.n.u1ErrorCodeValid = 1;
1515	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1516	break;
1517	}
1518	Log(("Trap %x at %RGv esi=%x\n", vector, (RTGCPTR)pCtx->rip, pCtx->esi));
1519	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1520
1521	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1522	goto ResumeExecution;
1523	}
1524	#endif
1525	default:
1526	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1527	rc = VERR_EM_INTERNAL_ERROR;
1528	break;
1529
1530	} /* switch (vector) */
1531	break;
1532	}
1533
1534	case SVM_EXIT_NPF:
1535	{
1536	/* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1537	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1538	RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1539
1540	Assert(pVM->hwaccm.s.fNestedPaging);
1541	Log(("Nested page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1542	/* Exit qualification contains the linear address of the page fault. */
1543	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1544	TRPMSetErrorCode(pVM, errCode);
1545	TRPMSetFaultAddress(pVM, uFaultAddress);
1546
1547	/* Handle the pagefault trap for the nested shadow table. */
1548	rc = PGMR0Trap0eHandlerNestedPaging(pVM, PGMGetHostMode(pVM), errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1549	Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1550	if (rc == VINF_SUCCESS)
1551	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1552	Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1553	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1554
1555	TRPMResetTrap(pVM);
1556
1557	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1558	goto ResumeExecution;
1559	}
1560
1561	#ifdef VBOX_STRICT
1562	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1563	LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
1564	#endif
1565	/* Need to go back to the recompiler to emulate the instruction. */
1566	TRPMResetTrap(pVM);
1567	break;
1568	}
1569
1570	case SVM_EXIT_VINTR:
1571	/* A virtual interrupt is about to be delivered, which means IF=1. */
1572	Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1573	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1574	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1575	goto ResumeExecution;
1576
1577	case SVM_EXIT_FERR_FREEZE:
1578	case SVM_EXIT_INTR:
1579	case SVM_EXIT_NMI:
1580	case SVM_EXIT_SMI:
1581	case SVM_EXIT_INIT:
1582	/* External interrupt; leave to allow it to be dispatched again. */
1583	rc = VINF_EM_RAW_INTERRUPT;
1584	break;
1585
1586	case SVM_EXIT_WBINVD:
1587	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1588	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
1589	/* Skip instruction and continue directly. */
1590	pCtx->rip += 2; /* Note! hardcoded opcode size! */
1591	/* Continue execution.*/
1592	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1593	goto ResumeExecution;
1594
1595	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1596	{
1597	Log2(("SVM: Cpuid at %RGv for %x\n", (RTGCPTR)pCtx->rip, pCtx->eax));
1598	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
1599	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1600	if (rc == VINF_SUCCESS)
1601	{
1602	/* Update EIP and continue execution. */
1603	pCtx->rip += 2; /* Note! hardcoded opcode size! */
1604	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1605	goto ResumeExecution;
1606	}
1607	AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
1608	rc = VINF_EM_RAW_EMULATE_INSTR;
1609	break;
1610	}
1611
1612	case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1613	{
1614	Log2(("SVM: Rdtsc\n"));
1615	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1616	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1617	if (rc == VINF_SUCCESS)
1618	{
1619	/* Update EIP and continue execution. */
1620	pCtx->rip += 2; /* Note! hardcoded opcode size! */
1621	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1622	goto ResumeExecution;
1623	}
1624	AssertMsgFailed(("EMU: rdtsc failed with %Rrc\n", rc));
1625	rc = VINF_EM_RAW_EMULATE_INSTR;
1626	break;
1627	}
1628
1629	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1630	{
1631	Log2(("SVM: invlpg\n"));
1632	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
1633
1634	Assert(!pVM->hwaccm.s.fNestedPaging);
1635
1636	/* Truly a pita. Why can't SVM give the same information as VT-x? */
1637	rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1638	if (rc == VINF_SUCCESS)
1639	{
1640	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushPageInvlpg);
1641	goto ResumeExecution; /* eip already updated */
1642	}
1643	break;
1644	}
1645
1646	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1647	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1648	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1649	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1650	{
1651	uint32_t cbSize;
1652
1653	Log2(("SVM: %RGv mov cr%d, \n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
1654	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite);
1655	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1656
1657	switch (exitCode - SVM_EXIT_WRITE_CR0)
1658	{
1659	case 0:
1660	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1661	break;
1662	case 2:
1663	break;
1664	case 3:
1665	Assert(!pVM->hwaccm.s.fNestedPaging);
1666	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1667	break;
1668	case 4:
1669	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1670	break;
1671	case 8:
1672	break;
1673	default:
1674	AssertFailed();
1675	}
1676	/* Check if a sync operation is pending. */
1677	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1678	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1679	{
1680	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1681	AssertRC(rc);
1682
1683	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBCRxChange);
1684
1685	/* Must be set by PGMSyncCR3 */
1686	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PROTECTED \|\| pVCpu->hwaccm.s.fForceTLBFlush);
1687	}
1688	if (rc == VINF_SUCCESS)
1689	{
1690	/* EIP has been updated already. */
1691
1692	/* Only resume if successful. */
1693	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1694	goto ResumeExecution;
1695	}
1696	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1697	break;
1698	}
1699
1700	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1701	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1702	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1703	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1704	{
1705	uint32_t cbSize;
1706
1707	Log2(("SVM: %RGv mov x, cr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
1708	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead);
1709	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1710	if (rc == VINF_SUCCESS)
1711	{
1712	/* EIP has been updated already. */
1713
1714	/* Only resume if successful. */
1715	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1716	goto ResumeExecution;
1717	}
1718	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1719	break;
1720	}
1721
1722	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1723	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1724	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1725	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1726	{
1727	uint32_t cbSize;
1728
1729	Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
1730	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
1731
1732	if (!DBGFIsStepping(pVM))
1733	{
1734	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
1735
1736	/* Disable drx move intercepts. */
1737	pVMCB->ctrl.u16InterceptRdDRx = 0;
1738	pVMCB->ctrl.u16InterceptWrDRx = 0;
1739
1740	/* Save the host and load the guest debug state. */
1741	rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
1742	AssertRC(rc);
1743
1744	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1745	goto ResumeExecution;
1746	}
1747
1748	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1749	if (rc == VINF_SUCCESS)
1750	{
1751	/* EIP has been updated already. */
1752	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_DEBUG;
1753
1754	/* Only resume if successful. */
1755	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1756	goto ResumeExecution;
1757	}
1758	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1759	break;
1760	}
1761
1762	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1763	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1764	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1765	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1766	{
1767	uint32_t cbSize;
1768
1769	Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
1770	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
1771
1772	if (!DBGFIsStepping(pVM))
1773	{
1774	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
1775
1776	/* Disable drx move intercepts. */
1777	pVMCB->ctrl.u16InterceptRdDRx = 0;
1778	pVMCB->ctrl.u16InterceptWrDRx = 0;
1779
1780	/* Save the host and load the guest debug state. */
1781	rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
1782	AssertRC(rc);
1783
1784	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1785	goto ResumeExecution;
1786	}
1787
1788	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1789	if (rc == VINF_SUCCESS)
1790	{
1791	/* EIP has been updated already. */
1792
1793	/* Only resume if successful. */
1794	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1795	goto ResumeExecution;
1796	}
1797	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1798	break;
1799	}
1800
1801	/* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1802	case SVM_EXIT_IOIO: /* I/O instruction. */
1803	{
1804	SVM_IOIO_EXIT IoExitInfo;
1805	uint32_t uIOSize, uAndVal;
1806
1807	IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1808
1809	/** @todo could use a lookup table here */
1810	if (IoExitInfo.n.u1OP8)
1811	{
1812	uIOSize = 1;
1813	uAndVal = 0xff;
1814	}
1815	else
1816	if (IoExitInfo.n.u1OP16)
1817	{
1818	uIOSize = 2;
1819	uAndVal = 0xffff;
1820	}
1821	else
1822	if (IoExitInfo.n.u1OP32)
1823	{
1824	uIOSize = 4;
1825	uAndVal = 0xffffffff;
1826	}
1827	else
1828	{
1829	AssertFailed(); /* should be fatal. */
1830	rc = VINF_EM_RAW_EMULATE_INSTR;
1831	break;
1832	}
1833
1834	if (IoExitInfo.n.u1STR)
1835	{
1836	/* ins/outs */
1837	uint32_t prefix = 0;
1838	if (IoExitInfo.n.u1REP)
1839	prefix \|= PREFIX_REP;
1840
1841	if (IoExitInfo.n.u1Type == 0)
1842	{
1843	Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1844	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
1845	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1846	}
1847	else
1848	{
1849	Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1850	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
1851	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1852	}
1853	}
1854	else
1855	{
1856	/* normal in/out */
1857	Assert(!IoExitInfo.n.u1REP);
1858
1859	if (IoExitInfo.n.u1Type == 0)
1860	{
1861	Log2(("IOMIOPortWrite %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1862	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
1863	rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1864	}
1865	else
1866	{
1867	uint32_t u32Val = 0;
1868
1869	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
1870	rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1871	if (IOM_SUCCESS(rc))
1872	{
1873	/* Write back to the EAX register. */
1874	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1875	Log2(("IOMIOPortRead %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1876	}
1877	}
1878	}
1879	/*
1880	* Handled the I/O return codes.
1881	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1882	*/
1883	if (IOM_SUCCESS(rc))
1884	{
1885	/* Update EIP and continue execution. */
1886	pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1887	if (RT_LIKELY(rc == VINF_SUCCESS))
1888	{
1889	/* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
1890	if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
1891	{
1892	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
1893	for (unsigned i=0;i<4;i++)
1894	{
1895	unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
1896
1897	if ( (IoExitInfo.n.u16Port >= pCtx->dr[i] && IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen)
1898	&& (pCtx->dr[7] & (X86_DR7_L(i) \| X86_DR7_G(i)))
1899	&& (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
1900	{
1901	SVM_EVENT Event;
1902
1903	Assert(CPUMIsGuestDebugStateActive(pVM));
1904
1905	/* Clear all breakpoint status flags and set the one we just hit. */
1906	pCtx->dr[6] &= ~(X86_DR6_B0\|X86_DR6_B1\|X86_DR6_B2\|X86_DR6_B3);
1907	pCtx->dr[6] \|= (uint64_t)RT_BIT(i);
1908
1909	/* Note: AMD64 Architecture Programmer's Manual 13.1:
1910	* Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
1911	* the contents have been read.
1912	*/
1913	pVMCB->guest.u64DR6 = pCtx->dr[6];
1914
1915	/* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
1916	pCtx->dr[7] &= ~X86_DR7_GD;
1917
1918	/* Paranoia. */
1919	pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
1920	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
1921	pCtx->dr[7] \|= 0x400; /* must be one */
1922
1923	pVMCB->guest.u64DR7 = pCtx->dr[7];
1924
1925	/* Inject the exception. */
1926	Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
1927
1928	Event.au64[0] = 0;
1929	Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
1930	Event.n.u1Valid = 1;
1931	Event.n.u8Vector = X86_XCPT_DB;
1932
1933	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1934
1935	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1936	goto ResumeExecution;
1937	}
1938	}
1939	}
1940
1941	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1942	goto ResumeExecution;
1943	}
1944	Log2(("EM status from IO at %RGv %x size %d: %Rrc\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
1945	break;
1946	}
1947
1948	#ifdef VBOX_STRICT
1949	if (rc == VINF_IOM_HC_IOPORT_READ)
1950	Assert(IoExitInfo.n.u1Type != 0);
1951	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1952	Assert(IoExitInfo.n.u1Type == 0);
1953	else
1954	AssertMsg(RT_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
1955	#endif
1956	Log2(("Failed IO at %RGv %x size %d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1957	break;
1958	}
1959
1960	case SVM_EXIT_HLT:
1961	/** Check if external interrupts are pending; if so, don't switch back. */
1962	pCtx->rip++; /* skip hlt */
1963	if ( pCtx->eflags.Bits.u1IF
1964	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1965	goto ResumeExecution;
1966
1967	rc = VINF_EM_HALT;
1968	break;
1969
1970	case SVM_EXIT_RSM:
1971	case SVM_EXIT_INVLPGA:
1972	case SVM_EXIT_VMRUN:
1973	case SVM_EXIT_VMMCALL:
1974	case SVM_EXIT_VMLOAD:
1975	case SVM_EXIT_VMSAVE:
1976	case SVM_EXIT_STGI:
1977	case SVM_EXIT_CLGI:
1978	case SVM_EXIT_SKINIT:
1979	case SVM_EXIT_RDTSCP:
1980	{
1981	/* Unsupported instructions. */
1982	SVM_EVENT Event;
1983
1984	Event.au64[0] = 0;
1985	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1986	Event.n.u1Valid = 1;
1987	Event.n.u8Vector = X86_XCPT_UD;
1988
1989	Log(("Forced #UD trap at %RGv\n", (RTGCPTR)pCtx->rip));
1990	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1991
1992	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
1993	goto ResumeExecution;
1994	}
1995
1996	/* Emulate in ring 3. */
1997	case SVM_EXIT_MSR:
1998	{
1999	uint32_t cbSize;
2000
2001	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2002	Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
2003	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
2004	if (rc == VINF_SUCCESS)
2005	{
2006	/* EIP has been updated already. */
2007
2008	/* Only resume if successful. */
2009	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
2010	goto ResumeExecution;
2011	}
2012	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
2013	break;
2014	}
2015
2016	case SVM_EXIT_MONITOR:
2017	case SVM_EXIT_RDPMC:
2018	case SVM_EXIT_PAUSE:
2019	case SVM_EXIT_MWAIT_UNCOND:
2020	case SVM_EXIT_MWAIT_ARMED:
2021	case SVM_EXIT_TASK_SWITCH: /* can change CR3; emulate */
2022	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2023	break;
2024
2025	case SVM_EXIT_SHUTDOWN:
2026	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2027	break;
2028
2029	case SVM_EXIT_IDTR_READ:
2030	case SVM_EXIT_GDTR_READ:
2031	case SVM_EXIT_LDTR_READ:
2032	case SVM_EXIT_TR_READ:
2033	case SVM_EXIT_IDTR_WRITE:
2034	case SVM_EXIT_GDTR_WRITE:
2035	case SVM_EXIT_LDTR_WRITE:
2036	case SVM_EXIT_TR_WRITE:
2037	case SVM_EXIT_CR0_SEL_WRITE:
2038	default:
2039	/* Unexpected exit codes. */
2040	rc = VERR_EM_INTERNAL_ERROR;
2041	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
2042	break;
2043	}
2044
2045	end:
2046
2047	/* Signal changes for the recompiler. */
2048	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
2049
2050	/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
2051	if (exitCode == SVM_EXIT_INTR)
2052	{
2053	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
2054	/* On the next entry we'll only sync the host context. */
2055	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
2056	}
2057	else
2058	{
2059	/* On the next entry we'll sync everything. */
2060	/** @todo we can do better than this */
2061	/* Not in the VINF_PGM_CHANGE_MODE though! */
2062	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
2063	}
2064
2065	/* translate into a less severe return code */
2066	if (rc == VERR_EM_INTERPRETER)
2067	rc = VINF_EM_RAW_EMULATE_INSTR;
2068
2069	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
2070	return rc;
2071	}
2072
2073	/**
2074	* Enters the AMD-V session
2075	*
2076	* @returns VBox status code.
2077	* @param pVM The VM to operate on.
2078	* @param pVCpu The VM CPU to operate on.
2079	* @param pCpu CPU info struct
2080	*/
2081	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
2082	{
2083	Assert(pVM->hwaccm.s.svm.fSupported);
2084
2085	LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVCpu->hwaccm.s.idLastCpu, pVCpu->hwaccm.s.uCurrentASID));
2086	pVCpu->hwaccm.s.fResumeVM = false;
2087
2088	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
2089	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_LDTR;
2090
2091	return VINF_SUCCESS;
2092	}
2093
2094
2095	/**
2096	* Leaves the AMD-V session
2097	*
2098	* @returns VBox status code.
2099	* @param pVM The VM to operate on.
2100	* @param pVCpu The VM CPU to operate on.
2101	* @param pCtx CPU context
2102	*/
2103	VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2104	{
2105	SVM_VMCB pVMCB = (SVM_VMCB )pVCpu->hwaccm.s.svm.pVMCB;
2106
2107	Assert(pVM->hwaccm.s.svm.fSupported);
2108
2109	/* Save the guest debug state if necessary. */
2110	if (CPUMIsGuestDebugStateActive(pVM))
2111	{
2112	CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, false /* skip DR6 */);
2113
2114	/* Intercept all DRx reads and writes again. Changed later on. */
2115	pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
2116	pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
2117
2118	/* Resync the debug registers the next time. */
2119	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_DEBUG;
2120	}
2121	else
2122	Assert(pVMCB->ctrl.u16InterceptRdDRx == 0xFFFF && pVMCB->ctrl.u16InterceptWrDRx == 0xFFFF);
2123
2124	return VINF_SUCCESS;
2125	}
2126
2127
2128	static int svmR0InterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2129	{
2130	OP_PARAMVAL param1;
2131	RTGCPTR addr;
2132
2133	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2134	if(RT_FAILURE(rc))
2135	return VERR_EM_INTERPRETER;
2136
2137	switch(param1.type)
2138	{
2139	case PARMTYPE_IMMEDIATE:
2140	case PARMTYPE_ADDRESS:
2141	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
2142	return VERR_EM_INTERPRETER;
2143	addr = param1.val.val64;
2144	break;
2145
2146	default:
2147	return VERR_EM_INTERPRETER;
2148	}
2149
2150	/** @todo is addr always a flat linear address or ds based
2151	* (in absence of segment override prefixes)????
2152	*/
2153	rc = PGMInvalidatePage(pVM, addr);
2154	if (RT_SUCCESS(rc))
2155	{
2156	/* Manually invalidate the page for the VM's TLB. */
2157	Log(("SVMR0InvlpgA %RGv ASID=%d\n", addr, uASID));
2158	SVMR0InvlpgA(addr, uASID);
2159	return VINF_SUCCESS;
2160	}
2161	Assert(rc == VERR_REM_FLUSHED_PAGES_OVERFLOW);
2162	return rc;
2163	}
2164
2165	/**
2166	* Interprets INVLPG
2167	*
2168	* @returns VBox status code.
2169	* @retval VINF_* Scheduling instructions.
2170	* @retval VERR_EM_INTERPRETER Something we can't cope with.
2171	* @retval VERR_* Fatal errors.
2172	*
2173	* @param pVM The VM handle.
2174	* @param pRegFrame The register frame.
2175	* @param ASID Tagged TLB id for the guest
2176	*
2177	* Updates the EIP if an instruction was executed successfully.
2178	*/
2179	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2180	{
2181	/*
2182	* Only allow 32 & 64 bits code.
2183	*/
2184	DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
2185	if (enmMode != CPUMODE_16BIT)
2186	{
2187	RTGCPTR pbCode;
2188	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
2189	if (RT_SUCCESS(rc))
2190	{
2191	uint32_t cbOp;
2192	DISCPUSTATE Cpu;
2193
2194	Cpu.mode = enmMode;
2195	rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
2196	Assert(RT_FAILURE(rc) \|\| Cpu.pCurInstr->opcode == OP_INVLPG);
2197	if (RT_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
2198	{
2199	Assert(cbOp == Cpu.opsize);
2200	rc = svmR0InterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
2201	if (RT_SUCCESS(rc))
2202	{
2203	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
2204	}
2205	return rc;
2206	}
2207	}
2208	}
2209	return VERR_EM_INTERPRETER;
2210	}
2211
2212
2213	/**
2214	* Invalidates a guest page
2215	*
2216	* @returns VBox status code.
2217	* @param pVM The VM to operate on.
2218	* @param pVCpu The VM CPU to operate on.
2219	* @param GCVirt Page to invalidate
2220	*/
2221	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
2222	{
2223	bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB \| pVCpu->hwaccm.s.fForceTLBFlush;
2224
2225	/* Skip it if a TLB flush is already pending. */
2226	if (!fFlushPending)
2227	{
2228	SVM_VMCB *pVMCB;
2229
2230	Log2(("SVMR0InvalidatePage %RGv\n", GCVirt));
2231	AssertReturn(pVM, VERR_INVALID_PARAMETER);
2232	Assert(pVM->hwaccm.s.svm.fSupported);
2233
2234	/* @todo SMP */
2235	pVMCB = (SVM_VMCB *)pVM->aCpus[0].hwaccm.s.svm.pVMCB;
2236	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2237
2238	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushPageManual);
2239	SVMR0InvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2240	}
2241	return VINF_SUCCESS;
2242	}
2243
2244
2245	/**
2246	* Invalidates a guest page by physical address
2247	*
2248	* @returns VBox status code.
2249	* @param pVM The VM to operate on.
2250	* @param pVCpu The VM CPU to operate on.
2251	* @param GCPhys Page to invalidate
2252	*/
2253	VMMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
2254	{
2255	Assert(pVM->hwaccm.s.fNestedPaging);
2256	/* invlpga only invalidates TLB entries for guest virtual addresses; we have no choice but to force a TLB flush here. */
2257	pVCpu->hwaccm.s.fForceTLBFlush = true;
2258	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBInvlpga);
2259	return VINF_SUCCESS;
2260	}
2261
2262	#ifdef HC_ARCH_BITS == 32
2263	/**
2264	* Prepares for and executes VMRUN (64 bits guests from a 32 bits hosts).
2265	*
2266	* @returns VBox status code.
2267	* @param pVMCBHostPhys Physical address of host VMCB.
2268	* @param pVMCBPhys Physical address of the VMCB.
2269	* @param pCtx Guest context.
2270	*/
2271	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx)
2272	{
2273	return VERR_NOT_IMPLEMENTED;
2274	}
2275
2276	#endif /* HC_ARCH_BITS == 32 */

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 14366

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