1 | /* $Id: HWSVMR0.cpp 14945 2008-12-03 14:14:27Z vboxsync $ */
|
---|
2 | /** @file
|
---|
3 | * HWACCM SVM - Host Context Ring 0.
|
---|
4 | */
|
---|
5 |
|
---|
6 | /*
|
---|
7 | * Copyright (C) 2006-2007 Sun Microsystems, Inc.
|
---|
8 | *
|
---|
9 | * This file is part of VirtualBox Open Source Edition (OSE), as
|
---|
10 | * available from http://www.virtualbox.org. This file is free software;
|
---|
11 | * you can redistribute it and/or modify it under the terms of the GNU
|
---|
12 | * General Public License (GPL) as published by the Free Software
|
---|
13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
|
---|
14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
|
---|
15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
|
---|
16 | *
|
---|
17 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
|
---|
18 | * Clara, CA 95054 USA or visit http://www.sun.com if you need
|
---|
19 | * additional information or have any questions.
|
---|
20 | */
|
---|
21 |
|
---|
22 |
|
---|
23 | /*******************************************************************************
|
---|
24 | * Header Files *
|
---|
25 | *******************************************************************************/
|
---|
26 | #define LOG_GROUP LOG_GROUP_HWACCM
|
---|
27 | #include <VBox/hwaccm.h>
|
---|
28 | #include "HWACCMInternal.h"
|
---|
29 | #include <VBox/vm.h>
|
---|
30 | #include <VBox/x86.h>
|
---|
31 | #include <VBox/hwacc_svm.h>
|
---|
32 | #include <VBox/pgm.h>
|
---|
33 | #include <VBox/pdm.h>
|
---|
34 | #include <VBox/err.h>
|
---|
35 | #include <VBox/log.h>
|
---|
36 | #include <VBox/selm.h>
|
---|
37 | #include <VBox/iom.h>
|
---|
38 | #include <VBox/dis.h>
|
---|
39 | #include <VBox/dbgf.h>
|
---|
40 | #include <VBox/disopcode.h>
|
---|
41 | #include <iprt/param.h>
|
---|
42 | #include <iprt/assert.h>
|
---|
43 | #include <iprt/asm.h>
|
---|
44 | #include <iprt/cpuset.h>
|
---|
45 | #include <iprt/mp.h>
|
---|
46 | #include "HWSVMR0.h"
|
---|
47 |
|
---|
48 | /*******************************************************************************
|
---|
49 | * Internal Functions *
|
---|
50 | *******************************************************************************/
|
---|
51 | static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
|
---|
52 |
|
---|
53 | /*******************************************************************************
|
---|
54 | * Global Variables *
|
---|
55 | *******************************************************************************/
|
---|
56 | /* IO operation lookup arrays. */
|
---|
57 | static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
|
---|
58 |
|
---|
59 | /**
|
---|
60 | * Sets up and activates AMD-V on the current CPU
|
---|
61 | *
|
---|
62 | * @returns VBox status code.
|
---|
63 | * @param pCpu CPU info struct
|
---|
64 | * @param pVM The VM to operate on. (can be NULL after a resume!!)
|
---|
65 | * @param pvPageCpu Pointer to the global cpu page
|
---|
66 | * @param pPageCpuPhys Physical address of the global cpu page
|
---|
67 | */
|
---|
68 | VMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
|
---|
69 | {
|
---|
70 | AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
|
---|
71 | AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
|
---|
72 |
|
---|
73 | /* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
|
---|
74 |
|
---|
75 | #ifdef LOG_ENABLED
|
---|
76 | SUPR0Printf("SVMR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
|
---|
77 | #endif
|
---|
78 |
|
---|
79 | /* Turn on AMD-V in the EFER MSR. */
|
---|
80 | uint64_t val = ASMRdMsr(MSR_K6_EFER);
|
---|
81 | if (!(val & MSR_K6_EFER_SVME))
|
---|
82 | ASMWrMsr(MSR_K6_EFER, val | MSR_K6_EFER_SVME);
|
---|
83 |
|
---|
84 | /* Write the physical page address where the CPU will store the host state while executing the VM. */
|
---|
85 | ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
|
---|
86 |
|
---|
87 | return VINF_SUCCESS;
|
---|
88 | }
|
---|
89 |
|
---|
90 | /**
|
---|
91 | * Deactivates AMD-V on the current CPU
|
---|
92 | *
|
---|
93 | * @returns VBox status code.
|
---|
94 | * @param pCpu CPU info struct
|
---|
95 | * @param pvPageCpu Pointer to the global cpu page
|
---|
96 | * @param pPageCpuPhys Physical address of the global cpu page
|
---|
97 | */
|
---|
98 | VMMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
|
---|
99 | {
|
---|
100 | AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
|
---|
101 | AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
|
---|
102 |
|
---|
103 | #ifdef LOG_ENABLED
|
---|
104 | SUPR0Printf("SVMR0DisableCpu cpu %d\n", pCpu->idCpu);
|
---|
105 | #endif
|
---|
106 |
|
---|
107 | /* Turn off AMD-V in the EFER MSR. */
|
---|
108 | uint64_t val = ASMRdMsr(MSR_K6_EFER);
|
---|
109 | ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
|
---|
110 |
|
---|
111 | /* Invalidate host state physical address. */
|
---|
112 | ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
|
---|
113 |
|
---|
114 | return VINF_SUCCESS;
|
---|
115 | }
|
---|
116 |
|
---|
117 | /**
|
---|
118 | * Does Ring-0 per VM AMD-V init.
|
---|
119 | *
|
---|
120 | * @returns VBox status code.
|
---|
121 | * @param pVM The VM to operate on.
|
---|
122 | */
|
---|
123 | VMMR0DECL(int) SVMR0InitVM(PVM pVM)
|
---|
124 | {
|
---|
125 | int rc;
|
---|
126 |
|
---|
127 | pVM->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
|
---|
128 | pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
|
---|
129 | pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
|
---|
130 |
|
---|
131 | /* Allocate one page for the host context */
|
---|
132 | rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
|
---|
133 | if (RT_FAILURE(rc))
|
---|
134 | return rc;
|
---|
135 |
|
---|
136 | pVM->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCBHost);
|
---|
137 | pVM->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCBHost, 0);
|
---|
138 | ASMMemZeroPage(pVM->hwaccm.s.svm.pVMCBHost);
|
---|
139 |
|
---|
140 | /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
|
---|
141 | rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
|
---|
142 | if (RT_FAILURE(rc))
|
---|
143 | return rc;
|
---|
144 |
|
---|
145 | pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
|
---|
146 | pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
|
---|
147 | /* Set all bits to intercept all IO accesses. */
|
---|
148 | ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
|
---|
149 |
|
---|
150 | /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
|
---|
151 | rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
|
---|
152 | if (RT_FAILURE(rc))
|
---|
153 | return rc;
|
---|
154 |
|
---|
155 | pVM->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
|
---|
156 | pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
|
---|
157 | /* Set all bits to intercept all MSR accesses. */
|
---|
158 | ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
|
---|
159 |
|
---|
160 | /* Erratum 170 which requires a forced TLB flush for each world switch:
|
---|
161 | * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
|
---|
162 | *
|
---|
163 | * All BH-G1/2 and DH-G1/2 models include a fix:
|
---|
164 | * Athlon X2: 0x6b 1/2
|
---|
165 | * 0x68 1/2
|
---|
166 | * Athlon 64: 0x7f 1
|
---|
167 | * 0x6f 2
|
---|
168 | * Sempron: 0x7f 1/2
|
---|
169 | * 0x6f 2
|
---|
170 | * 0x6c 2
|
---|
171 | * 0x7c 2
|
---|
172 | * Turion 64: 0x68 2
|
---|
173 | *
|
---|
174 | */
|
---|
175 | uint32_t u32Dummy;
|
---|
176 | uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
|
---|
177 | ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
|
---|
178 | u32BaseFamily= (u32Version >> 8) & 0xf;
|
---|
179 | u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
|
---|
180 | u32Model = ((u32Version >> 4) & 0xf);
|
---|
181 | u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
|
---|
182 | u32Stepping = u32Version & 0xf;
|
---|
183 | if ( u32Family == 0xf
|
---|
184 | && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
|
---|
185 | && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
|
---|
186 | {
|
---|
187 | Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
|
---|
188 | pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
|
---|
189 | }
|
---|
190 |
|
---|
191 | /* Allocate VMCBs for all guest CPUs. */
|
---|
192 | for (unsigned i=0;i<pVM->cCPUs;i++)
|
---|
193 | {
|
---|
194 | pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
|
---|
195 |
|
---|
196 | /* Allocate one page for the VM control block (VMCB). */
|
---|
197 | rc = RTR0MemObjAllocCont(&pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
|
---|
198 | if (RT_FAILURE(rc))
|
---|
199 | return rc;
|
---|
200 |
|
---|
201 | pVM->aCpus[i].hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB);
|
---|
202 | pVM->aCpus[i].hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB, 0);
|
---|
203 | ASMMemZeroPage(pVM->aCpus[i].hwaccm.s.svm.pVMCB);
|
---|
204 | }
|
---|
205 |
|
---|
206 | return VINF_SUCCESS;
|
---|
207 | }
|
---|
208 |
|
---|
209 | /**
|
---|
210 | * Does Ring-0 per VM AMD-V termination.
|
---|
211 | *
|
---|
212 | * @returns VBox status code.
|
---|
213 | * @param pVM The VM to operate on.
|
---|
214 | */
|
---|
215 | VMMR0DECL(int) SVMR0TermVM(PVM pVM)
|
---|
216 | {
|
---|
217 | for (unsigned i=0;i<pVM->cCPUs;i++)
|
---|
218 | {
|
---|
219 | if (pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)
|
---|
220 | {
|
---|
221 | RTR0MemObjFree(pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB, false);
|
---|
222 | pVM->aCpus[i].hwaccm.s.svm.pVMCB = 0;
|
---|
223 | pVM->aCpus[i].hwaccm.s.svm.pVMCBPhys = 0;
|
---|
224 | pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
|
---|
225 | }
|
---|
226 | }
|
---|
227 | if (pVM->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ)
|
---|
228 | {
|
---|
229 | RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCBHost, false);
|
---|
230 | pVM->hwaccm.s.svm.pVMCBHost = 0;
|
---|
231 | pVM->hwaccm.s.svm.pVMCBHostPhys = 0;
|
---|
232 | pVM->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
|
---|
233 | }
|
---|
234 | if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)
|
---|
235 | {
|
---|
236 | RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
|
---|
237 | pVM->hwaccm.s.svm.pIOBitmap = 0;
|
---|
238 | pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
|
---|
239 | pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
|
---|
240 | }
|
---|
241 | if (pVM->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
|
---|
242 | {
|
---|
243 | RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
|
---|
244 | pVM->hwaccm.s.svm.pMSRBitmap = 0;
|
---|
245 | pVM->hwaccm.s.svm.pMSRBitmapPhys = 0;
|
---|
246 | pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
|
---|
247 | }
|
---|
248 | return VINF_SUCCESS;
|
---|
249 | }
|
---|
250 |
|
---|
251 | /**
|
---|
252 | * Sets up AMD-V for the specified VM
|
---|
253 | *
|
---|
254 | * @returns VBox status code.
|
---|
255 | * @param pVM The VM to operate on.
|
---|
256 | */
|
---|
257 | VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
|
---|
258 | {
|
---|
259 | int rc = VINF_SUCCESS;
|
---|
260 | SVM_VMCB *pVMCB;
|
---|
261 |
|
---|
262 | AssertReturn(pVM, VERR_INVALID_PARAMETER);
|
---|
263 |
|
---|
264 | Assert(pVM->hwaccm.s.svm.fSupported);
|
---|
265 |
|
---|
266 | for (unsigned i=0;i<pVM->cCPUs;i++)
|
---|
267 | {
|
---|
268 | pVMCB = (SVM_VMCB *)pVM->aCpus[i].hwaccm.s.svm.pVMCB;
|
---|
269 | AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
|
---|
270 |
|
---|
271 | /* Program the control fields. Most of them never have to be changed again. */
|
---|
272 | /* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
|
---|
273 | /* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical. */
|
---|
274 | if (!pVM->hwaccm.s.fNestedPaging)
|
---|
275 | pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
|
---|
276 | else
|
---|
277 | pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(4);
|
---|
278 |
|
---|
279 | /*
|
---|
280 | * CR0/3/4 writes must be intercepted for obvious reasons.
|
---|
281 | */
|
---|
282 | if (!pVM->hwaccm.s.fNestedPaging)
|
---|
283 | pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
|
---|
284 | else
|
---|
285 | pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(4) | RT_BIT(8);
|
---|
286 |
|
---|
287 | /* Intercept all DRx reads and writes by default. Changed later on. */
|
---|
288 | pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
|
---|
289 | pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
|
---|
290 |
|
---|
291 | /* Currently we don't care about DRx reads or writes. DRx registers are trashed.
|
---|
292 | * All breakpoints are automatically cleared when the VM exits.
|
---|
293 | */
|
---|
294 |
|
---|
295 | pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
|
---|
296 | #ifndef DEBUG
|
---|
297 | if (pVM->hwaccm.s.fNestedPaging)
|
---|
298 | pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
|
---|
299 | #endif
|
---|
300 |
|
---|
301 | pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
|
---|
302 | | SVM_CTRL1_INTERCEPT_VINTR
|
---|
303 | | SVM_CTRL1_INTERCEPT_NMI
|
---|
304 | | SVM_CTRL1_INTERCEPT_SMI
|
---|
305 | | SVM_CTRL1_INTERCEPT_INIT
|
---|
306 | | SVM_CTRL1_INTERCEPT_RDPMC
|
---|
307 | | SVM_CTRL1_INTERCEPT_CPUID
|
---|
308 | | SVM_CTRL1_INTERCEPT_RSM
|
---|
309 | | SVM_CTRL1_INTERCEPT_HLT
|
---|
310 | | SVM_CTRL1_INTERCEPT_INOUT_BITMAP
|
---|
311 | | SVM_CTRL1_INTERCEPT_MSR_SHADOW
|
---|
312 | | SVM_CTRL1_INTERCEPT_INVLPG
|
---|
313 | | SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
|
---|
314 | | SVM_CTRL1_INTERCEPT_TASK_SWITCH
|
---|
315 | | SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
|
---|
316 | | SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
|
---|
317 | ;
|
---|
318 | /* With nested paging we don't care about invlpg anymore. */
|
---|
319 | if (pVM->hwaccm.s.fNestedPaging)
|
---|
320 | pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
|
---|
321 |
|
---|
322 | pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
|
---|
323 | | SVM_CTRL2_INTERCEPT_VMMCALL
|
---|
324 | | SVM_CTRL2_INTERCEPT_VMLOAD
|
---|
325 | | SVM_CTRL2_INTERCEPT_VMSAVE
|
---|
326 | | SVM_CTRL2_INTERCEPT_STGI
|
---|
327 | | SVM_CTRL2_INTERCEPT_CLGI
|
---|
328 | | SVM_CTRL2_INTERCEPT_SKINIT
|
---|
329 | | SVM_CTRL2_INTERCEPT_WBINVD
|
---|
330 | | SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
|
---|
331 | ;
|
---|
332 | Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
|
---|
333 | Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
|
---|
334 | Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
|
---|
335 |
|
---|
336 | /* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
|
---|
337 | pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
|
---|
338 | /* Ignore the priority in the TPR; just deliver it when we tell it to. */
|
---|
339 | pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
|
---|
340 |
|
---|
341 | /* Set IO and MSR bitmap addresses. */
|
---|
342 | pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
|
---|
343 | pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
|
---|
344 |
|
---|
345 | /* No LBR virtualization. */
|
---|
346 | pVMCB->ctrl.u64LBRVirt = 0;
|
---|
347 |
|
---|
348 | /** The ASID must start at 1; the host uses 0. */
|
---|
349 | pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
|
---|
350 |
|
---|
351 | /** Setup the PAT msr (nested paging only) */
|
---|
352 | pVMCB->guest.u64GPAT = 0x0007040600070406ULL;
|
---|
353 | }
|
---|
354 | return rc;
|
---|
355 | }
|
---|
356 |
|
---|
357 |
|
---|
358 | /**
|
---|
359 | * Injects an event (trap or external interrupt)
|
---|
360 | *
|
---|
361 | * @param pVM The VM to operate on.
|
---|
362 | * @param pVMCB SVM control block
|
---|
363 | * @param pCtx CPU Context
|
---|
364 | * @param pIntInfo SVM interrupt info
|
---|
365 | */
|
---|
366 | inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB *pVMCB, CPUMCTX *pCtx, SVM_EVENT* pEvent)
|
---|
367 | {
|
---|
368 | #ifdef VBOX_STRICT
|
---|
369 | if (pEvent->n.u8Vector == 0xE)
|
---|
370 | Log(("SVM: Inject int %d at %RGv error code=%02x CR2=%RGv intInfo=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode, (RTGCPTR)pCtx->cr2, pEvent->au64[0]));
|
---|
371 | else
|
---|
372 | if (pEvent->n.u8Vector < 0x20)
|
---|
373 | Log(("SVM: Inject int %d at %RGv error code=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode));
|
---|
374 | else
|
---|
375 | {
|
---|
376 | Log(("INJ-EI: %x at %RGv\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip));
|
---|
377 | Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
|
---|
378 | Assert(pCtx->eflags.u32 & X86_EFL_IF);
|
---|
379 | }
|
---|
380 | #endif
|
---|
381 |
|
---|
382 | /* Set event injection state. */
|
---|
383 | pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
|
---|
384 | }
|
---|
385 |
|
---|
386 |
|
---|
387 | /**
|
---|
388 | * Checks for pending guest interrupts and injects them
|
---|
389 | *
|
---|
390 | * @returns VBox status code.
|
---|
391 | * @param pVM The VM to operate on.
|
---|
392 | * @param pVCpu The VM CPU to operate on.
|
---|
393 | * @param pVMCB SVM control block
|
---|
394 | * @param pCtx CPU Context
|
---|
395 | */
|
---|
396 | static int SVMR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx)
|
---|
397 | {
|
---|
398 | int rc;
|
---|
399 |
|
---|
400 | /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
|
---|
401 | if (pVCpu->hwaccm.s.Event.fPending)
|
---|
402 | {
|
---|
403 | SVM_EVENT Event;
|
---|
404 |
|
---|
405 | Log(("Reinjecting event %08x %08x at %RGv\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip));
|
---|
406 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
|
---|
407 | Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
|
---|
408 | SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
|
---|
409 |
|
---|
410 | pVCpu->hwaccm.s.Event.fPending = false;
|
---|
411 | return VINF_SUCCESS;
|
---|
412 | }
|
---|
413 |
|
---|
414 | if (pVM->hwaccm.s.fInjectNMI)
|
---|
415 | {
|
---|
416 | SVM_EVENT Event;
|
---|
417 |
|
---|
418 | Event.n.u8Vector = X86_XCPT_NMI;
|
---|
419 | Event.n.u1Valid = 1;
|
---|
420 | Event.n.u32ErrorCode = 0;
|
---|
421 | Event.n.u3Type = SVM_EVENT_NMI;
|
---|
422 |
|
---|
423 | SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
|
---|
424 | pVM->hwaccm.s.fInjectNMI = false;
|
---|
425 | return VINF_SUCCESS;
|
---|
426 | }
|
---|
427 |
|
---|
428 | /* When external interrupts are pending, we should exit the VM when IF is set. */
|
---|
429 | if ( !TRPMHasTrap(pVM)
|
---|
430 | && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
|
---|
431 | {
|
---|
432 | if ( !(pCtx->eflags.u32 & X86_EFL_IF)
|
---|
433 | || VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
|
---|
434 | {
|
---|
435 | if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
|
---|
436 | {
|
---|
437 | if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
|
---|
438 | LogFlow(("Enable irq window exit!\n"));
|
---|
439 | else
|
---|
440 | Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", (RTGCPTR)pCtx->rip));
|
---|
441 |
|
---|
442 | /** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
|
---|
443 | pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_VINTR;
|
---|
444 | pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
|
---|
445 | pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
|
---|
446 | }
|
---|
447 | }
|
---|
448 | else
|
---|
449 | {
|
---|
450 | uint8_t u8Interrupt;
|
---|
451 |
|
---|
452 | rc = PDMGetInterrupt(pVM, &u8Interrupt);
|
---|
453 | Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
|
---|
454 | if (RT_SUCCESS(rc))
|
---|
455 | {
|
---|
456 | rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
|
---|
457 | AssertRC(rc);
|
---|
458 | }
|
---|
459 | else
|
---|
460 | {
|
---|
461 | /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
|
---|
462 | Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)));
|
---|
463 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
|
---|
464 | /* Just continue */
|
---|
465 | }
|
---|
466 | }
|
---|
467 | }
|
---|
468 |
|
---|
469 | #ifdef VBOX_STRICT
|
---|
470 | if (TRPMHasTrap(pVM))
|
---|
471 | {
|
---|
472 | uint8_t u8Vector;
|
---|
473 | rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
|
---|
474 | AssertRC(rc);
|
---|
475 | }
|
---|
476 | #endif
|
---|
477 |
|
---|
478 | if ( pCtx->eflags.u32 & X86_EFL_IF
|
---|
479 | && (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
|
---|
480 | && TRPMHasTrap(pVM)
|
---|
481 | )
|
---|
482 | {
|
---|
483 | uint8_t u8Vector;
|
---|
484 | int rc;
|
---|
485 | TRPMEVENT enmType;
|
---|
486 | SVM_EVENT Event;
|
---|
487 | RTGCUINT u32ErrorCode;
|
---|
488 |
|
---|
489 | Event.au64[0] = 0;
|
---|
490 |
|
---|
491 | /* If a new event is pending, then dispatch it now. */
|
---|
492 | rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &u32ErrorCode, 0);
|
---|
493 | AssertRC(rc);
|
---|
494 | Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
|
---|
495 | Assert(enmType != TRPM_SOFTWARE_INT);
|
---|
496 |
|
---|
497 | /* Clear the pending trap. */
|
---|
498 | rc = TRPMResetTrap(pVM);
|
---|
499 | AssertRC(rc);
|
---|
500 |
|
---|
501 | Event.n.u8Vector = u8Vector;
|
---|
502 | Event.n.u1Valid = 1;
|
---|
503 | Event.n.u32ErrorCode = u32ErrorCode;
|
---|
504 |
|
---|
505 | if (enmType == TRPM_TRAP)
|
---|
506 | {
|
---|
507 | switch (u8Vector) {
|
---|
508 | case 8:
|
---|
509 | case 10:
|
---|
510 | case 11:
|
---|
511 | case 12:
|
---|
512 | case 13:
|
---|
513 | case 14:
|
---|
514 | case 17:
|
---|
515 | /* Valid error codes. */
|
---|
516 | Event.n.u1ErrorCodeValid = 1;
|
---|
517 | break;
|
---|
518 | default:
|
---|
519 | break;
|
---|
520 | }
|
---|
521 | if (u8Vector == X86_XCPT_NMI)
|
---|
522 | Event.n.u3Type = SVM_EVENT_NMI;
|
---|
523 | else
|
---|
524 | Event.n.u3Type = SVM_EVENT_EXCEPTION;
|
---|
525 | }
|
---|
526 | else
|
---|
527 | Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
|
---|
528 |
|
---|
529 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
|
---|
530 | SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
|
---|
531 | } /* if (interrupts can be dispatched) */
|
---|
532 |
|
---|
533 | return VINF_SUCCESS;
|
---|
534 | }
|
---|
535 |
|
---|
536 | /**
|
---|
537 | * Save the host state
|
---|
538 | *
|
---|
539 | * @returns VBox status code.
|
---|
540 | * @param pVM The VM to operate on.
|
---|
541 | * @param pVCpu The VM CPU to operate on.
|
---|
542 | */
|
---|
543 | VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
|
---|
544 | {
|
---|
545 | NOREF(pVM);
|
---|
546 | NOREF(pVCpu);
|
---|
547 | /* Nothing to do here. */
|
---|
548 | return VINF_SUCCESS;
|
---|
549 | }
|
---|
550 |
|
---|
551 | /**
|
---|
552 | * Loads the guest state
|
---|
553 | *
|
---|
554 | * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
|
---|
555 | *
|
---|
556 | * @returns VBox status code.
|
---|
557 | * @param pVM The VM to operate on.
|
---|
558 | * @param pVCpu The VM CPU to operate on.
|
---|
559 | * @param pCtx Guest context
|
---|
560 | */
|
---|
561 | VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
|
---|
562 | {
|
---|
563 | RTGCUINTPTR val;
|
---|
564 | SVM_VMCB *pVMCB;
|
---|
565 |
|
---|
566 | if (pVM == NULL)
|
---|
567 | return VERR_INVALID_PARAMETER;
|
---|
568 |
|
---|
569 | /* Setup AMD SVM. */
|
---|
570 | Assert(pVM->hwaccm.s.svm.fSupported);
|
---|
571 |
|
---|
572 | pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
|
---|
573 | AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
|
---|
574 |
|
---|
575 | /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
|
---|
576 | if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
|
---|
577 | {
|
---|
578 | SVM_WRITE_SELREG(CS, cs);
|
---|
579 | SVM_WRITE_SELREG(SS, ss);
|
---|
580 | SVM_WRITE_SELREG(DS, ds);
|
---|
581 | SVM_WRITE_SELREG(ES, es);
|
---|
582 | SVM_WRITE_SELREG(FS, fs);
|
---|
583 | SVM_WRITE_SELREG(GS, gs);
|
---|
584 | }
|
---|
585 |
|
---|
586 | /* Guest CPU context: LDTR. */
|
---|
587 | if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
|
---|
588 | {
|
---|
589 | SVM_WRITE_SELREG(LDTR, ldtr);
|
---|
590 | }
|
---|
591 |
|
---|
592 | /* Guest CPU context: TR. */
|
---|
593 | if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
|
---|
594 | {
|
---|
595 | SVM_WRITE_SELREG(TR, tr);
|
---|
596 | }
|
---|
597 |
|
---|
598 | /* Guest CPU context: GDTR. */
|
---|
599 | if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
|
---|
600 | {
|
---|
601 | pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
|
---|
602 | pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
|
---|
603 | }
|
---|
604 |
|
---|
605 | /* Guest CPU context: IDTR. */
|
---|
606 | if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
|
---|
607 | {
|
---|
608 | pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
|
---|
609 | pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
|
---|
610 | }
|
---|
611 |
|
---|
612 | /*
|
---|
613 | * Sysenter MSRs (unconditional)
|
---|
614 | */
|
---|
615 | pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
|
---|
616 | pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
|
---|
617 | pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
|
---|
618 |
|
---|
619 | /* Control registers */
|
---|
620 | if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
|
---|
621 | {
|
---|
622 | val = pCtx->cr0;
|
---|
623 | if (!CPUMIsGuestFPUStateActive(pVCpu))
|
---|
624 | {
|
---|
625 | /* Always use #NM exceptions to load the FPU/XMM state on demand. */
|
---|
626 | val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
|
---|
627 | }
|
---|
628 | else
|
---|
629 | {
|
---|
630 | /** @todo check if we support the old style mess correctly. */
|
---|
631 | if (!(val & X86_CR0_NE))
|
---|
632 | {
|
---|
633 | Log(("Forcing X86_CR0_NE!!!\n"));
|
---|
634 |
|
---|
635 | /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
|
---|
636 | if (!pVCpu->hwaccm.s.fFPUOldStyleOverride)
|
---|
637 | {
|
---|
638 | pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_MF);
|
---|
639 | pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
|
---|
640 | }
|
---|
641 | }
|
---|
642 | val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
|
---|
643 | }
|
---|
644 | /* Always enable caching. */
|
---|
645 | val &= ~(X86_CR0_CD|X86_CR0_NW);
|
---|
646 |
|
---|
647 | /* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
|
---|
648 | /* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
|
---|
649 | if (!pVM->hwaccm.s.fNestedPaging)
|
---|
650 | {
|
---|
651 | val |= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
|
---|
652 | val |= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
|
---|
653 | }
|
---|
654 | pVMCB->guest.u64CR0 = val;
|
---|
655 | }
|
---|
656 | /* CR2 as well */
|
---|
657 | pVMCB->guest.u64CR2 = pCtx->cr2;
|
---|
658 |
|
---|
659 | if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
|
---|
660 | {
|
---|
661 | /* Save our shadow CR3 register. */
|
---|
662 | if (pVM->hwaccm.s.fNestedPaging)
|
---|
663 | {
|
---|
664 | pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVM, PGMGetHostMode(pVM));
|
---|
665 | Assert(pVMCB->ctrl.u64NestedPagingCR3);
|
---|
666 | pVMCB->guest.u64CR3 = pCtx->cr3;
|
---|
667 | }
|
---|
668 | else
|
---|
669 | {
|
---|
670 | pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
|
---|
671 | Assert(pVMCB->guest.u64CR3);
|
---|
672 | }
|
---|
673 | }
|
---|
674 |
|
---|
675 | if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
|
---|
676 | {
|
---|
677 | val = pCtx->cr4;
|
---|
678 | if (!pVM->hwaccm.s.fNestedPaging)
|
---|
679 | {
|
---|
680 | switch(pVCpu->hwaccm.s.enmShadowMode)
|
---|
681 | {
|
---|
682 | case PGMMODE_REAL:
|
---|
683 | case PGMMODE_PROTECTED: /* Protected mode, no paging. */
|
---|
684 | AssertFailed();
|
---|
685 | return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
|
---|
686 |
|
---|
687 | case PGMMODE_32_BIT: /* 32-bit paging. */
|
---|
688 | break;
|
---|
689 |
|
---|
690 | case PGMMODE_PAE: /* PAE paging. */
|
---|
691 | case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
|
---|
692 | /** @todo use normal 32 bits paging */
|
---|
693 | val |= X86_CR4_PAE;
|
---|
694 | break;
|
---|
695 |
|
---|
696 | case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
|
---|
697 | case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
|
---|
698 | #ifdef VBOX_ENABLE_64_BITS_GUESTS
|
---|
699 | break;
|
---|
700 | #else
|
---|
701 | AssertFailed();
|
---|
702 | return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
|
---|
703 | #endif
|
---|
704 |
|
---|
705 | default: /* shut up gcc */
|
---|
706 | AssertFailed();
|
---|
707 | return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
|
---|
708 | }
|
---|
709 | }
|
---|
710 | pVMCB->guest.u64CR4 = val;
|
---|
711 | }
|
---|
712 |
|
---|
713 | /* Debug registers. */
|
---|
714 | if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
|
---|
715 | {
|
---|
716 | pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
|
---|
717 | pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
|
---|
718 |
|
---|
719 | pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
|
---|
720 | pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
|
---|
721 | pCtx->dr[7] |= 0x400; /* must be one */
|
---|
722 |
|
---|
723 | pVMCB->guest.u64DR7 = pCtx->dr[7];
|
---|
724 | pVMCB->guest.u64DR6 = pCtx->dr[6];
|
---|
725 |
|
---|
726 | /* Sync the debug state now if any breakpoint is armed. */
|
---|
727 | if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
|
---|
728 | && !CPUMIsGuestDebugStateActive(pVM)
|
---|
729 | && !DBGFIsStepping(pVM))
|
---|
730 | {
|
---|
731 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
|
---|
732 |
|
---|
733 | /* Disable drx move intercepts. */
|
---|
734 | pVMCB->ctrl.u16InterceptRdDRx = 0;
|
---|
735 | pVMCB->ctrl.u16InterceptWrDRx = 0;
|
---|
736 |
|
---|
737 | /* Save the host and load the guest debug state. */
|
---|
738 | int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
|
---|
739 | AssertRC(rc);
|
---|
740 | }
|
---|
741 | }
|
---|
742 |
|
---|
743 | /* EIP, ESP and EFLAGS */
|
---|
744 | pVMCB->guest.u64RIP = pCtx->rip;
|
---|
745 | pVMCB->guest.u64RSP = pCtx->rsp;
|
---|
746 | pVMCB->guest.u64RFlags = pCtx->eflags.u32;
|
---|
747 |
|
---|
748 | /* Set CPL */
|
---|
749 | pVMCB->guest.u8CPL = pCtx->csHid.Attr.n.u2Dpl;
|
---|
750 |
|
---|
751 | /* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
|
---|
752 | pVMCB->guest.u64RAX = pCtx->rax;
|
---|
753 |
|
---|
754 | /* vmrun will fail without MSR_K6_EFER_SVME. */
|
---|
755 | pVMCB->guest.u64EFER = pCtx->msrEFER | MSR_K6_EFER_SVME;
|
---|
756 |
|
---|
757 | /* 64 bits guest mode? */
|
---|
758 | if (pCtx->msrEFER & MSR_K6_EFER_LMA)
|
---|
759 | {
|
---|
760 | #if !defined(VBOX_WITH_64_BITS_GUESTS)
|
---|
761 | return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
|
---|
762 | #elif HC_ARCH_BITS == 32
|
---|
763 | pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
|
---|
764 | #else
|
---|
765 | pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun64;
|
---|
766 | #endif
|
---|
767 | /* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
|
---|
768 | pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
|
---|
769 | pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
|
---|
770 | }
|
---|
771 | else
|
---|
772 | {
|
---|
773 | /* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
|
---|
774 | pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
|
---|
775 |
|
---|
776 | pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun;
|
---|
777 | }
|
---|
778 |
|
---|
779 | /* TSC offset. */
|
---|
780 | if (TMCpuTickCanUseRealTSC(pVM, &pVMCB->ctrl.u64TSCOffset))
|
---|
781 | {
|
---|
782 | pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
|
---|
783 | pVMCB->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
|
---|
784 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
|
---|
785 | }
|
---|
786 | else
|
---|
787 | {
|
---|
788 | pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
|
---|
789 | pVMCB->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;
|
---|
790 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
|
---|
791 | }
|
---|
792 |
|
---|
793 | /* Sync the various msrs for 64 bits mode. */
|
---|
794 | pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
|
---|
795 | pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
|
---|
796 | pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
|
---|
797 | pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
|
---|
798 | pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
|
---|
799 |
|
---|
800 | #ifdef DEBUG
|
---|
801 | /* Intercept X86_XCPT_DB if stepping is enabled */
|
---|
802 | if (DBGFIsStepping(pVM))
|
---|
803 | pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_DB);
|
---|
804 | else
|
---|
805 | pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_DB);
|
---|
806 | #endif
|
---|
807 |
|
---|
808 | /* Done. */
|
---|
809 | pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
|
---|
810 |
|
---|
811 | return VINF_SUCCESS;
|
---|
812 | }
|
---|
813 |
|
---|
814 |
|
---|
815 | /**
|
---|
816 | * Runs guest code in an AMD-V VM.
|
---|
817 | *
|
---|
818 | * @returns VBox status code.
|
---|
819 | * @param pVM The VM to operate on.
|
---|
820 | * @param pVCpu The VM CPU to operate on.
|
---|
821 | * @param pCtx Guest context
|
---|
822 | */
|
---|
823 | VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
|
---|
824 | {
|
---|
825 | int rc = VINF_SUCCESS;
|
---|
826 | uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
|
---|
827 | SVM_VMCB *pVMCB;
|
---|
828 | bool fSyncTPR = false;
|
---|
829 | unsigned cResume = 0;
|
---|
830 | uint8_t u8LastVTPR;
|
---|
831 | PHWACCM_CPUINFO pCpu = 0;
|
---|
832 | #ifdef VBOX_STRICT
|
---|
833 | RTCPUID idCpuCheck;
|
---|
834 | #endif
|
---|
835 |
|
---|
836 | STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
|
---|
837 |
|
---|
838 | pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
|
---|
839 | AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
|
---|
840 |
|
---|
841 | /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
|
---|
842 | */
|
---|
843 | ResumeExecution:
|
---|
844 | Assert(!HWACCMR0SuspendPending());
|
---|
845 |
|
---|
846 | /* Safety precaution; looping for too long here can have a very bad effect on the host */
|
---|
847 | if (++cResume > HWACCM_MAX_RESUME_LOOPS)
|
---|
848 | {
|
---|
849 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
|
---|
850 | rc = VINF_EM_RAW_INTERRUPT;
|
---|
851 | goto end;
|
---|
852 | }
|
---|
853 |
|
---|
854 | /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
|
---|
855 | if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
|
---|
856 | {
|
---|
857 | Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
|
---|
858 | if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
|
---|
859 | {
|
---|
860 | /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
|
---|
861 | * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
|
---|
862 | * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
|
---|
863 | * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
|
---|
864 | */
|
---|
865 | VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
|
---|
866 | /* Irq inhibition is no longer active; clear the corresponding SVM state. */
|
---|
867 | pVMCB->ctrl.u64IntShadow = 0;
|
---|
868 | }
|
---|
869 | }
|
---|
870 | else
|
---|
871 | {
|
---|
872 | /* Irq inhibition is no longer active; clear the corresponding SVM state. */
|
---|
873 | pVMCB->ctrl.u64IntShadow = 0;
|
---|
874 | }
|
---|
875 |
|
---|
876 | /* Check for pending actions that force us to go back to ring 3. */
|
---|
877 | #ifdef DEBUG
|
---|
878 | /* Intercept X86_XCPT_DB if stepping is enabled */
|
---|
879 | if (!DBGFIsStepping(pVM))
|
---|
880 | #endif
|
---|
881 | {
|
---|
882 | if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 | VM_FF_TIMER))
|
---|
883 | {
|
---|
884 | VM_FF_CLEAR(pVM, VM_FF_TO_R3);
|
---|
885 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
|
---|
886 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
|
---|
887 | rc = VINF_EM_RAW_TO_R3;
|
---|
888 | goto end;
|
---|
889 | }
|
---|
890 | }
|
---|
891 |
|
---|
892 | /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
|
---|
893 | if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
|
---|
894 | {
|
---|
895 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
|
---|
896 | rc = VINF_EM_PENDING_REQUEST;
|
---|
897 | goto end;
|
---|
898 | }
|
---|
899 |
|
---|
900 | /* When external interrupts are pending, we should exit the VM when IF is set. */
|
---|
901 | /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
|
---|
902 | rc = SVMR0CheckPendingInterrupt(pVM, pVCpu, pVMCB, pCtx);
|
---|
903 | if (RT_FAILURE(rc))
|
---|
904 | {
|
---|
905 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
|
---|
906 | goto end;
|
---|
907 | }
|
---|
908 |
|
---|
909 | /* TPR caching using CR8 is only available in 64 bits mode */
|
---|
910 | /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
|
---|
911 | /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! */
|
---|
912 | if (pCtx->msrEFER & MSR_K6_EFER_LMA)
|
---|
913 | {
|
---|
914 | bool fPending;
|
---|
915 |
|
---|
916 | /* TPR caching in CR8 */
|
---|
917 | int rc = PDMApicGetTPR(pVM, &u8LastVTPR, &fPending);
|
---|
918 | AssertRC(rc);
|
---|
919 | pVMCB->ctrl.IntCtrl.n.u8VTPR = u8LastVTPR;
|
---|
920 |
|
---|
921 | if (fPending)
|
---|
922 | {
|
---|
923 | /* A TPR change could activate a pending interrupt, so catch cr8 writes. */
|
---|
924 | pVMCB->ctrl.u16InterceptWrCRx |= RT_BIT(8);
|
---|
925 | }
|
---|
926 | else
|
---|
927 | /* No interrupts are pending, so we don't need to be explicitely notified.
|
---|
928 | * There are enough world switches for detecting pending interrupts.
|
---|
929 | */
|
---|
930 | pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
|
---|
931 |
|
---|
932 | fSyncTPR = !fPending;
|
---|
933 | }
|
---|
934 |
|
---|
935 | /* All done! Let's start VM execution. */
|
---|
936 | STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, x);
|
---|
937 |
|
---|
938 | /* Enable nested paging if necessary (disabled each time after #VMEXIT). */
|
---|
939 | pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
|
---|
940 |
|
---|
941 | #ifdef LOG_ENABLED
|
---|
942 | pCpu = HWACCMR0GetCurrentCpu();
|
---|
943 | if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
|
---|
944 | || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
|
---|
945 | {
|
---|
946 | if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
|
---|
947 | Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
|
---|
948 | else
|
---|
949 | Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
|
---|
950 | }
|
---|
951 | if (pCpu->fFlushTLB)
|
---|
952 | Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
|
---|
953 | #endif
|
---|
954 |
|
---|
955 | /*
|
---|
956 | * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
|
---|
957 | * (until the actual world switch)
|
---|
958 | */
|
---|
959 |
|
---|
960 | #ifdef VBOX_STRICT
|
---|
961 | idCpuCheck = RTMpCpuId();
|
---|
962 | #endif
|
---|
963 |
|
---|
964 | /* Load the guest state; *must* be here as it sets up the shadow cr0 for lazy fpu syncing! */
|
---|
965 | rc = SVMR0LoadGuestState(pVM, pVCpu, pCtx);
|
---|
966 | if (rc != VINF_SUCCESS)
|
---|
967 | {
|
---|
968 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
|
---|
969 | goto end;
|
---|
970 | }
|
---|
971 |
|
---|
972 | pCpu = HWACCMR0GetCurrentCpu();
|
---|
973 | /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
|
---|
974 | /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
|
---|
975 | if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
|
---|
976 | /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
|
---|
977 | || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
|
---|
978 | {
|
---|
979 | /* Force a TLB flush on VM entry. */
|
---|
980 | pVCpu->hwaccm.s.fForceTLBFlush = true;
|
---|
981 | }
|
---|
982 | else
|
---|
983 | Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
|
---|
984 |
|
---|
985 | pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
|
---|
986 |
|
---|
987 | /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
|
---|
988 | if ( pVCpu->hwaccm.s.fForceTLBFlush
|
---|
989 | && !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
|
---|
990 | {
|
---|
991 | if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
|
---|
992 | || pCpu->fFlushTLB)
|
---|
993 | {
|
---|
994 | pCpu->fFlushTLB = false;
|
---|
995 | pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
|
---|
996 | pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
|
---|
997 | pCpu->cTLBFlushes++;
|
---|
998 | }
|
---|
999 | else
|
---|
1000 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
|
---|
1001 |
|
---|
1002 | pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
|
---|
1003 | pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
|
---|
1004 | }
|
---|
1005 | else
|
---|
1006 | {
|
---|
1007 | Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
|
---|
1008 |
|
---|
1009 | /* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
|
---|
1010 | if (!pCpu->uCurrentASID || !pVCpu->hwaccm.s.uCurrentASID)
|
---|
1011 | pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
|
---|
1012 |
|
---|
1013 | Assert(!pVM->hwaccm.s.svm.fAlwaysFlushTLB || pVCpu->hwaccm.s.fForceTLBFlush);
|
---|
1014 | pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVCpu->hwaccm.s.fForceTLBFlush;
|
---|
1015 | }
|
---|
1016 | AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
|
---|
1017 | AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
|
---|
1018 | AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
|
---|
1019 | pVMCB->ctrl.TLBCtrl.n.u32ASID = pVCpu->hwaccm.s.uCurrentASID;
|
---|
1020 |
|
---|
1021 | #ifdef VBOX_WITH_STATISTICS
|
---|
1022 | if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
|
---|
1023 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
|
---|
1024 | else
|
---|
1025 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
|
---|
1026 | #endif
|
---|
1027 |
|
---|
1028 | /* In case we execute a goto ResumeExecution later on. */
|
---|
1029 | pVCpu->hwaccm.s.fResumeVM = true;
|
---|
1030 | pVCpu->hwaccm.s.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
|
---|
1031 |
|
---|
1032 | Assert(sizeof(pVCpu->hwaccm.s.svm.pVMCBPhys) == 8);
|
---|
1033 | Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
|
---|
1034 | Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
|
---|
1035 | Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
|
---|
1036 | Assert(pVMCB->ctrl.u64LBRVirt == 0);
|
---|
1037 |
|
---|
1038 | #ifdef VBOX_STRICT
|
---|
1039 | Assert(idCpuCheck == RTMpCpuId());
|
---|
1040 | #endif
|
---|
1041 | TMNotifyStartOfExecution(pVM);
|
---|
1042 | pVCpu->hwaccm.s.svm.pfnVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu);
|
---|
1043 | TMNotifyEndOfExecution(pVM);
|
---|
1044 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, x);
|
---|
1045 |
|
---|
1046 | /*
|
---|
1047 | * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
|
---|
1048 | * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
|
---|
1049 | * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
|
---|
1050 | */
|
---|
1051 |
|
---|
1052 | STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit, x);
|
---|
1053 |
|
---|
1054 | /* Reason for the VM exit */
|
---|
1055 | exitCode = pVMCB->ctrl.u64ExitCode;
|
---|
1056 |
|
---|
1057 | if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
|
---|
1058 | {
|
---|
1059 | HWACCMDumpRegs(pVM, pCtx);
|
---|
1060 | #ifdef DEBUG
|
---|
1061 | Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
|
---|
1062 | Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
|
---|
1063 | Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
|
---|
1064 | Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
|
---|
1065 | Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
|
---|
1066 | Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
|
---|
1067 | Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
|
---|
1068 | Log(("ctrl.u64IOPMPhysAddr %RX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
|
---|
1069 | Log(("ctrl.u64MSRPMPhysAddr %RX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
|
---|
1070 | Log(("ctrl.u64TSCOffset %RX64\n", pVMCB->ctrl.u64TSCOffset));
|
---|
1071 |
|
---|
1072 | Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
|
---|
1073 | Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
|
---|
1074 | Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
|
---|
1075 | Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
|
---|
1076 |
|
---|
1077 | Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
|
---|
1078 | Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
|
---|
1079 | Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
|
---|
1080 | Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
|
---|
1081 | Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
|
---|
1082 | Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
|
---|
1083 | Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
|
---|
1084 | Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
|
---|
1085 | Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
|
---|
1086 | Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
|
---|
1087 |
|
---|
1088 | Log(("ctrl.u64IntShadow %RX64\n", pVMCB->ctrl.u64IntShadow));
|
---|
1089 | Log(("ctrl.u64ExitCode %RX64\n", pVMCB->ctrl.u64ExitCode));
|
---|
1090 | Log(("ctrl.u64ExitInfo1 %RX64\n", pVMCB->ctrl.u64ExitInfo1));
|
---|
1091 | Log(("ctrl.u64ExitInfo2 %RX64\n", pVMCB->ctrl.u64ExitInfo2));
|
---|
1092 | Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
|
---|
1093 | Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
|
---|
1094 | Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
|
---|
1095 | Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
|
---|
1096 | Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
|
---|
1097 | Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
|
---|
1098 | Log(("ctrl.NestedPaging %RX64\n", pVMCB->ctrl.NestedPaging.au64));
|
---|
1099 | Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
|
---|
1100 | Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
|
---|
1101 | Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
|
---|
1102 | Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
|
---|
1103 | Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
|
---|
1104 | Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
|
---|
1105 |
|
---|
1106 | Log(("ctrl.u64NestedPagingCR3 %RX64\n", pVMCB->ctrl.u64NestedPagingCR3));
|
---|
1107 | Log(("ctrl.u64LBRVirt %RX64\n", pVMCB->ctrl.u64LBRVirt));
|
---|
1108 |
|
---|
1109 | Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
|
---|
1110 | Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
|
---|
1111 | Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
|
---|
1112 | Log(("guest.CS.u64Base %RX64\n", pVMCB->guest.CS.u64Base));
|
---|
1113 | Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
|
---|
1114 | Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
|
---|
1115 | Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
|
---|
1116 | Log(("guest.DS.u64Base %RX64\n", pVMCB->guest.DS.u64Base));
|
---|
1117 | Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
|
---|
1118 | Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
|
---|
1119 | Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
|
---|
1120 | Log(("guest.ES.u64Base %RX64\n", pVMCB->guest.ES.u64Base));
|
---|
1121 | Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
|
---|
1122 | Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
|
---|
1123 | Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
|
---|
1124 | Log(("guest.FS.u64Base %RX64\n", pVMCB->guest.FS.u64Base));
|
---|
1125 | Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
|
---|
1126 | Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
|
---|
1127 | Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
|
---|
1128 | Log(("guest.GS.u64Base %RX64\n", pVMCB->guest.GS.u64Base));
|
---|
1129 |
|
---|
1130 | Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
|
---|
1131 | Log(("guest.GDTR.u64Base %RX64\n", pVMCB->guest.GDTR.u64Base));
|
---|
1132 |
|
---|
1133 | Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
|
---|
1134 | Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
|
---|
1135 | Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
|
---|
1136 | Log(("guest.LDTR.u64Base %RX64\n", pVMCB->guest.LDTR.u64Base));
|
---|
1137 |
|
---|
1138 | Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
|
---|
1139 | Log(("guest.IDTR.u64Base %RX64\n", pVMCB->guest.IDTR.u64Base));
|
---|
1140 |
|
---|
1141 | Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
|
---|
1142 | Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
|
---|
1143 | Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
|
---|
1144 | Log(("guest.TR.u64Base %RX64\n", pVMCB->guest.TR.u64Base));
|
---|
1145 |
|
---|
1146 | Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
|
---|
1147 | Log(("guest.u64CR0 %RX64\n", pVMCB->guest.u64CR0));
|
---|
1148 | Log(("guest.u64CR2 %RX64\n", pVMCB->guest.u64CR2));
|
---|
1149 | Log(("guest.u64CR3 %RX64\n", pVMCB->guest.u64CR3));
|
---|
1150 | Log(("guest.u64CR4 %RX64\n", pVMCB->guest.u64CR4));
|
---|
1151 | Log(("guest.u64DR6 %RX64\n", pVMCB->guest.u64DR6));
|
---|
1152 | Log(("guest.u64DR7 %RX64\n", pVMCB->guest.u64DR7));
|
---|
1153 |
|
---|
1154 | Log(("guest.u64RIP %RX64\n", pVMCB->guest.u64RIP));
|
---|
1155 | Log(("guest.u64RSP %RX64\n", pVMCB->guest.u64RSP));
|
---|
1156 | Log(("guest.u64RAX %RX64\n", pVMCB->guest.u64RAX));
|
---|
1157 | Log(("guest.u64RFlags %RX64\n", pVMCB->guest.u64RFlags));
|
---|
1158 |
|
---|
1159 | Log(("guest.u64SysEnterCS %RX64\n", pVMCB->guest.u64SysEnterCS));
|
---|
1160 | Log(("guest.u64SysEnterEIP %RX64\n", pVMCB->guest.u64SysEnterEIP));
|
---|
1161 | Log(("guest.u64SysEnterESP %RX64\n", pVMCB->guest.u64SysEnterESP));
|
---|
1162 |
|
---|
1163 | Log(("guest.u64EFER %RX64\n", pVMCB->guest.u64EFER));
|
---|
1164 | Log(("guest.u64STAR %RX64\n", pVMCB->guest.u64STAR));
|
---|
1165 | Log(("guest.u64LSTAR %RX64\n", pVMCB->guest.u64LSTAR));
|
---|
1166 | Log(("guest.u64CSTAR %RX64\n", pVMCB->guest.u64CSTAR));
|
---|
1167 | Log(("guest.u64SFMASK %RX64\n", pVMCB->guest.u64SFMASK));
|
---|
1168 | Log(("guest.u64KernelGSBase %RX64\n", pVMCB->guest.u64KernelGSBase));
|
---|
1169 | Log(("guest.u64GPAT %RX64\n", pVMCB->guest.u64GPAT));
|
---|
1170 | Log(("guest.u64DBGCTL %RX64\n", pVMCB->guest.u64DBGCTL));
|
---|
1171 | Log(("guest.u64BR_FROM %RX64\n", pVMCB->guest.u64BR_FROM));
|
---|
1172 | Log(("guest.u64BR_TO %RX64\n", pVMCB->guest.u64BR_TO));
|
---|
1173 | Log(("guest.u64LASTEXCPFROM %RX64\n", pVMCB->guest.u64LASTEXCPFROM));
|
---|
1174 | Log(("guest.u64LASTEXCPTO %RX64\n", pVMCB->guest.u64LASTEXCPTO));
|
---|
1175 |
|
---|
1176 | #endif
|
---|
1177 | rc = VERR_SVM_UNABLE_TO_START_VM;
|
---|
1178 | goto end;
|
---|
1179 | }
|
---|
1180 |
|
---|
1181 | /* Let's first sync back eip, esp, and eflags. */
|
---|
1182 | pCtx->rip = pVMCB->guest.u64RIP;
|
---|
1183 | pCtx->rsp = pVMCB->guest.u64RSP;
|
---|
1184 | pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
|
---|
1185 | /* eax is saved/restore across the vmrun instruction */
|
---|
1186 | pCtx->rax = pVMCB->guest.u64RAX;
|
---|
1187 |
|
---|
1188 | pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
|
---|
1189 |
|
---|
1190 | /* Can be updated behind our back in the nested paging case. */
|
---|
1191 | pCtx->cr2 = pVMCB->guest.u64CR2;
|
---|
1192 |
|
---|
1193 | /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
|
---|
1194 | SVM_READ_SELREG(SS, ss);
|
---|
1195 | SVM_READ_SELREG(CS, cs);
|
---|
1196 | SVM_READ_SELREG(DS, ds);
|
---|
1197 | SVM_READ_SELREG(ES, es);
|
---|
1198 | SVM_READ_SELREG(FS, fs);
|
---|
1199 | SVM_READ_SELREG(GS, gs);
|
---|
1200 |
|
---|
1201 | /*
|
---|
1202 | * System MSRs
|
---|
1203 | */
|
---|
1204 | pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
|
---|
1205 | pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
|
---|
1206 | pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
|
---|
1207 |
|
---|
1208 | /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR; must sync everything otherwise we can get out of sync when jumping to ring 3. */
|
---|
1209 | SVM_READ_SELREG(LDTR, ldtr);
|
---|
1210 | SVM_READ_SELREG(TR, tr);
|
---|
1211 |
|
---|
1212 | pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
|
---|
1213 | pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
|
---|
1214 |
|
---|
1215 | pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
|
---|
1216 | pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
|
---|
1217 |
|
---|
1218 | /* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
|
---|
1219 | /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
|
---|
1220 | if ( pVM->hwaccm.s.fNestedPaging
|
---|
1221 | && pCtx->cr3 != pVMCB->guest.u64CR3)
|
---|
1222 | {
|
---|
1223 | CPUMSetGuestCR3(pVM, pVMCB->guest.u64CR3);
|
---|
1224 | PGMUpdateCR3(pVM, pVMCB->guest.u64CR3);
|
---|
1225 | }
|
---|
1226 |
|
---|
1227 | /* Note! NOW IT'S SAFE FOR LOGGING! */
|
---|
1228 |
|
---|
1229 | /* Take care of instruction fusing (sti, mov ss) (see 15.20.5 Interrupt Shadows) */
|
---|
1230 | if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
|
---|
1231 | {
|
---|
1232 | Log(("uInterruptState %x rip=%RGv\n", pVMCB->ctrl.u64IntShadow, (RTGCPTR)pCtx->rip));
|
---|
1233 | EMSetInhibitInterruptsPC(pVM, pCtx->rip);
|
---|
1234 | }
|
---|
1235 | else
|
---|
1236 | VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
|
---|
1237 |
|
---|
1238 | Log2(("exitCode = %x\n", exitCode));
|
---|
1239 |
|
---|
1240 | /* Sync back DR6 as it could have been changed by hitting breakpoints. */
|
---|
1241 | pCtx->dr[6] = pVMCB->guest.u64DR6;
|
---|
1242 | /* DR7.GD can be cleared by debug exceptions, so sync it back as well. */
|
---|
1243 | pCtx->dr[7] = pVMCB->guest.u64DR7;
|
---|
1244 |
|
---|
1245 | /* Check if an injected event was interrupted prematurely. */
|
---|
1246 | pVCpu->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
|
---|
1247 | if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
|
---|
1248 | && pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
|
---|
1249 | {
|
---|
1250 | Log(("Pending inject %RX64 at %RGv exit=%08x\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitCode));
|
---|
1251 |
|
---|
1252 | #ifdef LOG_ENABLED
|
---|
1253 | SVM_EVENT Event;
|
---|
1254 | Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
|
---|
1255 |
|
---|
1256 | if ( exitCode == SVM_EXIT_EXCEPTION_E
|
---|
1257 | && Event.n.u8Vector == 0xE)
|
---|
1258 | {
|
---|
1259 | Log(("Double fault!\n"));
|
---|
1260 | }
|
---|
1261 | #endif
|
---|
1262 |
|
---|
1263 | pVCpu->hwaccm.s.Event.fPending = true;
|
---|
1264 | /* Error code present? (redundant) */
|
---|
1265 | if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
|
---|
1266 | {
|
---|
1267 | pVCpu->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
|
---|
1268 | }
|
---|
1269 | else
|
---|
1270 | pVCpu->hwaccm.s.Event.errCode = 0;
|
---|
1271 | }
|
---|
1272 | #ifdef VBOX_WITH_STATISTICS
|
---|
1273 | if (exitCode == SVM_EXIT_NPF)
|
---|
1274 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
|
---|
1275 | else
|
---|
1276 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
|
---|
1277 | #endif
|
---|
1278 |
|
---|
1279 | if (fSyncTPR)
|
---|
1280 | {
|
---|
1281 | rc = PDMApicSetTPR(pVM, pVMCB->ctrl.IntCtrl.n.u8VTPR);
|
---|
1282 | AssertRC(rc);
|
---|
1283 | }
|
---|
1284 |
|
---|
1285 | /* Deal with the reason of the VM-exit. */
|
---|
1286 | switch (exitCode)
|
---|
1287 | {
|
---|
1288 | case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
|
---|
1289 | case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
|
---|
1290 | case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
|
---|
1291 | case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
|
---|
1292 | case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
|
---|
1293 | case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
|
---|
1294 | case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
|
---|
1295 | case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
|
---|
1296 | {
|
---|
1297 | /* Pending trap. */
|
---|
1298 | SVM_EVENT Event;
|
---|
1299 | uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
|
---|
1300 |
|
---|
1301 | Log2(("Hardware/software interrupt %d\n", vector));
|
---|
1302 | switch (vector)
|
---|
1303 | {
|
---|
1304 | case X86_XCPT_DB:
|
---|
1305 | {
|
---|
1306 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
|
---|
1307 |
|
---|
1308 | /* Note that we don't support guest and host-initiated debugging at the same time. */
|
---|
1309 | Assert(DBGFIsStepping(pVM));
|
---|
1310 |
|
---|
1311 | rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
|
---|
1312 | if (rc == VINF_EM_RAW_GUEST_TRAP)
|
---|
1313 | {
|
---|
1314 | Log(("Trap %x (debug) at %016RX64\n", vector, pCtx->rip));
|
---|
1315 |
|
---|
1316 | /* Reinject the exception. */
|
---|
1317 | Event.au64[0] = 0;
|
---|
1318 | Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
|
---|
1319 | Event.n.u1Valid = 1;
|
---|
1320 | Event.n.u8Vector = X86_XCPT_DB;
|
---|
1321 |
|
---|
1322 | SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
|
---|
1323 |
|
---|
1324 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
|
---|
1325 | goto ResumeExecution;
|
---|
1326 | }
|
---|
1327 | /* Return to ring 3 to deal with the debug exit code. */
|
---|
1328 | break;
|
---|
1329 | }
|
---|
1330 |
|
---|
1331 | case X86_XCPT_NM:
|
---|
1332 | {
|
---|
1333 | Log(("#NM fault at %RGv\n", (RTGCPTR)pCtx->rip));
|
---|
1334 |
|
---|
1335 | /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
|
---|
1336 | /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
|
---|
1337 | rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
|
---|
1338 | if (rc == VINF_SUCCESS)
|
---|
1339 | {
|
---|
1340 | Assert(CPUMIsGuestFPUStateActive(pVCpu));
|
---|
1341 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
|
---|
1342 |
|
---|
1343 | /* Continue execution. */
|
---|
1344 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
|
---|
1345 | pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
|
---|
1346 |
|
---|
1347 | goto ResumeExecution;
|
---|
1348 | }
|
---|
1349 |
|
---|
1350 | Log(("Forward #NM fault to the guest\n"));
|
---|
1351 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
|
---|
1352 |
|
---|
1353 | Event.au64[0] = 0;
|
---|
1354 | Event.n.u3Type = SVM_EVENT_EXCEPTION;
|
---|
1355 | Event.n.u1Valid = 1;
|
---|
1356 | Event.n.u8Vector = X86_XCPT_NM;
|
---|
1357 |
|
---|
1358 | SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
|
---|
1359 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
|
---|
1360 | goto ResumeExecution;
|
---|
1361 | }
|
---|
1362 |
|
---|
1363 | case X86_XCPT_PF: /* Page fault */
|
---|
1364 | {
|
---|
1365 | uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
|
---|
1366 | RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
|
---|
1367 |
|
---|
1368 | #ifdef DEBUG
|
---|
1369 | if (pVM->hwaccm.s.fNestedPaging)
|
---|
1370 | { /* A genuine pagefault.
|
---|
1371 | * Forward the trap to the guest by injecting the exception and resuming execution.
|
---|
1372 | */
|
---|
1373 | Log(("Guest page fault at %RGv cr2=%RGv error code %x rsp=%RGv\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
|
---|
1374 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
|
---|
1375 |
|
---|
1376 | /* Now we must update CR2. */
|
---|
1377 | pCtx->cr2 = uFaultAddress;
|
---|
1378 |
|
---|
1379 | Event.au64[0] = 0;
|
---|
1380 | Event.n.u3Type = SVM_EVENT_EXCEPTION;
|
---|
1381 | Event.n.u1Valid = 1;
|
---|
1382 | Event.n.u8Vector = X86_XCPT_PF;
|
---|
1383 | Event.n.u1ErrorCodeValid = 1;
|
---|
1384 | Event.n.u32ErrorCode = errCode;
|
---|
1385 |
|
---|
1386 | SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
|
---|
1387 |
|
---|
1388 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
|
---|
1389 | goto ResumeExecution;
|
---|
1390 | }
|
---|
1391 | #endif
|
---|
1392 | Assert(!pVM->hwaccm.s.fNestedPaging);
|
---|
1393 |
|
---|
1394 | Log2(("Page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
|
---|
1395 | /* Exit qualification contains the linear address of the page fault. */
|
---|
1396 | TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
|
---|
1397 | TRPMSetErrorCode(pVM, errCode);
|
---|
1398 | TRPMSetFaultAddress(pVM, uFaultAddress);
|
---|
1399 |
|
---|
1400 | /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
|
---|
1401 | rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
|
---|
1402 | Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
|
---|
1403 | if (rc == VINF_SUCCESS)
|
---|
1404 | { /* We've successfully synced our shadow pages, so let's just continue execution. */
|
---|
1405 | Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
|
---|
1406 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
|
---|
1407 |
|
---|
1408 | TRPMResetTrap(pVM);
|
---|
1409 |
|
---|
1410 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
|
---|
1411 | goto ResumeExecution;
|
---|
1412 | }
|
---|
1413 | else
|
---|
1414 | if (rc == VINF_EM_RAW_GUEST_TRAP)
|
---|
1415 | { /* A genuine pagefault.
|
---|
1416 | * Forward the trap to the guest by injecting the exception and resuming execution.
|
---|
1417 | */
|
---|
1418 | Log2(("Forward page fault to the guest\n"));
|
---|
1419 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
|
---|
1420 | /* The error code might have been changed. */
|
---|
1421 | errCode = TRPMGetErrorCode(pVM);
|
---|
1422 |
|
---|
1423 | TRPMResetTrap(pVM);
|
---|
1424 |
|
---|
1425 | /* Now we must update CR2. */
|
---|
1426 | pCtx->cr2 = uFaultAddress;
|
---|
1427 |
|
---|
1428 | Event.au64[0] = 0;
|
---|
1429 | Event.n.u3Type = SVM_EVENT_EXCEPTION;
|
---|
1430 | Event.n.u1Valid = 1;
|
---|
1431 | Event.n.u8Vector = X86_XCPT_PF;
|
---|
1432 | Event.n.u1ErrorCodeValid = 1;
|
---|
1433 | Event.n.u32ErrorCode = errCode;
|
---|
1434 |
|
---|
1435 | SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
|
---|
1436 |
|
---|
1437 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
|
---|
1438 | goto ResumeExecution;
|
---|
1439 | }
|
---|
1440 | #ifdef VBOX_STRICT
|
---|
1441 | if (rc != VINF_EM_RAW_EMULATE_INSTR)
|
---|
1442 | LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
|
---|
1443 | #endif
|
---|
1444 | /* Need to go back to the recompiler to emulate the instruction. */
|
---|
1445 | TRPMResetTrap(pVM);
|
---|
1446 | break;
|
---|
1447 | }
|
---|
1448 |
|
---|
1449 | case X86_XCPT_MF: /* Floating point exception. */
|
---|
1450 | {
|
---|
1451 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
|
---|
1452 | if (!(pCtx->cr0 & X86_CR0_NE))
|
---|
1453 | {
|
---|
1454 | /* old style FPU error reporting needs some extra work. */
|
---|
1455 | /** @todo don't fall back to the recompiler, but do it manually. */
|
---|
1456 | rc = VINF_EM_RAW_EMULATE_INSTR;
|
---|
1457 | break;
|
---|
1458 | }
|
---|
1459 | Log(("Trap %x at %RGv\n", vector, (RTGCPTR)pCtx->rip));
|
---|
1460 |
|
---|
1461 | Event.au64[0] = 0;
|
---|
1462 | Event.n.u3Type = SVM_EVENT_EXCEPTION;
|
---|
1463 | Event.n.u1Valid = 1;
|
---|
1464 | Event.n.u8Vector = X86_XCPT_MF;
|
---|
1465 |
|
---|
1466 | SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
|
---|
1467 |
|
---|
1468 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
|
---|
1469 | goto ResumeExecution;
|
---|
1470 | }
|
---|
1471 |
|
---|
1472 | #ifdef VBOX_STRICT
|
---|
1473 | case X86_XCPT_GP: /* General protection failure exception.*/
|
---|
1474 | case X86_XCPT_UD: /* Unknown opcode exception. */
|
---|
1475 | case X86_XCPT_DE: /* Divide error. */
|
---|
1476 | case X86_XCPT_SS: /* Stack segment exception. */
|
---|
1477 | case X86_XCPT_NP: /* Segment not present exception. */
|
---|
1478 | {
|
---|
1479 | Event.au64[0] = 0;
|
---|
1480 | Event.n.u3Type = SVM_EVENT_EXCEPTION;
|
---|
1481 | Event.n.u1Valid = 1;
|
---|
1482 | Event.n.u8Vector = vector;
|
---|
1483 |
|
---|
1484 | switch(vector)
|
---|
1485 | {
|
---|
1486 | case X86_XCPT_GP:
|
---|
1487 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
|
---|
1488 | Event.n.u1ErrorCodeValid = 1;
|
---|
1489 | Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
|
---|
1490 | break;
|
---|
1491 | case X86_XCPT_DE:
|
---|
1492 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
|
---|
1493 | break;
|
---|
1494 | case X86_XCPT_UD:
|
---|
1495 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
|
---|
1496 | break;
|
---|
1497 | case X86_XCPT_SS:
|
---|
1498 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
|
---|
1499 | Event.n.u1ErrorCodeValid = 1;
|
---|
1500 | Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
|
---|
1501 | break;
|
---|
1502 | case X86_XCPT_NP:
|
---|
1503 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
|
---|
1504 | Event.n.u1ErrorCodeValid = 1;
|
---|
1505 | Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
|
---|
1506 | break;
|
---|
1507 | }
|
---|
1508 | Log(("Trap %x at %RGv esi=%x\n", vector, (RTGCPTR)pCtx->rip, pCtx->esi));
|
---|
1509 | SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
|
---|
1510 |
|
---|
1511 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
|
---|
1512 | goto ResumeExecution;
|
---|
1513 | }
|
---|
1514 | #endif
|
---|
1515 | default:
|
---|
1516 | AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
|
---|
1517 | rc = VERR_EM_INTERNAL_ERROR;
|
---|
1518 | break;
|
---|
1519 |
|
---|
1520 | } /* switch (vector) */
|
---|
1521 | break;
|
---|
1522 | }
|
---|
1523 |
|
---|
1524 | case SVM_EXIT_NPF:
|
---|
1525 | {
|
---|
1526 | /* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
|
---|
1527 | uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
|
---|
1528 | RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
|
---|
1529 |
|
---|
1530 | Assert(pVM->hwaccm.s.fNestedPaging);
|
---|
1531 | Log(("Nested page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
|
---|
1532 | /* Exit qualification contains the linear address of the page fault. */
|
---|
1533 | TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
|
---|
1534 | TRPMSetErrorCode(pVM, errCode);
|
---|
1535 | TRPMSetFaultAddress(pVM, uFaultAddress);
|
---|
1536 |
|
---|
1537 | /* Handle the pagefault trap for the nested shadow table. */
|
---|
1538 | rc = PGMR0Trap0eHandlerNestedPaging(pVM, PGMGetHostMode(pVM), errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
|
---|
1539 | Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
|
---|
1540 | if (rc == VINF_SUCCESS)
|
---|
1541 | { /* We've successfully synced our shadow pages, so let's just continue execution. */
|
---|
1542 | Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
|
---|
1543 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
|
---|
1544 |
|
---|
1545 | TRPMResetTrap(pVM);
|
---|
1546 |
|
---|
1547 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
|
---|
1548 | goto ResumeExecution;
|
---|
1549 | }
|
---|
1550 |
|
---|
1551 | #ifdef VBOX_STRICT
|
---|
1552 | if (rc != VINF_EM_RAW_EMULATE_INSTR)
|
---|
1553 | LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
|
---|
1554 | #endif
|
---|
1555 | /* Need to go back to the recompiler to emulate the instruction. */
|
---|
1556 | TRPMResetTrap(pVM);
|
---|
1557 | break;
|
---|
1558 | }
|
---|
1559 |
|
---|
1560 | case SVM_EXIT_VINTR:
|
---|
1561 | /* A virtual interrupt is about to be delivered, which means IF=1. */
|
---|
1562 | Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
|
---|
1563 | pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
|
---|
1564 | pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
|
---|
1565 | goto ResumeExecution;
|
---|
1566 |
|
---|
1567 | case SVM_EXIT_FERR_FREEZE:
|
---|
1568 | case SVM_EXIT_INTR:
|
---|
1569 | case SVM_EXIT_NMI:
|
---|
1570 | case SVM_EXIT_SMI:
|
---|
1571 | case SVM_EXIT_INIT:
|
---|
1572 | /* External interrupt; leave to allow it to be dispatched again. */
|
---|
1573 | rc = VINF_EM_RAW_INTERRUPT;
|
---|
1574 | break;
|
---|
1575 |
|
---|
1576 | case SVM_EXIT_WBINVD:
|
---|
1577 | case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
|
---|
1578 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
|
---|
1579 | /* Skip instruction and continue directly. */
|
---|
1580 | pCtx->rip += 2; /* Note! hardcoded opcode size! */
|
---|
1581 | /* Continue execution.*/
|
---|
1582 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
|
---|
1583 | goto ResumeExecution;
|
---|
1584 |
|
---|
1585 | case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
|
---|
1586 | {
|
---|
1587 | Log2(("SVM: Cpuid at %RGv for %x\n", (RTGCPTR)pCtx->rip, pCtx->eax));
|
---|
1588 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
|
---|
1589 | rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
|
---|
1590 | if (rc == VINF_SUCCESS)
|
---|
1591 | {
|
---|
1592 | /* Update EIP and continue execution. */
|
---|
1593 | pCtx->rip += 2; /* Note! hardcoded opcode size! */
|
---|
1594 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
|
---|
1595 | goto ResumeExecution;
|
---|
1596 | }
|
---|
1597 | AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
|
---|
1598 | rc = VINF_EM_RAW_EMULATE_INSTR;
|
---|
1599 | break;
|
---|
1600 | }
|
---|
1601 |
|
---|
1602 | case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
|
---|
1603 | {
|
---|
1604 | Log2(("SVM: Rdtsc\n"));
|
---|
1605 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
|
---|
1606 | rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
|
---|
1607 | if (rc == VINF_SUCCESS)
|
---|
1608 | {
|
---|
1609 | /* Update EIP and continue execution. */
|
---|
1610 | pCtx->rip += 2; /* Note! hardcoded opcode size! */
|
---|
1611 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
|
---|
1612 | goto ResumeExecution;
|
---|
1613 | }
|
---|
1614 | AssertMsgFailed(("EMU: rdtsc failed with %Rrc\n", rc));
|
---|
1615 | rc = VINF_EM_RAW_EMULATE_INSTR;
|
---|
1616 | break;
|
---|
1617 | }
|
---|
1618 |
|
---|
1619 | case SVM_EXIT_RDTSCP: /* Guest software attempted to execute RDTSCP. */
|
---|
1620 | {
|
---|
1621 | Log2(("SVM: Rdtscp\n"));
|
---|
1622 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
|
---|
1623 | rc = EMInterpretRdtscp(pVM, pCtx);
|
---|
1624 | if (rc == VINF_SUCCESS)
|
---|
1625 | {
|
---|
1626 | /* Update EIP and continue execution. */
|
---|
1627 | pCtx->rip += 3; /* Note! hardcoded opcode size! */
|
---|
1628 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
|
---|
1629 | goto ResumeExecution;
|
---|
1630 | }
|
---|
1631 | AssertMsgFailed(("EMU: rdtscp failed with %Rrc\n", rc));
|
---|
1632 | rc = VINF_EM_RAW_EMULATE_INSTR;
|
---|
1633 | break;
|
---|
1634 | }
|
---|
1635 |
|
---|
1636 | case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
|
---|
1637 | {
|
---|
1638 | Log2(("SVM: invlpg\n"));
|
---|
1639 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
|
---|
1640 |
|
---|
1641 | Assert(!pVM->hwaccm.s.fNestedPaging);
|
---|
1642 |
|
---|
1643 | /* Truly a pita. Why can't SVM give the same information as VT-x? */
|
---|
1644 | rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
|
---|
1645 | if (rc == VINF_SUCCESS)
|
---|
1646 | {
|
---|
1647 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushPageInvlpg);
|
---|
1648 | goto ResumeExecution; /* eip already updated */
|
---|
1649 | }
|
---|
1650 | break;
|
---|
1651 | }
|
---|
1652 |
|
---|
1653 | case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
|
---|
1654 | case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
|
---|
1655 | case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
|
---|
1656 | case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
|
---|
1657 | {
|
---|
1658 | uint32_t cbSize;
|
---|
1659 |
|
---|
1660 | Log2(("SVM: %RGv mov cr%d, \n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
|
---|
1661 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite);
|
---|
1662 | rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
|
---|
1663 |
|
---|
1664 | switch (exitCode - SVM_EXIT_WRITE_CR0)
|
---|
1665 | {
|
---|
1666 | case 0:
|
---|
1667 | pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
|
---|
1668 | break;
|
---|
1669 | case 2:
|
---|
1670 | break;
|
---|
1671 | case 3:
|
---|
1672 | Assert(!pVM->hwaccm.s.fNestedPaging);
|
---|
1673 | pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
|
---|
1674 | break;
|
---|
1675 | case 4:
|
---|
1676 | pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
|
---|
1677 | break;
|
---|
1678 | case 8:
|
---|
1679 | break;
|
---|
1680 | default:
|
---|
1681 | AssertFailed();
|
---|
1682 | }
|
---|
1683 | /* Check if a sync operation is pending. */
|
---|
1684 | if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
|
---|
1685 | && VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
|
---|
1686 | {
|
---|
1687 | rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
|
---|
1688 | AssertRC(rc);
|
---|
1689 |
|
---|
1690 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBCRxChange);
|
---|
1691 |
|
---|
1692 | /* Must be set by PGMSyncCR3 */
|
---|
1693 | Assert(PGMGetGuestMode(pVM) <= PGMMODE_PROTECTED || pVCpu->hwaccm.s.fForceTLBFlush);
|
---|
1694 | }
|
---|
1695 | if (rc == VINF_SUCCESS)
|
---|
1696 | {
|
---|
1697 | /* EIP has been updated already. */
|
---|
1698 |
|
---|
1699 | /* Only resume if successful. */
|
---|
1700 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
|
---|
1701 | goto ResumeExecution;
|
---|
1702 | }
|
---|
1703 | Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
|
---|
1704 | break;
|
---|
1705 | }
|
---|
1706 |
|
---|
1707 | case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
|
---|
1708 | case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
|
---|
1709 | case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
|
---|
1710 | case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
|
---|
1711 | {
|
---|
1712 | uint32_t cbSize;
|
---|
1713 |
|
---|
1714 | Log2(("SVM: %RGv mov x, cr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
|
---|
1715 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead);
|
---|
1716 | rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
|
---|
1717 | if (rc == VINF_SUCCESS)
|
---|
1718 | {
|
---|
1719 | /* EIP has been updated already. */
|
---|
1720 |
|
---|
1721 | /* Only resume if successful. */
|
---|
1722 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
|
---|
1723 | goto ResumeExecution;
|
---|
1724 | }
|
---|
1725 | Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
|
---|
1726 | break;
|
---|
1727 | }
|
---|
1728 |
|
---|
1729 | case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
|
---|
1730 | case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
|
---|
1731 | case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
|
---|
1732 | case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
|
---|
1733 | {
|
---|
1734 | uint32_t cbSize;
|
---|
1735 |
|
---|
1736 | Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
|
---|
1737 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
|
---|
1738 |
|
---|
1739 | if (!DBGFIsStepping(pVM))
|
---|
1740 | {
|
---|
1741 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
|
---|
1742 |
|
---|
1743 | /* Disable drx move intercepts. */
|
---|
1744 | pVMCB->ctrl.u16InterceptRdDRx = 0;
|
---|
1745 | pVMCB->ctrl.u16InterceptWrDRx = 0;
|
---|
1746 |
|
---|
1747 | /* Save the host and load the guest debug state. */
|
---|
1748 | rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
|
---|
1749 | AssertRC(rc);
|
---|
1750 |
|
---|
1751 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
|
---|
1752 | goto ResumeExecution;
|
---|
1753 | }
|
---|
1754 |
|
---|
1755 | rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
|
---|
1756 | if (rc == VINF_SUCCESS)
|
---|
1757 | {
|
---|
1758 | /* EIP has been updated already. */
|
---|
1759 | pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
|
---|
1760 |
|
---|
1761 | /* Only resume if successful. */
|
---|
1762 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
|
---|
1763 | goto ResumeExecution;
|
---|
1764 | }
|
---|
1765 | Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
|
---|
1766 | break;
|
---|
1767 | }
|
---|
1768 |
|
---|
1769 | case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
|
---|
1770 | case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
|
---|
1771 | case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
|
---|
1772 | case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
|
---|
1773 | {
|
---|
1774 | uint32_t cbSize;
|
---|
1775 |
|
---|
1776 | Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
|
---|
1777 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
|
---|
1778 |
|
---|
1779 | if (!DBGFIsStepping(pVM))
|
---|
1780 | {
|
---|
1781 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
|
---|
1782 |
|
---|
1783 | /* Disable drx move intercepts. */
|
---|
1784 | pVMCB->ctrl.u16InterceptRdDRx = 0;
|
---|
1785 | pVMCB->ctrl.u16InterceptWrDRx = 0;
|
---|
1786 |
|
---|
1787 | /* Save the host and load the guest debug state. */
|
---|
1788 | rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
|
---|
1789 | AssertRC(rc);
|
---|
1790 |
|
---|
1791 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
|
---|
1792 | goto ResumeExecution;
|
---|
1793 | }
|
---|
1794 |
|
---|
1795 | rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
|
---|
1796 | if (rc == VINF_SUCCESS)
|
---|
1797 | {
|
---|
1798 | /* EIP has been updated already. */
|
---|
1799 |
|
---|
1800 | /* Only resume if successful. */
|
---|
1801 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
|
---|
1802 | goto ResumeExecution;
|
---|
1803 | }
|
---|
1804 | Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
|
---|
1805 | break;
|
---|
1806 | }
|
---|
1807 |
|
---|
1808 | /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
|
---|
1809 | case SVM_EXIT_IOIO: /* I/O instruction. */
|
---|
1810 | {
|
---|
1811 | SVM_IOIO_EXIT IoExitInfo;
|
---|
1812 | uint32_t uIOSize, uAndVal;
|
---|
1813 |
|
---|
1814 | IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
|
---|
1815 |
|
---|
1816 | /** @todo could use a lookup table here */
|
---|
1817 | if (IoExitInfo.n.u1OP8)
|
---|
1818 | {
|
---|
1819 | uIOSize = 1;
|
---|
1820 | uAndVal = 0xff;
|
---|
1821 | }
|
---|
1822 | else
|
---|
1823 | if (IoExitInfo.n.u1OP16)
|
---|
1824 | {
|
---|
1825 | uIOSize = 2;
|
---|
1826 | uAndVal = 0xffff;
|
---|
1827 | }
|
---|
1828 | else
|
---|
1829 | if (IoExitInfo.n.u1OP32)
|
---|
1830 | {
|
---|
1831 | uIOSize = 4;
|
---|
1832 | uAndVal = 0xffffffff;
|
---|
1833 | }
|
---|
1834 | else
|
---|
1835 | {
|
---|
1836 | AssertFailed(); /* should be fatal. */
|
---|
1837 | rc = VINF_EM_RAW_EMULATE_INSTR;
|
---|
1838 | break;
|
---|
1839 | }
|
---|
1840 |
|
---|
1841 | if (IoExitInfo.n.u1STR)
|
---|
1842 | {
|
---|
1843 | /* ins/outs */
|
---|
1844 | DISCPUSTATE Cpu;
|
---|
1845 |
|
---|
1846 | /* Disassemble manually to deal with segment prefixes. */
|
---|
1847 | rc = EMInterpretDisasOne(pVM, CPUMCTX2CORE(pCtx), &Cpu, NULL);
|
---|
1848 | if (rc == VINF_SUCCESS)
|
---|
1849 | {
|
---|
1850 | if (IoExitInfo.n.u1Type == 0)
|
---|
1851 | {
|
---|
1852 | Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
|
---|
1853 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
|
---|
1854 | rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, Cpu.prefix, uIOSize);
|
---|
1855 | }
|
---|
1856 | else
|
---|
1857 | {
|
---|
1858 | Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
|
---|
1859 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
|
---|
1860 | rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, Cpu.prefix, uIOSize);
|
---|
1861 | }
|
---|
1862 | }
|
---|
1863 | else
|
---|
1864 | rc = VINF_EM_RAW_EMULATE_INSTR;
|
---|
1865 | }
|
---|
1866 | else
|
---|
1867 | {
|
---|
1868 | /* normal in/out */
|
---|
1869 | Assert(!IoExitInfo.n.u1REP);
|
---|
1870 |
|
---|
1871 | if (IoExitInfo.n.u1Type == 0)
|
---|
1872 | {
|
---|
1873 | Log2(("IOMIOPortWrite %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
|
---|
1874 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
|
---|
1875 | rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
|
---|
1876 | }
|
---|
1877 | else
|
---|
1878 | {
|
---|
1879 | uint32_t u32Val = 0;
|
---|
1880 |
|
---|
1881 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
|
---|
1882 | rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
|
---|
1883 | if (IOM_SUCCESS(rc))
|
---|
1884 | {
|
---|
1885 | /* Write back to the EAX register. */
|
---|
1886 | pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
|
---|
1887 | Log2(("IOMIOPortRead %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
|
---|
1888 | }
|
---|
1889 | }
|
---|
1890 | }
|
---|
1891 | /*
|
---|
1892 | * Handled the I/O return codes.
|
---|
1893 | * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
|
---|
1894 | */
|
---|
1895 | if (IOM_SUCCESS(rc))
|
---|
1896 | {
|
---|
1897 | /* Update EIP and continue execution. */
|
---|
1898 | pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
|
---|
1899 | if (RT_LIKELY(rc == VINF_SUCCESS))
|
---|
1900 | {
|
---|
1901 | /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
|
---|
1902 | if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
|
---|
1903 | {
|
---|
1904 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
|
---|
1905 | for (unsigned i=0;i<4;i++)
|
---|
1906 | {
|
---|
1907 | unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
|
---|
1908 |
|
---|
1909 | if ( (IoExitInfo.n.u16Port >= pCtx->dr[i] && IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen)
|
---|
1910 | && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
|
---|
1911 | && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
|
---|
1912 | {
|
---|
1913 | SVM_EVENT Event;
|
---|
1914 |
|
---|
1915 | Assert(CPUMIsGuestDebugStateActive(pVM));
|
---|
1916 |
|
---|
1917 | /* Clear all breakpoint status flags and set the one we just hit. */
|
---|
1918 | pCtx->dr[6] &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
|
---|
1919 | pCtx->dr[6] |= (uint64_t)RT_BIT(i);
|
---|
1920 |
|
---|
1921 | /* Note: AMD64 Architecture Programmer's Manual 13.1:
|
---|
1922 | * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
|
---|
1923 | * the contents have been read.
|
---|
1924 | */
|
---|
1925 | pVMCB->guest.u64DR6 = pCtx->dr[6];
|
---|
1926 |
|
---|
1927 | /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
|
---|
1928 | pCtx->dr[7] &= ~X86_DR7_GD;
|
---|
1929 |
|
---|
1930 | /* Paranoia. */
|
---|
1931 | pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
|
---|
1932 | pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
|
---|
1933 | pCtx->dr[7] |= 0x400; /* must be one */
|
---|
1934 |
|
---|
1935 | pVMCB->guest.u64DR7 = pCtx->dr[7];
|
---|
1936 |
|
---|
1937 | /* Inject the exception. */
|
---|
1938 | Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
|
---|
1939 |
|
---|
1940 | Event.au64[0] = 0;
|
---|
1941 | Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
|
---|
1942 | Event.n.u1Valid = 1;
|
---|
1943 | Event.n.u8Vector = X86_XCPT_DB;
|
---|
1944 |
|
---|
1945 | SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
|
---|
1946 |
|
---|
1947 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
|
---|
1948 | goto ResumeExecution;
|
---|
1949 | }
|
---|
1950 | }
|
---|
1951 | }
|
---|
1952 |
|
---|
1953 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
|
---|
1954 | goto ResumeExecution;
|
---|
1955 | }
|
---|
1956 | Log2(("EM status from IO at %RGv %x size %d: %Rrc\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
|
---|
1957 | break;
|
---|
1958 | }
|
---|
1959 |
|
---|
1960 | #ifdef VBOX_STRICT
|
---|
1961 | if (rc == VINF_IOM_HC_IOPORT_READ)
|
---|
1962 | Assert(IoExitInfo.n.u1Type != 0);
|
---|
1963 | else if (rc == VINF_IOM_HC_IOPORT_WRITE)
|
---|
1964 | Assert(IoExitInfo.n.u1Type == 0);
|
---|
1965 | else
|
---|
1966 | AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
|
---|
1967 | #endif
|
---|
1968 | Log2(("Failed IO at %RGv %x size %d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
|
---|
1969 | break;
|
---|
1970 | }
|
---|
1971 |
|
---|
1972 | case SVM_EXIT_HLT:
|
---|
1973 | /** Check if external interrupts are pending; if so, don't switch back. */
|
---|
1974 | pCtx->rip++; /* skip hlt */
|
---|
1975 | if ( pCtx->eflags.Bits.u1IF
|
---|
1976 | && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
|
---|
1977 | goto ResumeExecution;
|
---|
1978 |
|
---|
1979 | rc = VINF_EM_HALT;
|
---|
1980 | break;
|
---|
1981 |
|
---|
1982 | case SVM_EXIT_RSM:
|
---|
1983 | case SVM_EXIT_INVLPGA:
|
---|
1984 | case SVM_EXIT_VMRUN:
|
---|
1985 | case SVM_EXIT_VMMCALL:
|
---|
1986 | case SVM_EXIT_VMLOAD:
|
---|
1987 | case SVM_EXIT_VMSAVE:
|
---|
1988 | case SVM_EXIT_STGI:
|
---|
1989 | case SVM_EXIT_CLGI:
|
---|
1990 | case SVM_EXIT_SKINIT:
|
---|
1991 | {
|
---|
1992 | /* Unsupported instructions. */
|
---|
1993 | SVM_EVENT Event;
|
---|
1994 |
|
---|
1995 | Event.au64[0] = 0;
|
---|
1996 | Event.n.u3Type = SVM_EVENT_EXCEPTION;
|
---|
1997 | Event.n.u1Valid = 1;
|
---|
1998 | Event.n.u8Vector = X86_XCPT_UD;
|
---|
1999 |
|
---|
2000 | Log(("Forced #UD trap at %RGv\n", (RTGCPTR)pCtx->rip));
|
---|
2001 | SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
|
---|
2002 |
|
---|
2003 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
|
---|
2004 | goto ResumeExecution;
|
---|
2005 | }
|
---|
2006 |
|
---|
2007 | /* Emulate in ring 3. */
|
---|
2008 | case SVM_EXIT_MSR:
|
---|
2009 | {
|
---|
2010 | uint32_t cbSize;
|
---|
2011 |
|
---|
2012 | /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
|
---|
2013 | Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
|
---|
2014 | rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
|
---|
2015 | if (rc == VINF_SUCCESS)
|
---|
2016 | {
|
---|
2017 | /* EIP has been updated already. */
|
---|
2018 |
|
---|
2019 | /* Only resume if successful. */
|
---|
2020 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
|
---|
2021 | goto ResumeExecution;
|
---|
2022 | }
|
---|
2023 | AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
|
---|
2024 | break;
|
---|
2025 | }
|
---|
2026 |
|
---|
2027 | case SVM_EXIT_MONITOR:
|
---|
2028 | case SVM_EXIT_RDPMC:
|
---|
2029 | case SVM_EXIT_PAUSE:
|
---|
2030 | case SVM_EXIT_MWAIT_UNCOND:
|
---|
2031 | case SVM_EXIT_MWAIT_ARMED:
|
---|
2032 | case SVM_EXIT_TASK_SWITCH: /* can change CR3; emulate */
|
---|
2033 | rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
|
---|
2034 | break;
|
---|
2035 |
|
---|
2036 | case SVM_EXIT_SHUTDOWN:
|
---|
2037 | rc = VINF_EM_RESET; /* Triple fault equals a reset. */
|
---|
2038 | break;
|
---|
2039 |
|
---|
2040 | case SVM_EXIT_IDTR_READ:
|
---|
2041 | case SVM_EXIT_GDTR_READ:
|
---|
2042 | case SVM_EXIT_LDTR_READ:
|
---|
2043 | case SVM_EXIT_TR_READ:
|
---|
2044 | case SVM_EXIT_IDTR_WRITE:
|
---|
2045 | case SVM_EXIT_GDTR_WRITE:
|
---|
2046 | case SVM_EXIT_LDTR_WRITE:
|
---|
2047 | case SVM_EXIT_TR_WRITE:
|
---|
2048 | case SVM_EXIT_CR0_SEL_WRITE:
|
---|
2049 | default:
|
---|
2050 | /* Unexpected exit codes. */
|
---|
2051 | rc = VERR_EM_INTERNAL_ERROR;
|
---|
2052 | AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
|
---|
2053 | break;
|
---|
2054 | }
|
---|
2055 |
|
---|
2056 | end:
|
---|
2057 |
|
---|
2058 | /* Signal changes for the recompiler. */
|
---|
2059 | CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
|
---|
2060 |
|
---|
2061 | /* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
|
---|
2062 | if (exitCode == SVM_EXIT_INTR)
|
---|
2063 | {
|
---|
2064 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
|
---|
2065 | /* On the next entry we'll only sync the host context. */
|
---|
2066 | pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
|
---|
2067 | }
|
---|
2068 | else
|
---|
2069 | {
|
---|
2070 | /* On the next entry we'll sync everything. */
|
---|
2071 | /** @todo we can do better than this */
|
---|
2072 | /* Not in the VINF_PGM_CHANGE_MODE though! */
|
---|
2073 | pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
|
---|
2074 | }
|
---|
2075 |
|
---|
2076 | /* translate into a less severe return code */
|
---|
2077 | if (rc == VERR_EM_INTERPRETER)
|
---|
2078 | rc = VINF_EM_RAW_EMULATE_INSTR;
|
---|
2079 |
|
---|
2080 | STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit, x);
|
---|
2081 | return rc;
|
---|
2082 | }
|
---|
2083 |
|
---|
2084 | /**
|
---|
2085 | * Enters the AMD-V session
|
---|
2086 | *
|
---|
2087 | * @returns VBox status code.
|
---|
2088 | * @param pVM The VM to operate on.
|
---|
2089 | * @param pVCpu The VM CPU to operate on.
|
---|
2090 | * @param pCpu CPU info struct
|
---|
2091 | */
|
---|
2092 | VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
|
---|
2093 | {
|
---|
2094 | Assert(pVM->hwaccm.s.svm.fSupported);
|
---|
2095 |
|
---|
2096 | LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVCpu->hwaccm.s.idLastCpu, pVCpu->hwaccm.s.uCurrentASID));
|
---|
2097 | pVCpu->hwaccm.s.fResumeVM = false;
|
---|
2098 |
|
---|
2099 | /* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
|
---|
2100 | pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_LDTR;
|
---|
2101 |
|
---|
2102 | return VINF_SUCCESS;
|
---|
2103 | }
|
---|
2104 |
|
---|
2105 |
|
---|
2106 | /**
|
---|
2107 | * Leaves the AMD-V session
|
---|
2108 | *
|
---|
2109 | * @returns VBox status code.
|
---|
2110 | * @param pVM The VM to operate on.
|
---|
2111 | * @param pVCpu The VM CPU to operate on.
|
---|
2112 | * @param pCtx CPU context
|
---|
2113 | */
|
---|
2114 | VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
|
---|
2115 | {
|
---|
2116 | SVM_VMCB *pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
|
---|
2117 |
|
---|
2118 | Assert(pVM->hwaccm.s.svm.fSupported);
|
---|
2119 |
|
---|
2120 | /* Save the guest debug state if necessary. */
|
---|
2121 | if (CPUMIsGuestDebugStateActive(pVM))
|
---|
2122 | {
|
---|
2123 | CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, false /* skip DR6 */);
|
---|
2124 |
|
---|
2125 | /* Intercept all DRx reads and writes again. Changed later on. */
|
---|
2126 | pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
|
---|
2127 | pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
|
---|
2128 |
|
---|
2129 | /* Resync the debug registers the next time. */
|
---|
2130 | pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
|
---|
2131 | }
|
---|
2132 | else
|
---|
2133 | Assert(pVMCB->ctrl.u16InterceptRdDRx == 0xFFFF && pVMCB->ctrl.u16InterceptWrDRx == 0xFFFF);
|
---|
2134 |
|
---|
2135 | return VINF_SUCCESS;
|
---|
2136 | }
|
---|
2137 |
|
---|
2138 |
|
---|
2139 | static int svmR0InterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
|
---|
2140 | {
|
---|
2141 | OP_PARAMVAL param1;
|
---|
2142 | RTGCPTR addr;
|
---|
2143 |
|
---|
2144 | int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, ¶m1, PARAM_SOURCE);
|
---|
2145 | if(RT_FAILURE(rc))
|
---|
2146 | return VERR_EM_INTERPRETER;
|
---|
2147 |
|
---|
2148 | switch(param1.type)
|
---|
2149 | {
|
---|
2150 | case PARMTYPE_IMMEDIATE:
|
---|
2151 | case PARMTYPE_ADDRESS:
|
---|
2152 | if(!(param1.flags & (PARAM_VAL32|PARAM_VAL64)))
|
---|
2153 | return VERR_EM_INTERPRETER;
|
---|
2154 | addr = param1.val.val64;
|
---|
2155 | break;
|
---|
2156 |
|
---|
2157 | default:
|
---|
2158 | return VERR_EM_INTERPRETER;
|
---|
2159 | }
|
---|
2160 |
|
---|
2161 | /** @todo is addr always a flat linear address or ds based
|
---|
2162 | * (in absence of segment override prefixes)????
|
---|
2163 | */
|
---|
2164 | rc = PGMInvalidatePage(pVM, addr);
|
---|
2165 | if (RT_SUCCESS(rc))
|
---|
2166 | {
|
---|
2167 | /* Manually invalidate the page for the VM's TLB. */
|
---|
2168 | Log(("SVMR0InvlpgA %RGv ASID=%d\n", addr, uASID));
|
---|
2169 | SVMR0InvlpgA(addr, uASID);
|
---|
2170 | return VINF_SUCCESS;
|
---|
2171 | }
|
---|
2172 | Assert(rc == VERR_REM_FLUSHED_PAGES_OVERFLOW);
|
---|
2173 | return rc;
|
---|
2174 | }
|
---|
2175 |
|
---|
2176 | /**
|
---|
2177 | * Interprets INVLPG
|
---|
2178 | *
|
---|
2179 | * @returns VBox status code.
|
---|
2180 | * @retval VINF_* Scheduling instructions.
|
---|
2181 | * @retval VERR_EM_INTERPRETER Something we can't cope with.
|
---|
2182 | * @retval VERR_* Fatal errors.
|
---|
2183 | *
|
---|
2184 | * @param pVM The VM handle.
|
---|
2185 | * @param pRegFrame The register frame.
|
---|
2186 | * @param ASID Tagged TLB id for the guest
|
---|
2187 | *
|
---|
2188 | * Updates the EIP if an instruction was executed successfully.
|
---|
2189 | */
|
---|
2190 | static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
|
---|
2191 | {
|
---|
2192 | /*
|
---|
2193 | * Only allow 32 & 64 bits code.
|
---|
2194 | */
|
---|
2195 | DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
|
---|
2196 | if (enmMode != CPUMODE_16BIT)
|
---|
2197 | {
|
---|
2198 | RTGCPTR pbCode;
|
---|
2199 | int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
|
---|
2200 | if (RT_SUCCESS(rc))
|
---|
2201 | {
|
---|
2202 | uint32_t cbOp;
|
---|
2203 | DISCPUSTATE Cpu;
|
---|
2204 |
|
---|
2205 | Cpu.mode = enmMode;
|
---|
2206 | rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
|
---|
2207 | Assert(RT_FAILURE(rc) || Cpu.pCurInstr->opcode == OP_INVLPG);
|
---|
2208 | if (RT_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
|
---|
2209 | {
|
---|
2210 | Assert(cbOp == Cpu.opsize);
|
---|
2211 | rc = svmR0InterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
|
---|
2212 | if (RT_SUCCESS(rc))
|
---|
2213 | {
|
---|
2214 | pRegFrame->rip += cbOp; /* Move on to the next instruction. */
|
---|
2215 | }
|
---|
2216 | return rc;
|
---|
2217 | }
|
---|
2218 | }
|
---|
2219 | }
|
---|
2220 | return VERR_EM_INTERPRETER;
|
---|
2221 | }
|
---|
2222 |
|
---|
2223 |
|
---|
2224 | /**
|
---|
2225 | * Invalidates a guest page
|
---|
2226 | *
|
---|
2227 | * @returns VBox status code.
|
---|
2228 | * @param pVM The VM to operate on.
|
---|
2229 | * @param pVCpu The VM CPU to operate on.
|
---|
2230 | * @param GCVirt Page to invalidate
|
---|
2231 | */
|
---|
2232 | VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
|
---|
2233 | {
|
---|
2234 | bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB | pVCpu->hwaccm.s.fForceTLBFlush;
|
---|
2235 |
|
---|
2236 | /* Skip it if a TLB flush is already pending. */
|
---|
2237 | if (!fFlushPending)
|
---|
2238 | {
|
---|
2239 | SVM_VMCB *pVMCB;
|
---|
2240 |
|
---|
2241 | Log2(("SVMR0InvalidatePage %RGv\n", GCVirt));
|
---|
2242 | AssertReturn(pVM, VERR_INVALID_PARAMETER);
|
---|
2243 | Assert(pVM->hwaccm.s.svm.fSupported);
|
---|
2244 |
|
---|
2245 | /* @todo SMP */
|
---|
2246 | pVMCB = (SVM_VMCB *)pVM->aCpus[0].hwaccm.s.svm.pVMCB;
|
---|
2247 | AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
|
---|
2248 |
|
---|
2249 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushPageManual);
|
---|
2250 | SVMR0InvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
|
---|
2251 | }
|
---|
2252 | return VINF_SUCCESS;
|
---|
2253 | }
|
---|
2254 |
|
---|
2255 |
|
---|
2256 | /**
|
---|
2257 | * Invalidates a guest page by physical address
|
---|
2258 | *
|
---|
2259 | * @returns VBox status code.
|
---|
2260 | * @param pVM The VM to operate on.
|
---|
2261 | * @param pVCpu The VM CPU to operate on.
|
---|
2262 | * @param GCPhys Page to invalidate
|
---|
2263 | */
|
---|
2264 | VMMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
|
---|
2265 | {
|
---|
2266 | Assert(pVM->hwaccm.s.fNestedPaging);
|
---|
2267 | /* invlpga only invalidates TLB entries for guest virtual addresses; we have no choice but to force a TLB flush here. */
|
---|
2268 | pVCpu->hwaccm.s.fForceTLBFlush = true;
|
---|
2269 | STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBInvlpga);
|
---|
2270 | return VINF_SUCCESS;
|
---|
2271 | }
|
---|
2272 |
|
---|
2273 | #if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
|
---|
2274 | /**
|
---|
2275 | * Prepares for and executes VMRUN (64 bits guests from a 32 bits hosts).
|
---|
2276 | *
|
---|
2277 | * @returns VBox status code.
|
---|
2278 | * @param pVMCBHostPhys Physical address of host VMCB.
|
---|
2279 | * @param pVMCBPhys Physical address of the VMCB.
|
---|
2280 | * @param pCtx Guest context.
|
---|
2281 | * @param pVM The VM to operate on.
|
---|
2282 | * @param pVCpu The VMCPU to operate on.
|
---|
2283 | */
|
---|
2284 | DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
|
---|
2285 | {
|
---|
2286 | return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnVMXGCStartVM64);
|
---|
2287 | }
|
---|
2288 |
|
---|
2289 | /**
|
---|
2290 | * Executes the specified handler in 64 mode
|
---|
2291 | *
|
---|
2292 | * @returns VBox status code.
|
---|
2293 | * @param pVM The VM to operate on.
|
---|
2294 | * @param pVCpu The VMCPU to operate on.
|
---|
2295 | * @param pCtx Guest context
|
---|
2296 | * @param pfnHandler RC handler
|
---|
2297 | */
|
---|
2298 | VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler)
|
---|
2299 | {
|
---|
2300 | int rc;
|
---|
2301 | RTCCUINTREG uFlags;
|
---|
2302 |
|
---|
2303 | /* @todo This code is not guest SMP safe (hyper context) */
|
---|
2304 | AssertReturn(pVM->cCPUs == 1, VERR_ACCESS_DENIED);
|
---|
2305 |
|
---|
2306 | uFlags = ASMIntDisableFlags();
|
---|
2307 |
|
---|
2308 | CPUMSetHyperESP(pVM, VMMGetStackRC(pVM));
|
---|
2309 | CPUMSetHyperEIP(pVM, pfnHandler);
|
---|
2310 |
|
---|
2311 | /* Call switcher. */
|
---|
2312 | rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM);
|
---|
2313 |
|
---|
2314 | ASMSetFlags(uFlags);
|
---|
2315 | return rc;
|
---|
2316 | }
|
---|
2317 |
|
---|
2318 | #endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) */
|
---|