HWSVMR0.cpp@ 15410

Last change on this file since 15410 was 15410, checked in by vboxsync, 16 years ago
PGM: Deal with pgmPoolAlloc failure in MapCR3 without relying on having to clear the pool. The MapCR3 action will be postponed to SyncCR3.
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1	/* $Id: HWSVMR0.cpp 15410 2008-12-13 01:04:17Z vboxsync $ */
2	/** @file
3	* HWACCM SVM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_svm.h>
32	#include <VBox/pgm.h>
33	#include <VBox/pdm.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <VBox/selm.h>
37	#include <VBox/iom.h>
38	#include <VBox/dis.h>
39	#include <VBox/dbgf.h>
40	#include <VBox/disopcode.h>
41	#include <iprt/param.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm.h>
44	#include <iprt/cpuset.h>
45	#include <iprt/mp.h>
46	#include "HWSVMR0.h"
47
48	/*******************************************************************************
49	* Internal Functions *
50	*******************************************************************************/
51	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
52
53	/*******************************************************************************
54	* Global Variables *
55	*******************************************************************************/
56	/* IO operation lookup arrays. */
57	static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
58
59	/**
60	* Sets up and activates AMD-V on the current CPU
61	*
62	* @returns VBox status code.
63	* @param pCpu CPU info struct
64	* @param pVM The VM to operate on. (can be NULL after a resume!!)
65	* @param pvPageCpu Pointer to the global cpu page
66	* @param pPageCpuPhys Physical address of the global cpu page
67	*/
68	VMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
69	{
70	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
71	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
72
73	/* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
74
75	#ifdef LOG_ENABLED
76	SUPR0Printf("SVMR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
77	#endif
78
79	/* Turn on AMD-V in the EFER MSR. */
80	uint64_t val = ASMRdMsr(MSR_K6_EFER);
81	if (!(val & MSR_K6_EFER_SVME))
82	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
83
84	/* Write the physical page address where the CPU will store the host state while executing the VM. */
85	ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
86
87	return VINF_SUCCESS;
88	}
89
90	/**
91	* Deactivates AMD-V on the current CPU
92	*
93	* @returns VBox status code.
94	* @param pCpu CPU info struct
95	* @param pvPageCpu Pointer to the global cpu page
96	* @param pPageCpuPhys Physical address of the global cpu page
97	*/
98	VMMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
99	{
100	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
101	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
102
103	#ifdef LOG_ENABLED
104	SUPR0Printf("SVMR0DisableCpu cpu %d\n", pCpu->idCpu);
105	#endif
106
107	/* Turn off AMD-V in the EFER MSR. */
108	uint64_t val = ASMRdMsr(MSR_K6_EFER);
109	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
110
111	/* Invalidate host state physical address. */
112	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
113
114	return VINF_SUCCESS;
115	}
116
117	/**
118	* Does Ring-0 per VM AMD-V init.
119	*
120	* @returns VBox status code.
121	* @param pVM The VM to operate on.
122	*/
123	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
124	{
125	int rc;
126
127	pVM->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
128	pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
129	pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
130
131	/* Allocate one page for the host context */
132	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
133	if (RT_FAILURE(rc))
134	return rc;
135
136	pVM->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCBHost);
137	pVM->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCBHost, 0);
138	ASMMemZeroPage(pVM->hwaccm.s.svm.pVMCBHost);
139
140	/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
141	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
142	if (RT_FAILURE(rc))
143	return rc;
144
145	pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
146	pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
147	/* Set all bits to intercept all IO accesses. */
148	ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
149
150	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
151	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
152	if (RT_FAILURE(rc))
153	return rc;
154
155	pVM->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
156	pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
157	/* Set all bits to intercept all MSR accesses. */
158	ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
159
160	/* Erratum 170 which requires a forced TLB flush for each world switch:
161	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
162	*
163	* All BH-G1/2 and DH-G1/2 models include a fix:
164	* Athlon X2: 0x6b 1/2
165	* 0x68 1/2
166	* Athlon 64: 0x7f 1
167	* 0x6f 2
168	* Sempron: 0x7f 1/2
169	* 0x6f 2
170	* 0x6c 2
171	* 0x7c 2
172	* Turion 64: 0x68 2
173	*
174	*/
175	uint32_t u32Dummy;
176	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
177	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
178	u32BaseFamily= (u32Version >> 8) & 0xf;
179	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
180	u32Model = ((u32Version >> 4) & 0xf);
181	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
182	u32Stepping = u32Version & 0xf;
183	if ( u32Family == 0xf
184	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
185	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
186	{
187	Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
188	pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
189	}
190
191	/* Allocate VMCBs for all guest CPUs. */
192	for (unsigned i=0;i<pVM->cCPUs;i++)
193	{
194	pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
195
196	/* Allocate one page for the VM control block (VMCB). */
197	rc = RTR0MemObjAllocCont(&pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
198	if (RT_FAILURE(rc))
199	return rc;
200
201	pVM->aCpus[i].hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB);
202	pVM->aCpus[i].hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB, 0);
203	ASMMemZeroPage(pVM->aCpus[i].hwaccm.s.svm.pVMCB);
204	}
205
206	return VINF_SUCCESS;
207	}
208
209	/**
210	* Does Ring-0 per VM AMD-V termination.
211	*
212	* @returns VBox status code.
213	* @param pVM The VM to operate on.
214	*/
215	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
216	{
217	for (unsigned i=0;i<pVM->cCPUs;i++)
218	{
219	if (pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)
220	{
221	RTR0MemObjFree(pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB, false);
222	pVM->aCpus[i].hwaccm.s.svm.pVMCB = 0;
223	pVM->aCpus[i].hwaccm.s.svm.pVMCBPhys = 0;
224	pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
225	}
226	}
227	if (pVM->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ)
228	{
229	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCBHost, false);
230	pVM->hwaccm.s.svm.pVMCBHost = 0;
231	pVM->hwaccm.s.svm.pVMCBHostPhys = 0;
232	pVM->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
233	}
234	if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)
235	{
236	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
237	pVM->hwaccm.s.svm.pIOBitmap = 0;
238	pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
239	pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
240	}
241	if (pVM->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
242	{
243	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
244	pVM->hwaccm.s.svm.pMSRBitmap = 0;
245	pVM->hwaccm.s.svm.pMSRBitmapPhys = 0;
246	pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
247	}
248	return VINF_SUCCESS;
249	}
250
251	/**
252	* Sets up AMD-V for the specified VM
253	*
254	* @returns VBox status code.
255	* @param pVM The VM to operate on.
256	*/
257	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
258	{
259	int rc = VINF_SUCCESS;
260	SVM_VMCB *pVMCB;
261
262	AssertReturn(pVM, VERR_INVALID_PARAMETER);
263
264	Assert(pVM->hwaccm.s.svm.fSupported);
265
266	for (unsigned i=0;i<pVM->cCPUs;i++)
267	{
268	pVMCB = (SVM_VMCB *)pVM->aCpus[i].hwaccm.s.svm.pVMCB;
269	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
270
271	/* Program the control fields. Most of them never have to be changed again. */
272	/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
273	/* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical. */
274	if (!pVM->hwaccm.s.fNestedPaging)
275	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
276	else
277	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
278
279	/*
280	* CR0/3/4 writes must be intercepted for obvious reasons.
281	*/
282	if (!pVM->hwaccm.s.fNestedPaging)
283	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
284	else
285	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4) \| RT_BIT(8);
286
287	/* Intercept all DRx reads and writes by default. Changed later on. */
288	pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
289	pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
290
291	/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
292	* All breakpoints are automatically cleared when the VM exits.
293	*/
294
295	pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
296	#ifndef DEBUG
297	if (pVM->hwaccm.s.fNestedPaging)
298	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
299	#endif
300
301	pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
302	\| SVM_CTRL1_INTERCEPT_VINTR
303	\| SVM_CTRL1_INTERCEPT_NMI
304	\| SVM_CTRL1_INTERCEPT_SMI
305	\| SVM_CTRL1_INTERCEPT_INIT
306	\| SVM_CTRL1_INTERCEPT_RDPMC
307	\| SVM_CTRL1_INTERCEPT_CPUID
308	\| SVM_CTRL1_INTERCEPT_RSM
309	\| SVM_CTRL1_INTERCEPT_HLT
310	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
311	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
312	\| SVM_CTRL1_INTERCEPT_INVLPG
313	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
314	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH
315	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
316	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
317	;
318	/* With nested paging we don't care about invlpg anymore. */
319	if (pVM->hwaccm.s.fNestedPaging)
320	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
321
322	pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
323	\| SVM_CTRL2_INTERCEPT_VMMCALL
324	\| SVM_CTRL2_INTERCEPT_VMLOAD
325	\| SVM_CTRL2_INTERCEPT_VMSAVE
326	\| SVM_CTRL2_INTERCEPT_STGI
327	\| SVM_CTRL2_INTERCEPT_CLGI
328	\| SVM_CTRL2_INTERCEPT_SKINIT
329	\| SVM_CTRL2_INTERCEPT_WBINVD
330	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
331	;
332	Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
333	Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
334	Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
335
336	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
337	pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
338	/* Ignore the priority in the TPR; just deliver it when we tell it to. */
339	pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
340
341	/* Set IO and MSR bitmap addresses. */
342	pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
343	pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
344
345	/* No LBR virtualization. */
346	pVMCB->ctrl.u64LBRVirt = 0;
347
348	/** The ASID must start at 1; the host uses 0. */
349	pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
350
351	/** Setup the PAT msr (nested paging only) */
352	pVMCB->guest.u64GPAT = 0x0007040600070406ULL;
353	}
354	return rc;
355	}
356
357
358	/**
359	* Injects an event (trap or external interrupt)
360	*
361	* @param pVM The VM to operate on.
362	* @param pVMCB SVM control block
363	* @param pCtx CPU Context
364	* @param pIntInfo SVM interrupt info
365	*/
366	inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx, SVM_EVENT* pEvent)
367	{
368	#ifdef VBOX_STRICT
369	if (pEvent->n.u8Vector == 0xE)
370	Log(("SVM: Inject int %d at %RGv error code=%02x CR2=%RGv intInfo=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode, (RTGCPTR)pCtx->cr2, pEvent->au64[0]));
371	else
372	if (pEvent->n.u8Vector < 0x20)
373	Log(("SVM: Inject int %d at %RGv error code=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode));
374	else
375	{
376	Log(("INJ-EI: %x at %RGv\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip));
377	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
378	Assert(pCtx->eflags.u32 & X86_EFL_IF);
379	}
380	#endif
381
382	/* Set event injection state. */
383	pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
384	}
385
386
387	/**
388	* Checks for pending guest interrupts and injects them
389	*
390	* @returns VBox status code.
391	* @param pVM The VM to operate on.
392	* @param pVCpu The VM CPU to operate on.
393	* @param pVMCB SVM control block
394	* @param pCtx CPU Context
395	*/
396	static int SVMR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, SVM_VMCB pVMCB, CPUMCTX pCtx)
397	{
398	int rc;
399
400	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
401	if (pVCpu->hwaccm.s.Event.fPending)
402	{
403	SVM_EVENT Event;
404
405	Log(("Reinjecting event %08x %08x at %RGv\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip));
406	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
407	Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
408	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
409
410	pVCpu->hwaccm.s.Event.fPending = false;
411	return VINF_SUCCESS;
412	}
413
414	if (pVM->hwaccm.s.fInjectNMI)
415	{
416	SVM_EVENT Event;
417
418	Event.n.u8Vector = X86_XCPT_NMI;
419	Event.n.u1Valid = 1;
420	Event.n.u32ErrorCode = 0;
421	Event.n.u3Type = SVM_EVENT_NMI;
422
423	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
424	pVM->hwaccm.s.fInjectNMI = false;
425	return VINF_SUCCESS;
426	}
427
428	/* When external interrupts are pending, we should exit the VM when IF is set. */
429	if ( !TRPMHasTrap(pVM)
430	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
431	{
432	if ( !(pCtx->eflags.u32 & X86_EFL_IF)
433	\|\| VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
434	{
435	if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
436	{
437	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
438	LogFlow(("Enable irq window exit!\n"));
439	else
440	Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", (RTGCPTR)pCtx->rip));
441
442	/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
443	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
444	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
445	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
446	}
447	}
448	else
449	{
450	uint8_t u8Interrupt;
451
452	rc = PDMGetInterrupt(pVM, &u8Interrupt);
453	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
454	if (RT_SUCCESS(rc))
455	{
456	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
457	AssertRC(rc);
458	}
459	else
460	{
461	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
462	Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)));
463	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
464	/* Just continue */
465	}
466	}
467	}
468
469	#ifdef VBOX_STRICT
470	if (TRPMHasTrap(pVM))
471	{
472	uint8_t u8Vector;
473	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
474	AssertRC(rc);
475	}
476	#endif
477
478	if ( pCtx->eflags.u32 & X86_EFL_IF
479	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
480	&& TRPMHasTrap(pVM)
481	)
482	{
483	uint8_t u8Vector;
484	int rc;
485	TRPMEVENT enmType;
486	SVM_EVENT Event;
487	RTGCUINT u32ErrorCode;
488
489	Event.au64[0] = 0;
490
491	/* If a new event is pending, then dispatch it now. */
492	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &u32ErrorCode, 0);
493	AssertRC(rc);
494	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
495	Assert(enmType != TRPM_SOFTWARE_INT);
496
497	/* Clear the pending trap. */
498	rc = TRPMResetTrap(pVM);
499	AssertRC(rc);
500
501	Event.n.u8Vector = u8Vector;
502	Event.n.u1Valid = 1;
503	Event.n.u32ErrorCode = u32ErrorCode;
504
505	if (enmType == TRPM_TRAP)
506	{
507	switch (u8Vector) {
508	case 8:
509	case 10:
510	case 11:
511	case 12:
512	case 13:
513	case 14:
514	case 17:
515	/* Valid error codes. */
516	Event.n.u1ErrorCodeValid = 1;
517	break;
518	default:
519	break;
520	}
521	if (u8Vector == X86_XCPT_NMI)
522	Event.n.u3Type = SVM_EVENT_NMI;
523	else
524	Event.n.u3Type = SVM_EVENT_EXCEPTION;
525	}
526	else
527	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
528
529	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
530	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
531	} /* if (interrupts can be dispatched) */
532
533	return VINF_SUCCESS;
534	}
535
536	/**
537	* Save the host state
538	*
539	* @returns VBox status code.
540	* @param pVM The VM to operate on.
541	* @param pVCpu The VM CPU to operate on.
542	*/
543	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
544	{
545	NOREF(pVM);
546	NOREF(pVCpu);
547	/* Nothing to do here. */
548	return VINF_SUCCESS;
549	}
550
551	/**
552	* Loads the guest state
553	*
554	* NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
555	*
556	* @returns VBox status code.
557	* @param pVM The VM to operate on.
558	* @param pVCpu The VM CPU to operate on.
559	* @param pCtx Guest context
560	*/
561	VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
562	{
563	RTGCUINTPTR val;
564	SVM_VMCB *pVMCB;
565
566	if (pVM == NULL)
567	return VERR_INVALID_PARAMETER;
568
569	/* Setup AMD SVM. */
570	Assert(pVM->hwaccm.s.svm.fSupported);
571
572	pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
573	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
574
575	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
576	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
577	{
578	SVM_WRITE_SELREG(CS, cs);
579	SVM_WRITE_SELREG(SS, ss);
580	SVM_WRITE_SELREG(DS, ds);
581	SVM_WRITE_SELREG(ES, es);
582	SVM_WRITE_SELREG(FS, fs);
583	SVM_WRITE_SELREG(GS, gs);
584	}
585
586	/* Guest CPU context: LDTR. */
587	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
588	{
589	SVM_WRITE_SELREG(LDTR, ldtr);
590	}
591
592	/* Guest CPU context: TR. */
593	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
594	{
595	SVM_WRITE_SELREG(TR, tr);
596	}
597
598	/* Guest CPU context: GDTR. */
599	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
600	{
601	pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
602	pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
603	}
604
605	/* Guest CPU context: IDTR. */
606	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
607	{
608	pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
609	pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
610	}
611
612	/*
613	* Sysenter MSRs (unconditional)
614	*/
615	pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
616	pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
617	pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
618
619	/* Control registers */
620	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
621	{
622	val = pCtx->cr0;
623	if (!CPUMIsGuestFPUStateActive(pVCpu))
624	{
625	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
626	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
627	}
628	else
629	{
630	/** @todo check if we support the old style mess correctly. */
631	if (!(val & X86_CR0_NE))
632	{
633	Log(("Forcing X86_CR0_NE!!!\n"));
634
635	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
636	if (!pVCpu->hwaccm.s.fFPUOldStyleOverride)
637	{
638	pVMCB->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_MF);
639	pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
640	}
641	}
642	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
643	}
644	/* Always enable caching. */
645	val &= ~(X86_CR0_CD\|X86_CR0_NW);
646
647	/* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
648	/* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
649	if (!pVM->hwaccm.s.fNestedPaging)
650	{
651	val \|= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
652	val \|= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
653	}
654	pVMCB->guest.u64CR0 = val;
655	}
656	/* CR2 as well */
657	pVMCB->guest.u64CR2 = pCtx->cr2;
658
659	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
660	{
661	/* Save our shadow CR3 register. */
662	if (pVM->hwaccm.s.fNestedPaging)
663	{
664	PGMMODE enmShwPagingMode;
665
666	#if HC_ARCH_BITS == 32
667	if (CPUMIsGuestInLongModeEx(pCtx))
668	enmShwPagingMode = PGMMODE_AMD64_NX;
669	else
670	#endif
671	enmShwPagingMode = PGMGetHostMode(pVM);
672
673	pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVM, enmShwPagingMode);
674	Assert(pVMCB->ctrl.u64NestedPagingCR3);
675	pVMCB->guest.u64CR3 = pCtx->cr3;
676	}
677	else
678	{
679	pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
680	Assert(pVMCB->guest.u64CR3 \|\| VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL));
681	}
682	}
683
684	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
685	{
686	val = pCtx->cr4;
687	if (!pVM->hwaccm.s.fNestedPaging)
688	{
689	switch(pVCpu->hwaccm.s.enmShadowMode)
690	{
691	case PGMMODE_REAL:
692	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
693	AssertFailed();
694	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
695
696	case PGMMODE_32_BIT: /* 32-bit paging. */
697	break;
698
699	case PGMMODE_PAE: /* PAE paging. */
700	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
701	/** @todo use normal 32 bits paging */
702	val \|= X86_CR4_PAE;
703	break;
704
705	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
706	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
707	#ifdef VBOX_ENABLE_64_BITS_GUESTS
708	break;
709	#else
710	AssertFailed();
711	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
712	#endif
713
714	default: /* shut up gcc */
715	AssertFailed();
716	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
717	}
718	}
719	pVMCB->guest.u64CR4 = val;
720	}
721
722	/* Debug registers. */
723	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
724	{
725	pCtx->dr[6] \|= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
726	pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
727
728	pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
729	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
730	pCtx->dr[7] \|= 0x400; /* must be one */
731
732	pVMCB->guest.u64DR7 = pCtx->dr[7];
733	pVMCB->guest.u64DR6 = pCtx->dr[6];
734
735	/* Sync the debug state now if any breakpoint is armed. */
736	if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK\|X86_DR7_GD))
737	&& !CPUMIsGuestDebugStateActive(pVM)
738	&& !DBGFIsStepping(pVM))
739	{
740	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
741
742	/* Disable drx move intercepts. */
743	pVMCB->ctrl.u16InterceptRdDRx = 0;
744	pVMCB->ctrl.u16InterceptWrDRx = 0;
745
746	/* Save the host and load the guest debug state. */
747	int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
748	AssertRC(rc);
749	}
750	}
751
752	/* EIP, ESP and EFLAGS */
753	pVMCB->guest.u64RIP = pCtx->rip;
754	pVMCB->guest.u64RSP = pCtx->rsp;
755	pVMCB->guest.u64RFlags = pCtx->eflags.u32;
756
757	/* Set CPL */
758	pVMCB->guest.u8CPL = pCtx->csHid.Attr.n.u2Dpl;
759
760	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
761	pVMCB->guest.u64RAX = pCtx->rax;
762
763	/* vmrun will fail without MSR_K6_EFER_SVME. */
764	pVMCB->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
765
766	/* 64 bits guest mode? */
767	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
768	{
769	#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
770	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
771	#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
772	pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
773	#else
774	# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
775	if (!pVM->hwaccm.s.fAllow64BitGuests)
776	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
777	# endif
778	pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun64;
779	#endif
780	/* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
781	pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
782	pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
783	}
784	else
785	{
786	/* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
787	pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
788
789	pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun;
790	}
791
792	/* TSC offset. */
793	if (TMCpuTickCanUseRealTSC(pVM, &pVMCB->ctrl.u64TSCOffset))
794	{
795	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
796	pVMCB->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
797	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
798	}
799	else
800	{
801	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
802	pVMCB->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
803	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
804	}
805
806	/* Sync the various msrs for 64 bits mode. */
807	pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
808	pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
809	pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
810	pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
811	pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
812
813	#ifdef DEBUG
814	/* Intercept X86_XCPT_DB if stepping is enabled */
815	if (DBGFIsStepping(pVM))
816	pVMCB->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_DB);
817	else
818	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_DB);
819	#endif
820
821	/* Done. */
822	pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
823
824	return VINF_SUCCESS;
825	}
826
827
828	/**
829	* Runs guest code in an AMD-V VM.
830	*
831	* @returns VBox status code.
832	* @param pVM The VM to operate on.
833	* @param pVCpu The VM CPU to operate on.
834	* @param pCtx Guest context
835	*/
836	VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
837	{
838	int rc = VINF_SUCCESS;
839	uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
840	SVM_VMCB *pVMCB;
841	bool fSyncTPR = false;
842	unsigned cResume = 0;
843	uint8_t u8LastVTPR;
844	PHWACCM_CPUINFO pCpu = 0;
845	#ifdef VBOX_STRICT
846	RTCPUID idCpuCheck;
847	#endif
848
849	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
850
851	pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
852	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
853
854	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
855	*/
856	ResumeExecution:
857	Assert(!HWACCMR0SuspendPending());
858
859	/* Safety precaution; looping for too long here can have a very bad effect on the host */
860	if (++cResume > HWACCM_MAX_RESUME_LOOPS)
861	{
862	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
863	rc = VINF_EM_RAW_INTERRUPT;
864	goto end;
865	}
866
867	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
868	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
869	{
870	Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
871	if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
872	{
873	/* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
874	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
875	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
876	* break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
877	*/
878	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
879	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
880	pVMCB->ctrl.u64IntShadow = 0;
881	}
882	}
883	else
884	{
885	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
886	pVMCB->ctrl.u64IntShadow = 0;
887	}
888
889	/* Check for pending actions that force us to go back to ring 3. */
890	#ifdef DEBUG
891	/* Intercept X86_XCPT_DB if stepping is enabled */
892	if (!DBGFIsStepping(pVM))
893	#endif
894	{
895	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
896	{
897	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
898	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
899	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
900	rc = VINF_EM_RAW_TO_R3;
901	goto end;
902	}
903	}
904
905	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
906	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
907	{
908	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
909	rc = VINF_EM_PENDING_REQUEST;
910	goto end;
911	}
912
913	/* When external interrupts are pending, we should exit the VM when IF is set. */
914	/* Note! After VM_FF_INHIBIT_INTERRUPTS check!!! */
915	rc = SVMR0CheckPendingInterrupt(pVM, pVCpu, pVMCB, pCtx);
916	if (RT_FAILURE(rc))
917	{
918	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
919	goto end;
920	}
921
922	/* TPR caching using CR8 is only available in 64 bits mode */
923	/* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
924	/* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! */
925	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
926	{
927	bool fPending;
928
929	/* TPR caching in CR8 */
930	int rc = PDMApicGetTPR(pVM, &u8LastVTPR, &fPending);
931	AssertRC(rc);
932	pVMCB->ctrl.IntCtrl.n.u8VTPR = u8LastVTPR;
933
934	if (fPending)
935	{
936	/* A TPR change could activate a pending interrupt, so catch cr8 writes. */
937	pVMCB->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
938	}
939	else
940	/* No interrupts are pending, so we don't need to be explicitely notified.
941	* There are enough world switches for detecting pending interrupts.
942	*/
943	pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
944
945	fSyncTPR = !fPending;
946	}
947
948	/* All done! Let's start VM execution. */
949	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, x);
950
951	/* Enable nested paging if necessary (disabled each time after #VMEXIT). */
952	pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
953
954	#ifdef LOG_ENABLED
955	pCpu = HWACCMR0GetCurrentCpu();
956	if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
957	\|\| pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
958	{
959	if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
960	Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
961	else
962	Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
963	}
964	if (pCpu->fFlushTLB)
965	Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
966	#endif
967
968	/*
969	* NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
970	* (until the actual world switch)
971	*/
972
973	#ifdef VBOX_STRICT
974	idCpuCheck = RTMpCpuId();
975	#endif
976
977	/* Load the guest state; must be here as it sets up the shadow cr0 for lazy fpu syncing! */
978	rc = SVMR0LoadGuestState(pVM, pVCpu, pCtx);
979	if (rc != VINF_SUCCESS)
980	{
981	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
982	goto end;
983	}
984
985	pCpu = HWACCMR0GetCurrentCpu();
986	/* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
987	/* Note that this can happen both for start and resume due to long jumps back to ring 3. */
988	if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
989	/* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
990	\|\| pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
991	{
992	/* Force a TLB flush on VM entry. */
993	pVCpu->hwaccm.s.fForceTLBFlush = true;
994	}
995	else
996	Assert(!pCpu->fFlushTLB \|\| pVM->hwaccm.s.svm.fAlwaysFlushTLB);
997
998	pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
999
1000	/* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1001	if ( pVCpu->hwaccm.s.fForceTLBFlush
1002	&& !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
1003	{
1004	if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1005	\|\| pCpu->fFlushTLB)
1006	{
1007	pCpu->fFlushTLB = false;
1008	pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1009	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
1010	pCpu->cTLBFlushes++;
1011	}
1012	else
1013	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1014
1015	pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1016	pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1017	}
1018	else
1019	{
1020	Assert(!pCpu->fFlushTLB \|\| pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1021
1022	/* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
1023	if (!pCpu->uCurrentASID \|\| !pVCpu->hwaccm.s.uCurrentASID)
1024	pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
1025
1026	Assert(!pVM->hwaccm.s.svm.fAlwaysFlushTLB \|\| pVCpu->hwaccm.s.fForceTLBFlush);
1027	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVCpu->hwaccm.s.fForceTLBFlush;
1028	}
1029	AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1030	AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1031	AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1032	pVMCB->ctrl.TLBCtrl.n.u32ASID = pVCpu->hwaccm.s.uCurrentASID;
1033
1034	#ifdef VBOX_WITH_STATISTICS
1035	if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
1036	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1037	else
1038	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1039	#endif
1040
1041	/* In case we execute a goto ResumeExecution later on. */
1042	pVCpu->hwaccm.s.fResumeVM = true;
1043	pVCpu->hwaccm.s.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
1044
1045	Assert(sizeof(pVCpu->hwaccm.s.svm.pVMCBPhys) == 8);
1046	Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
1047	Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
1048	Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
1049	Assert(pVMCB->ctrl.u64LBRVirt == 0);
1050
1051	#ifdef VBOX_STRICT
1052	Assert(idCpuCheck == RTMpCpuId());
1053	#endif
1054	TMNotifyStartOfExecution(pVM);
1055	pVCpu->hwaccm.s.svm.pfnVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu);
1056	TMNotifyEndOfExecution(pVM);
1057	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, x);
1058
1059	/*
1060	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1061	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1062	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1063	*/
1064
1065	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, x);
1066
1067	/* Reason for the VM exit */
1068	exitCode = pVMCB->ctrl.u64ExitCode;
1069
1070	if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
1071	{
1072	HWACCMDumpRegs(pVM, pCtx);
1073	#ifdef DEBUG
1074	Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
1075	Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
1076	Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
1077	Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
1078	Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
1079	Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
1080	Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
1081	Log(("ctrl.u64IOPMPhysAddr %RX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
1082	Log(("ctrl.u64MSRPMPhysAddr %RX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
1083	Log(("ctrl.u64TSCOffset %RX64\n", pVMCB->ctrl.u64TSCOffset));
1084
1085	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
1086	Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
1087	Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
1088	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
1089
1090	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
1091	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
1092	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
1093	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
1094	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
1095	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
1096	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
1097	Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
1098	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
1099	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
1100
1101	Log(("ctrl.u64IntShadow %RX64\n", pVMCB->ctrl.u64IntShadow));
1102	Log(("ctrl.u64ExitCode %RX64\n", pVMCB->ctrl.u64ExitCode));
1103	Log(("ctrl.u64ExitInfo1 %RX64\n", pVMCB->ctrl.u64ExitInfo1));
1104	Log(("ctrl.u64ExitInfo2 %RX64\n", pVMCB->ctrl.u64ExitInfo2));
1105	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
1106	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
1107	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
1108	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
1109	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
1110	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
1111	Log(("ctrl.NestedPaging %RX64\n", pVMCB->ctrl.NestedPaging.au64));
1112	Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
1113	Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
1114	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
1115	Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
1116	Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
1117	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
1118
1119	Log(("ctrl.u64NestedPagingCR3 %RX64\n", pVMCB->ctrl.u64NestedPagingCR3));
1120	Log(("ctrl.u64LBRVirt %RX64\n", pVMCB->ctrl.u64LBRVirt));
1121
1122	Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
1123	Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1124	Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1125	Log(("guest.CS.u64Base %RX64\n", pVMCB->guest.CS.u64Base));
1126	Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1127	Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1128	Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1129	Log(("guest.DS.u64Base %RX64\n", pVMCB->guest.DS.u64Base));
1130	Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1131	Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1132	Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1133	Log(("guest.ES.u64Base %RX64\n", pVMCB->guest.ES.u64Base));
1134	Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1135	Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1136	Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1137	Log(("guest.FS.u64Base %RX64\n", pVMCB->guest.FS.u64Base));
1138	Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1139	Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1140	Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1141	Log(("guest.GS.u64Base %RX64\n", pVMCB->guest.GS.u64Base));
1142
1143	Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1144	Log(("guest.GDTR.u64Base %RX64\n", pVMCB->guest.GDTR.u64Base));
1145
1146	Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1147	Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1148	Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1149	Log(("guest.LDTR.u64Base %RX64\n", pVMCB->guest.LDTR.u64Base));
1150
1151	Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1152	Log(("guest.IDTR.u64Base %RX64\n", pVMCB->guest.IDTR.u64Base));
1153
1154	Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1155	Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1156	Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1157	Log(("guest.TR.u64Base %RX64\n", pVMCB->guest.TR.u64Base));
1158
1159	Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1160	Log(("guest.u64CR0 %RX64\n", pVMCB->guest.u64CR0));
1161	Log(("guest.u64CR2 %RX64\n", pVMCB->guest.u64CR2));
1162	Log(("guest.u64CR3 %RX64\n", pVMCB->guest.u64CR3));
1163	Log(("guest.u64CR4 %RX64\n", pVMCB->guest.u64CR4));
1164	Log(("guest.u64DR6 %RX64\n", pVMCB->guest.u64DR6));
1165	Log(("guest.u64DR7 %RX64\n", pVMCB->guest.u64DR7));
1166
1167	Log(("guest.u64RIP %RX64\n", pVMCB->guest.u64RIP));
1168	Log(("guest.u64RSP %RX64\n", pVMCB->guest.u64RSP));
1169	Log(("guest.u64RAX %RX64\n", pVMCB->guest.u64RAX));
1170	Log(("guest.u64RFlags %RX64\n", pVMCB->guest.u64RFlags));
1171
1172	Log(("guest.u64SysEnterCS %RX64\n", pVMCB->guest.u64SysEnterCS));
1173	Log(("guest.u64SysEnterEIP %RX64\n", pVMCB->guest.u64SysEnterEIP));
1174	Log(("guest.u64SysEnterESP %RX64\n", pVMCB->guest.u64SysEnterESP));
1175
1176	Log(("guest.u64EFER %RX64\n", pVMCB->guest.u64EFER));
1177	Log(("guest.u64STAR %RX64\n", pVMCB->guest.u64STAR));
1178	Log(("guest.u64LSTAR %RX64\n", pVMCB->guest.u64LSTAR));
1179	Log(("guest.u64CSTAR %RX64\n", pVMCB->guest.u64CSTAR));
1180	Log(("guest.u64SFMASK %RX64\n", pVMCB->guest.u64SFMASK));
1181	Log(("guest.u64KernelGSBase %RX64\n", pVMCB->guest.u64KernelGSBase));
1182	Log(("guest.u64GPAT %RX64\n", pVMCB->guest.u64GPAT));
1183	Log(("guest.u64DBGCTL %RX64\n", pVMCB->guest.u64DBGCTL));
1184	Log(("guest.u64BR_FROM %RX64\n", pVMCB->guest.u64BR_FROM));
1185	Log(("guest.u64BR_TO %RX64\n", pVMCB->guest.u64BR_TO));
1186	Log(("guest.u64LASTEXCPFROM %RX64\n", pVMCB->guest.u64LASTEXCPFROM));
1187	Log(("guest.u64LASTEXCPTO %RX64\n", pVMCB->guest.u64LASTEXCPTO));
1188
1189	#endif
1190	rc = VERR_SVM_UNABLE_TO_START_VM;
1191	goto end;
1192	}
1193
1194	/* Let's first sync back eip, esp, and eflags. */
1195	pCtx->rip = pVMCB->guest.u64RIP;
1196	pCtx->rsp = pVMCB->guest.u64RSP;
1197	pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1198	/* eax is saved/restore across the vmrun instruction */
1199	pCtx->rax = pVMCB->guest.u64RAX;
1200
1201	pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
1202
1203	/* Can be updated behind our back in the nested paging case. */
1204	pCtx->cr2 = pVMCB->guest.u64CR2;
1205
1206	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1207	SVM_READ_SELREG(SS, ss);
1208	SVM_READ_SELREG(CS, cs);
1209	SVM_READ_SELREG(DS, ds);
1210	SVM_READ_SELREG(ES, es);
1211	SVM_READ_SELREG(FS, fs);
1212	SVM_READ_SELREG(GS, gs);
1213
1214	/*
1215	* System MSRs
1216	*/
1217	pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1218	pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1219	pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1220
1221	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1222	SVM_READ_SELREG(LDTR, ldtr);
1223	SVM_READ_SELREG(TR, tr);
1224
1225	pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1226	pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1227
1228	pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1229	pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1230
1231	/* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1232	/* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1233	if ( pVM->hwaccm.s.fNestedPaging
1234	&& pCtx->cr3 != pVMCB->guest.u64CR3)
1235	{
1236	CPUMSetGuestCR3(pVM, pVMCB->guest.u64CR3);
1237	PGMUpdateCR3(pVM, pVMCB->guest.u64CR3);
1238	}
1239
1240	/* Note! NOW IT'S SAFE FOR LOGGING! */
1241
1242	/* Take care of instruction fusing (sti, mov ss) (see 15.20.5 Interrupt Shadows) */
1243	if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1244	{
1245	Log(("uInterruptState %x rip=%RGv\n", pVMCB->ctrl.u64IntShadow, (RTGCPTR)pCtx->rip));
1246	EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1247	}
1248	else
1249	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1250
1251	Log2(("exitCode = %x\n", exitCode));
1252
1253	/* Sync back DR6 as it could have been changed by hitting breakpoints. */
1254	pCtx->dr[6] = pVMCB->guest.u64DR6;
1255	/* DR7.GD can be cleared by debug exceptions, so sync it back as well. */
1256	pCtx->dr[7] = pVMCB->guest.u64DR7;
1257
1258	/* Check if an injected event was interrupted prematurely. */
1259	pVCpu->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1260	if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1261	&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1262	{
1263	Log(("Pending inject %RX64 at %RGv exit=%08x\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitCode));
1264
1265	#ifdef LOG_ENABLED
1266	SVM_EVENT Event;
1267	Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
1268
1269	if ( exitCode == SVM_EXIT_EXCEPTION_E
1270	&& Event.n.u8Vector == 0xE)
1271	{
1272	Log(("Double fault!\n"));
1273	}
1274	#endif
1275
1276	pVCpu->hwaccm.s.Event.fPending = true;
1277	/* Error code present? (redundant) */
1278	if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1279	{
1280	pVCpu->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1281	}
1282	else
1283	pVCpu->hwaccm.s.Event.errCode = 0;
1284	}
1285	#ifdef VBOX_WITH_STATISTICS
1286	if (exitCode == SVM_EXIT_NPF)
1287	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
1288	else
1289	STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1290	#endif
1291
1292	if (fSyncTPR)
1293	{
1294	rc = PDMApicSetTPR(pVM, pVMCB->ctrl.IntCtrl.n.u8VTPR);
1295	AssertRC(rc);
1296	}
1297
1298	/* Deal with the reason of the VM-exit. */
1299	switch (exitCode)
1300	{
1301	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1302	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1303	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1304	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1305	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1306	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1307	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1308	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1309	{
1310	/* Pending trap. */
1311	SVM_EVENT Event;
1312	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1313
1314	Log2(("Hardware/software interrupt %d\n", vector));
1315	switch (vector)
1316	{
1317	case X86_XCPT_DB:
1318	{
1319	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
1320
1321	/* Note that we don't support guest and host-initiated debugging at the same time. */
1322	Assert(DBGFIsStepping(pVM));
1323
1324	rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
1325	if (rc == VINF_EM_RAW_GUEST_TRAP)
1326	{
1327	Log(("Trap %x (debug) at %016RX64\n", vector, pCtx->rip));
1328
1329	/* Reinject the exception. */
1330	Event.au64[0] = 0;
1331	Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
1332	Event.n.u1Valid = 1;
1333	Event.n.u8Vector = X86_XCPT_DB;
1334
1335	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1336
1337	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1338	goto ResumeExecution;
1339	}
1340	/* Return to ring 3 to deal with the debug exit code. */
1341	break;
1342	}
1343
1344	case X86_XCPT_NM:
1345	{
1346	Log(("#NM fault at %RGv\n", (RTGCPTR)pCtx->rip));
1347
1348	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1349	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1350	rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
1351	if (rc == VINF_SUCCESS)
1352	{
1353	Assert(CPUMIsGuestFPUStateActive(pVCpu));
1354	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
1355
1356	/* Continue execution. */
1357	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1358	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1359
1360	goto ResumeExecution;
1361	}
1362
1363	Log(("Forward #NM fault to the guest\n"));
1364	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
1365
1366	Event.au64[0] = 0;
1367	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1368	Event.n.u1Valid = 1;
1369	Event.n.u8Vector = X86_XCPT_NM;
1370
1371	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1372	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1373	goto ResumeExecution;
1374	}
1375
1376	case X86_XCPT_PF: /* Page fault */
1377	{
1378	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1379	RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1380
1381	#ifdef DEBUG
1382	if (pVM->hwaccm.s.fNestedPaging)
1383	{ /* A genuine pagefault.
1384	* Forward the trap to the guest by injecting the exception and resuming execution.
1385	*/
1386	Log(("Guest page fault at %RGv cr2=%RGv error code %x rsp=%RGv\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
1387	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1388
1389	/* Now we must update CR2. */
1390	pCtx->cr2 = uFaultAddress;
1391
1392	Event.au64[0] = 0;
1393	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1394	Event.n.u1Valid = 1;
1395	Event.n.u8Vector = X86_XCPT_PF;
1396	Event.n.u1ErrorCodeValid = 1;
1397	Event.n.u32ErrorCode = errCode;
1398
1399	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1400
1401	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1402	goto ResumeExecution;
1403	}
1404	#endif
1405	Assert(!pVM->hwaccm.s.fNestedPaging);
1406
1407	Log2(("Page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1408	/* Exit qualification contains the linear address of the page fault. */
1409	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1410	TRPMSetErrorCode(pVM, errCode);
1411	TRPMSetFaultAddress(pVM, uFaultAddress);
1412
1413	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1414	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1415	Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1416	if (rc == VINF_SUCCESS)
1417	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1418	Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1419	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1420
1421	TRPMResetTrap(pVM);
1422
1423	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1424	goto ResumeExecution;
1425	}
1426	else
1427	if (rc == VINF_EM_RAW_GUEST_TRAP)
1428	{ /* A genuine pagefault.
1429	* Forward the trap to the guest by injecting the exception and resuming execution.
1430	*/
1431	Log2(("Forward page fault to the guest\n"));
1432	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1433	/* The error code might have been changed. */
1434	errCode = TRPMGetErrorCode(pVM);
1435
1436	TRPMResetTrap(pVM);
1437
1438	/* Now we must update CR2. */
1439	pCtx->cr2 = uFaultAddress;
1440
1441	Event.au64[0] = 0;
1442	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1443	Event.n.u1Valid = 1;
1444	Event.n.u8Vector = X86_XCPT_PF;
1445	Event.n.u1ErrorCodeValid = 1;
1446	Event.n.u32ErrorCode = errCode;
1447
1448	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1449
1450	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1451	goto ResumeExecution;
1452	}
1453	#ifdef VBOX_STRICT
1454	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1455	LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
1456	#endif
1457	/* Need to go back to the recompiler to emulate the instruction. */
1458	TRPMResetTrap(pVM);
1459	break;
1460	}
1461
1462	case X86_XCPT_MF: /* Floating point exception. */
1463	{
1464	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
1465	if (!(pCtx->cr0 & X86_CR0_NE))
1466	{
1467	/* old style FPU error reporting needs some extra work. */
1468	/** @todo don't fall back to the recompiler, but do it manually. */
1469	rc = VINF_EM_RAW_EMULATE_INSTR;
1470	break;
1471	}
1472	Log(("Trap %x at %RGv\n", vector, (RTGCPTR)pCtx->rip));
1473
1474	Event.au64[0] = 0;
1475	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1476	Event.n.u1Valid = 1;
1477	Event.n.u8Vector = X86_XCPT_MF;
1478
1479	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1480
1481	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1482	goto ResumeExecution;
1483	}
1484
1485	#ifdef VBOX_STRICT
1486	case X86_XCPT_GP: /* General protection failure exception.*/
1487	case X86_XCPT_UD: /* Unknown opcode exception. */
1488	case X86_XCPT_DE: /* Divide error. */
1489	case X86_XCPT_SS: /* Stack segment exception. */
1490	case X86_XCPT_NP: /* Segment not present exception. */
1491	{
1492	Event.au64[0] = 0;
1493	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1494	Event.n.u1Valid = 1;
1495	Event.n.u8Vector = vector;
1496
1497	switch(vector)
1498	{
1499	case X86_XCPT_GP:
1500	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
1501	Event.n.u1ErrorCodeValid = 1;
1502	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1503	break;
1504	case X86_XCPT_DE:
1505	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
1506	break;
1507	case X86_XCPT_UD:
1508	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
1509	break;
1510	case X86_XCPT_SS:
1511	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
1512	Event.n.u1ErrorCodeValid = 1;
1513	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1514	break;
1515	case X86_XCPT_NP:
1516	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
1517	Event.n.u1ErrorCodeValid = 1;
1518	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1519	break;
1520	}
1521	Log(("Trap %x at %RGv esi=%x\n", vector, (RTGCPTR)pCtx->rip, pCtx->esi));
1522	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1523
1524	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1525	goto ResumeExecution;
1526	}
1527	#endif
1528	default:
1529	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1530	rc = VERR_EM_INTERNAL_ERROR;
1531	break;
1532
1533	} /* switch (vector) */
1534	break;
1535	}
1536
1537	case SVM_EXIT_NPF:
1538	{
1539	/* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1540	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1541	RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1542	PGMMODE enmShwPagingMode;
1543
1544	Assert(pVM->hwaccm.s.fNestedPaging);
1545	Log(("Nested page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1546	/* Exit qualification contains the linear address of the page fault. */
1547	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1548	TRPMSetErrorCode(pVM, errCode);
1549	TRPMSetFaultAddress(pVM, uFaultAddress);
1550
1551	/* Handle the pagefault trap for the nested shadow table. */
1552	#if HC_ARCH_BITS == 32
1553	if (CPUMIsGuestInLongModeEx(pCtx))
1554	enmShwPagingMode = PGMMODE_AMD64_NX;
1555	else
1556	#endif
1557	enmShwPagingMode = PGMGetHostMode(pVM);
1558
1559	rc = PGMR0Trap0eHandlerNestedPaging(pVM, enmShwPagingMode, errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1560	Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1561	if (rc == VINF_SUCCESS)
1562	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1563	Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1564	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1565
1566	TRPMResetTrap(pVM);
1567
1568	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1569	goto ResumeExecution;
1570	}
1571
1572	#ifdef VBOX_STRICT
1573	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1574	LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
1575	#endif
1576	/* Need to go back to the recompiler to emulate the instruction. */
1577	TRPMResetTrap(pVM);
1578	break;
1579	}
1580
1581	case SVM_EXIT_VINTR:
1582	/* A virtual interrupt is about to be delivered, which means IF=1. */
1583	Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1584	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1585	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1586	goto ResumeExecution;
1587
1588	case SVM_EXIT_FERR_FREEZE:
1589	case SVM_EXIT_INTR:
1590	case SVM_EXIT_NMI:
1591	case SVM_EXIT_SMI:
1592	case SVM_EXIT_INIT:
1593	/* External interrupt; leave to allow it to be dispatched again. */
1594	rc = VINF_EM_RAW_INTERRUPT;
1595	break;
1596
1597	case SVM_EXIT_WBINVD:
1598	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1599	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
1600	/* Skip instruction and continue directly. */
1601	pCtx->rip += 2; /* Note! hardcoded opcode size! */
1602	/* Continue execution.*/
1603	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1604	goto ResumeExecution;
1605
1606	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1607	{
1608	Log2(("SVM: Cpuid at %RGv for %x\n", (RTGCPTR)pCtx->rip, pCtx->eax));
1609	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
1610	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1611	if (rc == VINF_SUCCESS)
1612	{
1613	/* Update EIP and continue execution. */
1614	pCtx->rip += 2; /* Note! hardcoded opcode size! */
1615	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1616	goto ResumeExecution;
1617	}
1618	AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
1619	rc = VINF_EM_RAW_EMULATE_INSTR;
1620	break;
1621	}
1622
1623	case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1624	{
1625	Log2(("SVM: Rdtsc\n"));
1626	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1627	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1628	if (rc == VINF_SUCCESS)
1629	{
1630	/* Update EIP and continue execution. */
1631	pCtx->rip += 2; /* Note! hardcoded opcode size! */
1632	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1633	goto ResumeExecution;
1634	}
1635	AssertMsgFailed(("EMU: rdtsc failed with %Rrc\n", rc));
1636	rc = VINF_EM_RAW_EMULATE_INSTR;
1637	break;
1638	}
1639
1640	case SVM_EXIT_RDTSCP: /* Guest software attempted to execute RDTSCP. */
1641	{
1642	Log2(("SVM: Rdtscp\n"));
1643	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1644	rc = EMInterpretRdtscp(pVM, pCtx);
1645	if (rc == VINF_SUCCESS)
1646	{
1647	/* Update EIP and continue execution. */
1648	pCtx->rip += 3; /* Note! hardcoded opcode size! */
1649	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1650	goto ResumeExecution;
1651	}
1652	AssertMsgFailed(("EMU: rdtscp failed with %Rrc\n", rc));
1653	rc = VINF_EM_RAW_EMULATE_INSTR;
1654	break;
1655	}
1656
1657	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1658	{
1659	Log2(("SVM: invlpg\n"));
1660	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
1661
1662	Assert(!pVM->hwaccm.s.fNestedPaging);
1663
1664	/* Truly a pita. Why can't SVM give the same information as VT-x? */
1665	rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1666	if (rc == VINF_SUCCESS)
1667	{
1668	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushPageInvlpg);
1669	goto ResumeExecution; /* eip already updated */
1670	}
1671	break;
1672	}
1673
1674	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1675	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1676	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1677	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1678	{
1679	uint32_t cbSize;
1680
1681	Log2(("SVM: %RGv mov cr%d, \n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
1682	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[exitCode - SVM_EXIT_WRITE_CR0]);
1683	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1684
1685	switch (exitCode - SVM_EXIT_WRITE_CR0)
1686	{
1687	case 0:
1688	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1689	break;
1690	case 2:
1691	break;
1692	case 3:
1693	Assert(!pVM->hwaccm.s.fNestedPaging);
1694	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1695	break;
1696	case 4:
1697	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1698	break;
1699	case 8:
1700	break;
1701	default:
1702	AssertFailed();
1703	}
1704	/* Check if a sync operation is pending. */
1705	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1706	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1707	{
1708	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1709	AssertRC(rc);
1710
1711	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBCRxChange);
1712
1713	/* Must be set by PGMSyncCR3 */
1714	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PROTECTED \|\| pVCpu->hwaccm.s.fForceTLBFlush);
1715	}
1716	if (rc == VINF_SUCCESS)
1717	{
1718	/* EIP has been updated already. */
1719
1720	/* Only resume if successful. */
1721	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1722	goto ResumeExecution;
1723	}
1724	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1725	break;
1726	}
1727
1728	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1729	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1730	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1731	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1732	{
1733	uint32_t cbSize;
1734
1735	Log2(("SVM: %RGv mov x, cr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
1736	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[exitCode - SVM_EXIT_WRITE_CR0]);
1737	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1738	if (rc == VINF_SUCCESS)
1739	{
1740	/* EIP has been updated already. */
1741
1742	/* Only resume if successful. */
1743	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1744	goto ResumeExecution;
1745	}
1746	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1747	break;
1748	}
1749
1750	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1751	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1752	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1753	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1754	{
1755	uint32_t cbSize;
1756
1757	Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
1758	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
1759
1760	if (!DBGFIsStepping(pVM))
1761	{
1762	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
1763
1764	/* Disable drx move intercepts. */
1765	pVMCB->ctrl.u16InterceptRdDRx = 0;
1766	pVMCB->ctrl.u16InterceptWrDRx = 0;
1767
1768	/* Save the host and load the guest debug state. */
1769	rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
1770	AssertRC(rc);
1771
1772	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1773	goto ResumeExecution;
1774	}
1775
1776	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1777	if (rc == VINF_SUCCESS)
1778	{
1779	/* EIP has been updated already. */
1780	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_DEBUG;
1781
1782	/* Only resume if successful. */
1783	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1784	goto ResumeExecution;
1785	}
1786	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1787	break;
1788	}
1789
1790	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1791	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1792	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1793	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1794	{
1795	uint32_t cbSize;
1796
1797	Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
1798	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
1799
1800	if (!DBGFIsStepping(pVM))
1801	{
1802	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
1803
1804	/* Disable drx move intercepts. */
1805	pVMCB->ctrl.u16InterceptRdDRx = 0;
1806	pVMCB->ctrl.u16InterceptWrDRx = 0;
1807
1808	/* Save the host and load the guest debug state. */
1809	rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
1810	AssertRC(rc);
1811
1812	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1813	goto ResumeExecution;
1814	}
1815
1816	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1817	if (rc == VINF_SUCCESS)
1818	{
1819	/* EIP has been updated already. */
1820
1821	/* Only resume if successful. */
1822	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1823	goto ResumeExecution;
1824	}
1825	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1826	break;
1827	}
1828
1829	/* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1830	case SVM_EXIT_IOIO: /* I/O instruction. */
1831	{
1832	SVM_IOIO_EXIT IoExitInfo;
1833	uint32_t uIOSize, uAndVal;
1834
1835	IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1836
1837	/** @todo could use a lookup table here */
1838	if (IoExitInfo.n.u1OP8)
1839	{
1840	uIOSize = 1;
1841	uAndVal = 0xff;
1842	}
1843	else
1844	if (IoExitInfo.n.u1OP16)
1845	{
1846	uIOSize = 2;
1847	uAndVal = 0xffff;
1848	}
1849	else
1850	if (IoExitInfo.n.u1OP32)
1851	{
1852	uIOSize = 4;
1853	uAndVal = 0xffffffff;
1854	}
1855	else
1856	{
1857	AssertFailed(); /* should be fatal. */
1858	rc = VINF_EM_RAW_EMULATE_INSTR;
1859	break;
1860	}
1861
1862	if (IoExitInfo.n.u1STR)
1863	{
1864	/* ins/outs */
1865	DISCPUSTATE Cpu;
1866
1867	/* Disassemble manually to deal with segment prefixes. */
1868	rc = EMInterpretDisasOne(pVM, CPUMCTX2CORE(pCtx), &Cpu, NULL);
1869	if (rc == VINF_SUCCESS)
1870	{
1871	if (IoExitInfo.n.u1Type == 0)
1872	{
1873	Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1874	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
1875	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, Cpu.prefix, uIOSize);
1876	}
1877	else
1878	{
1879	Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1880	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
1881	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, Cpu.prefix, uIOSize);
1882	}
1883	}
1884	else
1885	rc = VINF_EM_RAW_EMULATE_INSTR;
1886	}
1887	else
1888	{
1889	/* normal in/out */
1890	Assert(!IoExitInfo.n.u1REP);
1891
1892	if (IoExitInfo.n.u1Type == 0)
1893	{
1894	Log2(("IOMIOPortWrite %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1895	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
1896	rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1897	}
1898	else
1899	{
1900	uint32_t u32Val = 0;
1901
1902	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
1903	rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1904	if (IOM_SUCCESS(rc))
1905	{
1906	/* Write back to the EAX register. */
1907	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1908	Log2(("IOMIOPortRead %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1909	}
1910	}
1911	}
1912	/*
1913	* Handled the I/O return codes.
1914	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1915	*/
1916	if (IOM_SUCCESS(rc))
1917	{
1918	/* Update EIP and continue execution. */
1919	pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1920	if (RT_LIKELY(rc == VINF_SUCCESS))
1921	{
1922	/* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
1923	if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
1924	{
1925	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
1926	for (unsigned i=0;i<4;i++)
1927	{
1928	unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
1929
1930	if ( (IoExitInfo.n.u16Port >= pCtx->dr[i] && IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen)
1931	&& (pCtx->dr[7] & (X86_DR7_L(i) \| X86_DR7_G(i)))
1932	&& (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
1933	{
1934	SVM_EVENT Event;
1935
1936	Assert(CPUMIsGuestDebugStateActive(pVM));
1937
1938	/* Clear all breakpoint status flags and set the one we just hit. */
1939	pCtx->dr[6] &= ~(X86_DR6_B0\|X86_DR6_B1\|X86_DR6_B2\|X86_DR6_B3);
1940	pCtx->dr[6] \|= (uint64_t)RT_BIT(i);
1941
1942	/* Note: AMD64 Architecture Programmer's Manual 13.1:
1943	* Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
1944	* the contents have been read.
1945	*/
1946	pVMCB->guest.u64DR6 = pCtx->dr[6];
1947
1948	/* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
1949	pCtx->dr[7] &= ~X86_DR7_GD;
1950
1951	/* Paranoia. */
1952	pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
1953	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
1954	pCtx->dr[7] \|= 0x400; /* must be one */
1955
1956	pVMCB->guest.u64DR7 = pCtx->dr[7];
1957
1958	/* Inject the exception. */
1959	Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
1960
1961	Event.au64[0] = 0;
1962	Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
1963	Event.n.u1Valid = 1;
1964	Event.n.u8Vector = X86_XCPT_DB;
1965
1966	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1967
1968	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1969	goto ResumeExecution;
1970	}
1971	}
1972	}
1973
1974	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1975	goto ResumeExecution;
1976	}
1977	Log2(("EM status from IO at %RGv %x size %d: %Rrc\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
1978	break;
1979	}
1980
1981	#ifdef VBOX_STRICT
1982	if (rc == VINF_IOM_HC_IOPORT_READ)
1983	Assert(IoExitInfo.n.u1Type != 0);
1984	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1985	Assert(IoExitInfo.n.u1Type == 0);
1986	else
1987	AssertMsg(RT_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
1988	#endif
1989	Log2(("Failed IO at %RGv %x size %d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1990	break;
1991	}
1992
1993	case SVM_EXIT_HLT:
1994	/** Check if external interrupts are pending; if so, don't switch back. */
1995	pCtx->rip++; /* skip hlt */
1996	if ( pCtx->eflags.Bits.u1IF
1997	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1998	goto ResumeExecution;
1999
2000	rc = VINF_EM_HALT;
2001	break;
2002
2003	case SVM_EXIT_RSM:
2004	case SVM_EXIT_INVLPGA:
2005	case SVM_EXIT_VMRUN:
2006	case SVM_EXIT_VMMCALL:
2007	case SVM_EXIT_VMLOAD:
2008	case SVM_EXIT_VMSAVE:
2009	case SVM_EXIT_STGI:
2010	case SVM_EXIT_CLGI:
2011	case SVM_EXIT_SKINIT:
2012	{
2013	/* Unsupported instructions. */
2014	SVM_EVENT Event;
2015
2016	Event.au64[0] = 0;
2017	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2018	Event.n.u1Valid = 1;
2019	Event.n.u8Vector = X86_XCPT_UD;
2020
2021	Log(("Forced #UD trap at %RGv\n", (RTGCPTR)pCtx->rip));
2022	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
2023
2024	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2025	goto ResumeExecution;
2026	}
2027
2028	/* Emulate in ring 3. */
2029	case SVM_EXIT_MSR:
2030	{
2031	uint32_t cbSize;
2032
2033	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2034	Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
2035	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
2036	if (rc == VINF_SUCCESS)
2037	{
2038	/* EIP has been updated already. */
2039
2040	/* Only resume if successful. */
2041	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2042	goto ResumeExecution;
2043	}
2044	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
2045	break;
2046	}
2047
2048	case SVM_EXIT_MONITOR:
2049	case SVM_EXIT_RDPMC:
2050	case SVM_EXIT_PAUSE:
2051	case SVM_EXIT_MWAIT_UNCOND:
2052	case SVM_EXIT_MWAIT_ARMED:
2053	case SVM_EXIT_TASK_SWITCH: /* can change CR3; emulate */
2054	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2055	break;
2056
2057	case SVM_EXIT_SHUTDOWN:
2058	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2059	break;
2060
2061	case SVM_EXIT_IDTR_READ:
2062	case SVM_EXIT_GDTR_READ:
2063	case SVM_EXIT_LDTR_READ:
2064	case SVM_EXIT_TR_READ:
2065	case SVM_EXIT_IDTR_WRITE:
2066	case SVM_EXIT_GDTR_WRITE:
2067	case SVM_EXIT_LDTR_WRITE:
2068	case SVM_EXIT_TR_WRITE:
2069	case SVM_EXIT_CR0_SEL_WRITE:
2070	default:
2071	/* Unexpected exit codes. */
2072	rc = VERR_EM_INTERNAL_ERROR;
2073	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
2074	break;
2075	}
2076
2077	end:
2078
2079	/* Signal changes for the recompiler. */
2080	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
2081
2082	/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
2083	if (exitCode == SVM_EXIT_INTR)
2084	{
2085	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
2086	/* On the next entry we'll only sync the host context. */
2087	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
2088	}
2089	else
2090	{
2091	/* On the next entry we'll sync everything. */
2092	/** @todo we can do better than this */
2093	/* Not in the VINF_PGM_CHANGE_MODE though! */
2094	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
2095	}
2096
2097	/* translate into a less severe return code */
2098	if (rc == VERR_EM_INTERPRETER)
2099	rc = VINF_EM_RAW_EMULATE_INSTR;
2100
2101	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2102	return rc;
2103	}
2104
2105	/**
2106	* Enters the AMD-V session
2107	*
2108	* @returns VBox status code.
2109	* @param pVM The VM to operate on.
2110	* @param pVCpu The VM CPU to operate on.
2111	* @param pCpu CPU info struct
2112	*/
2113	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
2114	{
2115	Assert(pVM->hwaccm.s.svm.fSupported);
2116
2117	LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVCpu->hwaccm.s.idLastCpu, pVCpu->hwaccm.s.uCurrentASID));
2118	pVCpu->hwaccm.s.fResumeVM = false;
2119
2120	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
2121	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_LDTR;
2122
2123	return VINF_SUCCESS;
2124	}
2125
2126
2127	/**
2128	* Leaves the AMD-V session
2129	*
2130	* @returns VBox status code.
2131	* @param pVM The VM to operate on.
2132	* @param pVCpu The VM CPU to operate on.
2133	* @param pCtx CPU context
2134	*/
2135	VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2136	{
2137	SVM_VMCB pVMCB = (SVM_VMCB )pVCpu->hwaccm.s.svm.pVMCB;
2138
2139	Assert(pVM->hwaccm.s.svm.fSupported);
2140
2141	/* Save the guest debug state if necessary. */
2142	if (CPUMIsGuestDebugStateActive(pVM))
2143	{
2144	CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, false /* skip DR6 */);
2145
2146	/* Intercept all DRx reads and writes again. Changed later on. */
2147	pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
2148	pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
2149
2150	/* Resync the debug registers the next time. */
2151	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_DEBUG;
2152	}
2153	else
2154	Assert(pVMCB->ctrl.u16InterceptRdDRx == 0xFFFF && pVMCB->ctrl.u16InterceptWrDRx == 0xFFFF);
2155
2156	return VINF_SUCCESS;
2157	}
2158
2159
2160	static int svmR0InterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2161	{
2162	OP_PARAMVAL param1;
2163	RTGCPTR addr;
2164
2165	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2166	if(RT_FAILURE(rc))
2167	return VERR_EM_INTERPRETER;
2168
2169	switch(param1.type)
2170	{
2171	case PARMTYPE_IMMEDIATE:
2172	case PARMTYPE_ADDRESS:
2173	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
2174	return VERR_EM_INTERPRETER;
2175	addr = param1.val.val64;
2176	break;
2177
2178	default:
2179	return VERR_EM_INTERPRETER;
2180	}
2181
2182	/** @todo is addr always a flat linear address or ds based
2183	* (in absence of segment override prefixes)????
2184	*/
2185	rc = PGMInvalidatePage(pVM, addr);
2186	if (RT_SUCCESS(rc))
2187	{
2188	/* Manually invalidate the page for the VM's TLB. */
2189	Log(("SVMR0InvlpgA %RGv ASID=%d\n", addr, uASID));
2190	SVMR0InvlpgA(addr, uASID);
2191	return VINF_SUCCESS;
2192	}
2193	Assert(rc == VERR_REM_FLUSHED_PAGES_OVERFLOW);
2194	return rc;
2195	}
2196
2197	/**
2198	* Interprets INVLPG
2199	*
2200	* @returns VBox status code.
2201	* @retval VINF_* Scheduling instructions.
2202	* @retval VERR_EM_INTERPRETER Something we can't cope with.
2203	* @retval VERR_* Fatal errors.
2204	*
2205	* @param pVM The VM handle.
2206	* @param pRegFrame The register frame.
2207	* @param ASID Tagged TLB id for the guest
2208	*
2209	* Updates the EIP if an instruction was executed successfully.
2210	*/
2211	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2212	{
2213	/*
2214	* Only allow 32 & 64 bits code.
2215	*/
2216	DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
2217	if (enmMode != CPUMODE_16BIT)
2218	{
2219	RTGCPTR pbCode;
2220	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
2221	if (RT_SUCCESS(rc))
2222	{
2223	uint32_t cbOp;
2224	DISCPUSTATE Cpu;
2225
2226	Cpu.mode = enmMode;
2227	rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
2228	Assert(RT_FAILURE(rc) \|\| Cpu.pCurInstr->opcode == OP_INVLPG);
2229	if (RT_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
2230	{
2231	Assert(cbOp == Cpu.opsize);
2232	rc = svmR0InterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
2233	if (RT_SUCCESS(rc))
2234	{
2235	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
2236	}
2237	return rc;
2238	}
2239	}
2240	}
2241	return VERR_EM_INTERPRETER;
2242	}
2243
2244
2245	/**
2246	* Invalidates a guest page
2247	*
2248	* @returns VBox status code.
2249	* @param pVM The VM to operate on.
2250	* @param pVCpu The VM CPU to operate on.
2251	* @param GCVirt Page to invalidate
2252	*/
2253	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
2254	{
2255	bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB \| pVCpu->hwaccm.s.fForceTLBFlush;
2256
2257	/* Skip it if a TLB flush is already pending. */
2258	if (!fFlushPending)
2259	{
2260	SVM_VMCB *pVMCB;
2261
2262	Log2(("SVMR0InvalidatePage %RGv\n", GCVirt));
2263	AssertReturn(pVM, VERR_INVALID_PARAMETER);
2264	Assert(pVM->hwaccm.s.svm.fSupported);
2265
2266	/* @todo SMP */
2267	pVMCB = (SVM_VMCB *)pVM->aCpus[0].hwaccm.s.svm.pVMCB;
2268	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2269
2270	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushPageManual);
2271	#if HC_ARCH_BITS == 32
2272	/* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invlpga takes only 32 bits addresses. */
2273	if (CPUMIsGuestInLongMode(pVM))
2274	pVCpu->hwaccm.s.fForceTLBFlush = true;
2275	else
2276	#endif
2277	SVMR0InvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2278	}
2279	return VINF_SUCCESS;
2280	}
2281
2282
2283	/**
2284	* Invalidates a guest page by physical address
2285	*
2286	* @returns VBox status code.
2287	* @param pVM The VM to operate on.
2288	* @param pVCpu The VM CPU to operate on.
2289	* @param GCPhys Page to invalidate
2290	*/
2291	VMMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
2292	{
2293	Assert(pVM->hwaccm.s.fNestedPaging);
2294	/* invlpga only invalidates TLB entries for guest virtual addresses; we have no choice but to force a TLB flush here. */
2295	pVCpu->hwaccm.s.fForceTLBFlush = true;
2296	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBInvlpga);
2297	return VINF_SUCCESS;
2298	}
2299
2300	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
2301	/**
2302	* Prepares for and executes VMRUN (64 bits guests from a 32 bits hosts).
2303	*
2304	* @returns VBox status code.
2305	* @param pVMCBHostPhys Physical address of host VMCB.
2306	* @param pVMCBPhys Physical address of the VMCB.
2307	* @param pCtx Guest context.
2308	* @param pVM The VM to operate on.
2309	* @param pVCpu The VMCPU to operate on.
2310	*/
2311	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
2312	{
2313	uint32_t aParam[4];
2314
2315	aParam[0] = (uint32_t)(pVMCBHostPhys); /* Param 1: pVMCBHostPhys - Lo. */
2316	aParam[1] = (uint32_t)(pVMCBHostPhys >> 32); /* Param 1: pVMCBHostPhys - Hi. */
2317	aParam[2] = (uint32_t)(pVMCBPhys); /* Param 2: pVMCBPhys - Lo. */
2318	aParam[3] = (uint32_t)(pVMCBPhys >> 32); /* Param 2: pVMCBPhys - Hi. */
2319
2320	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSVMGCVMRun64, 4, &aParam[0]);
2321	}
2322
2323	/**
2324	* Executes the specified handler in 64 mode
2325	*
2326	* @returns VBox status code.
2327	* @param pVM The VM to operate on.
2328	* @param pVCpu The VMCPU to operate on.
2329	* @param pCtx Guest context
2330	* @param pfnHandler RC handler
2331	* @param cbParam Number of parameters
2332	* @param paParam Array of 32 bits parameters
2333	*/
2334	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
2335	{
2336	int rc;
2337	RTHCUINTREG uFlags;
2338
2339	/* @todo This code is not guest SMP safe (hyper context) */
2340	AssertReturn(pVM->cCPUs == 1, VERR_ACCESS_DENIED);
2341	Assert(pfnHandler);
2342
2343	uFlags = ASMIntDisableFlags();
2344
2345	CPUMSetHyperESP(pVM, VMMGetStackRC(pVM));
2346	CPUMSetHyperEIP(pVM, pfnHandler);
2347	for (int i=(int)cbParam-1;i>=0;i--)
2348	CPUMPushHyper(pVM, paParam[i]);
2349
2350	/* Call switcher. */
2351	rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM);
2352
2353	ASMSetFlags(uFlags);
2354	return rc;
2355	}
2356
2357	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) */

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 15410

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