HWSVMR0.cpp@ 20400

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1	/* $Id: HWSVMR0.cpp 20344 2009-06-05 15:54:01Z vboxsync $ */
2	/** @file
3	* HWACCM SVM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_svm.h>
32	#include <VBox/pgm.h>
33	#include <VBox/pdm.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <VBox/selm.h>
37	#include <VBox/iom.h>
38	#include <VBox/dis.h>
39	#include <VBox/dbgf.h>
40	#include <VBox/disopcode.h>
41	#include <iprt/param.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm.h>
44	#include <iprt/cpuset.h>
45	#include <iprt/mp.h>
46	#include <iprt/time.h>
47	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
48	# include <iprt/thread.h>
49	#endif
50	#include "HWSVMR0.h"
51
52	/*******************************************************************************
53	* Internal Functions *
54	*******************************************************************************/
55	static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID);
56	static int svmR0ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
57
58	/*******************************************************************************
59	* Global Variables *
60	*******************************************************************************/
61	/* IO operation lookup arrays. */
62	static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
63
64	/**
65	* Sets up and activates AMD-V on the current CPU
66	*
67	* @returns VBox status code.
68	* @param pCpu CPU info struct
69	* @param pVM The VM to operate on. (can be NULL after a resume!!)
70	* @param pvPageCpu Pointer to the global cpu page
71	* @param pPageCpuPhys Physical address of the global cpu page
72	*/
73	VMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
74	{
75	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
76	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
77
78	/* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
79
80	#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
81	SUPR0Printf("SVMR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
82	#endif
83
84	/* Turn on AMD-V in the EFER MSR. */
85	uint64_t val = ASMRdMsr(MSR_K6_EFER);
86	if (!(val & MSR_K6_EFER_SVME))
87	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
88
89	/* Write the physical page address where the CPU will store the host state while executing the VM. */
90	ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
91
92	return VINF_SUCCESS;
93	}
94
95	/**
96	* Deactivates AMD-V on the current CPU
97	*
98	* @returns VBox status code.
99	* @param pCpu CPU info struct
100	* @param pvPageCpu Pointer to the global cpu page
101	* @param pPageCpuPhys Physical address of the global cpu page
102	*/
103	VMMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
104	{
105	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
106	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
107
108	#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
109	SUPR0Printf("SVMR0DisableCpu cpu %d\n", pCpu->idCpu);
110	#endif
111
112	/* Turn off AMD-V in the EFER MSR. */
113	uint64_t val = ASMRdMsr(MSR_K6_EFER);
114	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
115
116	/* Invalidate host state physical address. */
117	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
118
119	return VINF_SUCCESS;
120	}
121
122	/**
123	* Does Ring-0 per VM AMD-V init.
124	*
125	* @returns VBox status code.
126	* @param pVM The VM to operate on.
127	*/
128	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
129	{
130	int rc;
131
132	pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
133	pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
134
135	/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
136	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
137	if (RT_FAILURE(rc))
138	return rc;
139
140	pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
141	pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
142	/* Set all bits to intercept all IO accesses. */
143	ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
144
145	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
146	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
147	if (RT_FAILURE(rc))
148	return rc;
149
150	pVM->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
151	pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
152	/* Set all bits to intercept all MSR accesses. */
153	ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
154
155	/* Erratum 170 which requires a forced TLB flush for each world switch:
156	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
157	*
158	* All BH-G1/2 and DH-G1/2 models include a fix:
159	* Athlon X2: 0x6b 1/2
160	* 0x68 1/2
161	* Athlon 64: 0x7f 1
162	* 0x6f 2
163	* Sempron: 0x7f 1/2
164	* 0x6f 2
165	* 0x6c 2
166	* 0x7c 2
167	* Turion 64: 0x68 2
168	*
169	*/
170	uint32_t u32Dummy;
171	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
172	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
173	u32BaseFamily= (u32Version >> 8) & 0xf;
174	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
175	u32Model = ((u32Version >> 4) & 0xf);
176	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
177	u32Stepping = u32Version & 0xf;
178	if ( u32Family == 0xf
179	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
180	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
181	{
182	Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
183	pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
184	}
185
186	/* Allocate VMCBs for all guest CPUs. */
187	for (unsigned i=0;i<pVM->cCPUs;i++)
188	{
189	PVMCPU pVCpu = &pVM->aCpus[i];
190
191	pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
192	pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
193
194	/* Allocate one page for the host context */
195	rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
196	if (RT_FAILURE(rc))
197	return rc;
198
199	pVCpu->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCBHost);
200	pVCpu->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 0);
201	ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCBHost);
202
203	/* Allocate one page for the VM control block (VMCB). */
204	rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
205	if (RT_FAILURE(rc))
206	return rc;
207
208	pVCpu->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCB);
209	pVCpu->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCB, 0);
210	ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCB);
211	}
212
213	return VINF_SUCCESS;
214	}
215
216	/**
217	* Does Ring-0 per VM AMD-V termination.
218	*
219	* @returns VBox status code.
220	* @param pVM The VM to operate on.
221	*/
222	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
223	{
224	for (unsigned i=0;i<pVM->cCPUs;i++)
225	{
226	PVMCPU pVCpu = &pVM->aCpus[i];
227
228	if (pVCpu->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ)
229	{
230	RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, false);
231	pVCpu->hwaccm.s.svm.pVMCBHost = 0;
232	pVCpu->hwaccm.s.svm.pVMCBHostPhys = 0;
233	pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
234	}
235
236	if (pVCpu->hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)
237	{
238	RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCB, false);
239	pVCpu->hwaccm.s.svm.pVMCB = 0;
240	pVCpu->hwaccm.s.svm.pVMCBPhys = 0;
241	pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
242	}
243	}
244	if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)
245	{
246	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
247	pVM->hwaccm.s.svm.pIOBitmap = 0;
248	pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
249	pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
250	}
251	if (pVM->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
252	{
253	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
254	pVM->hwaccm.s.svm.pMSRBitmap = 0;
255	pVM->hwaccm.s.svm.pMSRBitmapPhys = 0;
256	pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
257	}
258	return VINF_SUCCESS;
259	}
260
261	/**
262	* Sets up AMD-V for the specified VM
263	*
264	* @returns VBox status code.
265	* @param pVM The VM to operate on.
266	*/
267	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
268	{
269	int rc = VINF_SUCCESS;
270	SVM_VMCB *pVMCB;
271
272	AssertReturn(pVM, VERR_INVALID_PARAMETER);
273
274	Assert(pVM->hwaccm.s.svm.fSupported);
275
276	for (unsigned i=0;i<pVM->cCPUs;i++)
277	{
278	pVMCB = (SVM_VMCB *)pVM->aCpus[i].hwaccm.s.svm.pVMCB;
279	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
280
281	/* Program the control fields. Most of them never have to be changed again. */
282	/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
283	/* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical. */
284	if (!pVM->hwaccm.s.fNestedPaging)
285	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
286	else
287	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
288
289	/*
290	* CR0/3/4 writes must be intercepted for obvious reasons.
291	*/
292	if (!pVM->hwaccm.s.fNestedPaging)
293	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
294	else
295	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4) \| RT_BIT(8);
296
297	/* Intercept all DRx reads and writes by default. Changed later on. */
298	pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
299	pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
300
301	/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
302	* All breakpoints are automatically cleared when the VM exits.
303	*/
304
305	pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
306	#ifndef DEBUG
307	if (pVM->hwaccm.s.fNestedPaging)
308	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
309	#endif
310
311	pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
312	\| SVM_CTRL1_INTERCEPT_VINTR
313	\| SVM_CTRL1_INTERCEPT_NMI
314	\| SVM_CTRL1_INTERCEPT_SMI
315	\| SVM_CTRL1_INTERCEPT_INIT
316	\| SVM_CTRL1_INTERCEPT_RDPMC
317	\| SVM_CTRL1_INTERCEPT_CPUID
318	\| SVM_CTRL1_INTERCEPT_RSM
319	\| SVM_CTRL1_INTERCEPT_HLT
320	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
321	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
322	\| SVM_CTRL1_INTERCEPT_INVLPG
323	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
324	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH
325	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
326	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
327	;
328	/* With nested paging we don't care about invlpg anymore. */
329	if (pVM->hwaccm.s.fNestedPaging)
330	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
331
332	pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
333	\| SVM_CTRL2_INTERCEPT_VMMCALL
334	\| SVM_CTRL2_INTERCEPT_VMLOAD
335	\| SVM_CTRL2_INTERCEPT_VMSAVE
336	\| SVM_CTRL2_INTERCEPT_STGI
337	\| SVM_CTRL2_INTERCEPT_CLGI
338	\| SVM_CTRL2_INTERCEPT_SKINIT
339	\| SVM_CTRL2_INTERCEPT_WBINVD
340	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
341	;
342	Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
343	Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
344	Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
345
346	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
347	pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
348	/* Ignore the priority in the TPR; just deliver it when we tell it to. */
349	pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
350
351	/* Set IO and MSR bitmap addresses. */
352	pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
353	pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
354
355	/* No LBR virtualization. */
356	pVMCB->ctrl.u64LBRVirt = 0;
357
358	/** The ASID must start at 1; the host uses 0. */
359	pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
360
361	/** Setup the PAT msr (nested paging only) */
362	pVMCB->guest.u64GPAT = 0x0007040600070406ULL;
363	}
364	return rc;
365	}
366
367
368	/**
369	* Injects an event (trap or external interrupt)
370	*
371	* @param pVCpu The VMCPU to operate on.
372	* @param pVMCB SVM control block
373	* @param pCtx CPU Context
374	* @param pIntInfo SVM interrupt info
375	*/
376	inline void SVMR0InjectEvent(PVMCPU pVCpu, SVM_VMCB pVMCB, CPUMCTX pCtx, SVM_EVENT* pEvent)
377	{
378	#ifdef VBOX_WITH_STATISTICS
379	STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
380	#endif
381
382	#ifdef VBOX_STRICT
383	if (pEvent->n.u8Vector == 0xE)
384	Log(("SVM: Inject int %d at %RGv error code=%02x CR2=%RGv intInfo=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode, (RTGCPTR)pCtx->cr2, pEvent->au64[0]));
385	else
386	if (pEvent->n.u8Vector < 0x20)
387	Log(("SVM: Inject int %d at %RGv error code=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode));
388	else
389	{
390	Log(("INJ-EI: %x at %RGv\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip));
391	Assert(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
392	Assert(pCtx->eflags.u32 & X86_EFL_IF);
393	}
394	#endif
395
396	/* Set event injection state. */
397	pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
398	}
399
400
401	/**
402	* Checks for pending guest interrupts and injects them
403	*
404	* @returns VBox status code.
405	* @param pVM The VM to operate on.
406	* @param pVCpu The VM CPU to operate on.
407	* @param pVMCB SVM control block
408	* @param pCtx CPU Context
409	*/
410	static int SVMR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, SVM_VMCB pVMCB, CPUMCTX pCtx)
411	{
412	int rc;
413
414	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
415	if (pVCpu->hwaccm.s.Event.fPending)
416	{
417	SVM_EVENT Event;
418
419	Log(("Reinjecting event %08x %08x at %RGv\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip));
420	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
421	Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
422	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
423
424	pVCpu->hwaccm.s.Event.fPending = false;
425	return VINF_SUCCESS;
426	}
427
428	if (pVM->hwaccm.s.fInjectNMI)
429	{
430	SVM_EVENT Event;
431
432	Event.n.u8Vector = X86_XCPT_NMI;
433	Event.n.u1Valid = 1;
434	Event.n.u32ErrorCode = 0;
435	Event.n.u3Type = SVM_EVENT_NMI;
436
437	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
438	pVM->hwaccm.s.fInjectNMI = false;
439	return VINF_SUCCESS;
440	}
441
442	/* When external interrupts are pending, we should exit the VM when IF is set. */
443	if ( !TRPMHasTrap(pVCpu)
444	&& VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC\|VMCPU_FF_INTERRUPT_PIC)))
445	{
446	if ( !(pCtx->eflags.u32 & X86_EFL_IF)
447	\|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
448	{
449	if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
450	{
451	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
452	LogFlow(("Enable irq window exit!\n"));
453	else
454	Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", (RTGCPTR)pCtx->rip));
455
456	/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
457	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
458	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
459	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
460	}
461	}
462	else
463	{
464	uint8_t u8Interrupt;
465
466	rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
467	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
468	if (RT_SUCCESS(rc))
469	{
470	rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
471	AssertRC(rc);
472	}
473	else
474	{
475	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
476	Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC\|VMCPU_FF_INTERRUPT_PIC)));
477	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
478	/* Just continue */
479	}
480	}
481	}
482
483	#ifdef VBOX_STRICT
484	if (TRPMHasTrap(pVCpu))
485	{
486	uint8_t u8Vector;
487	rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
488	AssertRC(rc);
489	}
490	#endif
491
492	if ( (pCtx->eflags.u32 & X86_EFL_IF)
493	&& (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
494	&& TRPMHasTrap(pVCpu)
495	)
496	{
497	uint8_t u8Vector;
498	int rc;
499	TRPMEVENT enmType;
500	SVM_EVENT Event;
501	RTGCUINT u32ErrorCode;
502
503	Event.au64[0] = 0;
504
505	/* If a new event is pending, then dispatch it now. */
506	rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &u32ErrorCode, 0);
507	AssertRC(rc);
508	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
509	Assert(enmType != TRPM_SOFTWARE_INT);
510
511	/* Clear the pending trap. */
512	rc = TRPMResetTrap(pVCpu);
513	AssertRC(rc);
514
515	Event.n.u8Vector = u8Vector;
516	Event.n.u1Valid = 1;
517	Event.n.u32ErrorCode = u32ErrorCode;
518
519	if (enmType == TRPM_TRAP)
520	{
521	switch (u8Vector) {
522	case 8:
523	case 10:
524	case 11:
525	case 12:
526	case 13:
527	case 14:
528	case 17:
529	/* Valid error codes. */
530	Event.n.u1ErrorCodeValid = 1;
531	break;
532	default:
533	break;
534	}
535	if (u8Vector == X86_XCPT_NMI)
536	Event.n.u3Type = SVM_EVENT_NMI;
537	else
538	Event.n.u3Type = SVM_EVENT_EXCEPTION;
539	}
540	else
541	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
542
543	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
544	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
545	} /* if (interrupts can be dispatched) */
546
547	return VINF_SUCCESS;
548	}
549
550	/**
551	* Save the host state
552	*
553	* @returns VBox status code.
554	* @param pVM The VM to operate on.
555	* @param pVCpu The VM CPU to operate on.
556	*/
557	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
558	{
559	NOREF(pVM);
560	NOREF(pVCpu);
561	/* Nothing to do here. */
562	return VINF_SUCCESS;
563	}
564
565	/**
566	* Loads the guest state
567	*
568	* NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
569	*
570	* @returns VBox status code.
571	* @param pVM The VM to operate on.
572	* @param pVCpu The VM CPU to operate on.
573	* @param pCtx Guest context
574	*/
575	VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
576	{
577	RTGCUINTPTR val;
578	SVM_VMCB *pVMCB;
579
580	if (pVM == NULL)
581	return VERR_INVALID_PARAMETER;
582
583	/* Setup AMD SVM. */
584	Assert(pVM->hwaccm.s.svm.fSupported);
585
586	pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
587	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
588
589	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
590	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
591	{
592	SVM_WRITE_SELREG(CS, cs);
593	SVM_WRITE_SELREG(SS, ss);
594	SVM_WRITE_SELREG(DS, ds);
595	SVM_WRITE_SELREG(ES, es);
596	SVM_WRITE_SELREG(FS, fs);
597	SVM_WRITE_SELREG(GS, gs);
598	}
599
600	/* Guest CPU context: LDTR. */
601	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
602	{
603	SVM_WRITE_SELREG(LDTR, ldtr);
604	}
605
606	/* Guest CPU context: TR. */
607	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
608	{
609	SVM_WRITE_SELREG(TR, tr);
610	}
611
612	/* Guest CPU context: GDTR. */
613	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
614	{
615	pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
616	pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
617	}
618
619	/* Guest CPU context: IDTR. */
620	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
621	{
622	pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
623	pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
624	}
625
626	/*
627	* Sysenter MSRs (unconditional)
628	*/
629	pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
630	pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
631	pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
632
633	/* Control registers */
634	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
635	{
636	val = pCtx->cr0;
637	if (!CPUMIsGuestFPUStateActive(pVCpu))
638	{
639	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
640	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
641	}
642	else
643	{
644	/** @todo check if we support the old style mess correctly. */
645	if (!(val & X86_CR0_NE))
646	{
647	Log(("Forcing X86_CR0_NE!!!\n"));
648
649	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
650	if (!pVCpu->hwaccm.s.fFPUOldStyleOverride)
651	{
652	pVMCB->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_MF);
653	pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
654	}
655	}
656	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
657	}
658	/* Always enable caching. */
659	val &= ~(X86_CR0_CD\|X86_CR0_NW);
660
661	/* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
662	/* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
663	if (!pVM->hwaccm.s.fNestedPaging)
664	{
665	val \|= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
666	val \|= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
667	}
668	pVMCB->guest.u64CR0 = val;
669	}
670	/* CR2 as well */
671	pVMCB->guest.u64CR2 = pCtx->cr2;
672
673	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
674	{
675	/* Save our shadow CR3 register. */
676	if (pVM->hwaccm.s.fNestedPaging)
677	{
678	PGMMODE enmShwPagingMode;
679
680	#if HC_ARCH_BITS == 32
681	if (CPUMIsGuestInLongModeEx(pCtx))
682	enmShwPagingMode = PGMMODE_AMD64_NX;
683	else
684	#endif
685	enmShwPagingMode = PGMGetHostMode(pVM);
686
687	pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
688	Assert(pVMCB->ctrl.u64NestedPagingCR3);
689	pVMCB->guest.u64CR3 = pCtx->cr3;
690	}
691	else
692	{
693	pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
694	Assert(pVMCB->guest.u64CR3 \|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
695	}
696	}
697
698	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
699	{
700	val = pCtx->cr4;
701	if (!pVM->hwaccm.s.fNestedPaging)
702	{
703	switch(pVCpu->hwaccm.s.enmShadowMode)
704	{
705	case PGMMODE_REAL:
706	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
707	AssertFailed();
708	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
709
710	case PGMMODE_32_BIT: /* 32-bit paging. */
711	val &= ~X86_CR4_PAE;
712	break;
713
714	case PGMMODE_PAE: /* PAE paging. */
715	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
716	/** @todo use normal 32 bits paging */
717	val \|= X86_CR4_PAE;
718	break;
719
720	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
721	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
722	#ifdef VBOX_ENABLE_64_BITS_GUESTS
723	break;
724	#else
725	AssertFailed();
726	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
727	#endif
728
729	default: /* shut up gcc */
730	AssertFailed();
731	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
732	}
733	}
734	pVMCB->guest.u64CR4 = val;
735	}
736
737	/* Debug registers. */
738	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
739	{
740	pCtx->dr[6] \|= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
741	pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
742
743	pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
744	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
745	pCtx->dr[7] \|= 0x400; /* must be one */
746
747	pVMCB->guest.u64DR7 = pCtx->dr[7];
748	pVMCB->guest.u64DR6 = pCtx->dr[6];
749
750	/* Sync the debug state now if any breakpoint is armed. */
751	if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK\|X86_DR7_GD))
752	&& !CPUMIsGuestDebugStateActive(pVCpu)
753	&& !DBGFIsStepping(pVCpu))
754	{
755	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
756
757	/* Disable drx move intercepts. */
758	pVMCB->ctrl.u16InterceptRdDRx = 0;
759	pVMCB->ctrl.u16InterceptWrDRx = 0;
760
761	/* Save the host and load the guest debug state. */
762	int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
763	AssertRC(rc);
764	}
765	}
766
767	/* EIP, ESP and EFLAGS */
768	pVMCB->guest.u64RIP = pCtx->rip;
769	pVMCB->guest.u64RSP = pCtx->rsp;
770	pVMCB->guest.u64RFlags = pCtx->eflags.u32;
771
772	/* Set CPL */
773	pVMCB->guest.u8CPL = pCtx->csHid.Attr.n.u2Dpl;
774
775	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
776	pVMCB->guest.u64RAX = pCtx->rax;
777
778	/* vmrun will fail without MSR_K6_EFER_SVME. */
779	pVMCB->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
780
781	/* 64 bits guest mode? */
782	if (CPUMIsGuestInLongModeEx(pCtx))
783	{
784	#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
785	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
786	#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
787	pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
788	#else
789	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
790	if (!pVM->hwaccm.s.fAllow64BitGuests)
791	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
792	# endif
793	pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun64;
794	#endif
795	/* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
796	pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
797	pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
798	}
799	else
800	{
801	/* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
802	pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
803
804	pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun;
805	}
806
807	/* TSC offset. */
808	if (TMCpuTickCanUseRealTSC(pVCpu, &pVMCB->ctrl.u64TSCOffset))
809	{
810	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
811	pVMCB->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
812	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
813	}
814	else
815	{
816	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
817	pVMCB->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
818	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
819	}
820
821	/* Sync the various msrs for 64 bits mode. */
822	pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
823	pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
824	pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
825	pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
826	pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
827
828	#ifdef DEBUG
829	/* Intercept X86_XCPT_DB if stepping is enabled */
830	if (DBGFIsStepping(pVCpu))
831	pVMCB->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_DB);
832	else
833	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_DB);
834	#endif
835
836	/* Done. */
837	pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
838
839	return VINF_SUCCESS;
840	}
841
842
843	/**
844	* Runs guest code in an AMD-V VM.
845	*
846	* @returns VBox status code.
847	* @param pVM The VM to operate on.
848	* @param pVCpu The VM CPU to operate on.
849	* @param pCtx Guest context
850	*/
851	VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
852	{
853	int rc = VINF_SUCCESS;
854	uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
855	SVM_VMCB *pVMCB;
856	bool fSyncTPR = false;
857	unsigned cResume = 0;
858	uint8_t u8LastVTPR;
859	PHWACCM_CPUINFO pCpu = 0;
860	RTCCUINTREG uOldEFlags = ~(RTCCUINTREG)0;
861	#ifdef VBOX_STRICT
862	RTCPUID idCpuCheck;
863	#endif
864	#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
865	uint64_t u64LastTime = RTTimeMilliTS();
866	#endif
867
868	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
869
870	pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
871	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
872
873	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
874	*/
875	ResumeExecution:
876	Assert(!HWACCMR0SuspendPending());
877
878	/* Safety precaution; looping for too long here can have a very bad effect on the host */
879	if (RT_UNLIKELY(++cResume > pVM->hwaccm.s.cMaxResumeLoops))
880	{
881	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
882	rc = VINF_EM_RAW_INTERRUPT;
883	goto end;
884	}
885
886	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
887	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
888	{
889	Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
890	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
891	{
892	/* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
893	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
894	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
895	* break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
896	*/
897	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
898	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
899	pVMCB->ctrl.u64IntShadow = 0;
900	}
901	}
902	else
903	{
904	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
905	pVMCB->ctrl.u64IntShadow = 0;
906	}
907
908	#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
909	if (RT_UNLIKELY(cResume & 0xf) == 0)
910	{
911	uint64_t u64CurTime = RTTimeMilliTS();
912
913	if (RT_UNLIKELY(u64CurTime > u64LastTime))
914	{
915	u64LastTime = u64CurTime;
916	TMTimerPollVoid(pVM, pVCpu);
917	}
918	}
919	#endif
920
921	/* Check for pending actions that force us to go back to ring 3. */
922	#ifdef DEBUG
923	/* Intercept X86_XCPT_DB if stepping is enabled */
924	if (!DBGFIsStepping(pVCpu))
925	#endif
926	{
927	if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK)
928	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
929	{
930	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
931	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
932	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
933	rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
934	goto end;
935	}
936	}
937
938	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
939	if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
940	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
941	{
942	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
943	rc = VINF_EM_PENDING_REQUEST;
944	goto end;
945	}
946
947	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
948	/*
949	* Exit to ring-3 preemption/work is pending.
950	*
951	* Interrupts are disabled before the call to make sure we don't miss any interrupt
952	* that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
953	* further down, but SVMR0CheckPendingInterrupt makes that hard.)
954	*
955	* Note! Interrupts must be disabled done before we check for TLB flushes; TLB
956	* shootdowns rely on this.
957	*/
958	uOldEFlags = ASMIntDisableFlags();
959	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
960	{
961	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);
962	rc = VINF_EM_RAW_INTERRUPT;
963	goto end;
964	}
965	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
966	#endif
967
968	/* When external interrupts are pending, we should exit the VM when IF is set. */
969	/* Note! After VM_FF_INHIBIT_INTERRUPTS check!!! */
970	rc = SVMR0CheckPendingInterrupt(pVM, pVCpu, pVMCB, pCtx);
971	if (RT_FAILURE(rc))
972	{
973	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
974	goto end;
975	}
976
977	/* TPR caching using CR8 is only available in 64 bits mode or with 32 bits guests when X86_CPUID_AMD_FEATURE_ECX_CR8L is supported. */
978	/* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! */
979	if (pVM->hwaccm.s.fHasIoApic)
980	{
981	bool fPending;
982
983	/* TPR caching in CR8 */
984	int rc = PDMApicGetTPR(pVCpu, &u8LastVTPR, &fPending);
985	AssertRC(rc);
986	pVMCB->ctrl.IntCtrl.n.u8VTPR = u8LastVTPR;
987
988	if (fPending)
989	{
990	/* A TPR change could activate a pending interrupt, so catch cr8 writes. */
991	pVMCB->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
992	}
993	else
994	/* No interrupts are pending, so we don't need to be explicitely notified.
995	* There are enough world switches for detecting pending interrupts.
996	*/
997	pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
998
999	fSyncTPR = !fPending;
1000	}
1001
1002	/* All done! Let's start VM execution. */
1003	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, x);
1004
1005	/* Enable nested paging if necessary (disabled each time after #VMEXIT). */
1006	pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
1007
1008	#ifdef LOG_ENABLED
1009	pCpu = HWACCMR0GetCurrentCpu();
1010	if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1011	\|\| pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1012	{
1013	if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
1014	Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
1015	else
1016	Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1017	}
1018	if (pCpu->fFlushTLB)
1019	Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
1020	#endif
1021
1022	/*
1023	* NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1024	* (until the actual world switch)
1025	*/
1026	#ifdef VBOX_STRICT
1027	idCpuCheck = RTMpCpuId();
1028	#endif
1029	#ifdef LOG_LOGGING
1030	VMMR0LogFlushDisable(pVCpu);
1031	#endif
1032
1033	/* Load the guest state; must be here as it sets up the shadow cr0 for lazy fpu syncing! */
1034	rc = SVMR0LoadGuestState(pVM, pVCpu, pCtx);
1035	if (rc != VINF_SUCCESS)
1036	{
1037	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1038	goto end;
1039	}
1040
1041	#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1042	/* Disable interrupts to make sure a poke will interrupt execution.
1043	* This must be done before we check for TLB flushes; TLB shootdowns rely on this.
1044	*/
1045	uOldEFlags = ASMIntDisableFlags();
1046	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1047	#endif
1048
1049	pCpu = HWACCMR0GetCurrentCpu();
1050	/* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1051	/* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1052	if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1053	/* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1054	\|\| pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1055	{
1056	/* Force a TLB flush on VM entry. */
1057	pVCpu->hwaccm.s.fForceTLBFlush = true;
1058	}
1059	else
1060	Assert(!pCpu->fFlushTLB \|\| pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1061
1062	pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1063
1064	/* Check for tlb shootdown flushes. */
1065	if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH_BIT))
1066	pVCpu->hwaccm.s.fForceTLBFlush = true;
1067
1068	/* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1069	if ( pVCpu->hwaccm.s.fForceTLBFlush
1070	&& !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
1071	{
1072	if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1073	\|\| pCpu->fFlushTLB)
1074	{
1075	pCpu->fFlushTLB = false;
1076	pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1077	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
1078	pCpu->cTLBFlushes++;
1079	}
1080	else
1081	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1082
1083	pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1084	pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1085	}
1086	else
1087	{
1088	Assert(!pCpu->fFlushTLB \|\| pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1089
1090	/* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
1091	if (!pCpu->uCurrentASID \|\| !pVCpu->hwaccm.s.uCurrentASID)
1092	pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
1093
1094	Assert(!pVM->hwaccm.s.svm.fAlwaysFlushTLB \|\| pVCpu->hwaccm.s.fForceTLBFlush);
1095	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVCpu->hwaccm.s.fForceTLBFlush;
1096
1097	if ( !pVM->hwaccm.s.svm.fAlwaysFlushTLB
1098	&& VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1099	{
1100	/* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1101	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1102	for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1103	SVMR0InvlpgA(pVCpu->hwaccm.s.TlbShootdown.aPages[i], pVMCB->ctrl.TLBCtrl.n.u32ASID);
1104	}
1105	}
1106	pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1107	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1108
1109	AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1110	AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1111	AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1112	pVMCB->ctrl.TLBCtrl.n.u32ASID = pVCpu->hwaccm.s.uCurrentASID;
1113
1114	#ifdef VBOX_WITH_STATISTICS
1115	if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
1116	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1117	else
1118	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1119	#endif
1120
1121	/* In case we execute a goto ResumeExecution later on. */
1122	pVCpu->hwaccm.s.fResumeVM = true;
1123	pVCpu->hwaccm.s.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
1124
1125	Assert(sizeof(pVCpu->hwaccm.s.svm.pVMCBPhys) == 8);
1126	Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
1127	Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
1128	Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
1129	Assert(pVMCB->ctrl.u64LBRVirt == 0);
1130
1131	#ifdef VBOX_STRICT
1132	Assert(idCpuCheck == RTMpCpuId());
1133	#endif
1134	TMNotifyStartOfExecution(pVCpu);
1135	pVCpu->hwaccm.s.svm.pfnVMRun(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu);
1136	TMNotifyEndOfExecution(pVCpu);
1137	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
1138	ASMSetFlags(uOldEFlags);
1139	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1140	uOldEFlags = ~(RTCCUINTREG)0;
1141	#endif
1142	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, x);
1143
1144	/*
1145	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1146	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1147	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1148	*/
1149
1150	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, x);
1151
1152	/* Reason for the VM exit */
1153	exitCode = pVMCB->ctrl.u64ExitCode;
1154
1155	if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
1156	{
1157	HWACCMDumpRegs(pVM, pVCpu, pCtx);
1158	#ifdef DEBUG
1159	Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
1160	Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
1161	Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
1162	Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
1163	Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
1164	Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
1165	Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
1166	Log(("ctrl.u64IOPMPhysAddr %RX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
1167	Log(("ctrl.u64MSRPMPhysAddr %RX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
1168	Log(("ctrl.u64TSCOffset %RX64\n", pVMCB->ctrl.u64TSCOffset));
1169
1170	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
1171	Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
1172	Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
1173	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
1174
1175	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
1176	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
1177	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
1178	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
1179	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
1180	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
1181	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
1182	Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
1183	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
1184	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
1185
1186	Log(("ctrl.u64IntShadow %RX64\n", pVMCB->ctrl.u64IntShadow));
1187	Log(("ctrl.u64ExitCode %RX64\n", pVMCB->ctrl.u64ExitCode));
1188	Log(("ctrl.u64ExitInfo1 %RX64\n", pVMCB->ctrl.u64ExitInfo1));
1189	Log(("ctrl.u64ExitInfo2 %RX64\n", pVMCB->ctrl.u64ExitInfo2));
1190	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
1191	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
1192	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
1193	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
1194	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
1195	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
1196	Log(("ctrl.NestedPaging %RX64\n", pVMCB->ctrl.NestedPaging.au64));
1197	Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
1198	Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
1199	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
1200	Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
1201	Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
1202	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
1203
1204	Log(("ctrl.u64NestedPagingCR3 %RX64\n", pVMCB->ctrl.u64NestedPagingCR3));
1205	Log(("ctrl.u64LBRVirt %RX64\n", pVMCB->ctrl.u64LBRVirt));
1206
1207	Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
1208	Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1209	Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1210	Log(("guest.CS.u64Base %RX64\n", pVMCB->guest.CS.u64Base));
1211	Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1212	Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1213	Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1214	Log(("guest.DS.u64Base %RX64\n", pVMCB->guest.DS.u64Base));
1215	Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1216	Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1217	Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1218	Log(("guest.ES.u64Base %RX64\n", pVMCB->guest.ES.u64Base));
1219	Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1220	Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1221	Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1222	Log(("guest.FS.u64Base %RX64\n", pVMCB->guest.FS.u64Base));
1223	Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1224	Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1225	Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1226	Log(("guest.GS.u64Base %RX64\n", pVMCB->guest.GS.u64Base));
1227
1228	Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1229	Log(("guest.GDTR.u64Base %RX64\n", pVMCB->guest.GDTR.u64Base));
1230
1231	Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1232	Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1233	Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1234	Log(("guest.LDTR.u64Base %RX64\n", pVMCB->guest.LDTR.u64Base));
1235
1236	Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1237	Log(("guest.IDTR.u64Base %RX64\n", pVMCB->guest.IDTR.u64Base));
1238
1239	Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1240	Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1241	Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1242	Log(("guest.TR.u64Base %RX64\n", pVMCB->guest.TR.u64Base));
1243
1244	Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1245	Log(("guest.u64CR0 %RX64\n", pVMCB->guest.u64CR0));
1246	Log(("guest.u64CR2 %RX64\n", pVMCB->guest.u64CR2));
1247	Log(("guest.u64CR3 %RX64\n", pVMCB->guest.u64CR3));
1248	Log(("guest.u64CR4 %RX64\n", pVMCB->guest.u64CR4));
1249	Log(("guest.u64DR6 %RX64\n", pVMCB->guest.u64DR6));
1250	Log(("guest.u64DR7 %RX64\n", pVMCB->guest.u64DR7));
1251
1252	Log(("guest.u64RIP %RX64\n", pVMCB->guest.u64RIP));
1253	Log(("guest.u64RSP %RX64\n", pVMCB->guest.u64RSP));
1254	Log(("guest.u64RAX %RX64\n", pVMCB->guest.u64RAX));
1255	Log(("guest.u64RFlags %RX64\n", pVMCB->guest.u64RFlags));
1256
1257	Log(("guest.u64SysEnterCS %RX64\n", pVMCB->guest.u64SysEnterCS));
1258	Log(("guest.u64SysEnterEIP %RX64\n", pVMCB->guest.u64SysEnterEIP));
1259	Log(("guest.u64SysEnterESP %RX64\n", pVMCB->guest.u64SysEnterESP));
1260
1261	Log(("guest.u64EFER %RX64\n", pVMCB->guest.u64EFER));
1262	Log(("guest.u64STAR %RX64\n", pVMCB->guest.u64STAR));
1263	Log(("guest.u64LSTAR %RX64\n", pVMCB->guest.u64LSTAR));
1264	Log(("guest.u64CSTAR %RX64\n", pVMCB->guest.u64CSTAR));
1265	Log(("guest.u64SFMASK %RX64\n", pVMCB->guest.u64SFMASK));
1266	Log(("guest.u64KernelGSBase %RX64\n", pVMCB->guest.u64KernelGSBase));
1267	Log(("guest.u64GPAT %RX64\n", pVMCB->guest.u64GPAT));
1268	Log(("guest.u64DBGCTL %RX64\n", pVMCB->guest.u64DBGCTL));
1269	Log(("guest.u64BR_FROM %RX64\n", pVMCB->guest.u64BR_FROM));
1270	Log(("guest.u64BR_TO %RX64\n", pVMCB->guest.u64BR_TO));
1271	Log(("guest.u64LASTEXCPFROM %RX64\n", pVMCB->guest.u64LASTEXCPFROM));
1272	Log(("guest.u64LASTEXCPTO %RX64\n", pVMCB->guest.u64LASTEXCPTO));
1273
1274	#endif
1275	rc = VERR_SVM_UNABLE_TO_START_VM;
1276	goto end;
1277	}
1278
1279	/* Let's first sync back eip, esp, and eflags. */
1280	pCtx->rip = pVMCB->guest.u64RIP;
1281	pCtx->rsp = pVMCB->guest.u64RSP;
1282	pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1283	/* eax is saved/restore across the vmrun instruction */
1284	pCtx->rax = pVMCB->guest.u64RAX;
1285
1286	pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
1287
1288	/* Can be updated behind our back in the nested paging case. */
1289	pCtx->cr2 = pVMCB->guest.u64CR2;
1290
1291	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1292	SVM_READ_SELREG(SS, ss);
1293	SVM_READ_SELREG(CS, cs);
1294	SVM_READ_SELREG(DS, ds);
1295	SVM_READ_SELREG(ES, es);
1296	SVM_READ_SELREG(FS, fs);
1297	SVM_READ_SELREG(GS, gs);
1298
1299	/*
1300	* System MSRs
1301	*/
1302	pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1303	pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1304	pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1305
1306	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1307	SVM_READ_SELREG(LDTR, ldtr);
1308	SVM_READ_SELREG(TR, tr);
1309
1310	pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1311	pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1312
1313	pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1314	pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1315
1316	/* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1317	/* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1318	if ( pVM->hwaccm.s.fNestedPaging
1319	&& pCtx->cr3 != pVMCB->guest.u64CR3)
1320	{
1321	CPUMSetGuestCR3(pVCpu, pVMCB->guest.u64CR3);
1322	PGMUpdateCR3(pVCpu, pVMCB->guest.u64CR3);
1323	}
1324
1325	/* Note! NOW IT'S SAFE FOR LOGGING! */
1326	#ifdef LOG_LOGGING
1327	VMMR0LogFlushEnable(pVCpu);
1328	#endif
1329
1330	/* Take care of instruction fusing (sti, mov ss) (see 15.20.5 Interrupt Shadows) */
1331	if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1332	{
1333	Log(("uInterruptState %x rip=%RGv\n", pVMCB->ctrl.u64IntShadow, (RTGCPTR)pCtx->rip));
1334	EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
1335	}
1336	else
1337	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1338
1339	Log2(("exitCode = %x\n", exitCode));
1340
1341	/* Sync back DR6 as it could have been changed by hitting breakpoints. */
1342	pCtx->dr[6] = pVMCB->guest.u64DR6;
1343	/* DR7.GD can be cleared by debug exceptions, so sync it back as well. */
1344	pCtx->dr[7] = pVMCB->guest.u64DR7;
1345
1346	/* Check if an injected event was interrupted prematurely. */
1347	pVCpu->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1348	if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1349	&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1350	{
1351	Log(("Pending inject %RX64 at %RGv exit=%08x\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitCode));
1352
1353	#ifdef LOG_ENABLED
1354	SVM_EVENT Event;
1355	Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
1356
1357	if ( exitCode == SVM_EXIT_EXCEPTION_E
1358	&& Event.n.u8Vector == 0xE)
1359	{
1360	Log(("Double fault!\n"));
1361	}
1362	#endif
1363
1364	pVCpu->hwaccm.s.Event.fPending = true;
1365	/* Error code present? (redundant) */
1366	if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1367	pVCpu->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1368	else
1369	pVCpu->hwaccm.s.Event.errCode = 0;
1370	}
1371	#ifdef VBOX_WITH_STATISTICS
1372	if (exitCode == SVM_EXIT_NPF)
1373	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
1374	else
1375	STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1376	#endif
1377
1378	if (fSyncTPR)
1379	{
1380	rc = PDMApicSetTPR(pVCpu, pVMCB->ctrl.IntCtrl.n.u8VTPR);
1381	AssertRC(rc);
1382	}
1383
1384	/* Deal with the reason of the VM-exit. */
1385	switch (exitCode)
1386	{
1387	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1388	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1389	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1390	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1391	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1392	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1393	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1394	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1395	{
1396	/* Pending trap. */
1397	SVM_EVENT Event;
1398	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1399
1400	Log2(("Hardware/software interrupt %d\n", vector));
1401	switch (vector)
1402	{
1403	case X86_XCPT_DB:
1404	{
1405	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
1406
1407	/* Note that we don't support guest and host-initiated debugging at the same time. */
1408	Assert(DBGFIsStepping(pVCpu));
1409
1410	rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
1411	if (rc == VINF_EM_RAW_GUEST_TRAP)
1412	{
1413	Log(("Trap %x (debug) at %016RX64\n", vector, pCtx->rip));
1414
1415	/* Reinject the exception. */
1416	Event.au64[0] = 0;
1417	Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
1418	Event.n.u1Valid = 1;
1419	Event.n.u8Vector = X86_XCPT_DB;
1420
1421	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1422
1423	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1424	goto ResumeExecution;
1425	}
1426	/* Return to ring 3 to deal with the debug exit code. */
1427	break;
1428	}
1429
1430	case X86_XCPT_NM:
1431	{
1432	Log(("#NM fault at %RGv\n", (RTGCPTR)pCtx->rip));
1433
1434	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1435	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1436	rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
1437	if (rc == VINF_SUCCESS)
1438	{
1439	Assert(CPUMIsGuestFPUStateActive(pVCpu));
1440	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
1441
1442	/* Continue execution. */
1443	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1444	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1445
1446	goto ResumeExecution;
1447	}
1448
1449	Log(("Forward #NM fault to the guest\n"));
1450	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
1451
1452	Event.au64[0] = 0;
1453	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1454	Event.n.u1Valid = 1;
1455	Event.n.u8Vector = X86_XCPT_NM;
1456
1457	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1458	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1459	goto ResumeExecution;
1460	}
1461
1462	case X86_XCPT_PF: /* Page fault */
1463	{
1464	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1465	RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1466
1467	#ifdef DEBUG
1468	if (pVM->hwaccm.s.fNestedPaging)
1469	{ /* A genuine pagefault.
1470	* Forward the trap to the guest by injecting the exception and resuming execution.
1471	*/
1472	Log(("Guest page fault at %04X:%RGv cr2=%RGv error code %x rsp=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
1473	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1474
1475	/* Now we must update CR2. */
1476	pCtx->cr2 = uFaultAddress;
1477
1478	Event.au64[0] = 0;
1479	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1480	Event.n.u1Valid = 1;
1481	Event.n.u8Vector = X86_XCPT_PF;
1482	Event.n.u1ErrorCodeValid = 1;
1483	Event.n.u32ErrorCode = errCode;
1484
1485	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1486
1487	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1488	goto ResumeExecution;
1489	}
1490	#endif
1491	Assert(!pVM->hwaccm.s.fNestedPaging);
1492
1493	#if 0
1494	/* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1495	if ( (uFaultAddress & 0xfff) == 0x080
1496	&& pVM->hwaccm.s.fHasIoApic
1497	&& !(errCode & X86_TRAP_PF_P) /* not present */
1498	&& !CPUMIsGuestInLongModeEx(pCtx))
1499	{
1500	RTGCPHYS GCPhysApicBase, GCPhys;
1501	PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1502	GCPhysApicBase &= PAGE_BASE_GC_MASK;
1503
1504	rc = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL, &GCPhys);
1505	if ( rc == VINF_SUCCESS
1506	&& GCPhys == GCPhysApicBase)
1507	{
1508	Log(("Replace TPR access at %RGv\n", pCtx->rip));
1509
1510	DISCPUSTATE Cpu;
1511	unsigned cbOp;
1512	rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);
1513	AssertRC(rc);
1514	if ( rc == VINF_SUCCESS
1515	&& Cpu.pCurInstr->opcode == OP_MOV
1516	&& (cbOp == 5 \|\| cbOp == 6))
1517	{
1518	uint8_t szInstr[15];
1519	if ( (errCode & X86_TRAP_PF_RW)
1520	&& Cpu.param1.disp32 == (uint32_t)uFaultAddress
1521	&& Cpu.param2.flags == USE_REG_GEN32)
1522	{
1523	/* 0xF0, 0x0F, 0x22, 0xC0 = mov cr8, eax */
1524	szInstr[0] = 0xF0;
1525	szInstr[1] = 0x0F;
1526	szInstr[2] = 0x22;
1527	szInstr[3] = 0xC0 \| Cpu.param2.base.reg_gen;
1528	for (unsigned i = 4; i < cbOp; i++)
1529	szInstr[i] = 0x90; /* nop */
1530
1531	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, cbOp);
1532	AssertRC(rc);
1533
1534	Log(("Acceptable write candidate!\n"));
1535	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1536	goto ResumeExecution;
1537	}
1538	else
1539	if ( Cpu.param2.disp32 == (uint32_t)uFaultAddress
1540	&& Cpu.param1.flags == USE_REG_GEN32)
1541	{
1542	/* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1543	szInstr[0] = 0xF0;
1544	szInstr[1] = 0x0F;
1545	szInstr[2] = 0x20;
1546	szInstr[3] = 0xC0 \| Cpu.param1.base.reg_gen;
1547	for (unsigned i = 4; i < cbOp; i++)
1548	szInstr[i] = 0x90; /* nop */
1549
1550	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, cbOp);
1551	AssertRC(rc);
1552
1553	Log(("Acceptable read candidate!\n"));
1554	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1555	goto ResumeExecution;
1556	}
1557	}
1558	}
1559	}
1560	#endif
1561
1562	Log2(("Page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1563	/* Exit qualification contains the linear address of the page fault. */
1564	TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1565	TRPMSetErrorCode(pVCpu, errCode);
1566	TRPMSetFaultAddress(pVCpu, uFaultAddress);
1567
1568	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1569	rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1570	Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1571	if (rc == VINF_SUCCESS)
1572	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1573	Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1574	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1575
1576	TRPMResetTrap(pVCpu);
1577
1578	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1579	goto ResumeExecution;
1580	}
1581	else
1582	if (rc == VINF_EM_RAW_GUEST_TRAP)
1583	{ /* A genuine pagefault.
1584	* Forward the trap to the guest by injecting the exception and resuming execution.
1585	*/
1586	Log2(("Forward page fault to the guest\n"));
1587	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1588	/* The error code might have been changed. */
1589	errCode = TRPMGetErrorCode(pVCpu);
1590
1591	TRPMResetTrap(pVCpu);
1592
1593	/* Now we must update CR2. */
1594	pCtx->cr2 = uFaultAddress;
1595
1596	Event.au64[0] = 0;
1597	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1598	Event.n.u1Valid = 1;
1599	Event.n.u8Vector = X86_XCPT_PF;
1600	Event.n.u1ErrorCodeValid = 1;
1601	Event.n.u32ErrorCode = errCode;
1602
1603	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1604
1605	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1606	goto ResumeExecution;
1607	}
1608	#ifdef VBOX_STRICT
1609	if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
1610	LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
1611	#endif
1612	/* Need to go back to the recompiler to emulate the instruction. */
1613	TRPMResetTrap(pVCpu);
1614	break;
1615	}
1616
1617	case X86_XCPT_MF: /* Floating point exception. */
1618	{
1619	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
1620	if (!(pCtx->cr0 & X86_CR0_NE))
1621	{
1622	/* old style FPU error reporting needs some extra work. */
1623	/** @todo don't fall back to the recompiler, but do it manually. */
1624	rc = VINF_EM_RAW_EMULATE_INSTR;
1625	break;
1626	}
1627	Log(("Trap %x at %RGv\n", vector, (RTGCPTR)pCtx->rip));
1628
1629	Event.au64[0] = 0;
1630	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1631	Event.n.u1Valid = 1;
1632	Event.n.u8Vector = X86_XCPT_MF;
1633
1634	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1635
1636	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1637	goto ResumeExecution;
1638	}
1639
1640	#ifdef VBOX_STRICT
1641	case X86_XCPT_GP: /* General protection failure exception.*/
1642	case X86_XCPT_UD: /* Unknown opcode exception. */
1643	case X86_XCPT_DE: /* Divide error. */
1644	case X86_XCPT_SS: /* Stack segment exception. */
1645	case X86_XCPT_NP: /* Segment not present exception. */
1646	{
1647	Event.au64[0] = 0;
1648	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1649	Event.n.u1Valid = 1;
1650	Event.n.u8Vector = vector;
1651
1652	switch(vector)
1653	{
1654	case X86_XCPT_GP:
1655	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
1656	Event.n.u1ErrorCodeValid = 1;
1657	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1658	break;
1659	case X86_XCPT_DE:
1660	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
1661	break;
1662	case X86_XCPT_UD:
1663	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
1664	break;
1665	case X86_XCPT_SS:
1666	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
1667	Event.n.u1ErrorCodeValid = 1;
1668	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1669	break;
1670	case X86_XCPT_NP:
1671	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
1672	Event.n.u1ErrorCodeValid = 1;
1673	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1674	break;
1675	}
1676	Log(("Trap %x at %04x:%RGv esi=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->esi));
1677	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1678
1679	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1680	goto ResumeExecution;
1681	}
1682	#endif
1683	default:
1684	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1685	rc = VERR_EM_INTERNAL_ERROR;
1686	break;
1687
1688	} /* switch (vector) */
1689	break;
1690	}
1691
1692	case SVM_EXIT_NPF:
1693	{
1694	/* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1695	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1696	RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1697	PGMMODE enmShwPagingMode;
1698
1699	Assert(pVM->hwaccm.s.fNestedPaging);
1700	LogFlow(("Nested page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1701
1702	#if 0
1703	/* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1704	if ( (uFaultAddress & 0xfff) == 0x080
1705	&& pVM->hwaccm.s.fHasIoApic
1706	&& !(errCode & X86_TRAP_PF_P) /* not present */
1707	&& CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
1708	&& !CPUMIsGuestInLongModeEx(pCtx))
1709	{
1710	RTGCPHYS GCPhysApicBase;
1711	PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1712	GCPhysApicBase &= PAGE_BASE_GC_MASK;
1713
1714	if (uFaultAddress == GCPhysApicBase + 0x80)
1715	{
1716	rc = svmR0ReplaceTprInstr(pVM, pVCpu, pCtx);
1717	if (rc == VINF_SUCCESS)
1718	{
1719	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1720	goto ResumeExecution;
1721	}
1722
1723	rc = IOMMMIOPhysHandler(pVM, errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1724	if (rc == VINF_SUCCESS)
1725	{
1726	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1727	goto ResumeExecution; /* rip already updated */
1728	}
1729	}
1730	}
1731	#endif
1732
1733	/* Exit qualification contains the linear address of the page fault. */
1734	TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1735	TRPMSetErrorCode(pVCpu, errCode);
1736	TRPMSetFaultAddress(pVCpu, uFaultAddress);
1737
1738	/* Handle the pagefault trap for the nested shadow table. */
1739	#if HC_ARCH_BITS == 32
1740	if (CPUMIsGuestInLongModeEx(pCtx))
1741	enmShwPagingMode = PGMMODE_AMD64_NX;
1742	else
1743	#endif
1744	enmShwPagingMode = PGMGetHostMode(pVM);
1745
1746	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmShwPagingMode, errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1747	Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1748	if (rc == VINF_SUCCESS)
1749	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1750	Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1751	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1752
1753	TRPMResetTrap(pVCpu);
1754
1755	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1756	goto ResumeExecution;
1757	}
1758
1759	#ifdef VBOX_STRICT
1760	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1761	LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
1762	#endif
1763	/* Need to go back to the recompiler to emulate the instruction. */
1764	TRPMResetTrap(pVCpu);
1765	break;
1766	}
1767
1768	case SVM_EXIT_VINTR:
1769	/* A virtual interrupt is about to be delivered, which means IF=1. */
1770	Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1771	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1772	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1773	goto ResumeExecution;
1774
1775	case SVM_EXIT_FERR_FREEZE:
1776	case SVM_EXIT_INTR:
1777	case SVM_EXIT_NMI:
1778	case SVM_EXIT_SMI:
1779	case SVM_EXIT_INIT:
1780	/* External interrupt; leave to allow it to be dispatched again. */
1781	rc = VINF_EM_RAW_INTERRUPT;
1782	break;
1783
1784	case SVM_EXIT_WBINVD:
1785	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1786	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
1787	/* Skip instruction and continue directly. */
1788	pCtx->rip += 2; /* Note! hardcoded opcode size! */
1789	/* Continue execution.*/
1790	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1791	goto ResumeExecution;
1792
1793	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1794	{
1795	Log2(("SVM: Cpuid at %RGv for %x\n", (RTGCPTR)pCtx->rip, pCtx->eax));
1796	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
1797	rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1798	if (rc == VINF_SUCCESS)
1799	{
1800	/* Update EIP and continue execution. */
1801	pCtx->rip += 2; /* Note! hardcoded opcode size! */
1802	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1803	goto ResumeExecution;
1804	}
1805	AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
1806	rc = VINF_EM_RAW_EMULATE_INSTR;
1807	break;
1808	}
1809
1810	case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1811	{
1812	Log2(("SVM: Rdtsc\n"));
1813	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1814	rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1815	if (rc == VINF_SUCCESS)
1816	{
1817	/* Update EIP and continue execution. */
1818	pCtx->rip += 2; /* Note! hardcoded opcode size! */
1819	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1820	goto ResumeExecution;
1821	}
1822	rc = VINF_EM_RAW_EMULATE_INSTR;
1823	break;
1824	}
1825
1826	case SVM_EXIT_RDPMC: /* Guest software attempted to execute RDPMC. */
1827	{
1828	Log2(("SVM: Rdpmc %x\n", pCtx->ecx));
1829	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdpmc);
1830	rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1831	if (rc == VINF_SUCCESS)
1832	{
1833	/* Update EIP and continue execution. */
1834	pCtx->rip += 2; /* Note! hardcoded opcode size! */
1835	goto ResumeExecution;
1836	}
1837	rc = VINF_EM_RAW_EMULATE_INSTR;
1838	break;
1839	}
1840
1841	case SVM_EXIT_RDTSCP: /* Guest software attempted to execute RDTSCP. */
1842	{
1843	Log2(("SVM: Rdtscp\n"));
1844	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1845	rc = EMInterpretRdtscp(pVM, pVCpu, pCtx);
1846	if (rc == VINF_SUCCESS)
1847	{
1848	/* Update EIP and continue execution. */
1849	pCtx->rip += 3; /* Note! hardcoded opcode size! */
1850	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1851	goto ResumeExecution;
1852	}
1853	AssertMsgFailed(("EMU: rdtscp failed with %Rrc\n", rc));
1854	rc = VINF_EM_RAW_EMULATE_INSTR;
1855	break;
1856	}
1857
1858	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1859	{
1860	Log2(("SVM: invlpg\n"));
1861	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
1862
1863	Assert(!pVM->hwaccm.s.fNestedPaging);
1864
1865	/* Truly a pita. Why can't SVM give the same information as VT-x? */
1866	rc = svmR0InterpretInvpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1867	if (rc == VINF_SUCCESS)
1868	{
1869	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushPageInvlpg);
1870	goto ResumeExecution; /* eip already updated */
1871	}
1872	break;
1873	}
1874
1875	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1876	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1877	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1878	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1879	{
1880	uint32_t cbSize;
1881
1882	Log2(("SVM: %RGv mov cr%d, \n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
1883	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[exitCode - SVM_EXIT_WRITE_CR0]);
1884	rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
1885
1886	switch (exitCode - SVM_EXIT_WRITE_CR0)
1887	{
1888	case 0:
1889	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1890	break;
1891	case 2:
1892	break;
1893	case 3:
1894	Assert(!pVM->hwaccm.s.fNestedPaging);
1895	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1896	break;
1897	case 4:
1898	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1899	break;
1900	case 8:
1901	break;
1902	default:
1903	AssertFailed();
1904	}
1905	/* Check if a sync operation is pending. */
1906	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1907	&& VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1908	{
1909	rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1910	AssertRC(rc);
1911
1912	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBCRxChange);
1913
1914	/* Must be set by PGMSyncCR3 */
1915	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3 \|\| PGMGetGuestMode(pVCpu) <= PGMMODE_PROTECTED \|\| pVCpu->hwaccm.s.fForceTLBFlush,
1916	("rc=%Rrc mode=%d fForceTLBFlush=%RTbool\n", rc, PGMGetGuestMode(pVCpu), pVCpu->hwaccm.s.fForceTLBFlush));
1917	}
1918	if (rc == VINF_SUCCESS)
1919	{
1920	/* EIP has been updated already. */
1921
1922	/* Only resume if successful. */
1923	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1924	goto ResumeExecution;
1925	}
1926	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1927	break;
1928	}
1929
1930	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1931	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1932	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1933	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1934	{
1935	uint32_t cbSize;
1936
1937	Log2(("SVM: %RGv mov x, cr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
1938	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[exitCode - SVM_EXIT_READ_CR0]);
1939	rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
1940	if (rc == VINF_SUCCESS)
1941	{
1942	/* EIP has been updated already. */
1943
1944	/* Only resume if successful. */
1945	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1946	goto ResumeExecution;
1947	}
1948	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1949	break;
1950	}
1951
1952	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1953	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1954	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1955	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1956	{
1957	uint32_t cbSize;
1958
1959	Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
1960	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
1961
1962	if (!DBGFIsStepping(pVCpu))
1963	{
1964	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
1965
1966	/* Disable drx move intercepts. */
1967	pVMCB->ctrl.u16InterceptRdDRx = 0;
1968	pVMCB->ctrl.u16InterceptWrDRx = 0;
1969
1970	/* Save the host and load the guest debug state. */
1971	rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
1972	AssertRC(rc);
1973
1974	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1975	goto ResumeExecution;
1976	}
1977
1978	rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
1979	if (rc == VINF_SUCCESS)
1980	{
1981	/* EIP has been updated already. */
1982	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_DEBUG;
1983
1984	/* Only resume if successful. */
1985	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1986	goto ResumeExecution;
1987	}
1988	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1989	break;
1990	}
1991
1992	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1993	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1994	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1995	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1996	{
1997	uint32_t cbSize;
1998
1999	Log2(("SVM: %RGv mov x, dr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
2000	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
2001
2002	if (!DBGFIsStepping(pVCpu))
2003	{
2004	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2005
2006	/* Disable drx move intercepts. */
2007	pVMCB->ctrl.u16InterceptRdDRx = 0;
2008	pVMCB->ctrl.u16InterceptWrDRx = 0;
2009
2010	/* Save the host and load the guest debug state. */
2011	rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2012	AssertRC(rc);
2013
2014	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2015	goto ResumeExecution;
2016	}
2017
2018	rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2019	if (rc == VINF_SUCCESS)
2020	{
2021	/* EIP has been updated already. */
2022
2023	/* Only resume if successful. */
2024	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2025	goto ResumeExecution;
2026	}
2027	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
2028	break;
2029	}
2030
2031	/* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2032	case SVM_EXIT_IOIO: /* I/O instruction. */
2033	{
2034	SVM_IOIO_EXIT IoExitInfo;
2035	uint32_t uIOSize, uAndVal;
2036
2037	IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
2038
2039	/** @todo could use a lookup table here */
2040	if (IoExitInfo.n.u1OP8)
2041	{
2042	uIOSize = 1;
2043	uAndVal = 0xff;
2044	}
2045	else
2046	if (IoExitInfo.n.u1OP16)
2047	{
2048	uIOSize = 2;
2049	uAndVal = 0xffff;
2050	}
2051	else
2052	if (IoExitInfo.n.u1OP32)
2053	{
2054	uIOSize = 4;
2055	uAndVal = 0xffffffff;
2056	}
2057	else
2058	{
2059	AssertFailed(); /* should be fatal. */
2060	rc = VINF_EM_RAW_EMULATE_INSTR;
2061	break;
2062	}
2063
2064	if (IoExitInfo.n.u1STR)
2065	{
2066	/* ins/outs */
2067	DISCPUSTATE Cpu;
2068
2069	/* Disassemble manually to deal with segment prefixes. */
2070	rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, NULL);
2071	if (rc == VINF_SUCCESS)
2072	{
2073	if (IoExitInfo.n.u1Type == 0)
2074	{
2075	Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2076	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
2077	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, Cpu.prefix, uIOSize);
2078	}
2079	else
2080	{
2081	Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2082	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
2083	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, Cpu.prefix, uIOSize);
2084	}
2085	}
2086	else
2087	rc = VINF_EM_RAW_EMULATE_INSTR;
2088	}
2089	else
2090	{
2091	/* normal in/out */
2092	Assert(!IoExitInfo.n.u1REP);
2093
2094	if (IoExitInfo.n.u1Type == 0)
2095	{
2096	Log2(("IOMIOPortWrite %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
2097	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
2098	rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
2099	}
2100	else
2101	{
2102	uint32_t u32Val = 0;
2103
2104	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
2105	rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
2106	if (IOM_SUCCESS(rc))
2107	{
2108	/* Write back to the EAX register. */
2109	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
2110	Log2(("IOMIOPortRead %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
2111	}
2112	}
2113	}
2114	/*
2115	* Handled the I/O return codes.
2116	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2117	*/
2118	if (IOM_SUCCESS(rc))
2119	{
2120	/* Update EIP and continue execution. */
2121	pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
2122	if (RT_LIKELY(rc == VINF_SUCCESS))
2123	{
2124	/* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
2125	if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
2126	{
2127	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
2128	for (unsigned i=0;i<4;i++)
2129	{
2130	unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
2131
2132	if ( (IoExitInfo.n.u16Port >= pCtx->dr[i] && IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen)
2133	&& (pCtx->dr[7] & (X86_DR7_L(i) \| X86_DR7_G(i)))
2134	&& (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
2135	{
2136	SVM_EVENT Event;
2137
2138	Assert(CPUMIsGuestDebugStateActive(pVCpu));
2139
2140	/* Clear all breakpoint status flags and set the one we just hit. */
2141	pCtx->dr[6] &= ~(X86_DR6_B0\|X86_DR6_B1\|X86_DR6_B2\|X86_DR6_B3);
2142	pCtx->dr[6] \|= (uint64_t)RT_BIT(i);
2143
2144	/* Note: AMD64 Architecture Programmer's Manual 13.1:
2145	* Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
2146	* the contents have been read.
2147	*/
2148	pVMCB->guest.u64DR6 = pCtx->dr[6];
2149
2150	/* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2151	pCtx->dr[7] &= ~X86_DR7_GD;
2152
2153	/* Paranoia. */
2154	pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2155	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
2156	pCtx->dr[7] \|= 0x400; /* must be one */
2157
2158	pVMCB->guest.u64DR7 = pCtx->dr[7];
2159
2160	/* Inject the exception. */
2161	Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
2162
2163	Event.au64[0] = 0;
2164	Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
2165	Event.n.u1Valid = 1;
2166	Event.n.u8Vector = X86_XCPT_DB;
2167
2168	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2169
2170	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2171	goto ResumeExecution;
2172	}
2173	}
2174	}
2175
2176	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2177	goto ResumeExecution;
2178	}
2179	Log2(("EM status from IO at %RGv %x size %d: %Rrc\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
2180	break;
2181	}
2182
2183	#ifdef VBOX_STRICT
2184	if (rc == VINF_IOM_HC_IOPORT_READ)
2185	Assert(IoExitInfo.n.u1Type != 0);
2186	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2187	Assert(IoExitInfo.n.u1Type == 0);
2188	else
2189	AssertMsg(RT_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
2190	#endif
2191	Log2(("Failed IO at %RGv %x size %d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2192	break;
2193	}
2194
2195	case SVM_EXIT_HLT:
2196	/** Check if external interrupts are pending; if so, don't switch back. */
2197	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
2198	pCtx->rip++; /* skip hlt */
2199	if ( pCtx->eflags.Bits.u1IF
2200	&& VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC\|VMCPU_FF_INTERRUPT_PIC)))
2201	goto ResumeExecution;
2202
2203	rc = VINF_EM_HALT;
2204	break;
2205
2206	case SVM_EXIT_MWAIT_UNCOND:
2207	Log2(("SVM: mwait\n"));
2208	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMwait);
2209	rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2210	if ( rc == VINF_EM_HALT
2211	\|\| rc == VINF_SUCCESS)
2212	{
2213	/* Update EIP and continue execution. */
2214	pCtx->rip += 3; /* Note: hardcoded opcode size assumption! */
2215
2216	/** Check if external interrupts are pending; if so, don't switch back. */
2217	if ( rc == VINF_SUCCESS
2218	\|\| ( rc == VINF_EM_HALT
2219	&& pCtx->eflags.Bits.u1IF
2220	&& VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC\|VMCPU_FF_INTERRUPT_PIC)))
2221	)
2222	goto ResumeExecution;
2223	}
2224	AssertMsg(rc == VERR_EM_INTERPRETER \|\| rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", rc));
2225	break;
2226
2227	case SVM_EXIT_RSM:
2228	case SVM_EXIT_INVLPGA:
2229	case SVM_EXIT_VMRUN:
2230	case SVM_EXIT_VMMCALL:
2231	case SVM_EXIT_VMLOAD:
2232	case SVM_EXIT_VMSAVE:
2233	case SVM_EXIT_STGI:
2234	case SVM_EXIT_CLGI:
2235	case SVM_EXIT_SKINIT:
2236	{
2237	/* Unsupported instructions. */
2238	SVM_EVENT Event;
2239
2240	Event.au64[0] = 0;
2241	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2242	Event.n.u1Valid = 1;
2243	Event.n.u8Vector = X86_XCPT_UD;
2244
2245	Log(("Forced #UD trap at %RGv\n", (RTGCPTR)pCtx->rip));
2246	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2247
2248	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2249	goto ResumeExecution;
2250	}
2251
2252	/* Emulate in ring 3. */
2253	case SVM_EXIT_MSR:
2254	{
2255	uint32_t cbSize;
2256
2257	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2258	STAM_COUNTER_INC((pVMCB->ctrl.u64ExitInfo1 == 0) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
2259	Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
2260	rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2261	if (rc == VINF_SUCCESS)
2262	{
2263	/* EIP has been updated already. */
2264
2265	/* Only resume if successful. */
2266	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2267	goto ResumeExecution;
2268	}
2269	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
2270	break;
2271	}
2272
2273	case SVM_EXIT_MONITOR:
2274	case SVM_EXIT_PAUSE:
2275	case SVM_EXIT_MWAIT_ARMED:
2276	case SVM_EXIT_TASK_SWITCH: /* can change CR3; emulate */
2277	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2278	break;
2279
2280	case SVM_EXIT_SHUTDOWN:
2281	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2282	break;
2283
2284	case SVM_EXIT_IDTR_READ:
2285	case SVM_EXIT_GDTR_READ:
2286	case SVM_EXIT_LDTR_READ:
2287	case SVM_EXIT_TR_READ:
2288	case SVM_EXIT_IDTR_WRITE:
2289	case SVM_EXIT_GDTR_WRITE:
2290	case SVM_EXIT_LDTR_WRITE:
2291	case SVM_EXIT_TR_WRITE:
2292	case SVM_EXIT_CR0_SEL_WRITE:
2293	default:
2294	/* Unexpected exit codes. */
2295	rc = VERR_EM_INTERNAL_ERROR;
2296	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
2297	break;
2298	}
2299
2300	end:
2301
2302	/* Signal changes for the recompiler. */
2303	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
2304
2305	/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
2306	if (exitCode == SVM_EXIT_INTR)
2307	{
2308	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
2309	/* On the next entry we'll only sync the host context. */
2310	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
2311	}
2312	else
2313	{
2314	/* On the next entry we'll sync everything. */
2315	/** @todo we can do better than this */
2316	/* Not in the VINF_PGM_CHANGE_MODE though! */
2317	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
2318	}
2319
2320	/* translate into a less severe return code */
2321	if (rc == VERR_EM_INTERPRETER)
2322	rc = VINF_EM_RAW_EMULATE_INSTR;
2323
2324	/* Just set the correct state here instead of trying to catch every goto above. */
2325	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
2326
2327	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2328	/* Restore interrupts if we exitted after disabling them. */
2329	if (uOldEFlags != ~(RTCCUINTREG)0)
2330	ASMSetFlags(uOldEFlags);
2331	#endif
2332
2333	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2334	return rc;
2335	}
2336
2337	/**
2338	* Emulate simple mov tpr instruction
2339	*
2340	* @returns VBox status code.
2341	* @param pVCpu The VM CPU to operate on.
2342	* @param pDisState Disassembly state
2343	* @param pCtx CPU context
2344	* @param cbOp Opcode size
2345	*/
2346	static int svmR0EmulateTprMov(PVMCPU pVCpu, DISCPUSTATE *pDisState, PCPUMCTX pCtx, unsigned cbOp)
2347	{
2348	int rc;
2349
2350	if (pDisState->param1.flags == USE_DISPLACEMENT32)
2351	{
2352	/* write */
2353	uint8_t u8Tpr;
2354
2355	/* Fetch the new TPR value */
2356	if (pDisState->param2.flags == USE_REG_GEN32)
2357	{
2358	uint32_t val;
2359
2360	rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pDisState->param2.base.reg_gen, &val);
2361	AssertRC(rc);
2362	u8Tpr = val >> 4;
2363	}
2364	else
2365	if (pDisState->param2.flags == USE_IMMEDIATE32)
2366	{
2367	u8Tpr = (uint8_t)pDisState->param2.parval >> 4;
2368	}
2369	else
2370	return VERR_EM_INTERPRETER;
2371
2372	rc = PDMApicSetTPR(pVCpu, u8Tpr);
2373	AssertRC(rc);
2374
2375	pCtx->rip += cbOp;
2376	return VINF_SUCCESS;
2377	}
2378	else
2379	if (pDisState->param2.flags == USE_DISPLACEMENT32)
2380	{
2381	/* read */
2382	bool fPending;
2383	uint8_t u8Tpr;
2384
2385	/* TPR caching in CR8 */
2386	rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending);
2387	AssertRC(rc);
2388
2389	rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pDisState->param1.base.reg_gen, u8Tpr << 4);
2390	AssertRC(rc);
2391
2392	pCtx->rip += cbOp;
2393	return VINF_SUCCESS;
2394	}
2395	return VERR_EM_INTERPRETER;
2396	}
2397
2398	/**
2399	* Attempt to patch TPR mmio instructions
2400	*
2401	* @returns VBox status code.
2402	* @param pVM The VM to operate on.
2403	* @param pVCpu The VM CPU to operate on.
2404	* @param pCtx CPU context
2405	*/
2406	static int svmR0ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2407	{
2408	RTGCPTR oldrip = pCtx->rip;
2409	DISCPUSTATE Cpu;
2410	unsigned cbOp;
2411
2412	Log(("Replace TPR access at %RGv\n", pCtx->rip));
2413
2414	int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);
2415	AssertRC(rc);
2416	if ( rc == VINF_SUCCESS
2417	&& Cpu.pCurInstr->opcode == OP_MOV)
2418	{
2419	uint8_t szInstr[15];
2420	if ( cbOp == 10
2421	&& Cpu.param1.flags == USE_DISPLACEMENT32
2422	&& Cpu.param2.flags == USE_IMMEDIATE32)
2423	{
2424	/* Found:
2425	* mov [fffe0080], immediate_dword (10 bytes)
2426	*
2427	* Replace with:
2428	* mov free_register, immediate_dword >> 4 (5 bytes)
2429	* mov cr8, free_register (4 bytes)
2430	* nop (1 byte)
2431	*
2432	*/
2433	uint32_t u32tpr = (uint32_t)Cpu.param2.parval;
2434
2435	u32tpr = (u32tpr >> 4) & 0xf;
2436
2437	/* Check if the next instruction overwrites a general purpose register. If
2438	* it does, then we can safely use it ourselves.
2439	*/
2440	pCtx->rip += cbOp;
2441	rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);
2442	pCtx->rip = oldrip;
2443	if ( rc == VINF_SUCCESS
2444	&& Cpu.pCurInstr->opcode == OP_MOV
2445	&& Cpu.param1.flags == USE_REG_GEN32)
2446	{
2447	/* 0xB8, dword immediate = mov eax, dword immediate */
2448	szInstr[0] = 0xB8 + Cpu.param1.base.reg_gen;
2449	szInstr[1] = (uint8_t)u32tpr;
2450	szInstr[2] = 0;
2451	szInstr[3] = 0;
2452	szInstr[4] = 0;
2453
2454	/* 0xF0, 0x0F, 0x22, 0xC0 = mov cr8, eax */
2455	szInstr[5] = 0xF0;
2456	szInstr[6] = 0x0F;
2457	szInstr[7] = 0x22;
2458	szInstr[8] = 0xC0 \| Cpu.param1.base.reg_gen;
2459	szInstr[9] = 0x90; /* nop */
2460
2461	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, 10);
2462	AssertRC(rc);
2463
2464	Log(("Acceptable write candidate!\n"));
2465	return VINF_SUCCESS;
2466	}
2467	}
2468	else
2469	{
2470	if ( Cpu.param2.flags == USE_REG_GEN32
2471	&& cbOp == 6)
2472	{
2473	RTGCPTR GCPtrTpr = (uint32_t)Cpu.param1.disp32;
2474	uint32_t uMmioReg = Cpu.param2.base.reg_gen;
2475
2476	/* Found:
2477	* mov dword [fffe0080], eax (6 bytes)
2478	* Check if next instruction is a TPR read:
2479	* mov ecx, dword [fffe0080] (5 bytes)
2480	*/
2481	pCtx->rip += cbOp;
2482	rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);
2483	pCtx->rip = oldrip;
2484	if ( rc == VINF_SUCCESS
2485	&& Cpu.pCurInstr->opcode == OP_MOV
2486	&& Cpu.param1.flags == USE_REG_GEN32
2487	&& Cpu.param2.flags == USE_DISPLACEMENT32
2488	&& Cpu.param2.disp32 == (uint32_t)GCPtrTpr
2489	&& cbOp == 5)
2490	{
2491	/* mov new_reg, uMmioReg */
2492	szInstr[0] = 0x89;
2493	szInstr[1] = MAKE_MODRM(3, uMmioReg, Cpu.param1.base.reg_gen);
2494
2495	/* Let's hope the guest won't mind us trashing the source register...
2496	* shr uMmioReg, 4
2497	*/
2498	szInstr[2] = 0xC1;
2499	szInstr[3] = 0xE8 \| uMmioReg;
2500	szInstr[4] = 4;
2501
2502	/* 0xF0, 0x0F, 0x22, 0xC0 = mov cr8, eax */
2503	szInstr[5] = 0xF0;
2504	szInstr[6] = 0x0F;
2505	szInstr[7] = 0x22;
2506	szInstr[8] = 0xC0 \| uMmioReg;
2507
2508	/* Two nop instructions */
2509	szInstr[9] = 0x90;
2510	szInstr[10] = 0x90;
2511
2512	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, 6+cbOp);
2513	AssertRC(rc);
2514
2515	Log(("Acceptable read/write candidate!\n"));
2516	return VINF_SUCCESS;
2517	}
2518	}
2519	else
2520	if ( Cpu.param1.flags == USE_REG_GEN32
2521	&& cbOp == 5)
2522	{
2523	uint32_t uMmioReg = Cpu.param1.base.reg_gen;
2524
2525	/* Found:
2526	* mov eax, dword [fffe0080] (5 bytes)
2527	* Check if next instruction is:
2528	* shr eax, 4
2529	*/
2530	pCtx->rip += cbOp;
2531	rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);
2532	pCtx->rip = oldrip;
2533	if ( rc == VINF_SUCCESS
2534	&& Cpu.pCurInstr->opcode == OP_SHR
2535	&& Cpu.param1.flags == USE_REG_GEN32
2536	&& Cpu.param1.base.reg_gen == uMmioReg
2537	&& Cpu.param2.flags == USE_IMMEDIATE8
2538	&& Cpu.param2.parval == 4)
2539	{
2540	/* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
2541	szInstr[0] = 0xF0;
2542	szInstr[1] = 0x0F;
2543	szInstr[2] = 0x20;
2544	szInstr[3] = 0xC0 \| Cpu.param1.base.reg_gen;
2545	for (unsigned i = 4; i < 5+cbOp; i++)
2546	szInstr[i] = 0x90; /* nop */
2547
2548	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, 5+cbOp);
2549	AssertRC(rc);
2550
2551	Log(("Acceptable read candidate!\n"));
2552	return VINF_SUCCESS;
2553	}
2554	}
2555	}
2556	rc = svmR0EmulateTprMov(pVCpu, &Cpu, pCtx, cbOp);
2557	if (rc != VINF_SUCCESS)
2558	return rc;
2559
2560	/* Emulated successfully, so continue. */
2561	return VINF_SUCCESS;
2562	}
2563	return VERR_ACCESS_DENIED;
2564	}
2565
2566	/**
2567	* Enters the AMD-V session
2568	*
2569	* @returns VBox status code.
2570	* @param pVM The VM to operate on.
2571	* @param pVCpu The VM CPU to operate on.
2572	* @param pCpu CPU info struct
2573	*/
2574	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
2575	{
2576	Assert(pVM->hwaccm.s.svm.fSupported);
2577
2578	LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVCpu->hwaccm.s.idLastCpu, pVCpu->hwaccm.s.uCurrentASID));
2579	pVCpu->hwaccm.s.fResumeVM = false;
2580
2581	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
2582	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_LDTR;
2583
2584	return VINF_SUCCESS;
2585	}
2586
2587
2588	/**
2589	* Leaves the AMD-V session
2590	*
2591	* @returns VBox status code.
2592	* @param pVM The VM to operate on.
2593	* @param pVCpu The VM CPU to operate on.
2594	* @param pCtx CPU context
2595	*/
2596	VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2597	{
2598	SVM_VMCB pVMCB = (SVM_VMCB )pVCpu->hwaccm.s.svm.pVMCB;
2599
2600	Assert(pVM->hwaccm.s.svm.fSupported);
2601
2602	/* Save the guest debug state if necessary. */
2603	if (CPUMIsGuestDebugStateActive(pVCpu))
2604	{
2605	CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, false /* skip DR6 */);
2606
2607	/* Intercept all DRx reads and writes again. Changed later on. */
2608	pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
2609	pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
2610
2611	/* Resync the debug registers the next time. */
2612	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_DEBUG;
2613	}
2614	else
2615	Assert(pVMCB->ctrl.u16InterceptRdDRx == 0xFFFF && pVMCB->ctrl.u16InterceptWrDRx == 0xFFFF);
2616
2617	return VINF_SUCCESS;
2618	}
2619
2620
2621	static int svmR0InterpretInvlPg(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2622	{
2623	OP_PARAMVAL param1;
2624	RTGCPTR addr;
2625
2626	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2627	if(RT_FAILURE(rc))
2628	return VERR_EM_INTERPRETER;
2629
2630	switch(param1.type)
2631	{
2632	case PARMTYPE_IMMEDIATE:
2633	case PARMTYPE_ADDRESS:
2634	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
2635	return VERR_EM_INTERPRETER;
2636	addr = param1.val.val64;
2637	break;
2638
2639	default:
2640	return VERR_EM_INTERPRETER;
2641	}
2642
2643	/** @todo is addr always a flat linear address or ds based
2644	* (in absence of segment override prefixes)????
2645	*/
2646	rc = PGMInvalidatePage(pVCpu, addr);
2647	if (RT_SUCCESS(rc))
2648	{
2649	/* Manually invalidate the page for the VM's TLB. */
2650	Log(("SVMR0InvlpgA %RGv ASID=%d\n", addr, uASID));
2651	SVMR0InvlpgA(addr, uASID);
2652	return VINF_SUCCESS;
2653	}
2654	Assert(rc == VERR_REM_FLUSHED_PAGES_OVERFLOW);
2655	return rc;
2656	}
2657
2658	/**
2659	* Interprets INVLPG
2660	*
2661	* @returns VBox status code.
2662	* @retval VINF_* Scheduling instructions.
2663	* @retval VERR_EM_INTERPRETER Something we can't cope with.
2664	* @retval VERR_* Fatal errors.
2665	*
2666	* @param pVM The VM handle.
2667	* @param pRegFrame The register frame.
2668	* @param ASID Tagged TLB id for the guest
2669	*
2670	* Updates the EIP if an instruction was executed successfully.
2671	*/
2672	static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2673	{
2674	/*
2675	* Only allow 32 & 64 bits code.
2676	*/
2677	DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
2678	if (enmMode != CPUMODE_16BIT)
2679	{
2680	RTGCPTR pbCode;
2681	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
2682	if (RT_SUCCESS(rc))
2683	{
2684	uint32_t cbOp;
2685	DISCPUSTATE Cpu;
2686
2687	Cpu.mode = enmMode;
2688	rc = EMInterpretDisasOneEx(pVM, pVCpu, pbCode, pRegFrame, &Cpu, &cbOp);
2689	Assert(RT_FAILURE(rc) \|\| Cpu.pCurInstr->opcode == OP_INVLPG);
2690	if (RT_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
2691	{
2692	Assert(cbOp == Cpu.opsize);
2693	rc = svmR0InterpretInvlPg(pVCpu, &Cpu, pRegFrame, uASID);
2694	if (RT_SUCCESS(rc))
2695	{
2696	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
2697	}
2698	return rc;
2699	}
2700	}
2701	}
2702	return VERR_EM_INTERPRETER;
2703	}
2704
2705
2706	/**
2707	* Invalidates a guest page
2708	*
2709	* @returns VBox status code.
2710	* @param pVM The VM to operate on.
2711	* @param pVCpu The VM CPU to operate on.
2712	* @param GCVirt Page to invalidate
2713	*/
2714	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
2715	{
2716	bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB \| pVCpu->hwaccm.s.fForceTLBFlush;
2717
2718	/* Skip it if a TLB flush is already pending. */
2719	if (!fFlushPending)
2720	{
2721	SVM_VMCB *pVMCB;
2722
2723	Log2(("SVMR0InvalidatePage %RGv\n", GCVirt));
2724	AssertReturn(pVM, VERR_INVALID_PARAMETER);
2725	Assert(pVM->hwaccm.s.svm.fSupported);
2726
2727	/* @todo SMP */
2728	pVMCB = (SVM_VMCB *)pVM->aCpus[0].hwaccm.s.svm.pVMCB;
2729	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2730
2731	#if HC_ARCH_BITS == 32
2732	/* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invlpga takes only 32 bits addresses. */
2733	if (CPUMIsGuestInLongMode(pVCpu))
2734	pVCpu->hwaccm.s.fForceTLBFlush = true;
2735	else
2736	#endif
2737	SVMR0InvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2738	}
2739	return VINF_SUCCESS;
2740	}
2741
2742
2743	#if 0 /* obsolete, but left here for clarification. */
2744	/**
2745	* Invalidates a guest page by physical address
2746	*
2747	* @returns VBox status code.
2748	* @param pVM The VM to operate on.
2749	* @param pVCpu The VM CPU to operate on.
2750	* @param GCPhys Page to invalidate
2751	*/
2752	VMMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
2753	{
2754	Assert(pVM->hwaccm.s.fNestedPaging);
2755	/* invlpga only invalidates TLB entries for guest virtual addresses; we have no choice but to force a TLB flush here. */
2756	pVCpu->hwaccm.s.fForceTLBFlush = true;
2757	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBInvlpga);
2758	return VINF_SUCCESS;
2759	}
2760	#endif
2761
2762	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2763	/**
2764	* Prepares for and executes VMRUN (64 bits guests from a 32 bits hosts).
2765	*
2766	* @returns VBox status code.
2767	* @param pVMCBHostPhys Physical address of host VMCB.
2768	* @param pVMCBPhys Physical address of the VMCB.
2769	* @param pCtx Guest context.
2770	* @param pVM The VM to operate on.
2771	* @param pVCpu The VMCPU to operate on.
2772	*/
2773	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
2774	{
2775	uint32_t aParam[4];
2776
2777	aParam[0] = (uint32_t)(pVMCBHostPhys); /* Param 1: pVMCBHostPhys - Lo. */
2778	aParam[1] = (uint32_t)(pVMCBHostPhys >> 32); /* Param 1: pVMCBHostPhys - Hi. */
2779	aParam[2] = (uint32_t)(pVMCBPhys); /* Param 2: pVMCBPhys - Lo. */
2780	aParam[3] = (uint32_t)(pVMCBPhys >> 32); /* Param 2: pVMCBPhys - Hi. */
2781
2782	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSVMGCVMRun64, 4, &aParam[0]);
2783	}
2784
2785	/**
2786	* Executes the specified handler in 64 mode
2787	*
2788	* @returns VBox status code.
2789	* @param pVM The VM to operate on.
2790	* @param pVCpu The VMCPU to operate on.
2791	* @param pCtx Guest context
2792	* @param pfnHandler RC handler
2793	* @param cbParam Number of parameters
2794	* @param paParam Array of 32 bits parameters
2795	*/
2796	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
2797	{
2798	int rc;
2799	RTHCUINTREG uOldEFlags;
2800
2801	/* @todo This code is not guest SMP safe (hyper stack and switchers) */
2802	AssertReturn(pVM->cCPUs == 1, VERR_TOO_MANY_CPUS);
2803	Assert(pfnHandler);
2804
2805	uOldEFlags = ASMIntDisableFlags();
2806
2807	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVM));
2808	CPUMSetHyperEIP(pVCpu, pfnHandler);
2809	for (int i=(int)cbParam-1;i>=0;i--)
2810	CPUMPushHyper(pVCpu, paParam[i]);
2811
2812	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2813	/* Call switcher. */
2814	rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM);
2815	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2816
2817	ASMSetFlags(uOldEFlags);
2818	return rc;
2819	}
2820
2821	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 20400

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