HWSVMR0.cpp@ 20769

Last change on this file since 20769 was 20769, checked in by vboxsync, 16 years ago
VMM: don't forget to enable R0 logging again if we are leaving VMXR0RunGuestCode() early
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1	/* $Id: HWSVMR0.cpp 20769 2009-06-22 12:32:11Z vboxsync $ */
2	/** @file
3	* HWACCM SVM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_svm.h>
32	#include <VBox/pgm.h>
33	#include <VBox/pdm.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <VBox/selm.h>
37	#include <VBox/iom.h>
38	#include <VBox/dis.h>
39	#include <VBox/dbgf.h>
40	#include <VBox/disopcode.h>
41	#include <iprt/param.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm.h>
44	#include <iprt/cpuset.h>
45	#include <iprt/mp.h>
46	#include <iprt/time.h>
47	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
48	# include <iprt/thread.h>
49	#endif
50	#include "HWSVMR0.h"
51
52	/*******************************************************************************
53	* Internal Functions *
54	*******************************************************************************/
55	static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID);
56	static int svmR0ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
57
58	/*******************************************************************************
59	* Global Variables *
60	*******************************************************************************/
61	/* IO operation lookup arrays. */
62	static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
63
64	/**
65	* Sets up and activates AMD-V on the current CPU
66	*
67	* @returns VBox status code.
68	* @param pCpu CPU info struct
69	* @param pVM The VM to operate on. (can be NULL after a resume!!)
70	* @param pvPageCpu Pointer to the global cpu page
71	* @param pPageCpuPhys Physical address of the global cpu page
72	*/
73	VMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
74	{
75	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
76	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
77
78	/* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
79
80	#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
81	SUPR0Printf("SVMR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
82	#endif
83
84	/* Turn on AMD-V in the EFER MSR. */
85	uint64_t val = ASMRdMsr(MSR_K6_EFER);
86	if (!(val & MSR_K6_EFER_SVME))
87	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
88
89	/* Write the physical page address where the CPU will store the host state while executing the VM. */
90	ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
91
92	return VINF_SUCCESS;
93	}
94
95	/**
96	* Deactivates AMD-V on the current CPU
97	*
98	* @returns VBox status code.
99	* @param pCpu CPU info struct
100	* @param pvPageCpu Pointer to the global cpu page
101	* @param pPageCpuPhys Physical address of the global cpu page
102	*/
103	VMMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
104	{
105	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
106	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
107
108	#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
109	SUPR0Printf("SVMR0DisableCpu cpu %d\n", pCpu->idCpu);
110	#endif
111
112	/* Turn off AMD-V in the EFER MSR. */
113	uint64_t val = ASMRdMsr(MSR_K6_EFER);
114	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
115
116	/* Invalidate host state physical address. */
117	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
118
119	return VINF_SUCCESS;
120	}
121
122	/**
123	* Does Ring-0 per VM AMD-V init.
124	*
125	* @returns VBox status code.
126	* @param pVM The VM to operate on.
127	*/
128	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
129	{
130	int rc;
131
132	pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
133	pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
134
135	/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
136	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
137	if (RT_FAILURE(rc))
138	return rc;
139
140	pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
141	pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
142	/* Set all bits to intercept all IO accesses. */
143	ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
144
145	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
146	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
147	if (RT_FAILURE(rc))
148	return rc;
149
150	pVM->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
151	pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
152	/* Set all bits to intercept all MSR accesses. */
153	ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
154
155	/* Erratum 170 which requires a forced TLB flush for each world switch:
156	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
157	*
158	* All BH-G1/2 and DH-G1/2 models include a fix:
159	* Athlon X2: 0x6b 1/2
160	* 0x68 1/2
161	* Athlon 64: 0x7f 1
162	* 0x6f 2
163	* Sempron: 0x7f 1/2
164	* 0x6f 2
165	* 0x6c 2
166	* 0x7c 2
167	* Turion 64: 0x68 2
168	*
169	*/
170	uint32_t u32Dummy;
171	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
172	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
173	u32BaseFamily= (u32Version >> 8) & 0xf;
174	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
175	u32Model = ((u32Version >> 4) & 0xf);
176	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
177	u32Stepping = u32Version & 0xf;
178	if ( u32Family == 0xf
179	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
180	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
181	{
182	Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
183	pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
184	}
185
186	/* Allocate VMCBs for all guest CPUs. */
187	for (unsigned i=0;i<pVM->cCPUs;i++)
188	{
189	PVMCPU pVCpu = &pVM->aCpus[i];
190
191	pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
192	pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
193
194	/* Allocate one page for the host context */
195	rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
196	if (RT_FAILURE(rc))
197	return rc;
198
199	pVCpu->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCBHost);
200	pVCpu->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 0);
201	ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCBHost);
202
203	/* Allocate one page for the VM control block (VMCB). */
204	rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
205	if (RT_FAILURE(rc))
206	return rc;
207
208	pVCpu->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCB);
209	pVCpu->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCB, 0);
210	ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCB);
211	}
212
213	return VINF_SUCCESS;
214	}
215
216	/**
217	* Does Ring-0 per VM AMD-V termination.
218	*
219	* @returns VBox status code.
220	* @param pVM The VM to operate on.
221	*/
222	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
223	{
224	for (unsigned i=0;i<pVM->cCPUs;i++)
225	{
226	PVMCPU pVCpu = &pVM->aCpus[i];
227
228	if (pVCpu->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ)
229	{
230	RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, false);
231	pVCpu->hwaccm.s.svm.pVMCBHost = 0;
232	pVCpu->hwaccm.s.svm.pVMCBHostPhys = 0;
233	pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
234	}
235
236	if (pVCpu->hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)
237	{
238	RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCB, false);
239	pVCpu->hwaccm.s.svm.pVMCB = 0;
240	pVCpu->hwaccm.s.svm.pVMCBPhys = 0;
241	pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
242	}
243	}
244	if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)
245	{
246	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
247	pVM->hwaccm.s.svm.pIOBitmap = 0;
248	pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
249	pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
250	}
251	if (pVM->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
252	{
253	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
254	pVM->hwaccm.s.svm.pMSRBitmap = 0;
255	pVM->hwaccm.s.svm.pMSRBitmapPhys = 0;
256	pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
257	}
258	return VINF_SUCCESS;
259	}
260
261	/**
262	* Sets up AMD-V for the specified VM
263	*
264	* @returns VBox status code.
265	* @param pVM The VM to operate on.
266	*/
267	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
268	{
269	int rc = VINF_SUCCESS;
270	SVM_VMCB *pVMCB;
271
272	AssertReturn(pVM, VERR_INVALID_PARAMETER);
273
274	Assert(pVM->hwaccm.s.svm.fSupported);
275
276	for (unsigned i=0;i<pVM->cCPUs;i++)
277	{
278	pVMCB = (SVM_VMCB *)pVM->aCpus[i].hwaccm.s.svm.pVMCB;
279	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
280
281	/* Program the control fields. Most of them never have to be changed again. */
282	/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
283	/* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical. */
284	if (!pVM->hwaccm.s.fNestedPaging)
285	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
286	else
287	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
288
289	/*
290	* CR0/3/4 writes must be intercepted for obvious reasons.
291	*/
292	if (!pVM->hwaccm.s.fNestedPaging)
293	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
294	else
295	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4) \| RT_BIT(8);
296
297	/* Intercept all DRx reads and writes by default. Changed later on. */
298	pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
299	pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
300
301	/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
302	* All breakpoints are automatically cleared when the VM exits.
303	*/
304
305	pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
306	#ifndef DEBUG
307	if (pVM->hwaccm.s.fNestedPaging)
308	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
309	#endif
310
311	pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
312	\| SVM_CTRL1_INTERCEPT_VINTR
313	\| SVM_CTRL1_INTERCEPT_NMI
314	\| SVM_CTRL1_INTERCEPT_SMI
315	\| SVM_CTRL1_INTERCEPT_INIT
316	\| SVM_CTRL1_INTERCEPT_RDPMC
317	\| SVM_CTRL1_INTERCEPT_CPUID
318	\| SVM_CTRL1_INTERCEPT_RSM
319	\| SVM_CTRL1_INTERCEPT_HLT
320	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
321	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
322	\| SVM_CTRL1_INTERCEPT_INVLPG
323	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
324	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH
325	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
326	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
327	;
328	/* With nested paging we don't care about invlpg anymore. */
329	if (pVM->hwaccm.s.fNestedPaging)
330	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
331
332	pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
333	\| SVM_CTRL2_INTERCEPT_VMMCALL
334	\| SVM_CTRL2_INTERCEPT_VMLOAD
335	\| SVM_CTRL2_INTERCEPT_VMSAVE
336	\| SVM_CTRL2_INTERCEPT_STGI
337	\| SVM_CTRL2_INTERCEPT_CLGI
338	\| SVM_CTRL2_INTERCEPT_SKINIT
339	\| SVM_CTRL2_INTERCEPT_WBINVD
340	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
341	;
342	Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
343	Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
344	Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
345
346	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
347	pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
348	/* Ignore the priority in the TPR; just deliver it when we tell it to. */
349	pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
350
351	/* Set IO and MSR bitmap addresses. */
352	pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
353	pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
354
355	/* No LBR virtualization. */
356	pVMCB->ctrl.u64LBRVirt = 0;
357
358	/** The ASID must start at 1; the host uses 0. */
359	pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
360
361	/** Setup the PAT msr (nested paging only) */
362	pVMCB->guest.u64GPAT = 0x0007040600070406ULL;
363	}
364	return rc;
365	}
366
367
368	/**
369	* Injects an event (trap or external interrupt)
370	*
371	* @param pVCpu The VMCPU to operate on.
372	* @param pVMCB SVM control block
373	* @param pCtx CPU Context
374	* @param pIntInfo SVM interrupt info
375	*/
376	inline void SVMR0InjectEvent(PVMCPU pVCpu, SVM_VMCB pVMCB, CPUMCTX pCtx, SVM_EVENT* pEvent)
377	{
378	#ifdef VBOX_WITH_STATISTICS
379	STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
380	#endif
381
382	#ifdef VBOX_STRICT
383	if (pEvent->n.u8Vector == 0xE)
384	Log(("SVM: Inject int %d at %RGv error code=%02x CR2=%RGv intInfo=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode, (RTGCPTR)pCtx->cr2, pEvent->au64[0]));
385	else
386	if (pEvent->n.u8Vector < 0x20)
387	Log(("SVM: Inject int %d at %RGv error code=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode));
388	else
389	{
390	Log(("INJ-EI: %x at %RGv\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip));
391	Assert(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
392	Assert(pCtx->eflags.u32 & X86_EFL_IF);
393	}
394	#endif
395
396	/* Set event injection state. */
397	pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
398	}
399
400
401	/**
402	* Checks for pending guest interrupts and injects them
403	*
404	* @returns VBox status code.
405	* @param pVM The VM to operate on.
406	* @param pVCpu The VM CPU to operate on.
407	* @param pVMCB SVM control block
408	* @param pCtx CPU Context
409	*/
410	static int SVMR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, SVM_VMCB pVMCB, CPUMCTX pCtx)
411	{
412	int rc;
413
414	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
415	if (pVCpu->hwaccm.s.Event.fPending)
416	{
417	SVM_EVENT Event;
418
419	Log(("Reinjecting event %08x %08x at %RGv\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip));
420	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
421	Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
422	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
423
424	pVCpu->hwaccm.s.Event.fPending = false;
425	return VINF_SUCCESS;
426	}
427
428	if (pVM->hwaccm.s.fInjectNMI)
429	{
430	SVM_EVENT Event;
431
432	Event.n.u8Vector = X86_XCPT_NMI;
433	Event.n.u1Valid = 1;
434	Event.n.u32ErrorCode = 0;
435	Event.n.u3Type = SVM_EVENT_NMI;
436
437	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
438	pVM->hwaccm.s.fInjectNMI = false;
439	return VINF_SUCCESS;
440	}
441
442	/* When external interrupts are pending, we should exit the VM when IF is set. */
443	if ( !TRPMHasTrap(pVCpu)
444	&& VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC\|VMCPU_FF_INTERRUPT_PIC)))
445	{
446	if ( !(pCtx->eflags.u32 & X86_EFL_IF)
447	\|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
448	{
449	if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
450	{
451	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
452	LogFlow(("Enable irq window exit!\n"));
453	else
454	Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", (RTGCPTR)pCtx->rip));
455
456	/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
457	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
458	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
459	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
460	}
461	}
462	else
463	{
464	uint8_t u8Interrupt;
465
466	rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
467	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
468	if (RT_SUCCESS(rc))
469	{
470	rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
471	AssertRC(rc);
472	}
473	else
474	{
475	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
476	Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC\|VMCPU_FF_INTERRUPT_PIC)));
477	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
478	/* Just continue */
479	}
480	}
481	}
482
483	#ifdef VBOX_STRICT
484	if (TRPMHasTrap(pVCpu))
485	{
486	uint8_t u8Vector;
487	rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
488	AssertRC(rc);
489	}
490	#endif
491
492	if ( (pCtx->eflags.u32 & X86_EFL_IF)
493	&& (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
494	&& TRPMHasTrap(pVCpu)
495	)
496	{
497	uint8_t u8Vector;
498	int rc;
499	TRPMEVENT enmType;
500	SVM_EVENT Event;
501	RTGCUINT u32ErrorCode;
502
503	Event.au64[0] = 0;
504
505	/* If a new event is pending, then dispatch it now. */
506	rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &u32ErrorCode, 0);
507	AssertRC(rc);
508	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
509	Assert(enmType != TRPM_SOFTWARE_INT);
510
511	/* Clear the pending trap. */
512	rc = TRPMResetTrap(pVCpu);
513	AssertRC(rc);
514
515	Event.n.u8Vector = u8Vector;
516	Event.n.u1Valid = 1;
517	Event.n.u32ErrorCode = u32ErrorCode;
518
519	if (enmType == TRPM_TRAP)
520	{
521	switch (u8Vector) {
522	case 8:
523	case 10:
524	case 11:
525	case 12:
526	case 13:
527	case 14:
528	case 17:
529	/* Valid error codes. */
530	Event.n.u1ErrorCodeValid = 1;
531	break;
532	default:
533	break;
534	}
535	if (u8Vector == X86_XCPT_NMI)
536	Event.n.u3Type = SVM_EVENT_NMI;
537	else
538	Event.n.u3Type = SVM_EVENT_EXCEPTION;
539	}
540	else
541	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
542
543	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
544	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
545	} /* if (interrupts can be dispatched) */
546
547	return VINF_SUCCESS;
548	}
549
550	/**
551	* Save the host state
552	*
553	* @returns VBox status code.
554	* @param pVM The VM to operate on.
555	* @param pVCpu The VM CPU to operate on.
556	*/
557	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
558	{
559	NOREF(pVM);
560	NOREF(pVCpu);
561	/* Nothing to do here. */
562	return VINF_SUCCESS;
563	}
564
565	/**
566	* Loads the guest state
567	*
568	* NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
569	*
570	* @returns VBox status code.
571	* @param pVM The VM to operate on.
572	* @param pVCpu The VM CPU to operate on.
573	* @param pCtx Guest context
574	*/
575	VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
576	{
577	RTGCUINTPTR val;
578	SVM_VMCB *pVMCB;
579
580	if (pVM == NULL)
581	return VERR_INVALID_PARAMETER;
582
583	/* Setup AMD SVM. */
584	Assert(pVM->hwaccm.s.svm.fSupported);
585
586	pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
587	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
588
589	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
590	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
591	{
592	SVM_WRITE_SELREG(CS, cs);
593	SVM_WRITE_SELREG(SS, ss);
594	SVM_WRITE_SELREG(DS, ds);
595	SVM_WRITE_SELREG(ES, es);
596	SVM_WRITE_SELREG(FS, fs);
597	SVM_WRITE_SELREG(GS, gs);
598	}
599
600	/* Guest CPU context: LDTR. */
601	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
602	{
603	SVM_WRITE_SELREG(LDTR, ldtr);
604	}
605
606	/* Guest CPU context: TR. */
607	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
608	{
609	SVM_WRITE_SELREG(TR, tr);
610	}
611
612	/* Guest CPU context: GDTR. */
613	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
614	{
615	pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
616	pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
617	}
618
619	/* Guest CPU context: IDTR. */
620	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
621	{
622	pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
623	pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
624	}
625
626	/*
627	* Sysenter MSRs (unconditional)
628	*/
629	pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
630	pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
631	pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
632
633	/* Control registers */
634	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
635	{
636	val = pCtx->cr0;
637	if (!CPUMIsGuestFPUStateActive(pVCpu))
638	{
639	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
640	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
641	}
642	else
643	{
644	/** @todo check if we support the old style mess correctly. */
645	if (!(val & X86_CR0_NE))
646	{
647	Log(("Forcing X86_CR0_NE!!!\n"));
648
649	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
650	if (!pVCpu->hwaccm.s.fFPUOldStyleOverride)
651	{
652	pVMCB->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_MF);
653	pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
654	}
655	}
656	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
657	}
658	/* Always enable caching. */
659	val &= ~(X86_CR0_CD\|X86_CR0_NW);
660
661	/* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
662	/* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
663	if (!pVM->hwaccm.s.fNestedPaging)
664	{
665	val \|= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
666	val \|= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
667	}
668	pVMCB->guest.u64CR0 = val;
669	}
670	/* CR2 as well */
671	pVMCB->guest.u64CR2 = pCtx->cr2;
672
673	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
674	{
675	/* Save our shadow CR3 register. */
676	if (pVM->hwaccm.s.fNestedPaging)
677	{
678	PGMMODE enmShwPagingMode;
679
680	#if HC_ARCH_BITS == 32
681	if (CPUMIsGuestInLongModeEx(pCtx))
682	enmShwPagingMode = PGMMODE_AMD64_NX;
683	else
684	#endif
685	enmShwPagingMode = PGMGetHostMode(pVM);
686
687	pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
688	Assert(pVMCB->ctrl.u64NestedPagingCR3);
689	pVMCB->guest.u64CR3 = pCtx->cr3;
690	}
691	else
692	{
693	pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
694	Assert(pVMCB->guest.u64CR3 \|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
695	}
696	}
697
698	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
699	{
700	val = pCtx->cr4;
701	if (!pVM->hwaccm.s.fNestedPaging)
702	{
703	switch(pVCpu->hwaccm.s.enmShadowMode)
704	{
705	case PGMMODE_REAL:
706	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
707	AssertFailed();
708	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
709
710	case PGMMODE_32_BIT: /* 32-bit paging. */
711	val &= ~X86_CR4_PAE;
712	break;
713
714	case PGMMODE_PAE: /* PAE paging. */
715	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
716	/** @todo use normal 32 bits paging */
717	val \|= X86_CR4_PAE;
718	break;
719
720	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
721	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
722	#ifdef VBOX_ENABLE_64_BITS_GUESTS
723	break;
724	#else
725	AssertFailed();
726	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
727	#endif
728
729	default: /* shut up gcc */
730	AssertFailed();
731	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
732	}
733	}
734	pVMCB->guest.u64CR4 = val;
735	}
736
737	/* Debug registers. */
738	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
739	{
740	pCtx->dr[6] \|= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
741	pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
742
743	pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
744	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
745	pCtx->dr[7] \|= 0x400; /* must be one */
746
747	pVMCB->guest.u64DR7 = pCtx->dr[7];
748	pVMCB->guest.u64DR6 = pCtx->dr[6];
749
750	/* Sync the debug state now if any breakpoint is armed. */
751	if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK\|X86_DR7_GD))
752	&& !CPUMIsGuestDebugStateActive(pVCpu)
753	&& !DBGFIsStepping(pVCpu))
754	{
755	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
756
757	/* Disable drx move intercepts. */
758	pVMCB->ctrl.u16InterceptRdDRx = 0;
759	pVMCB->ctrl.u16InterceptWrDRx = 0;
760
761	/* Save the host and load the guest debug state. */
762	int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
763	AssertRC(rc);
764	}
765	}
766
767	/* EIP, ESP and EFLAGS */
768	pVMCB->guest.u64RIP = pCtx->rip;
769	pVMCB->guest.u64RSP = pCtx->rsp;
770	pVMCB->guest.u64RFlags = pCtx->eflags.u32;
771
772	/* Set CPL */
773	pVMCB->guest.u8CPL = pCtx->csHid.Attr.n.u2Dpl;
774
775	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
776	pVMCB->guest.u64RAX = pCtx->rax;
777
778	/* vmrun will fail without MSR_K6_EFER_SVME. */
779	pVMCB->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
780
781	/* 64 bits guest mode? */
782	if (CPUMIsGuestInLongModeEx(pCtx))
783	{
784	#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
785	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
786	#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
787	pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
788	#else
789	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
790	if (!pVM->hwaccm.s.fAllow64BitGuests)
791	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
792	# endif
793	pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun64;
794	#endif
795	/* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
796	pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
797	pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
798	}
799	else
800	{
801	/* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
802	pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
803
804	pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun;
805	}
806
807	/* TSC offset. */
808	if (TMCpuTickCanUseRealTSC(pVCpu, &pVMCB->ctrl.u64TSCOffset))
809	{
810	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
811	pVMCB->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
812	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
813	}
814	else
815	{
816	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
817	pVMCB->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
818	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
819	}
820
821	/* Sync the various msrs for 64 bits mode. */
822	pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
823	pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
824	pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
825	pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
826	pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
827
828	#ifdef DEBUG
829	/* Intercept X86_XCPT_DB if stepping is enabled */
830	if (DBGFIsStepping(pVCpu))
831	pVMCB->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_DB);
832	else
833	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_DB);
834	#endif
835
836	/* Done. */
837	pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
838
839	return VINF_SUCCESS;
840	}
841
842
843	/**
844	* Runs guest code in an AMD-V VM.
845	*
846	* @returns VBox status code.
847	* @param pVM The VM to operate on.
848	* @param pVCpu The VM CPU to operate on.
849	* @param pCtx Guest context
850	*/
851	VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
852	{
853	int rc = VINF_SUCCESS;
854	uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
855	SVM_VMCB *pVMCB;
856	bool fSyncTPR = false;
857	unsigned cResume = 0;
858	uint8_t u8LastTPR;
859	PHWACCM_CPUINFO pCpu = 0;
860	RTCCUINTREG uOldEFlags = ~(RTCCUINTREG)0;
861	#ifdef VBOX_STRICT
862	RTCPUID idCpuCheck;
863	#endif
864	#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
865	uint64_t u64LastTime = RTTimeMilliTS();
866	#endif
867
868	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
869
870	pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
871	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
872
873	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
874	*/
875	ResumeExecution:
876	Assert(!HWACCMR0SuspendPending());
877
878	/* Safety precaution; looping for too long here can have a very bad effect on the host */
879	if (RT_UNLIKELY(++cResume > pVM->hwaccm.s.cMaxResumeLoops))
880	{
881	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
882	rc = VINF_EM_RAW_INTERRUPT;
883	goto end;
884	}
885
886	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
887	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
888	{
889	Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
890	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
891	{
892	/* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
893	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
894	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
895	* break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
896	*/
897	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
898	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
899	pVMCB->ctrl.u64IntShadow = 0;
900	}
901	}
902	else
903	{
904	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
905	pVMCB->ctrl.u64IntShadow = 0;
906	}
907
908	#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
909	if (RT_UNLIKELY(cResume & 0xf) == 0)
910	{
911	uint64_t u64CurTime = RTTimeMilliTS();
912
913	if (RT_UNLIKELY(u64CurTime > u64LastTime))
914	{
915	u64LastTime = u64CurTime;
916	TMTimerPollVoid(pVM, pVCpu);
917	}
918	}
919	#endif
920
921	/* Check for pending actions that force us to go back to ring 3. */
922	#ifdef DEBUG
923	/* Intercept X86_XCPT_DB if stepping is enabled */
924	if (!DBGFIsStepping(pVCpu))
925	#endif
926	{
927	if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK)
928	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
929	{
930	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
931	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
932	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
933	rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
934	goto end;
935	}
936	}
937
938	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
939	if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
940	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
941	{
942	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
943	rc = VINF_EM_PENDING_REQUEST;
944	goto end;
945	}
946
947	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
948	/*
949	* Exit to ring-3 preemption/work is pending.
950	*
951	* Interrupts are disabled before the call to make sure we don't miss any interrupt
952	* that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
953	* further down, but SVMR0CheckPendingInterrupt makes that impossible.)
954	*
955	* Note! Interrupts must be disabled done before we check for TLB flushes; TLB
956	* shootdowns rely on this.
957	*/
958	uOldEFlags = ASMIntDisableFlags();
959	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
960	{
961	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);
962	rc = VINF_EM_RAW_INTERRUPT;
963	goto end;
964	}
965	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
966	#endif
967
968	/* When external interrupts are pending, we should exit the VM when IF is set. */
969	/* Note! After VM_FF_INHIBIT_INTERRUPTS check!!! */
970	rc = SVMR0CheckPendingInterrupt(pVM, pVCpu, pVMCB, pCtx);
971	if (RT_FAILURE(rc))
972	{
973	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
974	goto end;
975	}
976
977	/* TPR caching using CR8 is only available in 64 bits mode or with 32 bits guests when X86_CPUID_AMD_FEATURE_ECX_CR8L is supported. */
978	/* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!!
979	* @todo query and update the TPR only when it could have been changed (mmio access)
980	*/
981	if (pVM->hwaccm.s.fHasIoApic)
982	{
983	bool fPending;
984
985	/* TPR caching in CR8 */
986	int rc = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);
987	AssertRC(rc);
988	pVMCB->ctrl.IntCtrl.n.u8VTPR = (u8LastTPR >> 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
989
990	if (fPending)
991	{
992	/* A TPR change could activate a pending interrupt, so catch cr8 writes. */
993	pVMCB->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
994	}
995	else
996	/* No interrupts are pending, so we don't need to be explicitely notified.
997	* There are enough world switches for detecting pending interrupts.
998	*/
999	pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1000
1001	fSyncTPR = !fPending;
1002	}
1003
1004	/* All done! Let's start VM execution. */
1005	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, x);
1006
1007	/* Enable nested paging if necessary (disabled each time after #VMEXIT). */
1008	pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
1009
1010	#ifdef LOG_ENABLED
1011	pCpu = HWACCMR0GetCurrentCpu();
1012	if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1013	\|\| pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1014	{
1015	if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
1016	Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
1017	else
1018	Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1019	}
1020	if (pCpu->fFlushTLB)
1021	Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
1022	#endif
1023
1024	/*
1025	* NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1026	* (until the actual world switch)
1027	*/
1028	#ifdef VBOX_STRICT
1029	idCpuCheck = RTMpCpuId();
1030	#endif
1031	VMMR0LogFlushDisable(pVCpu);
1032
1033	/* Load the guest state; must be here as it sets up the shadow cr0 for lazy fpu syncing! */
1034	rc = SVMR0LoadGuestState(pVM, pVCpu, pCtx);
1035	if (RT_UNLIKELY(rc != VINF_SUCCESS))
1036	{
1037	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1038	VMMR0LogFlushEnable(pVCpu);
1039	goto end;
1040	}
1041
1042	#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1043	/* Disable interrupts to make sure a poke will interrupt execution.
1044	* This must be done before we check for TLB flushes; TLB shootdowns rely on this.
1045	*/
1046	uOldEFlags = ASMIntDisableFlags();
1047	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1048	#endif
1049
1050	pCpu = HWACCMR0GetCurrentCpu();
1051	/* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1052	/* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1053	if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1054	/* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1055	\|\| pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1056	{
1057	/* Force a TLB flush on VM entry. */
1058	pVCpu->hwaccm.s.fForceTLBFlush = true;
1059	}
1060	else
1061	Assert(!pCpu->fFlushTLB \|\| pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1062
1063	pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1064
1065	/* Check for tlb shootdown flushes. */
1066	if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH_BIT))
1067	pVCpu->hwaccm.s.fForceTLBFlush = true;
1068
1069	/* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1070	if ( pVCpu->hwaccm.s.fForceTLBFlush
1071	&& !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
1072	{
1073	if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1074	\|\| pCpu->fFlushTLB)
1075	{
1076	pCpu->fFlushTLB = false;
1077	pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1078	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
1079	pCpu->cTLBFlushes++;
1080	}
1081	else
1082	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1083
1084	pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1085	pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1086	}
1087	else
1088	{
1089	Assert(!pCpu->fFlushTLB \|\| pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1090
1091	/* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
1092	if (!pCpu->uCurrentASID \|\| !pVCpu->hwaccm.s.uCurrentASID)
1093	pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
1094
1095	Assert(!pVM->hwaccm.s.svm.fAlwaysFlushTLB \|\| pVCpu->hwaccm.s.fForceTLBFlush);
1096	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVCpu->hwaccm.s.fForceTLBFlush;
1097
1098	if ( !pVM->hwaccm.s.svm.fAlwaysFlushTLB
1099	&& VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1100	{
1101	/* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1102	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1103	for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1104	SVMR0InvlpgA(pVCpu->hwaccm.s.TlbShootdown.aPages[i], pVMCB->ctrl.TLBCtrl.n.u32ASID);
1105	}
1106	}
1107	pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1108	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1109
1110	AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1111	AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1112	AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1113	pVMCB->ctrl.TLBCtrl.n.u32ASID = pVCpu->hwaccm.s.uCurrentASID;
1114
1115	#ifdef VBOX_WITH_STATISTICS
1116	if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
1117	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1118	else
1119	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1120	#endif
1121
1122	/* In case we execute a goto ResumeExecution later on. */
1123	pVCpu->hwaccm.s.fResumeVM = true;
1124	pVCpu->hwaccm.s.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
1125
1126	Assert(sizeof(pVCpu->hwaccm.s.svm.pVMCBPhys) == 8);
1127	Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
1128	Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
1129	Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
1130	Assert(pVMCB->ctrl.u64LBRVirt == 0);
1131
1132	#ifdef VBOX_STRICT
1133	Assert(idCpuCheck == RTMpCpuId());
1134	#endif
1135	TMNotifyStartOfExecution(pVCpu);
1136	pVCpu->hwaccm.s.svm.pfnVMRun(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu);
1137	TMNotifyEndOfExecution(pVCpu);
1138	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
1139	ASMSetFlags(uOldEFlags);
1140	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1141	uOldEFlags = ~(RTCCUINTREG)0;
1142	#endif
1143	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, x);
1144
1145	/*
1146	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1147	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1148	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1149	*/
1150
1151	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, x);
1152
1153	/* Reason for the VM exit */
1154	exitCode = pVMCB->ctrl.u64ExitCode;
1155
1156	if (RT_UNLIKELY(exitCode == (uint64_t)SVM_EXIT_INVALID)) /* Invalid guest state. */
1157	{
1158	HWACCMDumpRegs(pVM, pVCpu, pCtx);
1159	#ifdef DEBUG
1160	Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
1161	Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
1162	Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
1163	Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
1164	Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
1165	Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
1166	Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
1167	Log(("ctrl.u64IOPMPhysAddr %RX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
1168	Log(("ctrl.u64MSRPMPhysAddr %RX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
1169	Log(("ctrl.u64TSCOffset %RX64\n", pVMCB->ctrl.u64TSCOffset));
1170
1171	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
1172	Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
1173	Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
1174	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
1175
1176	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
1177	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
1178	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
1179	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
1180	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
1181	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
1182	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
1183	Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
1184	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
1185	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
1186
1187	Log(("ctrl.u64IntShadow %RX64\n", pVMCB->ctrl.u64IntShadow));
1188	Log(("ctrl.u64ExitCode %RX64\n", pVMCB->ctrl.u64ExitCode));
1189	Log(("ctrl.u64ExitInfo1 %RX64\n", pVMCB->ctrl.u64ExitInfo1));
1190	Log(("ctrl.u64ExitInfo2 %RX64\n", pVMCB->ctrl.u64ExitInfo2));
1191	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
1192	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
1193	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
1194	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
1195	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
1196	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
1197	Log(("ctrl.NestedPaging %RX64\n", pVMCB->ctrl.NestedPaging.au64));
1198	Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
1199	Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
1200	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
1201	Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
1202	Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
1203	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
1204
1205	Log(("ctrl.u64NestedPagingCR3 %RX64\n", pVMCB->ctrl.u64NestedPagingCR3));
1206	Log(("ctrl.u64LBRVirt %RX64\n", pVMCB->ctrl.u64LBRVirt));
1207
1208	Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
1209	Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1210	Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1211	Log(("guest.CS.u64Base %RX64\n", pVMCB->guest.CS.u64Base));
1212	Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1213	Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1214	Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1215	Log(("guest.DS.u64Base %RX64\n", pVMCB->guest.DS.u64Base));
1216	Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1217	Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1218	Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1219	Log(("guest.ES.u64Base %RX64\n", pVMCB->guest.ES.u64Base));
1220	Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1221	Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1222	Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1223	Log(("guest.FS.u64Base %RX64\n", pVMCB->guest.FS.u64Base));
1224	Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1225	Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1226	Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1227	Log(("guest.GS.u64Base %RX64\n", pVMCB->guest.GS.u64Base));
1228
1229	Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1230	Log(("guest.GDTR.u64Base %RX64\n", pVMCB->guest.GDTR.u64Base));
1231
1232	Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1233	Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1234	Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1235	Log(("guest.LDTR.u64Base %RX64\n", pVMCB->guest.LDTR.u64Base));
1236
1237	Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1238	Log(("guest.IDTR.u64Base %RX64\n", pVMCB->guest.IDTR.u64Base));
1239
1240	Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1241	Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1242	Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1243	Log(("guest.TR.u64Base %RX64\n", pVMCB->guest.TR.u64Base));
1244
1245	Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1246	Log(("guest.u64CR0 %RX64\n", pVMCB->guest.u64CR0));
1247	Log(("guest.u64CR2 %RX64\n", pVMCB->guest.u64CR2));
1248	Log(("guest.u64CR3 %RX64\n", pVMCB->guest.u64CR3));
1249	Log(("guest.u64CR4 %RX64\n", pVMCB->guest.u64CR4));
1250	Log(("guest.u64DR6 %RX64\n", pVMCB->guest.u64DR6));
1251	Log(("guest.u64DR7 %RX64\n", pVMCB->guest.u64DR7));
1252
1253	Log(("guest.u64RIP %RX64\n", pVMCB->guest.u64RIP));
1254	Log(("guest.u64RSP %RX64\n", pVMCB->guest.u64RSP));
1255	Log(("guest.u64RAX %RX64\n", pVMCB->guest.u64RAX));
1256	Log(("guest.u64RFlags %RX64\n", pVMCB->guest.u64RFlags));
1257
1258	Log(("guest.u64SysEnterCS %RX64\n", pVMCB->guest.u64SysEnterCS));
1259	Log(("guest.u64SysEnterEIP %RX64\n", pVMCB->guest.u64SysEnterEIP));
1260	Log(("guest.u64SysEnterESP %RX64\n", pVMCB->guest.u64SysEnterESP));
1261
1262	Log(("guest.u64EFER %RX64\n", pVMCB->guest.u64EFER));
1263	Log(("guest.u64STAR %RX64\n", pVMCB->guest.u64STAR));
1264	Log(("guest.u64LSTAR %RX64\n", pVMCB->guest.u64LSTAR));
1265	Log(("guest.u64CSTAR %RX64\n", pVMCB->guest.u64CSTAR));
1266	Log(("guest.u64SFMASK %RX64\n", pVMCB->guest.u64SFMASK));
1267	Log(("guest.u64KernelGSBase %RX64\n", pVMCB->guest.u64KernelGSBase));
1268	Log(("guest.u64GPAT %RX64\n", pVMCB->guest.u64GPAT));
1269	Log(("guest.u64DBGCTL %RX64\n", pVMCB->guest.u64DBGCTL));
1270	Log(("guest.u64BR_FROM %RX64\n", pVMCB->guest.u64BR_FROM));
1271	Log(("guest.u64BR_TO %RX64\n", pVMCB->guest.u64BR_TO));
1272	Log(("guest.u64LASTEXCPFROM %RX64\n", pVMCB->guest.u64LASTEXCPFROM));
1273	Log(("guest.u64LASTEXCPTO %RX64\n", pVMCB->guest.u64LASTEXCPTO));
1274
1275	#endif
1276	rc = VERR_SVM_UNABLE_TO_START_VM;
1277	VMMR0LogFlushEnable(pVCpu);
1278	goto end;
1279	}
1280
1281	/* Let's first sync back eip, esp, and eflags. */
1282	pCtx->rip = pVMCB->guest.u64RIP;
1283	pCtx->rsp = pVMCB->guest.u64RSP;
1284	pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1285	/* eax is saved/restore across the vmrun instruction */
1286	pCtx->rax = pVMCB->guest.u64RAX;
1287
1288	pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
1289
1290	/* Can be updated behind our back in the nested paging case. */
1291	pCtx->cr2 = pVMCB->guest.u64CR2;
1292
1293	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1294	SVM_READ_SELREG(SS, ss);
1295	SVM_READ_SELREG(CS, cs);
1296	SVM_READ_SELREG(DS, ds);
1297	SVM_READ_SELREG(ES, es);
1298	SVM_READ_SELREG(FS, fs);
1299	SVM_READ_SELREG(GS, gs);
1300
1301	/*
1302	* System MSRs
1303	*/
1304	pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1305	pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1306	pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1307
1308	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1309	SVM_READ_SELREG(LDTR, ldtr);
1310	SVM_READ_SELREG(TR, tr);
1311
1312	pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1313	pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1314
1315	pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1316	pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1317
1318	/* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1319	/* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1320	if ( pVM->hwaccm.s.fNestedPaging
1321	&& pCtx->cr3 != pVMCB->guest.u64CR3)
1322	{
1323	CPUMSetGuestCR3(pVCpu, pVMCB->guest.u64CR3);
1324	PGMUpdateCR3(pVCpu, pVMCB->guest.u64CR3);
1325	}
1326
1327	/* Note! NOW IT'S SAFE FOR LOGGING! */
1328	VMMR0LogFlushEnable(pVCpu);
1329
1330	/* Take care of instruction fusing (sti, mov ss) (see 15.20.5 Interrupt Shadows) */
1331	if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1332	{
1333	Log(("uInterruptState %x rip=%RGv\n", pVMCB->ctrl.u64IntShadow, (RTGCPTR)pCtx->rip));
1334	EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
1335	}
1336	else
1337	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1338
1339	Log2(("exitCode = %x\n", exitCode));
1340
1341	/* Sync back DR6 as it could have been changed by hitting breakpoints. */
1342	pCtx->dr[6] = pVMCB->guest.u64DR6;
1343	/* DR7.GD can be cleared by debug exceptions, so sync it back as well. */
1344	pCtx->dr[7] = pVMCB->guest.u64DR7;
1345
1346	/* Check if an injected event was interrupted prematurely. */
1347	pVCpu->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1348	if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1349	&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1350	{
1351	Log(("Pending inject %RX64 at %RGv exit=%08x\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitCode));
1352
1353	#ifdef LOG_ENABLED
1354	SVM_EVENT Event;
1355	Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
1356
1357	if ( exitCode == SVM_EXIT_EXCEPTION_E
1358	&& Event.n.u8Vector == 0xE)
1359	{
1360	Log(("Double fault!\n"));
1361	}
1362	#endif
1363
1364	pVCpu->hwaccm.s.Event.fPending = true;
1365	/* Error code present? (redundant) */
1366	if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1367	pVCpu->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1368	else
1369	pVCpu->hwaccm.s.Event.errCode = 0;
1370	}
1371	#ifdef VBOX_WITH_STATISTICS
1372	if (exitCode == SVM_EXIT_NPF)
1373	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
1374	else
1375	STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1376	#endif
1377
1378	/* Sync back the TPR if it was changed. */
1379	if ( fSyncTPR
1380	&& (u8LastTPR >> 4) != pVMCB->ctrl.IntCtrl.n.u8VTPR)
1381	{
1382	rc = PDMApicSetTPR(pVCpu, pVMCB->ctrl.IntCtrl.n.u8VTPR << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1383	AssertRC(rc);
1384	}
1385
1386	/* Deal with the reason of the VM-exit. */
1387	switch (exitCode)
1388	{
1389	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1390	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1391	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1392	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1393	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1394	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1395	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1396	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1397	{
1398	/* Pending trap. */
1399	SVM_EVENT Event;
1400	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1401
1402	Log2(("Hardware/software interrupt %d\n", vector));
1403	switch (vector)
1404	{
1405	case X86_XCPT_DB:
1406	{
1407	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
1408
1409	/* Note that we don't support guest and host-initiated debugging at the same time. */
1410	Assert(DBGFIsStepping(pVCpu));
1411
1412	rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
1413	if (rc == VINF_EM_RAW_GUEST_TRAP)
1414	{
1415	Log(("Trap %x (debug) at %016RX64\n", vector, pCtx->rip));
1416
1417	/* Reinject the exception. */
1418	Event.au64[0] = 0;
1419	Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
1420	Event.n.u1Valid = 1;
1421	Event.n.u8Vector = X86_XCPT_DB;
1422
1423	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1424
1425	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1426	goto ResumeExecution;
1427	}
1428	/* Return to ring 3 to deal with the debug exit code. */
1429	break;
1430	}
1431
1432	case X86_XCPT_NM:
1433	{
1434	Log(("#NM fault at %RGv\n", (RTGCPTR)pCtx->rip));
1435
1436	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1437	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1438	rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
1439	if (rc == VINF_SUCCESS)
1440	{
1441	Assert(CPUMIsGuestFPUStateActive(pVCpu));
1442	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
1443
1444	/* Continue execution. */
1445	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1446	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1447
1448	goto ResumeExecution;
1449	}
1450
1451	Log(("Forward #NM fault to the guest\n"));
1452	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
1453
1454	Event.au64[0] = 0;
1455	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1456	Event.n.u1Valid = 1;
1457	Event.n.u8Vector = X86_XCPT_NM;
1458
1459	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1460	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1461	goto ResumeExecution;
1462	}
1463
1464	case X86_XCPT_PF: /* Page fault */
1465	{
1466	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1467	RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1468
1469	#ifdef DEBUG
1470	if (pVM->hwaccm.s.fNestedPaging)
1471	{ /* A genuine pagefault.
1472	* Forward the trap to the guest by injecting the exception and resuming execution.
1473	*/
1474	Log(("Guest page fault at %04X:%RGv cr2=%RGv error code %x rsp=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
1475	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1476
1477	/* Now we must update CR2. */
1478	pCtx->cr2 = uFaultAddress;
1479
1480	Event.au64[0] = 0;
1481	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1482	Event.n.u1Valid = 1;
1483	Event.n.u8Vector = X86_XCPT_PF;
1484	Event.n.u1ErrorCodeValid = 1;
1485	Event.n.u32ErrorCode = errCode;
1486
1487	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1488
1489	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1490	goto ResumeExecution;
1491	}
1492	#endif
1493	Assert(!pVM->hwaccm.s.fNestedPaging);
1494
1495	#if 0
1496	/* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1497	if ( (uFaultAddress & 0xfff) == 0x080
1498	&& pVM->hwaccm.s.fHasIoApic
1499	&& !(errCode & X86_TRAP_PF_P) /* not present */
1500	&& !CPUMIsGuestInLongModeEx(pCtx))
1501	{
1502	RTGCPHYS GCPhysApicBase, GCPhys;
1503	PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1504	GCPhysApicBase &= PAGE_BASE_GC_MASK;
1505
1506	rc = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL, &GCPhys);
1507	if ( rc == VINF_SUCCESS
1508	&& GCPhys == GCPhysApicBase)
1509	{
1510	Log(("Replace TPR access at %RGv\n", pCtx->rip));
1511
1512	DISCPUSTATE Cpu;
1513	unsigned cbOp;
1514	rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);
1515	AssertRC(rc);
1516	if ( rc == VINF_SUCCESS
1517	&& Cpu.pCurInstr->opcode == OP_MOV
1518	&& (cbOp == 5 \|\| cbOp == 6))
1519	{
1520	uint8_t szInstr[15];
1521	if ( (errCode & X86_TRAP_PF_RW)
1522	&& Cpu.param1.disp32 == (uint32_t)uFaultAddress
1523	&& Cpu.param2.flags == USE_REG_GEN32)
1524	{
1525	/* 0xF0, 0x0F, 0x22, 0xC0 = mov cr8, eax */
1526	szInstr[0] = 0xF0;
1527	szInstr[1] = 0x0F;
1528	szInstr[2] = 0x22;
1529	szInstr[3] = 0xC0 \| Cpu.param2.base.reg_gen;
1530	for (unsigned i = 4; i < cbOp; i++)
1531	szInstr[i] = 0x90; /* nop */
1532
1533	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, cbOp);
1534	AssertRC(rc);
1535
1536	Log(("Acceptable write candidate!\n"));
1537	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1538	goto ResumeExecution;
1539	}
1540	else
1541	if ( Cpu.param2.disp32 == (uint32_t)uFaultAddress
1542	&& Cpu.param1.flags == USE_REG_GEN32)
1543	{
1544	/* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1545	szInstr[0] = 0xF0;
1546	szInstr[1] = 0x0F;
1547	szInstr[2] = 0x20;
1548	szInstr[3] = 0xC0 \| Cpu.param1.base.reg_gen;
1549	for (unsigned i = 4; i < cbOp; i++)
1550	szInstr[i] = 0x90; /* nop */
1551
1552	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, cbOp);
1553	AssertRC(rc);
1554
1555	Log(("Acceptable read candidate!\n"));
1556	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1557	goto ResumeExecution;
1558	}
1559	}
1560	}
1561	}
1562	#endif
1563
1564	Log2(("Page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1565	/* Exit qualification contains the linear address of the page fault. */
1566	TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1567	TRPMSetErrorCode(pVCpu, errCode);
1568	TRPMSetFaultAddress(pVCpu, uFaultAddress);
1569
1570	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1571	rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1572	Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1573	if (rc == VINF_SUCCESS)
1574	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1575	Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1576	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1577
1578	TRPMResetTrap(pVCpu);
1579
1580	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1581	goto ResumeExecution;
1582	}
1583	else
1584	if (rc == VINF_EM_RAW_GUEST_TRAP)
1585	{ /* A genuine pagefault.
1586	* Forward the trap to the guest by injecting the exception and resuming execution.
1587	*/
1588	Log2(("Forward page fault to the guest\n"));
1589	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1590	/* The error code might have been changed. */
1591	errCode = TRPMGetErrorCode(pVCpu);
1592
1593	TRPMResetTrap(pVCpu);
1594
1595	/* Now we must update CR2. */
1596	pCtx->cr2 = uFaultAddress;
1597
1598	Event.au64[0] = 0;
1599	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1600	Event.n.u1Valid = 1;
1601	Event.n.u8Vector = X86_XCPT_PF;
1602	Event.n.u1ErrorCodeValid = 1;
1603	Event.n.u32ErrorCode = errCode;
1604
1605	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1606
1607	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1608	goto ResumeExecution;
1609	}
1610	#ifdef VBOX_STRICT
1611	if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
1612	LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
1613	#endif
1614	/* Need to go back to the recompiler to emulate the instruction. */
1615	TRPMResetTrap(pVCpu);
1616	break;
1617	}
1618
1619	case X86_XCPT_MF: /* Floating point exception. */
1620	{
1621	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
1622	if (!(pCtx->cr0 & X86_CR0_NE))
1623	{
1624	/* old style FPU error reporting needs some extra work. */
1625	/** @todo don't fall back to the recompiler, but do it manually. */
1626	rc = VINF_EM_RAW_EMULATE_INSTR;
1627	break;
1628	}
1629	Log(("Trap %x at %RGv\n", vector, (RTGCPTR)pCtx->rip));
1630
1631	Event.au64[0] = 0;
1632	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1633	Event.n.u1Valid = 1;
1634	Event.n.u8Vector = X86_XCPT_MF;
1635
1636	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1637
1638	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1639	goto ResumeExecution;
1640	}
1641
1642	#ifdef VBOX_STRICT
1643	case X86_XCPT_GP: /* General protection failure exception.*/
1644	case X86_XCPT_UD: /* Unknown opcode exception. */
1645	case X86_XCPT_DE: /* Divide error. */
1646	case X86_XCPT_SS: /* Stack segment exception. */
1647	case X86_XCPT_NP: /* Segment not present exception. */
1648	{
1649	Event.au64[0] = 0;
1650	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1651	Event.n.u1Valid = 1;
1652	Event.n.u8Vector = vector;
1653
1654	switch(vector)
1655	{
1656	case X86_XCPT_GP:
1657	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
1658	Event.n.u1ErrorCodeValid = 1;
1659	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1660	break;
1661	case X86_XCPT_DE:
1662	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
1663	break;
1664	case X86_XCPT_UD:
1665	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
1666	break;
1667	case X86_XCPT_SS:
1668	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
1669	Event.n.u1ErrorCodeValid = 1;
1670	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1671	break;
1672	case X86_XCPT_NP:
1673	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
1674	Event.n.u1ErrorCodeValid = 1;
1675	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1676	break;
1677	}
1678	Log(("Trap %x at %04x:%RGv esi=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->esi));
1679	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1680
1681	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1682	goto ResumeExecution;
1683	}
1684	#endif
1685	default:
1686	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1687	rc = VERR_EM_INTERNAL_ERROR;
1688	break;
1689
1690	} /* switch (vector) */
1691	break;
1692	}
1693
1694	case SVM_EXIT_NPF:
1695	{
1696	/* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1697	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1698	RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1699	PGMMODE enmShwPagingMode;
1700
1701	Assert(pVM->hwaccm.s.fNestedPaging);
1702	LogFlow(("Nested page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1703
1704	#if 0
1705	/* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1706	if ( (uFaultAddress & 0xfff) == 0x080
1707	&& pVM->hwaccm.s.fHasIoApic
1708	&& !(errCode & X86_TRAP_PF_P) /* not present */
1709	&& CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
1710	&& !CPUMIsGuestInLongModeEx(pCtx))
1711	{
1712	RTGCPHYS GCPhysApicBase;
1713	PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1714	GCPhysApicBase &= PAGE_BASE_GC_MASK;
1715
1716	if (uFaultAddress == GCPhysApicBase + 0x80)
1717	{
1718	rc = svmR0ReplaceTprInstr(pVM, pVCpu, pCtx);
1719	if (rc == VINF_SUCCESS)
1720	{
1721	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1722	goto ResumeExecution;
1723	}
1724
1725	rc = IOMMMIOPhysHandler(pVM, errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1726	if (rc == VINF_SUCCESS)
1727	{
1728	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1729	goto ResumeExecution; /* rip already updated */
1730	}
1731	}
1732	}
1733	#endif
1734
1735	/* Exit qualification contains the linear address of the page fault. */
1736	TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1737	TRPMSetErrorCode(pVCpu, errCode);
1738	TRPMSetFaultAddress(pVCpu, uFaultAddress);
1739
1740	/* Handle the pagefault trap for the nested shadow table. */
1741	#if HC_ARCH_BITS == 32
1742	if (CPUMIsGuestInLongModeEx(pCtx))
1743	enmShwPagingMode = PGMMODE_AMD64_NX;
1744	else
1745	#endif
1746	enmShwPagingMode = PGMGetHostMode(pVM);
1747
1748	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmShwPagingMode, errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1749	Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1750	if (rc == VINF_SUCCESS)
1751	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1752	Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1753	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1754
1755	TRPMResetTrap(pVCpu);
1756
1757	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1758	goto ResumeExecution;
1759	}
1760
1761	#ifdef VBOX_STRICT
1762	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1763	LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
1764	#endif
1765	/* Need to go back to the recompiler to emulate the instruction. */
1766	TRPMResetTrap(pVCpu);
1767	break;
1768	}
1769
1770	case SVM_EXIT_VINTR:
1771	/* A virtual interrupt is about to be delivered, which means IF=1. */
1772	Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1773	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1774	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1775	goto ResumeExecution;
1776
1777	case SVM_EXIT_FERR_FREEZE:
1778	case SVM_EXIT_INTR:
1779	case SVM_EXIT_NMI:
1780	case SVM_EXIT_SMI:
1781	case SVM_EXIT_INIT:
1782	/* External interrupt; leave to allow it to be dispatched again. */
1783	rc = VINF_EM_RAW_INTERRUPT;
1784	break;
1785
1786	case SVM_EXIT_WBINVD:
1787	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1788	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
1789	/* Skip instruction and continue directly. */
1790	pCtx->rip += 2; /* Note! hardcoded opcode size! */
1791	/* Continue execution.*/
1792	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1793	goto ResumeExecution;
1794
1795	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1796	{
1797	Log2(("SVM: Cpuid at %RGv for %x\n", (RTGCPTR)pCtx->rip, pCtx->eax));
1798	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
1799	rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1800	if (rc == VINF_SUCCESS)
1801	{
1802	/* Update EIP and continue execution. */
1803	pCtx->rip += 2; /* Note! hardcoded opcode size! */
1804	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1805	goto ResumeExecution;
1806	}
1807	AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
1808	rc = VINF_EM_RAW_EMULATE_INSTR;
1809	break;
1810	}
1811
1812	case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1813	{
1814	Log2(("SVM: Rdtsc\n"));
1815	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1816	rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1817	if (rc == VINF_SUCCESS)
1818	{
1819	/* Update EIP and continue execution. */
1820	pCtx->rip += 2; /* Note! hardcoded opcode size! */
1821	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1822	goto ResumeExecution;
1823	}
1824	rc = VINF_EM_RAW_EMULATE_INSTR;
1825	break;
1826	}
1827
1828	case SVM_EXIT_RDPMC: /* Guest software attempted to execute RDPMC. */
1829	{
1830	Log2(("SVM: Rdpmc %x\n", pCtx->ecx));
1831	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdpmc);
1832	rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1833	if (rc == VINF_SUCCESS)
1834	{
1835	/* Update EIP and continue execution. */
1836	pCtx->rip += 2; /* Note! hardcoded opcode size! */
1837	goto ResumeExecution;
1838	}
1839	rc = VINF_EM_RAW_EMULATE_INSTR;
1840	break;
1841	}
1842
1843	case SVM_EXIT_RDTSCP: /* Guest software attempted to execute RDTSCP. */
1844	{
1845	Log2(("SVM: Rdtscp\n"));
1846	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1847	rc = EMInterpretRdtscp(pVM, pVCpu, pCtx);
1848	if (rc == VINF_SUCCESS)
1849	{
1850	/* Update EIP and continue execution. */
1851	pCtx->rip += 3; /* Note! hardcoded opcode size! */
1852	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1853	goto ResumeExecution;
1854	}
1855	AssertMsgFailed(("EMU: rdtscp failed with %Rrc\n", rc));
1856	rc = VINF_EM_RAW_EMULATE_INSTR;
1857	break;
1858	}
1859
1860	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1861	{
1862	Log2(("SVM: invlpg\n"));
1863	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
1864
1865	Assert(!pVM->hwaccm.s.fNestedPaging);
1866
1867	/* Truly a pita. Why can't SVM give the same information as VT-x? */
1868	rc = svmR0InterpretInvpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1869	if (rc == VINF_SUCCESS)
1870	{
1871	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushPageInvlpg);
1872	goto ResumeExecution; /* eip already updated */
1873	}
1874	break;
1875	}
1876
1877	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1878	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1879	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1880	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1881	{
1882	uint32_t cbSize;
1883
1884	Log2(("SVM: %RGv mov cr%d, \n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
1885	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[exitCode - SVM_EXIT_WRITE_CR0]);
1886	rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
1887
1888	switch (exitCode - SVM_EXIT_WRITE_CR0)
1889	{
1890	case 0:
1891	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1892	break;
1893	case 2:
1894	break;
1895	case 3:
1896	Assert(!pVM->hwaccm.s.fNestedPaging);
1897	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1898	break;
1899	case 4:
1900	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1901	break;
1902	case 8:
1903	break;
1904	default:
1905	AssertFailed();
1906	}
1907	/* Check if a sync operation is pending. */
1908	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1909	&& VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1910	{
1911	rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1912	AssertRC(rc);
1913
1914	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBCRxChange);
1915
1916	/* Must be set by PGMSyncCR3 */
1917	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3 \|\| PGMGetGuestMode(pVCpu) <= PGMMODE_PROTECTED \|\| pVCpu->hwaccm.s.fForceTLBFlush,
1918	("rc=%Rrc mode=%d fForceTLBFlush=%RTbool\n", rc, PGMGetGuestMode(pVCpu), pVCpu->hwaccm.s.fForceTLBFlush));
1919	}
1920	if (rc == VINF_SUCCESS)
1921	{
1922	/* EIP has been updated already. */
1923
1924	/* Only resume if successful. */
1925	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1926	goto ResumeExecution;
1927	}
1928	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1929	break;
1930	}
1931
1932	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1933	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1934	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1935	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1936	{
1937	uint32_t cbSize;
1938
1939	Log2(("SVM: %RGv mov x, cr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
1940	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[exitCode - SVM_EXIT_READ_CR0]);
1941	rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
1942	if (rc == VINF_SUCCESS)
1943	{
1944	/* EIP has been updated already. */
1945
1946	/* Only resume if successful. */
1947	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1948	goto ResumeExecution;
1949	}
1950	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1951	break;
1952	}
1953
1954	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1955	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1956	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1957	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1958	{
1959	uint32_t cbSize;
1960
1961	Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
1962	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
1963
1964	if (!DBGFIsStepping(pVCpu))
1965	{
1966	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
1967
1968	/* Disable drx move intercepts. */
1969	pVMCB->ctrl.u16InterceptRdDRx = 0;
1970	pVMCB->ctrl.u16InterceptWrDRx = 0;
1971
1972	/* Save the host and load the guest debug state. */
1973	rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
1974	AssertRC(rc);
1975
1976	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1977	goto ResumeExecution;
1978	}
1979
1980	rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
1981	if (rc == VINF_SUCCESS)
1982	{
1983	/* EIP has been updated already. */
1984	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_DEBUG;
1985
1986	/* Only resume if successful. */
1987	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1988	goto ResumeExecution;
1989	}
1990	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1991	break;
1992	}
1993
1994	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1995	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1996	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1997	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1998	{
1999	uint32_t cbSize;
2000
2001	Log2(("SVM: %RGv mov x, dr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
2002	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
2003
2004	if (!DBGFIsStepping(pVCpu))
2005	{
2006	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2007
2008	/* Disable drx move intercepts. */
2009	pVMCB->ctrl.u16InterceptRdDRx = 0;
2010	pVMCB->ctrl.u16InterceptWrDRx = 0;
2011
2012	/* Save the host and load the guest debug state. */
2013	rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2014	AssertRC(rc);
2015
2016	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2017	goto ResumeExecution;
2018	}
2019
2020	rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2021	if (rc == VINF_SUCCESS)
2022	{
2023	/* EIP has been updated already. */
2024
2025	/* Only resume if successful. */
2026	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2027	goto ResumeExecution;
2028	}
2029	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
2030	break;
2031	}
2032
2033	/* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2034	case SVM_EXIT_IOIO: /* I/O instruction. */
2035	{
2036	SVM_IOIO_EXIT IoExitInfo;
2037	uint32_t uIOSize, uAndVal;
2038
2039	IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
2040
2041	/** @todo could use a lookup table here */
2042	if (IoExitInfo.n.u1OP8)
2043	{
2044	uIOSize = 1;
2045	uAndVal = 0xff;
2046	}
2047	else
2048	if (IoExitInfo.n.u1OP16)
2049	{
2050	uIOSize = 2;
2051	uAndVal = 0xffff;
2052	}
2053	else
2054	if (IoExitInfo.n.u1OP32)
2055	{
2056	uIOSize = 4;
2057	uAndVal = 0xffffffff;
2058	}
2059	else
2060	{
2061	AssertFailed(); /* should be fatal. */
2062	rc = VINF_EM_RAW_EMULATE_INSTR;
2063	break;
2064	}
2065
2066	if (IoExitInfo.n.u1STR)
2067	{
2068	/* ins/outs */
2069	PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2070
2071	/* Disassemble manually to deal with segment prefixes. */
2072	rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL);
2073	if (rc == VINF_SUCCESS)
2074	{
2075	if (IoExitInfo.n.u1Type == 0)
2076	{
2077	Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2078	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
2079	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize);
2080	}
2081	else
2082	{
2083	Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2084	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
2085	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize);
2086	}
2087	}
2088	else
2089	rc = VINF_EM_RAW_EMULATE_INSTR;
2090	}
2091	else
2092	{
2093	/* normal in/out */
2094	Assert(!IoExitInfo.n.u1REP);
2095
2096	if (IoExitInfo.n.u1Type == 0)
2097	{
2098	Log2(("IOMIOPortWrite %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
2099	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
2100	rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
2101	}
2102	else
2103	{
2104	uint32_t u32Val = 0;
2105
2106	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
2107	rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
2108	if (IOM_SUCCESS(rc))
2109	{
2110	/* Write back to the EAX register. */
2111	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
2112	Log2(("IOMIOPortRead %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
2113	}
2114	}
2115	}
2116	/*
2117	* Handled the I/O return codes.
2118	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2119	*/
2120	if (IOM_SUCCESS(rc))
2121	{
2122	/* Update EIP and continue execution. */
2123	pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
2124	if (RT_LIKELY(rc == VINF_SUCCESS))
2125	{
2126	/* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
2127	if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
2128	{
2129	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
2130	for (unsigned i=0;i<4;i++)
2131	{
2132	unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
2133
2134	if ( (IoExitInfo.n.u16Port >= pCtx->dr[i] && IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen)
2135	&& (pCtx->dr[7] & (X86_DR7_L(i) \| X86_DR7_G(i)))
2136	&& (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
2137	{
2138	SVM_EVENT Event;
2139
2140	Assert(CPUMIsGuestDebugStateActive(pVCpu));
2141
2142	/* Clear all breakpoint status flags and set the one we just hit. */
2143	pCtx->dr[6] &= ~(X86_DR6_B0\|X86_DR6_B1\|X86_DR6_B2\|X86_DR6_B3);
2144	pCtx->dr[6] \|= (uint64_t)RT_BIT(i);
2145
2146	/* Note: AMD64 Architecture Programmer's Manual 13.1:
2147	* Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
2148	* the contents have been read.
2149	*/
2150	pVMCB->guest.u64DR6 = pCtx->dr[6];
2151
2152	/* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2153	pCtx->dr[7] &= ~X86_DR7_GD;
2154
2155	/* Paranoia. */
2156	pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2157	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
2158	pCtx->dr[7] \|= 0x400; /* must be one */
2159
2160	pVMCB->guest.u64DR7 = pCtx->dr[7];
2161
2162	/* Inject the exception. */
2163	Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
2164
2165	Event.au64[0] = 0;
2166	Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
2167	Event.n.u1Valid = 1;
2168	Event.n.u8Vector = X86_XCPT_DB;
2169
2170	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2171
2172	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2173	goto ResumeExecution;
2174	}
2175	}
2176	}
2177
2178	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2179	goto ResumeExecution;
2180	}
2181	Log2(("EM status from IO at %RGv %x size %d: %Rrc\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
2182	break;
2183	}
2184
2185	#ifdef VBOX_STRICT
2186	if (rc == VINF_IOM_HC_IOPORT_READ)
2187	Assert(IoExitInfo.n.u1Type != 0);
2188	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2189	Assert(IoExitInfo.n.u1Type == 0);
2190	else
2191	AssertMsg(RT_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
2192	#endif
2193	Log2(("Failed IO at %RGv %x size %d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2194	break;
2195	}
2196
2197	case SVM_EXIT_HLT:
2198	/** Check if external interrupts are pending; if so, don't switch back. */
2199	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
2200	pCtx->rip++; /* skip hlt */
2201	if ( pCtx->eflags.Bits.u1IF
2202	&& VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC\|VMCPU_FF_INTERRUPT_PIC)))
2203	goto ResumeExecution;
2204
2205	rc = VINF_EM_HALT;
2206	break;
2207
2208	case SVM_EXIT_MWAIT_UNCOND:
2209	Log2(("SVM: mwait\n"));
2210	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMwait);
2211	rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2212	if ( rc == VINF_EM_HALT
2213	\|\| rc == VINF_SUCCESS)
2214	{
2215	/* Update EIP and continue execution. */
2216	pCtx->rip += 3; /* Note: hardcoded opcode size assumption! */
2217
2218	/** Check if external interrupts are pending; if so, don't switch back. */
2219	if ( rc == VINF_SUCCESS
2220	\|\| ( rc == VINF_EM_HALT
2221	&& pCtx->eflags.Bits.u1IF
2222	&& VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC\|VMCPU_FF_INTERRUPT_PIC)))
2223	)
2224	goto ResumeExecution;
2225	}
2226	AssertMsg(rc == VERR_EM_INTERPRETER \|\| rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", rc));
2227	break;
2228
2229	case SVM_EXIT_RSM:
2230	case SVM_EXIT_INVLPGA:
2231	case SVM_EXIT_VMRUN:
2232	case SVM_EXIT_VMMCALL:
2233	case SVM_EXIT_VMLOAD:
2234	case SVM_EXIT_VMSAVE:
2235	case SVM_EXIT_STGI:
2236	case SVM_EXIT_CLGI:
2237	case SVM_EXIT_SKINIT:
2238	{
2239	/* Unsupported instructions. */
2240	SVM_EVENT Event;
2241
2242	Event.au64[0] = 0;
2243	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2244	Event.n.u1Valid = 1;
2245	Event.n.u8Vector = X86_XCPT_UD;
2246
2247	Log(("Forced #UD trap at %RGv\n", (RTGCPTR)pCtx->rip));
2248	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2249
2250	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2251	goto ResumeExecution;
2252	}
2253
2254	/* Emulate in ring 3. */
2255	case SVM_EXIT_MSR:
2256	{
2257	uint32_t cbSize;
2258
2259	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2260	STAM_COUNTER_INC((pVMCB->ctrl.u64ExitInfo1 == 0) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
2261	Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
2262	rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2263	if (rc == VINF_SUCCESS)
2264	{
2265	/* EIP has been updated already. */
2266
2267	/* Only resume if successful. */
2268	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2269	goto ResumeExecution;
2270	}
2271	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
2272	break;
2273	}
2274
2275	case SVM_EXIT_MONITOR:
2276	case SVM_EXIT_PAUSE:
2277	case SVM_EXIT_MWAIT_ARMED:
2278	case SVM_EXIT_TASK_SWITCH: /* can change CR3; emulate */
2279	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2280	break;
2281
2282	case SVM_EXIT_SHUTDOWN:
2283	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2284	break;
2285
2286	case SVM_EXIT_IDTR_READ:
2287	case SVM_EXIT_GDTR_READ:
2288	case SVM_EXIT_LDTR_READ:
2289	case SVM_EXIT_TR_READ:
2290	case SVM_EXIT_IDTR_WRITE:
2291	case SVM_EXIT_GDTR_WRITE:
2292	case SVM_EXIT_LDTR_WRITE:
2293	case SVM_EXIT_TR_WRITE:
2294	case SVM_EXIT_CR0_SEL_WRITE:
2295	default:
2296	/* Unexpected exit codes. */
2297	rc = VERR_EM_INTERNAL_ERROR;
2298	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
2299	break;
2300	}
2301
2302	end:
2303
2304	/* Signal changes for the recompiler. */
2305	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
2306
2307	/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
2308	if (exitCode == SVM_EXIT_INTR)
2309	{
2310	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
2311	/* On the next entry we'll only sync the host context. */
2312	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
2313	}
2314	else
2315	{
2316	/* On the next entry we'll sync everything. */
2317	/** @todo we can do better than this */
2318	/* Not in the VINF_PGM_CHANGE_MODE though! */
2319	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
2320	}
2321
2322	/* translate into a less severe return code */
2323	if (rc == VERR_EM_INTERPRETER)
2324	rc = VINF_EM_RAW_EMULATE_INSTR;
2325
2326	/* Just set the correct state here instead of trying to catch every goto above. */
2327	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
2328
2329	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2330	/* Restore interrupts if we exitted after disabling them. */
2331	if (uOldEFlags != ~(RTCCUINTREG)0)
2332	ASMSetFlags(uOldEFlags);
2333	#endif
2334
2335	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2336	return rc;
2337	}
2338
2339	/**
2340	* Emulate simple mov tpr instruction
2341	*
2342	* @returns VBox status code.
2343	* @param pVCpu The VM CPU to operate on.
2344	* @param pDis Disassembly state
2345	* @param pCtx CPU context
2346	* @param cbOp Opcode size
2347	*/
2348	static int svmR0EmulateTprMov(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTX pCtx, unsigned cbOp)
2349	{
2350	int rc;
2351
2352	if (pDis->param1.flags == USE_DISPLACEMENT32)
2353	{
2354	/* write */
2355	uint8_t u8Tpr;
2356
2357	/* Fetch the new TPR value */
2358	if (pDis->param2.flags == USE_REG_GEN32)
2359	{
2360	uint32_t val;
2361
2362	rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pDis->param2.base.reg_gen, &val);
2363	AssertRC(rc);
2364	u8Tpr = val;
2365	}
2366	else
2367	if (pDis->param2.flags == USE_IMMEDIATE32)
2368	{
2369	u8Tpr = (uint8_t)pDis->param2.parval;
2370	}
2371	else
2372	return VERR_EM_INTERPRETER;
2373
2374	rc = PDMApicSetTPR(pVCpu, u8Tpr);
2375	AssertRC(rc);
2376
2377	Log(("Emulated write successfully\n"));
2378	pCtx->rip += cbOp;
2379	return VINF_SUCCESS;
2380	}
2381	else
2382	if (pDis->param2.flags == USE_DISPLACEMENT32)
2383	{
2384	/* read */
2385	bool fPending;
2386	uint8_t u8Tpr;
2387
2388	/* TPR caching in CR8 */
2389	rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending);
2390	AssertRC(rc);
2391
2392	rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pDis->param1.base.reg_gen, u8Tpr);
2393	AssertRC(rc);
2394
2395	Log(("Emulated read successfully\n"));
2396	pCtx->rip += cbOp;
2397	return VINF_SUCCESS;
2398	}
2399	return VERR_EM_INTERPRETER;
2400	}
2401
2402	/**
2403	* Attempt to patch TPR mmio instructions
2404	*
2405	* @returns VBox status code.
2406	* @param pVM The VM to operate on.
2407	* @param pVCpu The VM CPU to operate on.
2408	* @param pCtx CPU context
2409	*/
2410	static int svmR0ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2411	{
2412	RTGCPTR oldrip = pCtx->rip;
2413	PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2414	unsigned cbOp;
2415
2416	Log(("Replace TPR access at %RGv\n", pCtx->rip));
2417
2418	int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
2419	AssertRC(rc);
2420	if ( rc == VINF_SUCCESS
2421	&& pDis->pCurInstr->opcode == OP_MOV)
2422	{
2423	#if 0
2424	uint8_t szInstr[15];
2425	if ( cbOp == 10
2426	&& pDis->param1.flags == USE_DISPLACEMENT32
2427	&& pDis->param2.flags == USE_IMMEDIATE32)
2428	{
2429	/* Found:
2430	* mov [fffe0080], immediate_dword (10 bytes)
2431	*
2432	* Replace with:
2433	* mov free_register, immediate_dword >> 4 (5 bytes)
2434	* mov cr8, free_register (4 bytes)
2435	* nop (1 byte)
2436	*
2437	*/
2438	uint32_t u32tpr = (uint32_t)pDis->param2.parval;
2439
2440	u32tpr = (u32tpr >> 4) & 0xf;
2441
2442	/* Check if the next instruction overwrites a general purpose register. If
2443	* it does, then we can safely use it ourselves.
2444	*/
2445	pCtx->rip += cbOp;
2446	rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
2447	pCtx->rip = oldrip;
2448	if ( rc == VINF_SUCCESS
2449	&& pDis->pCurInstr->opcode == OP_MOV
2450	&& pDis->param1.flags == USE_REG_GEN32)
2451	{
2452	/* 0xB8, dword immediate = mov eax, dword immediate */
2453	szInstr[0] = 0xB8 + pDis->param1.base.reg_gen;
2454	szInstr[1] = (uint8_t)u32tpr;
2455	szInstr[2] = 0;
2456	szInstr[3] = 0;
2457	szInstr[4] = 0;
2458
2459	/* 0xF0, 0x0F, 0x22, 0xC0 = mov cr8, eax */
2460	szInstr[5] = 0xF0;
2461	szInstr[6] = 0x0F;
2462	szInstr[7] = 0x22;
2463	szInstr[8] = 0xC0 \| pDis->param1.base.reg_gen;
2464	szInstr[9] = 0x90; /* nop */
2465
2466	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, 10);
2467	AssertRC(rc);
2468
2469	Log(("Acceptable write candidate!\n"));
2470	return VINF_SUCCESS;
2471	}
2472	}
2473	else
2474	{
2475	if ( pDis->param2.flags == USE_REG_GEN32
2476	&& cbOp == 6)
2477	{
2478	RTGCPTR GCPtrTpr = (uint32_t)pDis->param1.disp32;
2479	uint32_t uMmioReg = pDis->param2.base.reg_gen;
2480
2481	/* Found:
2482	* mov dword [fffe0080], eax (6 bytes)
2483	* Check if next instruction is a TPR read:
2484	* mov ecx, dword [fffe0080] (5 bytes)
2485	*/
2486	pCtx->rip += cbOp;
2487	rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
2488	pCtx->rip = oldrip;
2489	if ( rc == VINF_SUCCESS
2490	&& pDis->pCurInstr->opcode == OP_MOV
2491	&& pDis->param1.flags == USE_REG_GEN32
2492	&& pDis->param2.flags == USE_DISPLACEMENT32
2493	&& pDis->param2.disp32 == (uint32_t)GCPtrTpr
2494	&& cbOp == 5)
2495	{
2496	/* mov new_reg, uMmioReg */
2497	szInstr[0] = 0x89;
2498	szInstr[1] = MAKE_MODRM(3, uMmioReg, pDis->param1.base.reg_gen);
2499
2500	/* Let's hope the guest won't mind us trashing the source register...
2501	* shr uMmioReg, 4
2502	*/
2503	szInstr[2] = 0xC1;
2504	szInstr[3] = 0xE8 \| uMmioReg;
2505	szInstr[4] = 4;
2506
2507	/* 0xF0, 0x0F, 0x22, 0xC0 = mov cr8, eax */
2508	szInstr[5] = 0xF0;
2509	szInstr[6] = 0x0F;
2510	szInstr[7] = 0x22;
2511	szInstr[8] = 0xC0 \| uMmioReg;
2512
2513	/* Two nop instructions */
2514	szInstr[9] = 0x90;
2515	szInstr[10] = 0x90;
2516
2517	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, 6+cbOp);
2518	AssertRC(rc);
2519
2520	Log(("Acceptable read/write candidate!\n"));
2521	return VINF_SUCCESS;
2522	}
2523	}
2524	else
2525	if ( pDis->param1.flags == USE_REG_GEN32
2526	&& cbOp == 5)
2527	{
2528	uint32_t uMmioReg = pDis->param1.base.reg_gen;
2529
2530	/* Found:
2531	* mov eax, dword [fffe0080] (5 bytes)
2532	* Check if next instruction is:
2533	* shr eax, 4
2534	*/
2535	pCtx->rip += cbOp;
2536	rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
2537	pCtx->rip = oldrip;
2538	if ( rc == VINF_SUCCESS
2539	&& pDis->pCurInstr->opcode == OP_SHR
2540	&& pDis->param1.flags == USE_REG_GEN32
2541	&& pDis->param1.base.reg_gen == uMmioReg
2542	&& pDis->param2.flags == USE_IMMEDIATE8
2543	&& pDis->param2.parval == 4)
2544	{
2545	/* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
2546	szInstr[0] = 0xF0;
2547	szInstr[1] = 0x0F;
2548	szInstr[2] = 0x20;
2549	szInstr[3] = 0xC0 \| pDis->param1.base.reg_gen;
2550	for (unsigned i = 4; i < 5+cbOp; i++)
2551	szInstr[i] = 0x90; /* nop */
2552
2553	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, 5+cbOp);
2554	AssertRC(rc);
2555
2556	Log(("Acceptable read candidate!\n"));
2557	return VINF_SUCCESS;
2558	}
2559	}
2560	}
2561	#endif
2562	rc = svmR0EmulateTprMov(pVCpu, pDis, pCtx, cbOp);
2563	if (rc != VINF_SUCCESS)
2564	return rc;
2565
2566	/* Emulated successfully, so continue. */
2567	return VINF_SUCCESS;
2568	}
2569	return VERR_ACCESS_DENIED;
2570	}
2571
2572	/**
2573	* Enters the AMD-V session
2574	*
2575	* @returns VBox status code.
2576	* @param pVM The VM to operate on.
2577	* @param pVCpu The VM CPU to operate on.
2578	* @param pCpu CPU info struct
2579	*/
2580	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
2581	{
2582	Assert(pVM->hwaccm.s.svm.fSupported);
2583
2584	LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVCpu->hwaccm.s.idLastCpu, pVCpu->hwaccm.s.uCurrentASID));
2585	pVCpu->hwaccm.s.fResumeVM = false;
2586
2587	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
2588	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_LDTR;
2589
2590	return VINF_SUCCESS;
2591	}
2592
2593
2594	/**
2595	* Leaves the AMD-V session
2596	*
2597	* @returns VBox status code.
2598	* @param pVM The VM to operate on.
2599	* @param pVCpu The VM CPU to operate on.
2600	* @param pCtx CPU context
2601	*/
2602	VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2603	{
2604	SVM_VMCB pVMCB = (SVM_VMCB )pVCpu->hwaccm.s.svm.pVMCB;
2605
2606	Assert(pVM->hwaccm.s.svm.fSupported);
2607
2608	/* Save the guest debug state if necessary. */
2609	if (CPUMIsGuestDebugStateActive(pVCpu))
2610	{
2611	CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, false /* skip DR6 */);
2612
2613	/* Intercept all DRx reads and writes again. Changed later on. */
2614	pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
2615	pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
2616
2617	/* Resync the debug registers the next time. */
2618	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_DEBUG;
2619	}
2620	else
2621	Assert(pVMCB->ctrl.u16InterceptRdDRx == 0xFFFF && pVMCB->ctrl.u16InterceptWrDRx == 0xFFFF);
2622
2623	return VINF_SUCCESS;
2624	}
2625
2626
2627	static int svmR0InterpretInvlPg(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2628	{
2629	OP_PARAMVAL param1;
2630	RTGCPTR addr;
2631
2632	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2633	if(RT_FAILURE(rc))
2634	return VERR_EM_INTERPRETER;
2635
2636	switch(param1.type)
2637	{
2638	case PARMTYPE_IMMEDIATE:
2639	case PARMTYPE_ADDRESS:
2640	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
2641	return VERR_EM_INTERPRETER;
2642	addr = param1.val.val64;
2643	break;
2644
2645	default:
2646	return VERR_EM_INTERPRETER;
2647	}
2648
2649	/** @todo is addr always a flat linear address or ds based
2650	* (in absence of segment override prefixes)????
2651	*/
2652	rc = PGMInvalidatePage(pVCpu, addr);
2653	if (RT_SUCCESS(rc))
2654	{
2655	/* Manually invalidate the page for the VM's TLB. */
2656	Log(("SVMR0InvlpgA %RGv ASID=%d\n", addr, uASID));
2657	SVMR0InvlpgA(addr, uASID);
2658	return VINF_SUCCESS;
2659	}
2660	AssertRC(rc);
2661	return rc;
2662	}
2663
2664	/**
2665	* Interprets INVLPG
2666	*
2667	* @returns VBox status code.
2668	* @retval VINF_* Scheduling instructions.
2669	* @retval VERR_EM_INTERPRETER Something we can't cope with.
2670	* @retval VERR_* Fatal errors.
2671	*
2672	* @param pVM The VM handle.
2673	* @param pRegFrame The register frame.
2674	* @param ASID Tagged TLB id for the guest
2675	*
2676	* Updates the EIP if an instruction was executed successfully.
2677	*/
2678	static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2679	{
2680	/*
2681	* Only allow 32 & 64 bits code.
2682	*/
2683	DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
2684	if (enmMode != CPUMODE_16BIT)
2685	{
2686	RTGCPTR pbCode;
2687	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
2688	if (RT_SUCCESS(rc))
2689	{
2690	uint32_t cbOp;
2691	PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2692
2693	pDis->mode = enmMode;
2694	rc = EMInterpretDisasOneEx(pVM, pVCpu, pbCode, pRegFrame, pDis, &cbOp);
2695	Assert(RT_FAILURE(rc) \|\| pDis->pCurInstr->opcode == OP_INVLPG);
2696	if (RT_SUCCESS(rc) && pDis->pCurInstr->opcode == OP_INVLPG)
2697	{
2698	Assert(cbOp == pDis->opsize);
2699	rc = svmR0InterpretInvlPg(pVCpu, pDis, pRegFrame, uASID);
2700	if (RT_SUCCESS(rc))
2701	{
2702	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
2703	}
2704	return rc;
2705	}
2706	}
2707	}
2708	return VERR_EM_INTERPRETER;
2709	}
2710
2711
2712	/**
2713	* Invalidates a guest page
2714	*
2715	* @returns VBox status code.
2716	* @param pVM The VM to operate on.
2717	* @param pVCpu The VM CPU to operate on.
2718	* @param GCVirt Page to invalidate
2719	*/
2720	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
2721	{
2722	bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB \| pVCpu->hwaccm.s.fForceTLBFlush;
2723
2724	/* Skip it if a TLB flush is already pending. */
2725	if (!fFlushPending)
2726	{
2727	SVM_VMCB *pVMCB;
2728
2729	Log2(("SVMR0InvalidatePage %RGv\n", GCVirt));
2730	AssertReturn(pVM, VERR_INVALID_PARAMETER);
2731	Assert(pVM->hwaccm.s.svm.fSupported);
2732
2733	/* @todo SMP */
2734	pVMCB = (SVM_VMCB *)pVM->aCpus[0].hwaccm.s.svm.pVMCB;
2735	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2736
2737	#if HC_ARCH_BITS == 32
2738	/* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invlpga takes only 32 bits addresses. */
2739	if (CPUMIsGuestInLongMode(pVCpu))
2740	pVCpu->hwaccm.s.fForceTLBFlush = true;
2741	else
2742	#endif
2743	SVMR0InvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2744	}
2745	return VINF_SUCCESS;
2746	}
2747
2748
2749	#if 0 /* obsolete, but left here for clarification. */
2750	/**
2751	* Invalidates a guest page by physical address
2752	*
2753	* @returns VBox status code.
2754	* @param pVM The VM to operate on.
2755	* @param pVCpu The VM CPU to operate on.
2756	* @param GCPhys Page to invalidate
2757	*/
2758	VMMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
2759	{
2760	Assert(pVM->hwaccm.s.fNestedPaging);
2761	/* invlpga only invalidates TLB entries for guest virtual addresses; we have no choice but to force a TLB flush here. */
2762	pVCpu->hwaccm.s.fForceTLBFlush = true;
2763	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBInvlpga);
2764	return VINF_SUCCESS;
2765	}
2766	#endif
2767
2768	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2769	/**
2770	* Prepares for and executes VMRUN (64 bits guests from a 32 bits hosts).
2771	*
2772	* @returns VBox status code.
2773	* @param pVMCBHostPhys Physical address of host VMCB.
2774	* @param pVMCBPhys Physical address of the VMCB.
2775	* @param pCtx Guest context.
2776	* @param pVM The VM to operate on.
2777	* @param pVCpu The VMCPU to operate on.
2778	*/
2779	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
2780	{
2781	uint32_t aParam[4];
2782
2783	aParam[0] = (uint32_t)(pVMCBHostPhys); /* Param 1: pVMCBHostPhys - Lo. */
2784	aParam[1] = (uint32_t)(pVMCBHostPhys >> 32); /* Param 1: pVMCBHostPhys - Hi. */
2785	aParam[2] = (uint32_t)(pVMCBPhys); /* Param 2: pVMCBPhys - Lo. */
2786	aParam[3] = (uint32_t)(pVMCBPhys >> 32); /* Param 2: pVMCBPhys - Hi. */
2787
2788	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSVMGCVMRun64, 4, &aParam[0]);
2789	}
2790
2791	/**
2792	* Executes the specified handler in 64 mode
2793	*
2794	* @returns VBox status code.
2795	* @param pVM The VM to operate on.
2796	* @param pVCpu The VMCPU to operate on.
2797	* @param pCtx Guest context
2798	* @param pfnHandler RC handler
2799	* @param cbParam Number of parameters
2800	* @param paParam Array of 32 bits parameters
2801	*/
2802	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
2803	{
2804	int rc;
2805	RTHCUINTREG uOldEFlags;
2806
2807	/* @todo This code is not guest SMP safe (hyper stack and switchers) */
2808	AssertReturn(pVM->cCPUs == 1, VERR_TOO_MANY_CPUS);
2809	Assert(pfnHandler);
2810
2811	uOldEFlags = ASMIntDisableFlags();
2812
2813	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVM));
2814	CPUMSetHyperEIP(pVCpu, pfnHandler);
2815	for (int i=(int)cbParam-1;i>=0;i--)
2816	CPUMPushHyper(pVCpu, paParam[i]);
2817
2818	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2819	/* Call switcher. */
2820	rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM);
2821	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2822
2823	ASMSetFlags(uOldEFlags);
2824	return rc;
2825	}
2826
2827	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 20769

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