HWSVMR0.cpp@ 2097

Last change on this file since 2097 was 2097, checked in by vboxsync, 18 years ago
X86_CR0_PG must always be set in the guest CR0.
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1	/* $Id: HWSVMR0.cpp 2097 2007-04-16 12:42:34Z vboxsync $ */
2	/** @file
3	* HWACCM SVM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_svm.h>
32	#include <VBox/pgm.h>
33	#include <VBox/pdm.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <VBox/selm.h>
37	#include <VBox/iom.h>
38	#include <VBox/dis.h>
39	#include <VBox/disopcode.h>
40	#include <iprt/param.h>
41	#include <iprt/assert.h>
42	#include <iprt/asm.h>
43	#include "HWSVMR0.h"
44
45	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
46
47	/**
48	* Sets up and activates SVM
49	*
50	* @returns VBox status code.
51	* @param pVM The VM to operate on.
52	*/
53	HWACCMR0DECL(int) SVMR0Setup(PVM pVM)
54	{
55	int rc = VINF_SUCCESS;
56	SVM_VMCB *pVMCB;
57
58	if (pVM == NULL)
59	return VERR_INVALID_PARAMETER;
60
61	/* Setup AMD SVM. */
62	Assert(pVM->hwaccm.s.svm.fSupported);
63
64	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
65	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
66
67	/* Program the control fields. Most of them never have to be changed again. */
68	/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
69	/** @note CR0 & CR4 can be safely read when guest and shadow copies are identical. */
70	pVMCB->ctrl.u16InterceptRdCRx = BIT(0) \| BIT(3) \| BIT(4) \| BIT(8);
71
72	/*
73	* CR0/3/4 writes must be intercepted for obvious reasons.
74	*/
75	pVMCB->ctrl.u16InterceptWrCRx = BIT(0) \| BIT(3) \| BIT(4) \| BIT(8);
76
77	/* Intercept all DRx reads and writes. */
78	pVMCB->ctrl.u16InterceptRdDRx = BIT(0) \| BIT(1) \| BIT(2) \| BIT(3) \| BIT(4) \| BIT(5) \| BIT(6) \| BIT(7);
79	pVMCB->ctrl.u16InterceptWrDRx = BIT(0) \| BIT(1) \| BIT(2) \| BIT(3) \| BIT(4) \| BIT(5) \| BIT(6) \| BIT(7);
80
81	/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
82	* All breakpoints are automatically cleared when the VM exits.
83	*/
84
85	/** @todo nested paging */
86	/* Intercept #NM only; #PF is not relevant due to nested paging (we get a seperate exit code (SVM_EXIT_NPF) for
87	* pagefaults that need our attention).
88	*/
89	pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
90
91	pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
92	\| SVM_CTRL1_INTERCEPT_VINTR
93	\| SVM_CTRL1_INTERCEPT_NMI
94	\| SVM_CTRL1_INTERCEPT_SMI
95	\| SVM_CTRL1_INTERCEPT_INIT
96	\| SVM_CTRL1_INTERCEPT_CR0 /** @todo redundant? */
97	\| SVM_CTRL1_INTERCEPT_RDPMC
98	\| SVM_CTRL1_INTERCEPT_CPUID
99	\| SVM_CTRL1_INTERCEPT_RSM
100	\| SVM_CTRL1_INTERCEPT_HLT
101	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
102	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
103	\| SVM_CTRL1_INTERCEPT_INVLPG
104	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
105	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
106	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
107	;
108	pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
109	\| SVM_CTRL2_INTERCEPT_VMMCALL
110	\| SVM_CTRL2_INTERCEPT_VMLOAD
111	\| SVM_CTRL2_INTERCEPT_VMSAVE
112	\| SVM_CTRL2_INTERCEPT_STGI
113	\| SVM_CTRL2_INTERCEPT_CLGI
114	\| SVM_CTRL2_INTERCEPT_SKINIT
115	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
116	;
117	Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
118	Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
119	Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
120
121	/* Virtualize masking of INTR interrupts. */
122	pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
123
124	/* Set IO and MSR bitmap addresses. */
125	pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
126	pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
127
128	/* Enable nested paging. */
129	/** @todo how to detect support for this?? */
130	pVMCB->ctrl.u64NestedPaging = 0; /** @todo SVM_NESTED_PAGING_ENABLE; */
131
132	/* No LBR virtualization. */
133	pVMCB->ctrl.u64LBRVirt = 0;
134
135	return rc;
136	}
137
138
139	/**
140	* Injects an event (trap or external interrupt)
141	*
142	* @param pVM The VM to operate on.
143	* @param pVMCB SVM control block
144	* @param pCtx CPU Context
145	* @param pIntInfo SVM interrupt info
146	*/
147	inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx, SVM_EVENT* pEvent)
148	{
149	#ifdef VBOX_STRICT
150	if (pEvent->n.u8Vector == 0xE)
151	Log(("SVMR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
152	else
153	if (pEvent->n.u8Vector < 0x20)
154	Log(("SVMR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode));
155	else
156	{
157	Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->eip));
158	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
159	Assert(pCtx->eflags.u32 & X86_EFL_IF);
160	}
161	#endif
162
163	/* Set event injection state. */
164	pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
165	}
166
167
168	/**
169	* Checks for pending guest interrupts and injects them
170	*
171	* @returns VBox status code.
172	* @param pVM The VM to operate on.
173	* @param pVMCB SVM control block
174	* @param pCtx CPU Context
175	*/
176	static int SVMR0CheckPendingInterrupt(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx)
177	{
178	int rc;
179
180	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
181	if (pVM->hwaccm.s.Event.fPending)
182	{
183	SVM_EVENT Event;
184
185	Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
186	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
187	Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
188	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
189
190	pVM->hwaccm.s.Event.fPending = false;
191	return VINF_SUCCESS;
192	}
193
194	/* When external interrupts are pending, we should exit the VM when IF is set. */
195	if ( !TRPMHasTrap(pVM)
196	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
197	{
198	if (!(pCtx->eflags.u32 & X86_EFL_IF))
199	{
200	Log2(("Enable irq window exit!\n"));
201	/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
202	//// pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
203	//// AssertRC(rc);
204	}
205	else
206	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
207	{
208	uint8_t u8Interrupt;
209
210	rc = PDMGetInterrupt(pVM, &u8Interrupt);
211	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
212	if (VBOX_SUCCESS(rc))
213	{
214	rc = TRPMAssertTrap(pVM, u8Interrupt, false);
215	AssertRC(rc);
216	}
217	else
218	{
219	/* can't happen... */
220	AssertFailed();
221	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
222	return VINF_EM_RAW_INTERRUPT_PENDING;
223	}
224	}
225	else
226	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
227	}
228
229	#ifdef VBOX_STRICT
230	if (TRPMHasTrap(pVM))
231	{
232	uint8_t u8Vector;
233	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
234	AssertRC(rc);
235	Assert(u8Vector >= 0x20);
236	}
237	#endif
238
239	if ( pCtx->eflags.u32 & X86_EFL_IF
240	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
241	&& TRPMHasTrap(pVM)
242	)
243	{
244	uint8_t u8Vector;
245	int rc;
246	bool fSoftwareInt;
247	SVM_EVENT Event;
248	uint32_t u32ErrorCode;
249
250	Event.au64[0] = 0;
251
252	/* If a new event is pending, then dispatch it now. */
253	rc = TRPMQueryTrapAll(pVM, &u8Vector, &fSoftwareInt, &u32ErrorCode, 0);
254	AssertRC(rc);
255	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| u8Vector < 0x20);
256	Assert(fSoftwareInt == false);
257
258	/* Clear the pending trap. */
259	rc = TRPMResetTrap(pVM);
260	AssertRC(rc);
261
262	Event.n.u8Vector = u8Vector;
263	Event.n.u1Valid = 1;
264	Event.n.u32ErrorCode = u32ErrorCode;
265
266	switch (u8Vector) {
267	case 8:
268	case 10:
269	case 11:
270	case 12:
271	case 13:
272	case 14:
273	case 17:
274	/* Valid error codes. */
275	Event.n.u1ErrorCodeValid = 1;
276	break;
277	default:
278	break;
279	}
280
281	if (u8Vector == X86_XCPT_NMI)
282	Event.n.u3Type = SVM_EVENT_NMI;
283	else
284	if (u8Vector < 0x20)
285	Event.n.u3Type = SVM_EVENT_EXCEPTION;
286	else
287	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
288
289	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
290	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
291	} /* if (interrupts can be dispatched) */
292
293	return VINF_SUCCESS;
294	}
295
296
297	/**
298	* Loads the guest state
299	*
300	* @returns VBox status code.
301	* @param pVM The VM to operate on.
302	* @param pCtx Guest context
303	*/
304	HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
305	{
306	int rc = VINF_SUCCESS;
307	RTGCUINTPTR val;
308	SVM_VMCB *pVMCB;
309
310	if (pVM == NULL)
311	return VERR_INVALID_PARAMETER;
312
313	/* Setup AMD SVM. */
314	Assert(pVM->hwaccm.s.svm.fSupported);
315
316	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
317	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
318
319	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
320	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
321	{
322	SVM_WRITE_SELREG(CS, cs);
323	Assert(pVMCB->guest.CS.u16Sel \|\| !pVMCB->guest.CS.u16Attr);
324
325	SVM_WRITE_SELREG(SS, ss);
326	Assert(pVMCB->guest.SS.u16Sel \|\| !pVMCB->guest.SS.u16Attr);
327
328	SVM_WRITE_SELREG(DS, ds);
329	Assert(pVMCB->guest.DS.u16Sel \|\| !pVMCB->guest.DS.u16Attr);
330
331	SVM_WRITE_SELREG(ES, es);
332	Assert(pVMCB->guest.ES.u16Sel \|\| !pVMCB->guest.ES.u16Attr);
333
334	SVM_WRITE_SELREG(FS, fs);
335	Assert(pVMCB->guest.FS.u16Sel \|\| !pVMCB->guest.FS.u16Attr);
336
337	SVM_WRITE_SELREG(GS, gs);
338	Assert(pVMCB->guest.GS.u16Sel \|\| !pVMCB->guest.GS.u16Attr);
339	}
340
341	/* Guest CPU context: LDTR. */
342	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
343	{
344	SVM_WRITE_SELREG(LDTR, ldtr);
345	}
346
347	/* Guest CPU context: TR. */
348	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
349	{
350	SVM_WRITE_SELREG(TR, tr);
351	}
352
353	/* Guest CPU context: GDTR. */
354	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
355	{
356	pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
357	pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
358	}
359
360	/* Guest CPU context: IDTR. */
361	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
362	{
363	pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
364	pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
365	}
366
367	/*
368	* Sysenter MSRs
369	*/
370	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
371	{
372	pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
373	pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
374	pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
375	}
376
377	/* Control registers */
378	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
379	{
380	val = pCtx->cr0;
381	if (CPUMIsGuestFPUStateActive(pVM) == false)
382	{
383	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
384	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
385	}
386	else
387	{
388	Assert(pVM->hwaccm.s.svm.fResumeVM == true);
389	/** @todo check if we support the old style mess correctly. */
390	if (!(val & X86_CR0_NE))
391	{
392	Log(("Forcing X86_CR0_NE!!!\n"));
393
394	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
395	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
396	{
397	pVMCB->ctrl.u32InterceptException \|= BIT(16);
398	pVM->hwaccm.s.fFPUOldStyleOverride = true;
399	}
400	}
401	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
402	}
403	if (!(val & X86_CR0_CD))
404	val &= ~X86_CR0_NW; /* Illegal when cache is turned on. */
405
406	val \|= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
407	pVMCB->guest.u64CR0 = val;
408	}
409	/* CR2 as well */
410	pVMCB->guest.u64CR2 = pCtx->cr2;
411
412	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
413	{
414	/* Save our shadow CR3 register. */
415	pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
416	}
417
418	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
419	{
420	val = pCtx->cr4;
421	switch(pVM->hwaccm.s.enmShadowMode)
422	{
423	case PGMMODE_REAL:
424	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
425	AssertFailed();
426	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
427
428	case PGMMODE_32_BIT: /* 32-bit paging. */
429	break;
430
431	case PGMMODE_PAE: /* PAE paging. */
432	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
433	/** @todo use normal 32 bits paging */
434	val \|= X86_CR4_PAE;
435	break;
436
437	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
438	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
439	AssertFailed();
440	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
441
442	default: /* shut up gcc */
443	AssertFailed();
444	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
445	}
446	pVMCB->guest.u64CR4 = val;
447	}
448
449	/* Debug registers. */
450	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
451	{
452	/** @todo DR0-6 */
453	val = pCtx->dr7;
454	val &= ~(BIT(11) \| BIT(12) \| BIT(14) \| BIT(15)); /* must be zero */
455	val \|= 0x400; /* must be one */
456	#ifdef VBOX_STRICT
457	val = 0x400;
458	#endif
459	pVMCB->guest.u64DR7 = val;
460
461	pVMCB->guest.u64DR6 = pCtx->dr6;
462	}
463
464	/* EIP, ESP and EFLAGS */
465	pVMCB->guest.u64RIP = pCtx->eip;
466	pVMCB->guest.u64RSP = pCtx->esp;
467	pVMCB->guest.u64RFlags = pCtx->eflags.u32;
468
469	/* Set CPL */
470	if (!(pCtx->cr0 & X86_CR0_PE))
471	pVMCB->guest.u8CPL = 0;
472	else
473	if (pCtx->eflags.Bits.u1VM)
474	pVMCB->guest.u8CPL = 3;
475	else
476	pVMCB->guest.u8CPL = (pCtx->ss & X86_SEL_RPL);
477
478	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
479	pVMCB->guest.u64RAX = pCtx->eax;
480
481	/* vmrun will fail otherwise. */
482	pVMCB->guest.u64EFER = MSR_K6_EFER_SVME;
483
484	/** @note We can do more complex things with tagged TLBs. */
485	pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
486
487	/** TSC offset. */
488	pVMCB->ctrl.u64TSCOffset = TMCpuTickGetOffset(pVM);
489
490	/** @todo 64 bits stuff (?):
491	* - STAR
492	* - LSTAR
493	* - CSTAR
494	* - SFMASK
495	* - KernelGSBase
496	*/
497
498	/* Done. */
499	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
500
501	return rc;
502	}
503
504
505	/**
506	* Runs guest code in an SVM VM.
507	*
508	* @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
509	*
510	* @returns VBox status code.
511	* @param pVM The VM to operate on.
512	* @param pCtx Guest context
513	*/
514	HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
515	{
516	int rc = VINF_SUCCESS;
517	uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
518	SVM_VMCB *pVMCB;
519	bool fForceTLBFlush = false;
520
521	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
522
523	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
524	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
525
526	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
527	*/
528	ResumeExecution:
529
530	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
531	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
532	{
533	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
534	if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
535	{
536	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
537	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
538	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
539	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
540	*/
541	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
542	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
543	pVMCB->ctrl.u64IntShadow = 0;
544	}
545	}
546	else
547	{
548	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
549	pVMCB->ctrl.u64IntShadow = 0;
550	}
551
552	/* Check for pending actions that force us to go back to ring 3. */
553	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
554	{
555	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
556	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
557	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
558	rc = VINF_EM_RAW_TO_R3;
559	goto end;
560	}
561	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
562	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
563	{
564	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
565	rc = VINF_EM_PENDING_REQUEST;
566	goto end;
567	}
568
569	/* When external interrupts are pending, we should exit the VM when IF is set. */
570	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
571	rc = SVMR0CheckPendingInterrupt(pVM, pVMCB, pCtx);
572	if (VBOX_FAILURE(rc))
573	{
574	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
575	goto end;
576	}
577
578	/** @todo check timers?? */
579
580	/* Load the guest state */
581	rc = SVMR0LoadGuestState(pVM, pCtx);
582	if (rc != VINF_SUCCESS)
583	{
584	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
585	goto end;
586	}
587
588	/* All done! Let's start VM execution. */
589	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
590
591	/** Erratum #170 -> must force a TLB flush */
592	/** @todo supposed to be fixed in future by AMD */
593	fForceTLBFlush = true;
594
595	if ( pVM->hwaccm.s.svm.fResumeVM == false
596	\|\| fForceTLBFlush)
597	{
598	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1;
599	}
600	else
601	{
602	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 0;
603	}
604	/* In case we execute a goto ResumeExecution later on. */
605	pVM->hwaccm.s.svm.fResumeVM = true;
606	fForceTLBFlush = false;
607
608	Assert(sizeof(pVM->hwaccm.s.svm.pVMCBPhys) == 8);
609	Assert(pVMCB->ctrl.u32InterceptCtrl1 == ( SVM_CTRL1_INTERCEPT_INTR
610	\| SVM_CTRL1_INTERCEPT_VINTR
611	\| SVM_CTRL1_INTERCEPT_NMI
612	\| SVM_CTRL1_INTERCEPT_SMI
613	\| SVM_CTRL1_INTERCEPT_INIT
614	\| SVM_CTRL1_INTERCEPT_CR0 /** @todo redundant? */
615	\| SVM_CTRL1_INTERCEPT_RDPMC
616	\| SVM_CTRL1_INTERCEPT_CPUID
617	\| SVM_CTRL1_INTERCEPT_RSM
618	\| SVM_CTRL1_INTERCEPT_HLT
619	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
620	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
621	\| SVM_CTRL1_INTERCEPT_INVLPG
622	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
623	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
624	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE /* Legacy FPU FERR handling. */
625	));
626	Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
627	\| SVM_CTRL2_INTERCEPT_VMMCALL
628	\| SVM_CTRL2_INTERCEPT_VMLOAD
629	\| SVM_CTRL2_INTERCEPT_VMSAVE
630	\| SVM_CTRL2_INTERCEPT_STGI
631	\| SVM_CTRL2_INTERCEPT_CLGI
632	\| SVM_CTRL2_INTERCEPT_SKINIT
633	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
634	));
635	Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
636	Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
637	Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
638	Assert(pVMCB->ctrl.u64NestedPaging == 0);
639	Assert(pVMCB->ctrl.u64LBRVirt == 0);
640
641	SVMVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);
642	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
643
644	/**
645	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
646	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
647	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
648	*/
649
650	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
651
652	/* Reason for the VM exit */
653	exitCode = pVMCB->ctrl.u64ExitCode;
654
655	if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
656	{
657	HWACCMDumpRegs(pCtx);
658	#ifdef DEBUG
659	Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
660	Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
661	Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
662	Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
663	Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
664	Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
665	Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
666	Log(("ctrl.u64IOPMPhysAddr %VX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
667	Log(("ctrl.u64MSRPMPhysAddr %VX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
668	Log(("ctrl.u64TSCOffset %VX64\n", pVMCB->ctrl.u64TSCOffset));
669
670	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
671	Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
672	Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
673	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
674
675	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
676	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
677	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
678	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
679	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
680	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
681	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
682	Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
683	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
684	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
685
686	Log(("ctrl.u64IntShadow %VX64\n", pVMCB->ctrl.u64IntShadow));
687	Log(("ctrl.u64ExitCode %VX64\n", pVMCB->ctrl.u64ExitCode));
688	Log(("ctrl.u64ExitInfo1 %VX64\n", pVMCB->ctrl.u64ExitInfo1));
689	Log(("ctrl.u64ExitInfo2 %VX64\n", pVMCB->ctrl.u64ExitInfo2));
690	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
691	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
692	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
693	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
694	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
695	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
696	Log(("ctrl.u64NestedPaging %VX64\n", pVMCB->ctrl.u64NestedPaging));
697	Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
698	Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
699	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
700	Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
701	Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
702	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
703
704	Log(("ctrl.u64HostCR3 %VX64\n", pVMCB->ctrl.u64HostCR3));
705	Log(("ctrl.u64LBRVirt %VX64\n", pVMCB->ctrl.u64LBRVirt));
706
707	Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
708	Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
709	Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
710	Log(("guest.CS.u64Base %VX64\n", pVMCB->guest.CS.u64Base));
711	Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
712	Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
713	Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
714	Log(("guest.DS.u64Base %VX64\n", pVMCB->guest.DS.u64Base));
715	Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
716	Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
717	Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
718	Log(("guest.ES.u64Base %VX64\n", pVMCB->guest.ES.u64Base));
719	Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
720	Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
721	Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
722	Log(("guest.FS.u64Base %VX64\n", pVMCB->guest.FS.u64Base));
723	Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
724	Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
725	Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
726	Log(("guest.GS.u64Base %VX64\n", pVMCB->guest.GS.u64Base));
727
728	Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
729	Log(("guest.GDTR.u64Base %VX64\n", pVMCB->guest.GDTR.u64Base));
730
731	Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
732	Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
733	Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
734	Log(("guest.LDTR.u64Base %VX64\n", pVMCB->guest.LDTR.u64Base));
735
736	Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
737	Log(("guest.IDTR.u64Base %VX64\n", pVMCB->guest.IDTR.u64Base));
738
739	Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
740	Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
741	Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
742	Log(("guest.TR.u64Base %VX64\n", pVMCB->guest.TR.u64Base));
743
744	Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
745	Log(("guest.u64CR0 %VX64\n", pVMCB->guest.u64CR0));
746	Log(("guest.u64CR2 %VX64\n", pVMCB->guest.u64CR2));
747	Log(("guest.u64CR3 %VX64\n", pVMCB->guest.u64CR3));
748	Log(("guest.u64CR4 %VX64\n", pVMCB->guest.u64CR4));
749	Log(("guest.u64DR6 %VX64\n", pVMCB->guest.u64DR6));
750	Log(("guest.u64DR7 %VX64\n", pVMCB->guest.u64DR7));
751
752	Log(("guest.u64RIP %VX64\n", pVMCB->guest.u64RIP));
753	Log(("guest.u64RSP %VX64\n", pVMCB->guest.u64RSP));
754	Log(("guest.u64RAX %VX64\n", pVMCB->guest.u64RAX));
755	Log(("guest.u64RFlags %VX64\n", pVMCB->guest.u64RFlags));
756
757	Log(("guest.u64SysEnterCS %VX64\n", pVMCB->guest.u64SysEnterCS));
758	Log(("guest.u64SysEnterEIP %VX64\n", pVMCB->guest.u64SysEnterEIP));
759	Log(("guest.u64SysEnterESP %VX64\n", pVMCB->guest.u64SysEnterESP));
760
761	Log(("guest.u64EFER %VX64\n", pVMCB->guest.u64EFER));
762	Log(("guest.u64STAR %VX64\n", pVMCB->guest.u64STAR));
763	Log(("guest.u64LSTAR %VX64\n", pVMCB->guest.u64LSTAR));
764	Log(("guest.u64CSTAR %VX64\n", pVMCB->guest.u64CSTAR));
765	Log(("guest.u64SFMASK %VX64\n", pVMCB->guest.u64SFMASK));
766	Log(("guest.u64KernelGSBase %VX64\n", pVMCB->guest.u64KernelGSBase));
767	Log(("guest.u64GPAT %VX64\n", pVMCB->guest.u64GPAT));
768	Log(("guest.u64DBGCTL %VX64\n", pVMCB->guest.u64DBGCTL));
769	Log(("guest.u64BR_FROM %VX64\n", pVMCB->guest.u64BR_FROM));
770	Log(("guest.u64BR_TO %VX64\n", pVMCB->guest.u64BR_TO));
771	Log(("guest.u64LASTEXCPFROM %VX64\n", pVMCB->guest.u64LASTEXCPFROM));
772	Log(("guest.u64LASTEXCPTO %VX64\n", pVMCB->guest.u64LASTEXCPTO));
773
774	#endif
775	rc = VERR_SVM_UNABLE_TO_START_VM;
776	goto end;
777	}
778
779	/* Let's first sync back eip, esp, and eflags. */
780	pCtx->eip = pVMCB->guest.u64RIP;
781	pCtx->esp = pVMCB->guest.u64RSP;
782	pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
783	/* eax is saved/restore across the vmrun instruction */
784	pCtx->eax = pVMCB->guest.u64RAX;
785
786	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
787	SVM_READ_SELREG(SS, ss);
788	SVM_READ_SELREG(CS, cs);
789	SVM_READ_SELREG(DS, ds);
790	SVM_READ_SELREG(ES, es);
791	SVM_READ_SELREG(FS, fs);
792	SVM_READ_SELREG(GS, gs);
793
794	/** @note no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
795
796	/** @note NOW IT'S SAFE FOR LOGGING! */
797
798	/* Take care of instruction fusing (sti, mov ss) */
799	if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
800	{
801	Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->eip));
802	EMSetInhibitInterruptsPC(pVM, pCtx->eip);
803	}
804	else
805	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
806
807	Log2(("exitCode = %x\n", exitCode));
808
809	/* Check if an injected event was interrupted prematurely. */
810	pVM->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
811	if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
812	&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
813	{
814	Log(("Pending inject %VX64 at %08x exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitCode));
815	pVM->hwaccm.s.Event.fPending = true;
816	/* Error code present? (redundant) */
817	if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
818	{
819	pVM->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
820	}
821	else
822	pVM->hwaccm.s.Event.errCode = 0;
823	}
824	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReason[exitCode & MASK_EXITREASON_STAT]);
825
826	/* Deal with the reason of the VM-exit. */
827	switch (exitCode)
828	{
829	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
830	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
831	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
832	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
833	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
834	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
835	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
836	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
837	{
838	/* Pending trap. */
839	SVM_EVENT Event;
840	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
841
842	Log2(("Hardware/software interrupt %d\n", vector));
843	switch (vector)
844	{
845	case X86_XCPT_NM:
846	{
847	uint32_t oldCR0;
848
849	Log(("#NM fault at %VGv\n", pCtx->eip));
850
851	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
852	oldCR0 = ASMGetCR0();
853	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
854	rc = CPUMHandleLazyFPU(pVM);
855	if (rc == VINF_SUCCESS)
856	{
857	Assert(CPUMIsGuestFPUStateActive(pVM));
858
859	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
860	ASMSetCR0(oldCR0);
861
862	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
863
864	/* Continue execution. */
865	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
866	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
867
868	goto ResumeExecution;
869	}
870
871	Log(("Forward #NM fault to the guest\n"));
872	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
873
874	Event.au64[0] = 0;
875	Event.n.u3Type = SVM_EVENT_EXCEPTION;
876	Event.n.u1Valid = 1;
877	Event.n.u8Vector = X86_XCPT_NM;
878
879	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
880	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
881	goto ResumeExecution;
882	}
883
884	case X86_XCPT_PF: /* Page fault */
885	{
886	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
887	RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
888
889	Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
890	/* Exit qualification contains the linear address of the page fault. */
891	TRPMAssertTrap(pVM, X86_XCPT_PF, false);
892	TRPMSetErrorCode(pVM, errCode);
893	TRPMSetFaultAddress(pVM, uFaultAddress);
894
895	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
896	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
897	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
898	if (rc == VINF_SUCCESS)
899	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
900	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
901	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
902
903	TRPMResetTrap(pVM);
904
905	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
906	goto ResumeExecution;
907	}
908	else
909	if (rc == VINF_EM_RAW_GUEST_TRAP)
910	{ /* A genuine pagefault.
911	* Forward the trap to the guest by injecting the exception and resuming execution.
912	*/
913	Log2(("Forward page fault to the guest\n"));
914	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
915	/* The error code might have been changed. */
916	errCode = TRPMGetErrorCode(pVM);
917
918	TRPMResetTrap(pVM);
919
920	/* Now we must update CR2. */
921	pCtx->cr2 = uFaultAddress;
922
923	Event.au64[0] = 0;
924	Event.n.u3Type = SVM_EVENT_EXCEPTION;
925	Event.n.u1Valid = 1;
926	Event.n.u8Vector = X86_XCPT_PF;
927	Event.n.u1ErrorCodeValid = 1;
928	Event.n.u32ErrorCode = errCode;
929
930	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
931
932	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
933	goto ResumeExecution;
934	}
935	#ifdef VBOX_STRICT
936	if (rc != VINF_EM_RAW_EMULATE_INSTR)
937	Log(("PGMTrap0eHandler failed with %d\n", rc));
938	#endif
939	/* Need to go back to the recompiler to emulate the instruction. */
940	TRPMResetTrap(pVM);
941	break;
942	}
943
944	case X86_XCPT_MF: /* Floating point exception. */
945	{
946	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
947	if (!(pCtx->cr0 & X86_CR0_NE))
948	{
949	/* old style FPU error reporting needs some extra work. */
950	/** @todo don't fall back to the recompiler, but do it manually. */
951	rc = VINF_EM_RAW_EMULATE_INSTR;
952	break;
953	}
954	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
955
956	Event.au64[0] = 0;
957	Event.n.u3Type = SVM_EVENT_EXCEPTION;
958	Event.n.u1Valid = 1;
959	Event.n.u8Vector = X86_XCPT_MF;
960
961	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
962
963	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
964	goto ResumeExecution;
965	}
966
967	#ifdef VBOX_STRICT
968	case X86_XCPT_GP: /* General protection failure exception.*/
969	case X86_XCPT_UD: /* Unknown opcode exception. */
970	case X86_XCPT_DE: /* Debug exception. */
971	case X86_XCPT_SS: /* Stack segment exception. */
972	case X86_XCPT_NP: /* Segment not present exception. */
973	{
974	Event.au64[0] = 0;
975	Event.n.u3Type = SVM_EVENT_EXCEPTION;
976	Event.n.u1Valid = 1;
977	Event.n.u8Vector = vector;
978
979	switch(vector)
980	{
981	case X86_XCPT_GP:
982	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
983	Event.n.u1ErrorCodeValid = 1;
984	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
985	break;
986	case X86_XCPT_DE:
987	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
988	break;
989	case X86_XCPT_UD:
990	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
991	break;
992	case X86_XCPT_SS:
993	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
994	Event.n.u1ErrorCodeValid = 1;
995	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
996	break;
997	case X86_XCPT_NP:
998	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
999	Event.n.u1ErrorCodeValid = 1;
1000	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1001	break;
1002	}
1003
1004	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1005	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1006
1007	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1008	goto ResumeExecution;
1009	}
1010	#endif
1011	default:
1012	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1013	rc = VERR_EM_INTERNAL_ERROR;
1014	break;
1015
1016	} /* switch (vector) */
1017	break;
1018	}
1019
1020	case SVM_EXIT_FERR_FREEZE:
1021	case SVM_EXIT_INTR:
1022	case SVM_EXIT_NMI:
1023	case SVM_EXIT_SMI:
1024	case SVM_EXIT_INIT:
1025	case SVM_EXIT_VINTR:
1026	/* External interrupt; leave to allow it to be dispatched again. */
1027	rc = VINF_EM_RAW_INTERRUPT;
1028	break;
1029
1030	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1031	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1032	/* Skip instruction and continue directly. */
1033	pCtx->eip += 2; /** @note hardcoded opcode size! */
1034	/* Continue execution.*/
1035	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1036	goto ResumeExecution;
1037
1038	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1039	{
1040	Log2(("SVM: Cpuid %x\n", pCtx->eax));
1041	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1042	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1043	if (rc == VINF_SUCCESS)
1044	{
1045	/* Update EIP and continue execution. */
1046	pCtx->eip += 2; /** @note hardcoded opcode size! */
1047	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1048	goto ResumeExecution;
1049	}
1050	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1051	rc = VINF_EM_RAW_EMULATE_INSTR;
1052	break;
1053	}
1054
1055	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1056	{
1057	Log2(("SVM: invlpg\n"));
1058	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1059
1060	/* Truly a pita. Why can't SVM give the same information as VMX? */
1061	rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1062	break;
1063	}
1064
1065	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1066	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1067	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1068	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1069	{
1070	uint32_t cbSize;
1071
1072	Log2(("SVM: %VGv mov cr%d, \n", pCtx->eip, exitCode - SVM_EXIT_WRITE_CR0));
1073	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1074	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1075
1076	switch (exitCode - SVM_EXIT_WRITE_CR0)
1077	{
1078	case 0:
1079	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1080	break;
1081	case 2:
1082	break;
1083	case 3:
1084	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1085	break;
1086	case 4:
1087	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1088	break;
1089	default:
1090	AssertFailed();
1091	}
1092	/* Check if a sync operation is pending. */
1093	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1094	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1095	{
1096	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1097	AssertRC(rc);
1098
1099	/** @note Force a TLB flush. SVM requires us to do it manually. */
1100	fForceTLBFlush = true;
1101	}
1102	if (rc == VINF_SUCCESS)
1103	{
1104	/* EIP has been updated already. */
1105
1106	/* Only resume if successful. */
1107	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1108	goto ResumeExecution;
1109	}
1110	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1111	if (rc == VERR_EM_INTERPRETER)
1112	rc = VINF_EM_RAW_EMULATE_INSTR;
1113	break;
1114	}
1115
1116	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1117	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1118	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1119	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1120	{
1121	uint32_t cbSize;
1122
1123	Log2(("SVM: %VGv mov x, cr%d\n", pCtx->eip, exitCode - SVM_EXIT_READ_CR0));
1124	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1125	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1126	if (rc == VINF_SUCCESS)
1127	{
1128	/* EIP has been updated already. */
1129
1130	/* Only resume if successful. */
1131	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1132	goto ResumeExecution;
1133	}
1134	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1135	if (rc == VERR_EM_INTERPRETER)
1136	rc = VINF_EM_RAW_EMULATE_INSTR;
1137	break;
1138	}
1139
1140	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1141	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1142	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1143	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1144	{
1145	uint32_t cbSize;
1146
1147	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_WRITE_DR0));
1148	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1149	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1150	if (rc == VINF_SUCCESS)
1151	{
1152	/* EIP has been updated already. */
1153
1154	/* Only resume if successful. */
1155	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1156	goto ResumeExecution;
1157	}
1158	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1159	if (rc == VERR_EM_INTERPRETER)
1160	rc = VINF_EM_RAW_EMULATE_INSTR;
1161	break;
1162	}
1163
1164	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1165	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1166	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1167	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1168	{
1169	uint32_t cbSize;
1170
1171	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_READ_DR0));
1172	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1173	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1174	if (rc == VINF_SUCCESS)
1175	{
1176	/* EIP has been updated already. */
1177
1178	/* Only resume if successful. */
1179	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1180	goto ResumeExecution;
1181	}
1182	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1183	if (rc == VERR_EM_INTERPRETER)
1184	rc = VINF_EM_RAW_EMULATE_INSTR;
1185	break;
1186	}
1187
1188	/** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1189	case SVM_EXIT_IOIO: /* I/O instruction. */
1190	{
1191	SVM_IOIO_EXIT IoExitInfo;
1192	uint32_t uIOSize, uAndVal;
1193
1194	IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1195
1196	/** @todo could use a lookup table here */
1197	if (IoExitInfo.n.u1OP8)
1198	{
1199	uIOSize = 1;
1200	uAndVal = 0xff;
1201	}
1202	else
1203	if (IoExitInfo.n.u1OP16)
1204	{
1205	uIOSize = 2;
1206	uAndVal = 0xffff;
1207	}
1208	else
1209	if (IoExitInfo.n.u1OP32)
1210	{
1211	uIOSize = 4;
1212	uAndVal = 0xffffffff;
1213	}
1214	else
1215	{
1216	AssertFailed(); /* should be fatal. */
1217	rc = VINF_EM_RAW_EMULATE_INSTR;
1218	break;
1219	}
1220
1221	/* First simple in and out instructions. */
1222	/** @todo str & rep */
1223	if ( !IoExitInfo.n.u1REP
1224	&& !IoExitInfo.n.u1STR
1225	)
1226	{
1227	if (IoExitInfo.n.u1Type == 0)
1228	{
1229	Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1230	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1231	rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1232	}
1233	else
1234	{
1235	uint32_t u32Val = 0;
1236
1237	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1238	rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1239	if (rc == VINF_SUCCESS)
1240	{
1241	/* Write back to the EAX register. */
1242	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1243	Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1244	}
1245	}
1246	if (rc == VINF_SUCCESS)
1247	{
1248	/* Update EIP and continue execution. */
1249	pCtx->eip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1250	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1251	goto ResumeExecution;
1252	}
1253	Assert(rc == VINF_IOM_HC_IOPORT_READ \|\| rc == VINF_IOM_HC_IOPORT_WRITE);
1254	rc = (IoExitInfo.n.u1Type == 0) ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1255	}
1256	else
1257	rc = VINF_IOM_HC_IOPORT_READWRITE;
1258
1259	Log2(("Failed IO at %VGv %x size %d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1260
1261	break;
1262	}
1263
1264	case SVM_EXIT_HLT:
1265	/** Check if external interrupts are pending; if so, don't switch back. */
1266	if (VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1267	{
1268	pCtx->eip++; /* skip hlt */
1269	goto ResumeExecution;
1270	}
1271
1272	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1273	break;
1274
1275	case SVM_EXIT_RDPMC:
1276	case SVM_EXIT_RSM:
1277	case SVM_EXIT_INVLPGA:
1278	case SVM_EXIT_VMRUN:
1279	case SVM_EXIT_VMMCALL:
1280	case SVM_EXIT_VMLOAD:
1281	case SVM_EXIT_VMSAVE:
1282	case SVM_EXIT_STGI:
1283	case SVM_EXIT_CLGI:
1284	case SVM_EXIT_SKINIT:
1285	case SVM_EXIT_RDTSCP:
1286	{
1287	/* Unsupported instructions. */
1288	SVM_EVENT Event;
1289
1290	Event.au64[0] = 0;
1291	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1292	Event.n.u1Valid = 1;
1293	Event.n.u8Vector = X86_XCPT_UD;
1294
1295	Log(("Forced #UD trap at %VGv\n", pCtx->eip));
1296	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1297
1298	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1299	goto ResumeExecution;
1300	}
1301
1302	/* Emulate RDMSR & WRMSR in ring 3. */
1303	case SVM_EXIT_MSR:
1304	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1305	break;
1306
1307	case SVM_EXIT_NPF:
1308	AssertFailed(); /* unexpected */
1309	break;
1310
1311	case SVM_EXIT_SHUTDOWN:
1312	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1313	break;
1314
1315	case SVM_EXIT_PAUSE:
1316	case SVM_EXIT_IDTR_READ:
1317	case SVM_EXIT_GDTR_READ:
1318	case SVM_EXIT_LDTR_READ:
1319	case SVM_EXIT_TR_READ:
1320	case SVM_EXIT_IDTR_WRITE:
1321	case SVM_EXIT_GDTR_WRITE:
1322	case SVM_EXIT_LDTR_WRITE:
1323	case SVM_EXIT_TR_WRITE:
1324	case SVM_EXIT_CR0_SEL_WRITE:
1325	default:
1326	/* Unexpected exit codes. */
1327	rc = VERR_EM_INTERNAL_ERROR;
1328	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
1329	break;
1330	}
1331
1332	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1333	SVM_READ_SELREG(LDTR, ldtr);
1334	SVM_READ_SELREG(TR, tr);
1335
1336	pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1337	pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1338
1339	pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1340	pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1341
1342	/*
1343	* System MSRs
1344	*/
1345	pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1346	pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1347	pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1348
1349	/* Signal changes for the recompiler. */
1350	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
1351
1352	end:
1353
1354	/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
1355	if (exitCode == SVM_EXIT_INTR)
1356	{
1357	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1358	/* On the next entry we'll only sync the host context. */
1359	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
1360	}
1361	else
1362	{
1363	/* On the next entry we'll sync everything. */
1364	/** @todo we can do better than this */
1365	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
1366	}
1367
1368	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1369	return rc;
1370	}
1371
1372	/**
1373	* Enable SVM
1374	*
1375	* @returns VBox status code.
1376	* @param pVM The VM to operate on.
1377	*/
1378	HWACCMR0DECL(int) SVMR0Enable(PVM pVM)
1379	{
1380	uint64_t val;
1381
1382	Assert(pVM->hwaccm.s.svm.fSupported);
1383
1384	/* We must turn on SVM and setup the host state physical address, as those MSRs are per-cpu/core. */
1385
1386	/* Turn on SVM in the EFER MSR. */
1387	val = ASMRdMsr(MSR_K6_EFER);
1388	if (!(val & MSR_K6_EFER_SVME))
1389	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
1390
1391	/* Write the physical page address where the CPU will store the host state while executing the VM. */
1392	ASMWrMsr(MSR_K8_VM_HSAVE_PA, pVM->hwaccm.s.svm.pHStatePhys);
1393
1394	/* Force a TLB flush on VM entry. */
1395	pVM->hwaccm.s.svm.fResumeVM = false;
1396
1397	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
1398	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_LDTR;
1399
1400	return VINF_SUCCESS;
1401	}
1402
1403
1404	/**
1405	* Disable SVM
1406	*
1407	* @returns VBox status code.
1408	* @param pVM The VM to operate on.
1409	*/
1410	HWACCMR0DECL(int) SVMR0Disable(PVM pVM)
1411	{
1412	/** @todo hopefully this is not very expensive. */
1413
1414	/* Turn off SVM in the EFER MSR. */
1415	uint64_t val = ASMRdMsr(MSR_K6_EFER);
1416	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
1417
1418	/* Invalidate host state physical address. */
1419	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
1420
1421	Assert(pVM->hwaccm.s.svm.fSupported);
1422	return VINF_SUCCESS;
1423	}
1424
1425
1426	static int svmInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1427	{
1428	OP_PARAMVAL param1;
1429	RTGCPTR addr;
1430
1431	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1432	if(VBOX_FAILURE(rc))
1433	return VERR_EM_INTERPRETER;
1434
1435	switch(param1.type)
1436	{
1437	case PARMTYPE_IMMEDIATE:
1438	case PARMTYPE_ADDRESS:
1439	if(!(param1.flags & PARAM_VAL32))
1440	return VERR_EM_INTERPRETER;
1441	addr = (RTGCPTR)param1.val.val32;
1442	break;
1443
1444	default:
1445	return VERR_EM_INTERPRETER;
1446	}
1447
1448	/** @todo is addr always a flat linear address or ds based
1449	* (in absence of segment override prefixes)????
1450	*/
1451	rc = PGMInvalidatePage(pVM, addr);
1452	if (VBOX_SUCCESS(rc))
1453	{
1454	/* Manually invalidate the page for the VM's TLB. */
1455	SVMInvlpgA(addr, uASID);
1456	return VINF_SUCCESS;
1457	}
1458	/** @todo r=bird: we shouldn't ignore returns codes like this... I'm 99% sure the error is fatal. */
1459	return VERR_EM_INTERPRETER;
1460	}
1461
1462	/**
1463	* Interprets INVLPG
1464	*
1465	* @returns VBox status code.
1466	* @retval VINF_* Scheduling instructions.
1467	* @retval VERR_EM_INTERPRETER Something we can't cope with.
1468	* @retval VERR_* Fatal errors.
1469	*
1470	* @param pVM The VM handle.
1471	* @param pRegFrame The register frame.
1472	* @param ASID Tagged TLB id for the guest
1473	*
1474	* Updates the EIP if an instruction was executed successfully.
1475	*/
1476	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1477	{
1478	/*
1479	* Only allow 32-bit code.
1480	*/
1481	if (SELMIsSelector32Bit(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid))
1482	{
1483	RTGCPTR pbCode;
1484	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pbCode);
1485	if (VBOX_SUCCESS(rc))
1486	{
1487	uint32_t cbOp;
1488	DISCPUSTATE Cpu;
1489
1490	Cpu.mode = CPUMODE_32BIT;
1491	rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
1492	Assert(VBOX_FAILURE(rc) \|\| Cpu.pCurInstr->opcode == OP_INVLPG);
1493	if (VBOX_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
1494	{
1495	Assert(cbOp == Cpu.opsize);
1496	rc = svmInterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
1497	if (VBOX_SUCCESS(rc))
1498	{
1499	pRegFrame->eip += cbOp; /* Move on to the next instruction. */
1500	}
1501	return rc;
1502	}
1503	}
1504	}
1505	return VERR_EM_INTERPRETER;
1506	}
1507

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 2097

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