VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 21111

Last change on this file since 21111 was 21001, checked in by vboxsync, 16 years ago

HWACCM: Untested AMD-V fix for the xmm register corruption on Windows/AMD64.
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1/* $Id: HWSVMR0.cpp 21001 2009-06-26 23:18:11Z vboxsync $ */
2/** @file
3 * HWACCM SVM - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/hwacc_svm.h>
32#include <VBox/pgm.h>
33#include <VBox/pdm.h>
34#include <VBox/err.h>
35#include <VBox/log.h>
36#include <VBox/selm.h>
37#include <VBox/iom.h>
38#include <VBox/dis.h>
39#include <VBox/dbgf.h>
40#include <VBox/disopcode.h>
41#include <iprt/param.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/cpuset.h>
45#include <iprt/mp.h>
46#include <iprt/time.h>
47#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
48# include <iprt/thread.h>
49#endif
50#include "HWSVMR0.h"
51
52/*******************************************************************************
53* Internal Functions *
54*******************************************************************************/
55static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID);
56static int svmR0ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
57
58/*******************************************************************************
59* Global Variables *
60*******************************************************************************/
61/* IO operation lookup arrays. */
62static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
63
64/**
65 * Sets up and activates AMD-V on the current CPU
66 *
67 * @returns VBox status code.
68 * @param pCpu CPU info struct
69 * @param pVM The VM to operate on. (can be NULL after a resume!!)
70 * @param pvPageCpu Pointer to the global cpu page
71 * @param pPageCpuPhys Physical address of the global cpu page
72 */
73VMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
74{
75 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
76 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
77
78 /* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
79
80#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
81 SUPR0Printf("SVMR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
82#endif
83
84 /* Turn on AMD-V in the EFER MSR. */
85 uint64_t val = ASMRdMsr(MSR_K6_EFER);
86 if (!(val & MSR_K6_EFER_SVME))
87 ASMWrMsr(MSR_K6_EFER, val | MSR_K6_EFER_SVME);
88
89 /* Write the physical page address where the CPU will store the host state while executing the VM. */
90 ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
91
92 return VINF_SUCCESS;
93}
94
95/**
96 * Deactivates AMD-V on the current CPU
97 *
98 * @returns VBox status code.
99 * @param pCpu CPU info struct
100 * @param pvPageCpu Pointer to the global cpu page
101 * @param pPageCpuPhys Physical address of the global cpu page
102 */
103VMMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
104{
105 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
106 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
107
108#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
109 SUPR0Printf("SVMR0DisableCpu cpu %d\n", pCpu->idCpu);
110#endif
111
112 /* Turn off AMD-V in the EFER MSR. */
113 uint64_t val = ASMRdMsr(MSR_K6_EFER);
114 ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
115
116 /* Invalidate host state physical address. */
117 ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
118
119 return VINF_SUCCESS;
120}
121
122/**
123 * Does Ring-0 per VM AMD-V init.
124 *
125 * @returns VBox status code.
126 * @param pVM The VM to operate on.
127 */
128VMMR0DECL(int) SVMR0InitVM(PVM pVM)
129{
130 int rc;
131
132 pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
133 pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
134
135 /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
136 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
137 if (RT_FAILURE(rc))
138 return rc;
139
140 pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
141 pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
142 /* Set all bits to intercept all IO accesses. */
143 ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
144
145 /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
146 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
147 if (RT_FAILURE(rc))
148 return rc;
149
150 pVM->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
151 pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
152 /* Set all bits to intercept all MSR accesses. */
153 ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
154
155 /* Erratum 170 which requires a forced TLB flush for each world switch:
156 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
157 *
158 * All BH-G1/2 and DH-G1/2 models include a fix:
159 * Athlon X2: 0x6b 1/2
160 * 0x68 1/2
161 * Athlon 64: 0x7f 1
162 * 0x6f 2
163 * Sempron: 0x7f 1/2
164 * 0x6f 2
165 * 0x6c 2
166 * 0x7c 2
167 * Turion 64: 0x68 2
168 *
169 */
170 uint32_t u32Dummy;
171 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
172 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
173 u32BaseFamily= (u32Version >> 8) & 0xf;
174 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
175 u32Model = ((u32Version >> 4) & 0xf);
176 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
177 u32Stepping = u32Version & 0xf;
178 if ( u32Family == 0xf
179 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
180 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
181 {
182 Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
183 pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
184 }
185
186 /* Allocate VMCBs for all guest CPUs. */
187 for (unsigned i=0;i<pVM->cCPUs;i++)
188 {
189 PVMCPU pVCpu = &pVM->aCpus[i];
190
191 pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
192 pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
193
194 /* Allocate one page for the host context */
195 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
196 if (RT_FAILURE(rc))
197 return rc;
198
199 pVCpu->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCBHost);
200 pVCpu->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 0);
201 ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCBHost);
202
203 /* Allocate one page for the VM control block (VMCB). */
204 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
205 if (RT_FAILURE(rc))
206 return rc;
207
208 pVCpu->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCB);
209 pVCpu->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCB, 0);
210 ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCB);
211 }
212
213 return VINF_SUCCESS;
214}
215
216/**
217 * Does Ring-0 per VM AMD-V termination.
218 *
219 * @returns VBox status code.
220 * @param pVM The VM to operate on.
221 */
222VMMR0DECL(int) SVMR0TermVM(PVM pVM)
223{
224 for (unsigned i=0;i<pVM->cCPUs;i++)
225 {
226 PVMCPU pVCpu = &pVM->aCpus[i];
227
228 if (pVCpu->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ)
229 {
230 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, false);
231 pVCpu->hwaccm.s.svm.pVMCBHost = 0;
232 pVCpu->hwaccm.s.svm.pVMCBHostPhys = 0;
233 pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
234 }
235
236 if (pVCpu->hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)
237 {
238 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCB, false);
239 pVCpu->hwaccm.s.svm.pVMCB = 0;
240 pVCpu->hwaccm.s.svm.pVMCBPhys = 0;
241 pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
242 }
243 }
244 if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)
245 {
246 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
247 pVM->hwaccm.s.svm.pIOBitmap = 0;
248 pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
249 pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
250 }
251 if (pVM->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
252 {
253 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
254 pVM->hwaccm.s.svm.pMSRBitmap = 0;
255 pVM->hwaccm.s.svm.pMSRBitmapPhys = 0;
256 pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
257 }
258 return VINF_SUCCESS;
259}
260
261/**
262 * Sets up AMD-V for the specified VM
263 *
264 * @returns VBox status code.
265 * @param pVM The VM to operate on.
266 */
267VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
268{
269 int rc = VINF_SUCCESS;
270 SVM_VMCB *pVMCB;
271
272 AssertReturn(pVM, VERR_INVALID_PARAMETER);
273
274 Assert(pVM->hwaccm.s.svm.fSupported);
275
276 for (unsigned i=0;i<pVM->cCPUs;i++)
277 {
278 pVMCB = (SVM_VMCB *)pVM->aCpus[i].hwaccm.s.svm.pVMCB;
279 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
280
281 /* Program the control fields. Most of them never have to be changed again. */
282 /* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
283 /* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical. */
284 if (!pVM->hwaccm.s.fNestedPaging)
285 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
286 else
287 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(4);
288
289 /*
290 * CR0/3/4 writes must be intercepted for obvious reasons.
291 */
292 if (!pVM->hwaccm.s.fNestedPaging)
293 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
294 else
295 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(4) | RT_BIT(8);
296
297 /* Intercept all DRx reads and writes by default. Changed later on. */
298 pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
299 pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
300
301 /* Currently we don't care about DRx reads or writes. DRx registers are trashed.
302 * All breakpoints are automatically cleared when the VM exits.
303 */
304
305 pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
306#ifndef DEBUG
307 if (pVM->hwaccm.s.fNestedPaging)
308 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
309#endif
310
311 pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
312 | SVM_CTRL1_INTERCEPT_VINTR
313 | SVM_CTRL1_INTERCEPT_NMI
314 | SVM_CTRL1_INTERCEPT_SMI
315 | SVM_CTRL1_INTERCEPT_INIT
316 | SVM_CTRL1_INTERCEPT_RDPMC
317 | SVM_CTRL1_INTERCEPT_CPUID
318 | SVM_CTRL1_INTERCEPT_RSM
319 | SVM_CTRL1_INTERCEPT_HLT
320 | SVM_CTRL1_INTERCEPT_INOUT_BITMAP
321 | SVM_CTRL1_INTERCEPT_MSR_SHADOW
322 | SVM_CTRL1_INTERCEPT_INVLPG
323 | SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
324 | SVM_CTRL1_INTERCEPT_TASK_SWITCH
325 | SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
326 | SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
327 ;
328 /* With nested paging we don't care about invlpg anymore. */
329 if (pVM->hwaccm.s.fNestedPaging)
330 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
331
332 pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
333 | SVM_CTRL2_INTERCEPT_VMMCALL
334 | SVM_CTRL2_INTERCEPT_VMLOAD
335 | SVM_CTRL2_INTERCEPT_VMSAVE
336 | SVM_CTRL2_INTERCEPT_STGI
337 | SVM_CTRL2_INTERCEPT_CLGI
338 | SVM_CTRL2_INTERCEPT_SKINIT
339 | SVM_CTRL2_INTERCEPT_WBINVD
340 | SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
341 ;
342 Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
343 Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
344 Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
345
346 /* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
347 pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
348 /* Ignore the priority in the TPR; just deliver it when we tell it to. */
349 pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
350
351 /* Set IO and MSR bitmap addresses. */
352 pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
353 pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
354
355 /* No LBR virtualization. */
356 pVMCB->ctrl.u64LBRVirt = 0;
357
358 /** The ASID must start at 1; the host uses 0. */
359 pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
360
361 /** Setup the PAT msr (nested paging only) */
362 pVMCB->guest.u64GPAT = 0x0007040600070406ULL;
363 }
364 return rc;
365}
366
367
368/**
369 * Injects an event (trap or external interrupt)
370 *
371 * @param pVCpu The VMCPU to operate on.
372 * @param pVMCB SVM control block
373 * @param pCtx CPU Context
374 * @param pIntInfo SVM interrupt info
375 */
376inline void SVMR0InjectEvent(PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx, SVM_EVENT* pEvent)
377{
378#ifdef VBOX_WITH_STATISTICS
379 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
380#endif
381
382#ifdef VBOX_STRICT
383 if (pEvent->n.u8Vector == 0xE)
384 Log(("SVM: Inject int %d at %RGv error code=%02x CR2=%RGv intInfo=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode, (RTGCPTR)pCtx->cr2, pEvent->au64[0]));
385 else
386 if (pEvent->n.u8Vector < 0x20)
387 Log(("SVM: Inject int %d at %RGv error code=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode));
388 else
389 {
390 Log(("INJ-EI: %x at %RGv\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip));
391 Assert(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
392 Assert(pCtx->eflags.u32 & X86_EFL_IF);
393 }
394#endif
395
396 /* Set event injection state. */
397 pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
398}
399
400
401/**
402 * Checks for pending guest interrupts and injects them
403 *
404 * @returns VBox status code.
405 * @param pVM The VM to operate on.
406 * @param pVCpu The VM CPU to operate on.
407 * @param pVMCB SVM control block
408 * @param pCtx CPU Context
409 */
410static int SVMR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx)
411{
412 int rc;
413
414 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
415 if (pVCpu->hwaccm.s.Event.fPending)
416 {
417 SVM_EVENT Event;
418
419 Log(("Reinjecting event %08x %08x at %RGv\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip));
420 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
421 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
422 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
423
424 pVCpu->hwaccm.s.Event.fPending = false;
425 return VINF_SUCCESS;
426 }
427
428 /* If an active trap is already pending, then we must forward it first! */
429 if (!TRPMHasTrap(pVCpu))
430 {
431 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI_BIT))
432 {
433 SVM_EVENT Event;
434
435 Log(("CPU%d: injecting #NMI\n", pVCpu->idCpu));
436 Event.n.u8Vector = X86_XCPT_NMI;
437 Event.n.u1Valid = 1;
438 Event.n.u32ErrorCode = 0;
439 Event.n.u3Type = SVM_EVENT_NMI;
440
441 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
442 return VINF_SUCCESS;
443 }
444
445 /* @todo SMI interrupts. */
446
447 /* When external interrupts are pending, we should exit the VM when IF is set. */
448 if (VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
449 {
450 if ( !(pCtx->eflags.u32 & X86_EFL_IF)
451 || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
452 {
453 if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
454 {
455 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
456 LogFlow(("Enable irq window exit!\n"));
457 else
458 Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", (RTGCPTR)pCtx->rip));
459
460 /** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
461 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_VINTR;
462 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
463 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
464 }
465 }
466 else
467 {
468 uint8_t u8Interrupt;
469
470 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
471 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
472 if (RT_SUCCESS(rc))
473 {
474 rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
475 AssertRC(rc);
476 }
477 else
478 {
479 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
480 Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)));
481 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
482 /* Just continue */
483 }
484 }
485 }
486 }
487
488#ifdef VBOX_STRICT
489 if (TRPMHasTrap(pVCpu))
490 {
491 uint8_t u8Vector;
492 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
493 AssertRC(rc);
494 }
495#endif
496
497 if ( (pCtx->eflags.u32 & X86_EFL_IF)
498 && (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
499 && TRPMHasTrap(pVCpu)
500 )
501 {
502 uint8_t u8Vector;
503 int rc;
504 TRPMEVENT enmType;
505 SVM_EVENT Event;
506 RTGCUINT u32ErrorCode;
507
508 Event.au64[0] = 0;
509
510 /* If a new event is pending, then dispatch it now. */
511 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &u32ErrorCode, 0);
512 AssertRC(rc);
513 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
514 Assert(enmType != TRPM_SOFTWARE_INT);
515
516 /* Clear the pending trap. */
517 rc = TRPMResetTrap(pVCpu);
518 AssertRC(rc);
519
520 Event.n.u8Vector = u8Vector;
521 Event.n.u1Valid = 1;
522 Event.n.u32ErrorCode = u32ErrorCode;
523
524 if (enmType == TRPM_TRAP)
525 {
526 switch (u8Vector) {
527 case 8:
528 case 10:
529 case 11:
530 case 12:
531 case 13:
532 case 14:
533 case 17:
534 /* Valid error codes. */
535 Event.n.u1ErrorCodeValid = 1;
536 break;
537 default:
538 break;
539 }
540 if (u8Vector == X86_XCPT_NMI)
541 Event.n.u3Type = SVM_EVENT_NMI;
542 else
543 Event.n.u3Type = SVM_EVENT_EXCEPTION;
544 }
545 else
546 Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
547
548 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
549 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
550 } /* if (interrupts can be dispatched) */
551
552 return VINF_SUCCESS;
553}
554
555/**
556 * Save the host state
557 *
558 * @returns VBox status code.
559 * @param pVM The VM to operate on.
560 * @param pVCpu The VM CPU to operate on.
561 */
562VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
563{
564 NOREF(pVM);
565 NOREF(pVCpu);
566 /* Nothing to do here. */
567 return VINF_SUCCESS;
568}
569
570/**
571 * Loads the guest state
572 *
573 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
574 *
575 * @returns VBox status code.
576 * @param pVM The VM to operate on.
577 * @param pVCpu The VM CPU to operate on.
578 * @param pCtx Guest context
579 */
580VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
581{
582 RTGCUINTPTR val;
583 SVM_VMCB *pVMCB;
584
585 if (pVM == NULL)
586 return VERR_INVALID_PARAMETER;
587
588 /* Setup AMD SVM. */
589 Assert(pVM->hwaccm.s.svm.fSupported);
590
591 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
592 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
593
594 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
595 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
596 {
597 SVM_WRITE_SELREG(CS, cs);
598 SVM_WRITE_SELREG(SS, ss);
599 SVM_WRITE_SELREG(DS, ds);
600 SVM_WRITE_SELREG(ES, es);
601 SVM_WRITE_SELREG(FS, fs);
602 SVM_WRITE_SELREG(GS, gs);
603 }
604
605 /* Guest CPU context: LDTR. */
606 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
607 {
608 SVM_WRITE_SELREG(LDTR, ldtr);
609 }
610
611 /* Guest CPU context: TR. */
612 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
613 {
614 SVM_WRITE_SELREG(TR, tr);
615 }
616
617 /* Guest CPU context: GDTR. */
618 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
619 {
620 pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
621 pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
622 }
623
624 /* Guest CPU context: IDTR. */
625 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
626 {
627 pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
628 pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
629 }
630
631 /*
632 * Sysenter MSRs (unconditional)
633 */
634 pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
635 pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
636 pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
637
638 /* Control registers */
639 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
640 {
641 val = pCtx->cr0;
642 if (!CPUMIsGuestFPUStateActive(pVCpu))
643 {
644 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
645 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
646 }
647 else
648 {
649 /** @todo check if we support the old style mess correctly. */
650 if (!(val & X86_CR0_NE))
651 {
652 Log(("Forcing X86_CR0_NE!!!\n"));
653
654 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
655 if (!pVCpu->hwaccm.s.fFPUOldStyleOverride)
656 {
657 pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_MF);
658 pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
659 }
660 }
661 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
662 }
663 /* Always enable caching. */
664 val &= ~(X86_CR0_CD|X86_CR0_NW);
665
666 /* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
667 /* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
668 if (!pVM->hwaccm.s.fNestedPaging)
669 {
670 val |= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
671 val |= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
672 }
673 pVMCB->guest.u64CR0 = val;
674 }
675 /* CR2 as well */
676 pVMCB->guest.u64CR2 = pCtx->cr2;
677
678 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
679 {
680 /* Save our shadow CR3 register. */
681 if (pVM->hwaccm.s.fNestedPaging)
682 {
683 PGMMODE enmShwPagingMode;
684
685#if HC_ARCH_BITS == 32
686 if (CPUMIsGuestInLongModeEx(pCtx))
687 enmShwPagingMode = PGMMODE_AMD64_NX;
688 else
689#endif
690 enmShwPagingMode = PGMGetHostMode(pVM);
691
692 pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
693 Assert(pVMCB->ctrl.u64NestedPagingCR3);
694 pVMCB->guest.u64CR3 = pCtx->cr3;
695 }
696 else
697 {
698 pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
699 Assert(pVMCB->guest.u64CR3 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
700 }
701 }
702
703 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
704 {
705 val = pCtx->cr4;
706 if (!pVM->hwaccm.s.fNestedPaging)
707 {
708 switch(pVCpu->hwaccm.s.enmShadowMode)
709 {
710 case PGMMODE_REAL:
711 case PGMMODE_PROTECTED: /* Protected mode, no paging. */
712 AssertFailed();
713 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
714
715 case PGMMODE_32_BIT: /* 32-bit paging. */
716 val &= ~X86_CR4_PAE;
717 break;
718
719 case PGMMODE_PAE: /* PAE paging. */
720 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
721 /** @todo use normal 32 bits paging */
722 val |= X86_CR4_PAE;
723 break;
724
725 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
726 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
727#ifdef VBOX_ENABLE_64_BITS_GUESTS
728 break;
729#else
730 AssertFailed();
731 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
732#endif
733
734 default: /* shut up gcc */
735 AssertFailed();
736 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
737 }
738 }
739 pVMCB->guest.u64CR4 = val;
740 }
741
742 /* Debug registers. */
743 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
744 {
745 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
746 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
747
748 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
749 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
750 pCtx->dr[7] |= 0x400; /* must be one */
751
752 pVMCB->guest.u64DR7 = pCtx->dr[7];
753 pVMCB->guest.u64DR6 = pCtx->dr[6];
754
755 /* Sync the debug state now if any breakpoint is armed. */
756 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
757 && !CPUMIsGuestDebugStateActive(pVCpu)
758 && !DBGFIsStepping(pVCpu))
759 {
760 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
761
762 /* Disable drx move intercepts. */
763 pVMCB->ctrl.u16InterceptRdDRx = 0;
764 pVMCB->ctrl.u16InterceptWrDRx = 0;
765
766 /* Save the host and load the guest debug state. */
767 int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
768 AssertRC(rc);
769 }
770 }
771
772 /* EIP, ESP and EFLAGS */
773 pVMCB->guest.u64RIP = pCtx->rip;
774 pVMCB->guest.u64RSP = pCtx->rsp;
775 pVMCB->guest.u64RFlags = pCtx->eflags.u32;
776
777 /* Set CPL */
778 pVMCB->guest.u8CPL = pCtx->csHid.Attr.n.u2Dpl;
779
780 /* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
781 pVMCB->guest.u64RAX = pCtx->rax;
782
783 /* vmrun will fail without MSR_K6_EFER_SVME. */
784 pVMCB->guest.u64EFER = pCtx->msrEFER | MSR_K6_EFER_SVME;
785
786 /* 64 bits guest mode? */
787 if (CPUMIsGuestInLongModeEx(pCtx))
788 {
789#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
790 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
791#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
792 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
793#else
794# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
795 if (!pVM->hwaccm.s.fAllow64BitGuests)
796 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
797# endif
798 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun64;
799#endif
800 /* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
801 pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
802 pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
803 }
804 else
805 {
806 /* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
807 pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
808
809 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun;
810 }
811
812 /* TSC offset. */
813 if (TMCpuTickCanUseRealTSC(pVCpu, &pVMCB->ctrl.u64TSCOffset))
814 {
815 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
816 pVMCB->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
817 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
818 }
819 else
820 {
821 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
822 pVMCB->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;
823 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
824 }
825
826 /* Sync the various msrs for 64 bits mode. */
827 pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
828 pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
829 pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
830 pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
831 pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
832
833#ifdef DEBUG
834 /* Intercept X86_XCPT_DB if stepping is enabled */
835 if (DBGFIsStepping(pVCpu))
836 pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_DB);
837 else
838 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_DB);
839#endif
840
841 /* Done. */
842 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
843
844 return VINF_SUCCESS;
845}
846
847
848/**
849 * Runs guest code in an AMD-V VM.
850 *
851 * @returns VBox status code.
852 * @param pVM The VM to operate on.
853 * @param pVCpu The VM CPU to operate on.
854 * @param pCtx Guest context
855 */
856VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
857{
858 int rc = VINF_SUCCESS;
859 uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
860 SVM_VMCB *pVMCB;
861 bool fSyncTPR = false;
862 unsigned cResume = 0;
863 uint8_t u8LastTPR;
864 PHWACCM_CPUINFO pCpu = 0;
865 RTCCUINTREG uOldEFlags = ~(RTCCUINTREG)0;
866#ifdef VBOX_STRICT
867 RTCPUID idCpuCheck;
868#endif
869#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
870 uint64_t u64LastTime = RTTimeMilliTS();
871#endif
872
873 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
874
875 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
876 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
877
878 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
879 */
880ResumeExecution:
881 Assert(!HWACCMR0SuspendPending());
882
883 /* Safety precaution; looping for too long here can have a very bad effect on the host */
884 if (RT_UNLIKELY(++cResume > pVM->hwaccm.s.cMaxResumeLoops))
885 {
886 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
887 rc = VINF_EM_RAW_INTERRUPT;
888 goto end;
889 }
890
891 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
892 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
893 {
894 Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
895 if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
896 {
897 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
898 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
899 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
900 * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
901 */
902 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
903 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
904 pVMCB->ctrl.u64IntShadow = 0;
905 }
906 }
907 else
908 {
909 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
910 pVMCB->ctrl.u64IntShadow = 0;
911 }
912
913#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
914 if (RT_UNLIKELY(cResume & 0xf) == 0)
915 {
916 uint64_t u64CurTime = RTTimeMilliTS();
917
918 if (RT_UNLIKELY(u64CurTime > u64LastTime))
919 {
920 u64LastTime = u64CurTime;
921 TMTimerPollVoid(pVM, pVCpu);
922 }
923 }
924#endif
925
926 /* Check for pending actions that force us to go back to ring 3. */
927#ifdef DEBUG
928 /* Intercept X86_XCPT_DB if stepping is enabled */
929 if (!DBGFIsStepping(pVCpu))
930#endif
931 {
932 if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK)
933 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
934 {
935 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
936 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
937 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
938 rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
939 goto end;
940 }
941 }
942
943 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
944 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
945 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
946 {
947 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
948 rc = VINF_EM_PENDING_REQUEST;
949 goto end;
950 }
951
952#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
953 /*
954 * Exit to ring-3 preemption/work is pending.
955 *
956 * Interrupts are disabled before the call to make sure we don't miss any interrupt
957 * that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
958 * further down, but SVMR0CheckPendingInterrupt makes that impossible.)
959 *
960 * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
961 * shootdowns rely on this.
962 */
963 uOldEFlags = ASMIntDisableFlags();
964 if (RTThreadPreemptIsPending(NIL_RTTHREAD))
965 {
966 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);
967 rc = VINF_EM_RAW_INTERRUPT;
968 goto end;
969 }
970 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
971#endif
972
973 /* When external interrupts are pending, we should exit the VM when IF is set. */
974 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
975 rc = SVMR0CheckPendingInterrupt(pVM, pVCpu, pVMCB, pCtx);
976 if (RT_FAILURE(rc))
977 {
978 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
979 goto end;
980 }
981
982 /* TPR caching using CR8 is only available in 64 bits mode or with 32 bits guests when X86_CPUID_AMD_FEATURE_ECX_CR8L is supported. */
983 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!!
984 * @todo query and update the TPR only when it could have been changed (mmio access)
985 */
986 if (pVM->hwaccm.s.fHasIoApic)
987 {
988 bool fPending;
989
990 /* TPR caching in CR8 */
991 int rc = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);
992 AssertRC(rc);
993 pVMCB->ctrl.IntCtrl.n.u8VTPR = (u8LastTPR >> 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
994
995 if (fPending)
996 {
997 /* A TPR change could activate a pending interrupt, so catch cr8 writes. */
998 pVMCB->ctrl.u16InterceptWrCRx |= RT_BIT(8);
999 }
1000 else
1001 /* No interrupts are pending, so we don't need to be explicitely notified.
1002 * There are enough world switches for detecting pending interrupts.
1003 */
1004 pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1005
1006 fSyncTPR = !fPending;
1007 }
1008
1009 /* All done! Let's start VM execution. */
1010 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, x);
1011
1012 /* Enable nested paging if necessary (disabled each time after #VMEXIT). */
1013 pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
1014
1015#ifdef LOG_ENABLED
1016 pCpu = HWACCMR0GetCurrentCpu();
1017 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1018 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1019 {
1020 if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
1021 Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
1022 else
1023 Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1024 }
1025 if (pCpu->fFlushTLB)
1026 Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
1027#endif
1028
1029 /*
1030 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1031 * (until the actual world switch)
1032 */
1033#ifdef VBOX_STRICT
1034 idCpuCheck = RTMpCpuId();
1035#endif
1036 VMMR0LogFlushDisable(pVCpu);
1037
1038 /* Load the guest state; *must* be here as it sets up the shadow cr0 for lazy fpu syncing! */
1039 rc = SVMR0LoadGuestState(pVM, pVCpu, pCtx);
1040 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1041 {
1042 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1043 VMMR0LogFlushEnable(pVCpu);
1044 goto end;
1045 }
1046
1047#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1048 /* Disable interrupts to make sure a poke will interrupt execution.
1049 * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
1050 */
1051 uOldEFlags = ASMIntDisableFlags();
1052 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1053#endif
1054
1055 pCpu = HWACCMR0GetCurrentCpu();
1056 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1057 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1058 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1059 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1060 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1061 {
1062 /* Force a TLB flush on VM entry. */
1063 pVCpu->hwaccm.s.fForceTLBFlush = true;
1064 }
1065 else
1066 Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1067
1068 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1069
1070 /* Check for tlb shootdown flushes. */
1071 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH_BIT))
1072 pVCpu->hwaccm.s.fForceTLBFlush = true;
1073
1074 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1075 if ( pVCpu->hwaccm.s.fForceTLBFlush
1076 && !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
1077 {
1078 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1079 || pCpu->fFlushTLB)
1080 {
1081 pCpu->fFlushTLB = false;
1082 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1083 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
1084 pCpu->cTLBFlushes++;
1085 }
1086 else
1087 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1088
1089 pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1090 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1091 }
1092 else
1093 {
1094 Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1095
1096 /* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
1097 if (!pCpu->uCurrentASID || !pVCpu->hwaccm.s.uCurrentASID)
1098 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
1099
1100 Assert(!pVM->hwaccm.s.svm.fAlwaysFlushTLB || pVCpu->hwaccm.s.fForceTLBFlush);
1101 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVCpu->hwaccm.s.fForceTLBFlush;
1102
1103 if ( !pVM->hwaccm.s.svm.fAlwaysFlushTLB
1104 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1105 {
1106 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1107 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1108 for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1109 SVMR0InvlpgA(pVCpu->hwaccm.s.TlbShootdown.aPages[i], pVMCB->ctrl.TLBCtrl.n.u32ASID);
1110 }
1111 }
1112 pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1113 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1114
1115 AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1116 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1117 AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1118 pVMCB->ctrl.TLBCtrl.n.u32ASID = pVCpu->hwaccm.s.uCurrentASID;
1119
1120#ifdef VBOX_WITH_STATISTICS
1121 if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
1122 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1123 else
1124 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1125#endif
1126
1127 /* In case we execute a goto ResumeExecution later on. */
1128 pVCpu->hwaccm.s.fResumeVM = true;
1129 pVCpu->hwaccm.s.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
1130
1131 Assert(sizeof(pVCpu->hwaccm.s.svm.pVMCBPhys) == 8);
1132 Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
1133 Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
1134 Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
1135 Assert(pVMCB->ctrl.u64LBRVirt == 0);
1136
1137#ifdef VBOX_STRICT
1138 Assert(idCpuCheck == RTMpCpuId());
1139#endif
1140 TMNotifyStartOfExecution(pVCpu);
1141#ifdef VBOX_WITH_KERNEL_USING_XMM
1142 hwaccmR0SVMRunWrapXMM(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu, pVCpu->hwaccm.s.svm.pfnVMRun);
1143#else
1144 pVCpu->hwaccm.s.svm.pfnVMRun(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu);
1145#endif
1146 TMNotifyEndOfExecution(pVCpu);
1147 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
1148 ASMSetFlags(uOldEFlags);
1149#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1150 uOldEFlags = ~(RTCCUINTREG)0;
1151#endif
1152 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, x);
1153
1154 /*
1155 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1156 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1157 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1158 */
1159
1160 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, x);
1161
1162 /* Reason for the VM exit */
1163 exitCode = pVMCB->ctrl.u64ExitCode;
1164
1165 if (RT_UNLIKELY(exitCode == (uint64_t)SVM_EXIT_INVALID)) /* Invalid guest state. */
1166 {
1167 HWACCMDumpRegs(pVM, pVCpu, pCtx);
1168#ifdef DEBUG
1169 Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
1170 Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
1171 Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
1172 Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
1173 Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
1174 Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
1175 Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
1176 Log(("ctrl.u64IOPMPhysAddr %RX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
1177 Log(("ctrl.u64MSRPMPhysAddr %RX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
1178 Log(("ctrl.u64TSCOffset %RX64\n", pVMCB->ctrl.u64TSCOffset));
1179
1180 Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
1181 Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
1182 Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
1183 Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
1184
1185 Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
1186 Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
1187 Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
1188 Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
1189 Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
1190 Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
1191 Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
1192 Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
1193 Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
1194 Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
1195
1196 Log(("ctrl.u64IntShadow %RX64\n", pVMCB->ctrl.u64IntShadow));
1197 Log(("ctrl.u64ExitCode %RX64\n", pVMCB->ctrl.u64ExitCode));
1198 Log(("ctrl.u64ExitInfo1 %RX64\n", pVMCB->ctrl.u64ExitInfo1));
1199 Log(("ctrl.u64ExitInfo2 %RX64\n", pVMCB->ctrl.u64ExitInfo2));
1200 Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
1201 Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
1202 Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
1203 Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
1204 Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
1205 Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
1206 Log(("ctrl.NestedPaging %RX64\n", pVMCB->ctrl.NestedPaging.au64));
1207 Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
1208 Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
1209 Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
1210 Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
1211 Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
1212 Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
1213
1214 Log(("ctrl.u64NestedPagingCR3 %RX64\n", pVMCB->ctrl.u64NestedPagingCR3));
1215 Log(("ctrl.u64LBRVirt %RX64\n", pVMCB->ctrl.u64LBRVirt));
1216
1217 Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
1218 Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1219 Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1220 Log(("guest.CS.u64Base %RX64\n", pVMCB->guest.CS.u64Base));
1221 Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1222 Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1223 Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1224 Log(("guest.DS.u64Base %RX64\n", pVMCB->guest.DS.u64Base));
1225 Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1226 Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1227 Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1228 Log(("guest.ES.u64Base %RX64\n", pVMCB->guest.ES.u64Base));
1229 Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1230 Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1231 Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1232 Log(("guest.FS.u64Base %RX64\n", pVMCB->guest.FS.u64Base));
1233 Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1234 Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1235 Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1236 Log(("guest.GS.u64Base %RX64\n", pVMCB->guest.GS.u64Base));
1237
1238 Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1239 Log(("guest.GDTR.u64Base %RX64\n", pVMCB->guest.GDTR.u64Base));
1240
1241 Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1242 Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1243 Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1244 Log(("guest.LDTR.u64Base %RX64\n", pVMCB->guest.LDTR.u64Base));
1245
1246 Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1247 Log(("guest.IDTR.u64Base %RX64\n", pVMCB->guest.IDTR.u64Base));
1248
1249 Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1250 Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1251 Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1252 Log(("guest.TR.u64Base %RX64\n", pVMCB->guest.TR.u64Base));
1253
1254 Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1255 Log(("guest.u64CR0 %RX64\n", pVMCB->guest.u64CR0));
1256 Log(("guest.u64CR2 %RX64\n", pVMCB->guest.u64CR2));
1257 Log(("guest.u64CR3 %RX64\n", pVMCB->guest.u64CR3));
1258 Log(("guest.u64CR4 %RX64\n", pVMCB->guest.u64CR4));
1259 Log(("guest.u64DR6 %RX64\n", pVMCB->guest.u64DR6));
1260 Log(("guest.u64DR7 %RX64\n", pVMCB->guest.u64DR7));
1261
1262 Log(("guest.u64RIP %RX64\n", pVMCB->guest.u64RIP));
1263 Log(("guest.u64RSP %RX64\n", pVMCB->guest.u64RSP));
1264 Log(("guest.u64RAX %RX64\n", pVMCB->guest.u64RAX));
1265 Log(("guest.u64RFlags %RX64\n", pVMCB->guest.u64RFlags));
1266
1267 Log(("guest.u64SysEnterCS %RX64\n", pVMCB->guest.u64SysEnterCS));
1268 Log(("guest.u64SysEnterEIP %RX64\n", pVMCB->guest.u64SysEnterEIP));
1269 Log(("guest.u64SysEnterESP %RX64\n", pVMCB->guest.u64SysEnterESP));
1270
1271 Log(("guest.u64EFER %RX64\n", pVMCB->guest.u64EFER));
1272 Log(("guest.u64STAR %RX64\n", pVMCB->guest.u64STAR));
1273 Log(("guest.u64LSTAR %RX64\n", pVMCB->guest.u64LSTAR));
1274 Log(("guest.u64CSTAR %RX64\n", pVMCB->guest.u64CSTAR));
1275 Log(("guest.u64SFMASK %RX64\n", pVMCB->guest.u64SFMASK));
1276 Log(("guest.u64KernelGSBase %RX64\n", pVMCB->guest.u64KernelGSBase));
1277 Log(("guest.u64GPAT %RX64\n", pVMCB->guest.u64GPAT));
1278 Log(("guest.u64DBGCTL %RX64\n", pVMCB->guest.u64DBGCTL));
1279 Log(("guest.u64BR_FROM %RX64\n", pVMCB->guest.u64BR_FROM));
1280 Log(("guest.u64BR_TO %RX64\n", pVMCB->guest.u64BR_TO));
1281 Log(("guest.u64LASTEXCPFROM %RX64\n", pVMCB->guest.u64LASTEXCPFROM));
1282 Log(("guest.u64LASTEXCPTO %RX64\n", pVMCB->guest.u64LASTEXCPTO));
1283
1284#endif
1285 rc = VERR_SVM_UNABLE_TO_START_VM;
1286 VMMR0LogFlushEnable(pVCpu);
1287 goto end;
1288 }
1289
1290 /* Let's first sync back eip, esp, and eflags. */
1291 pCtx->rip = pVMCB->guest.u64RIP;
1292 pCtx->rsp = pVMCB->guest.u64RSP;
1293 pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1294 /* eax is saved/restore across the vmrun instruction */
1295 pCtx->rax = pVMCB->guest.u64RAX;
1296
1297 pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
1298
1299 /* Can be updated behind our back in the nested paging case. */
1300 pCtx->cr2 = pVMCB->guest.u64CR2;
1301
1302 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1303 SVM_READ_SELREG(SS, ss);
1304 SVM_READ_SELREG(CS, cs);
1305 SVM_READ_SELREG(DS, ds);
1306 SVM_READ_SELREG(ES, es);
1307 SVM_READ_SELREG(FS, fs);
1308 SVM_READ_SELREG(GS, gs);
1309
1310 /*
1311 * System MSRs
1312 */
1313 pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1314 pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1315 pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1316
1317 /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1318 SVM_READ_SELREG(LDTR, ldtr);
1319 SVM_READ_SELREG(TR, tr);
1320
1321 pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1322 pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1323
1324 pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1325 pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1326
1327 /* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1328 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1329 if ( pVM->hwaccm.s.fNestedPaging
1330 && pCtx->cr3 != pVMCB->guest.u64CR3)
1331 {
1332 CPUMSetGuestCR3(pVCpu, pVMCB->guest.u64CR3);
1333 PGMUpdateCR3(pVCpu, pVMCB->guest.u64CR3);
1334 }
1335
1336 /* Note! NOW IT'S SAFE FOR LOGGING! */
1337 VMMR0LogFlushEnable(pVCpu);
1338
1339 /* Take care of instruction fusing (sti, mov ss) (see 15.20.5 Interrupt Shadows) */
1340 if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1341 {
1342 Log(("uInterruptState %x rip=%RGv\n", pVMCB->ctrl.u64IntShadow, (RTGCPTR)pCtx->rip));
1343 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
1344 }
1345 else
1346 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1347
1348 Log2(("exitCode = %x\n", exitCode));
1349
1350 /* Sync back DR6 as it could have been changed by hitting breakpoints. */
1351 pCtx->dr[6] = pVMCB->guest.u64DR6;
1352 /* DR7.GD can be cleared by debug exceptions, so sync it back as well. */
1353 pCtx->dr[7] = pVMCB->guest.u64DR7;
1354
1355 /* Check if an injected event was interrupted prematurely. */
1356 pVCpu->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1357 if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1358 && pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1359 {
1360 Log(("Pending inject %RX64 at %RGv exit=%08x\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitCode));
1361
1362#ifdef LOG_ENABLED
1363 SVM_EVENT Event;
1364 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
1365
1366 if ( exitCode == SVM_EXIT_EXCEPTION_E
1367 && Event.n.u8Vector == 0xE)
1368 {
1369 Log(("Double fault!\n"));
1370 }
1371#endif
1372
1373 pVCpu->hwaccm.s.Event.fPending = true;
1374 /* Error code present? (redundant) */
1375 if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1376 pVCpu->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1377 else
1378 pVCpu->hwaccm.s.Event.errCode = 0;
1379 }
1380#ifdef VBOX_WITH_STATISTICS
1381 if (exitCode == SVM_EXIT_NPF)
1382 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
1383 else
1384 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1385#endif
1386
1387 /* Sync back the TPR if it was changed. */
1388 if ( fSyncTPR
1389 && (u8LastTPR >> 4) != pVMCB->ctrl.IntCtrl.n.u8VTPR)
1390 {
1391 rc = PDMApicSetTPR(pVCpu, pVMCB->ctrl.IntCtrl.n.u8VTPR << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1392 AssertRC(rc);
1393 }
1394
1395 /* Deal with the reason of the VM-exit. */
1396 switch (exitCode)
1397 {
1398 case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1399 case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1400 case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1401 case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1402 case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1403 case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1404 case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1405 case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1406 {
1407 /* Pending trap. */
1408 SVM_EVENT Event;
1409 uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1410
1411 Log2(("Hardware/software interrupt %d\n", vector));
1412 switch (vector)
1413 {
1414 case X86_XCPT_DB:
1415 {
1416 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
1417
1418 /* Note that we don't support guest and host-initiated debugging at the same time. */
1419 Assert(DBGFIsStepping(pVCpu));
1420
1421 rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
1422 if (rc == VINF_EM_RAW_GUEST_TRAP)
1423 {
1424 Log(("Trap %x (debug) at %016RX64\n", vector, pCtx->rip));
1425
1426 /* Reinject the exception. */
1427 Event.au64[0] = 0;
1428 Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
1429 Event.n.u1Valid = 1;
1430 Event.n.u8Vector = X86_XCPT_DB;
1431
1432 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1433
1434 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1435 goto ResumeExecution;
1436 }
1437 /* Return to ring 3 to deal with the debug exit code. */
1438 break;
1439 }
1440
1441 case X86_XCPT_NM:
1442 {
1443 Log(("#NM fault at %RGv\n", (RTGCPTR)pCtx->rip));
1444
1445 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1446 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1447 rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
1448 if (rc == VINF_SUCCESS)
1449 {
1450 Assert(CPUMIsGuestFPUStateActive(pVCpu));
1451 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
1452
1453 /* Continue execution. */
1454 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1455 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1456
1457 goto ResumeExecution;
1458 }
1459
1460 Log(("Forward #NM fault to the guest\n"));
1461 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
1462
1463 Event.au64[0] = 0;
1464 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1465 Event.n.u1Valid = 1;
1466 Event.n.u8Vector = X86_XCPT_NM;
1467
1468 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1469 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1470 goto ResumeExecution;
1471 }
1472
1473 case X86_XCPT_PF: /* Page fault */
1474 {
1475 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1476 RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1477
1478#ifdef DEBUG
1479 if (pVM->hwaccm.s.fNestedPaging)
1480 { /* A genuine pagefault.
1481 * Forward the trap to the guest by injecting the exception and resuming execution.
1482 */
1483 Log(("Guest page fault at %04X:%RGv cr2=%RGv error code %x rsp=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
1484 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1485
1486 /* Now we must update CR2. */
1487 pCtx->cr2 = uFaultAddress;
1488
1489 Event.au64[0] = 0;
1490 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1491 Event.n.u1Valid = 1;
1492 Event.n.u8Vector = X86_XCPT_PF;
1493 Event.n.u1ErrorCodeValid = 1;
1494 Event.n.u32ErrorCode = errCode;
1495
1496 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1497
1498 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1499 goto ResumeExecution;
1500 }
1501#endif
1502 Assert(!pVM->hwaccm.s.fNestedPaging);
1503
1504#if 0
1505 /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1506 if ( (uFaultAddress & 0xfff) == 0x080
1507 && pVM->hwaccm.s.fHasIoApic
1508 && !(errCode & X86_TRAP_PF_P) /* not present */
1509 && !CPUMIsGuestInLongModeEx(pCtx))
1510 {
1511 RTGCPHYS GCPhysApicBase, GCPhys;
1512 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1513 GCPhysApicBase &= PAGE_BASE_GC_MASK;
1514
1515 rc = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL, &GCPhys);
1516 if ( rc == VINF_SUCCESS
1517 && GCPhys == GCPhysApicBase)
1518 {
1519 Log(("Replace TPR access at %RGv\n", pCtx->rip));
1520
1521 DISCPUSTATE Cpu;
1522 unsigned cbOp;
1523 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);
1524 AssertRC(rc);
1525 if ( rc == VINF_SUCCESS
1526 && Cpu.pCurInstr->opcode == OP_MOV
1527 && (cbOp == 5 || cbOp == 6))
1528 {
1529 uint8_t szInstr[15];
1530 if ( (errCode & X86_TRAP_PF_RW)
1531 && Cpu.param1.disp32 == (uint32_t)uFaultAddress
1532 && Cpu.param2.flags == USE_REG_GEN32)
1533 {
1534 /* 0xF0, 0x0F, 0x22, 0xC0 = mov cr8, eax */
1535 szInstr[0] = 0xF0;
1536 szInstr[1] = 0x0F;
1537 szInstr[2] = 0x22;
1538 szInstr[3] = 0xC0 | Cpu.param2.base.reg_gen;
1539 for (unsigned i = 4; i < cbOp; i++)
1540 szInstr[i] = 0x90; /* nop */
1541
1542 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, cbOp);
1543 AssertRC(rc);
1544
1545 Log(("Acceptable write candidate!\n"));
1546 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1547 goto ResumeExecution;
1548 }
1549 else
1550 if ( Cpu.param2.disp32 == (uint32_t)uFaultAddress
1551 && Cpu.param1.flags == USE_REG_GEN32)
1552 {
1553 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1554 szInstr[0] = 0xF0;
1555 szInstr[1] = 0x0F;
1556 szInstr[2] = 0x20;
1557 szInstr[3] = 0xC0 | Cpu.param1.base.reg_gen;
1558 for (unsigned i = 4; i < cbOp; i++)
1559 szInstr[i] = 0x90; /* nop */
1560
1561 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, cbOp);
1562 AssertRC(rc);
1563
1564 Log(("Acceptable read candidate!\n"));
1565 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1566 goto ResumeExecution;
1567 }
1568 }
1569 }
1570 }
1571#endif
1572
1573 Log2(("Page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1574 /* Exit qualification contains the linear address of the page fault. */
1575 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1576 TRPMSetErrorCode(pVCpu, errCode);
1577 TRPMSetFaultAddress(pVCpu, uFaultAddress);
1578
1579 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1580 rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1581 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1582 if (rc == VINF_SUCCESS)
1583 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1584 Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1585 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1586
1587 TRPMResetTrap(pVCpu);
1588
1589 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1590 goto ResumeExecution;
1591 }
1592 else
1593 if (rc == VINF_EM_RAW_GUEST_TRAP)
1594 { /* A genuine pagefault.
1595 * Forward the trap to the guest by injecting the exception and resuming execution.
1596 */
1597 Log2(("Forward page fault to the guest\n"));
1598 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1599 /* The error code might have been changed. */
1600 errCode = TRPMGetErrorCode(pVCpu);
1601
1602 TRPMResetTrap(pVCpu);
1603
1604 /* Now we must update CR2. */
1605 pCtx->cr2 = uFaultAddress;
1606
1607 Event.au64[0] = 0;
1608 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1609 Event.n.u1Valid = 1;
1610 Event.n.u8Vector = X86_XCPT_PF;
1611 Event.n.u1ErrorCodeValid = 1;
1612 Event.n.u32ErrorCode = errCode;
1613
1614 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1615
1616 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1617 goto ResumeExecution;
1618 }
1619#ifdef VBOX_STRICT
1620 if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
1621 LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
1622#endif
1623 /* Need to go back to the recompiler to emulate the instruction. */
1624 TRPMResetTrap(pVCpu);
1625 break;
1626 }
1627
1628 case X86_XCPT_MF: /* Floating point exception. */
1629 {
1630 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
1631 if (!(pCtx->cr0 & X86_CR0_NE))
1632 {
1633 /* old style FPU error reporting needs some extra work. */
1634 /** @todo don't fall back to the recompiler, but do it manually. */
1635 rc = VINF_EM_RAW_EMULATE_INSTR;
1636 break;
1637 }
1638 Log(("Trap %x at %RGv\n", vector, (RTGCPTR)pCtx->rip));
1639
1640 Event.au64[0] = 0;
1641 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1642 Event.n.u1Valid = 1;
1643 Event.n.u8Vector = X86_XCPT_MF;
1644
1645 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1646
1647 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1648 goto ResumeExecution;
1649 }
1650
1651#ifdef VBOX_STRICT
1652 case X86_XCPT_GP: /* General protection failure exception.*/
1653 case X86_XCPT_UD: /* Unknown opcode exception. */
1654 case X86_XCPT_DE: /* Divide error. */
1655 case X86_XCPT_SS: /* Stack segment exception. */
1656 case X86_XCPT_NP: /* Segment not present exception. */
1657 {
1658 Event.au64[0] = 0;
1659 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1660 Event.n.u1Valid = 1;
1661 Event.n.u8Vector = vector;
1662
1663 switch(vector)
1664 {
1665 case X86_XCPT_GP:
1666 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
1667 Event.n.u1ErrorCodeValid = 1;
1668 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1669 break;
1670 case X86_XCPT_DE:
1671 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
1672 break;
1673 case X86_XCPT_UD:
1674 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
1675 break;
1676 case X86_XCPT_SS:
1677 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
1678 Event.n.u1ErrorCodeValid = 1;
1679 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1680 break;
1681 case X86_XCPT_NP:
1682 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
1683 Event.n.u1ErrorCodeValid = 1;
1684 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1685 break;
1686 }
1687 Log(("Trap %x at %04x:%RGv esi=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->esi));
1688 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1689
1690 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1691 goto ResumeExecution;
1692 }
1693#endif
1694 default:
1695 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1696 rc = VERR_EM_INTERNAL_ERROR;
1697 break;
1698
1699 } /* switch (vector) */
1700 break;
1701 }
1702
1703 case SVM_EXIT_NPF:
1704 {
1705 /* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1706 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1707 RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1708 PGMMODE enmShwPagingMode;
1709
1710 Assert(pVM->hwaccm.s.fNestedPaging);
1711 LogFlow(("Nested page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1712
1713#if 0
1714 /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1715 if ( (uFaultAddress & 0xfff) == 0x080
1716 && pVM->hwaccm.s.fHasIoApic
1717 && !(errCode & X86_TRAP_PF_P) /* not present */
1718 && CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
1719 && !CPUMIsGuestInLongModeEx(pCtx))
1720 {
1721 RTGCPHYS GCPhysApicBase;
1722 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1723 GCPhysApicBase &= PAGE_BASE_GC_MASK;
1724
1725 if (uFaultAddress == GCPhysApicBase + 0x80)
1726 {
1727 rc = svmR0ReplaceTprInstr(pVM, pVCpu, pCtx);
1728 if (rc == VINF_SUCCESS)
1729 {
1730 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1731 goto ResumeExecution;
1732 }
1733
1734 rc = IOMMMIOPhysHandler(pVM, errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1735 if (rc == VINF_SUCCESS)
1736 {
1737 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1738 goto ResumeExecution; /* rip already updated */
1739 }
1740 }
1741 }
1742#endif
1743
1744 /* Exit qualification contains the linear address of the page fault. */
1745 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1746 TRPMSetErrorCode(pVCpu, errCode);
1747 TRPMSetFaultAddress(pVCpu, uFaultAddress);
1748
1749 /* Handle the pagefault trap for the nested shadow table. */
1750#if HC_ARCH_BITS == 32
1751 if (CPUMIsGuestInLongModeEx(pCtx))
1752 enmShwPagingMode = PGMMODE_AMD64_NX;
1753 else
1754#endif
1755 enmShwPagingMode = PGMGetHostMode(pVM);
1756
1757 rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmShwPagingMode, errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1758 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1759 if (rc == VINF_SUCCESS)
1760 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1761 Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1762 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1763
1764 TRPMResetTrap(pVCpu);
1765
1766 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1767 goto ResumeExecution;
1768 }
1769
1770#ifdef VBOX_STRICT
1771 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1772 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
1773#endif
1774 /* Need to go back to the recompiler to emulate the instruction. */
1775 TRPMResetTrap(pVCpu);
1776 break;
1777 }
1778
1779 case SVM_EXIT_VINTR:
1780 /* A virtual interrupt is about to be delivered, which means IF=1. */
1781 Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1782 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1783 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1784 goto ResumeExecution;
1785
1786 case SVM_EXIT_FERR_FREEZE:
1787 case SVM_EXIT_INTR:
1788 case SVM_EXIT_NMI:
1789 case SVM_EXIT_SMI:
1790 case SVM_EXIT_INIT:
1791 /* External interrupt; leave to allow it to be dispatched again. */
1792 rc = VINF_EM_RAW_INTERRUPT;
1793 break;
1794
1795 case SVM_EXIT_WBINVD:
1796 case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1797 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
1798 /* Skip instruction and continue directly. */
1799 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1800 /* Continue execution.*/
1801 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1802 goto ResumeExecution;
1803
1804 case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1805 {
1806 Log2(("SVM: Cpuid at %RGv for %x\n", (RTGCPTR)pCtx->rip, pCtx->eax));
1807 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
1808 rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1809 if (rc == VINF_SUCCESS)
1810 {
1811 /* Update EIP and continue execution. */
1812 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1813 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1814 goto ResumeExecution;
1815 }
1816 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
1817 rc = VINF_EM_RAW_EMULATE_INSTR;
1818 break;
1819 }
1820
1821 case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1822 {
1823 Log2(("SVM: Rdtsc\n"));
1824 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1825 rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1826 if (rc == VINF_SUCCESS)
1827 {
1828 /* Update EIP and continue execution. */
1829 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1830 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1831 goto ResumeExecution;
1832 }
1833 rc = VINF_EM_RAW_EMULATE_INSTR;
1834 break;
1835 }
1836
1837 case SVM_EXIT_RDPMC: /* Guest software attempted to execute RDPMC. */
1838 {
1839 Log2(("SVM: Rdpmc %x\n", pCtx->ecx));
1840 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdpmc);
1841 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1842 if (rc == VINF_SUCCESS)
1843 {
1844 /* Update EIP and continue execution. */
1845 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1846 goto ResumeExecution;
1847 }
1848 rc = VINF_EM_RAW_EMULATE_INSTR;
1849 break;
1850 }
1851
1852 case SVM_EXIT_RDTSCP: /* Guest software attempted to execute RDTSCP. */
1853 {
1854 Log2(("SVM: Rdtscp\n"));
1855 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1856 rc = EMInterpretRdtscp(pVM, pVCpu, pCtx);
1857 if (rc == VINF_SUCCESS)
1858 {
1859 /* Update EIP and continue execution. */
1860 pCtx->rip += 3; /* Note! hardcoded opcode size! */
1861 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1862 goto ResumeExecution;
1863 }
1864 AssertMsgFailed(("EMU: rdtscp failed with %Rrc\n", rc));
1865 rc = VINF_EM_RAW_EMULATE_INSTR;
1866 break;
1867 }
1868
1869 case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1870 {
1871 Log2(("SVM: invlpg\n"));
1872 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
1873
1874 Assert(!pVM->hwaccm.s.fNestedPaging);
1875
1876 /* Truly a pita. Why can't SVM give the same information as VT-x? */
1877 rc = svmR0InterpretInvpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1878 if (rc == VINF_SUCCESS)
1879 {
1880 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushPageInvlpg);
1881 goto ResumeExecution; /* eip already updated */
1882 }
1883 break;
1884 }
1885
1886 case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1887 case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1888 case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1889 case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1890 {
1891 uint32_t cbSize;
1892
1893 Log2(("SVM: %RGv mov cr%d, \n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
1894 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[exitCode - SVM_EXIT_WRITE_CR0]);
1895 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
1896
1897 switch (exitCode - SVM_EXIT_WRITE_CR0)
1898 {
1899 case 0:
1900 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1901 break;
1902 case 2:
1903 break;
1904 case 3:
1905 Assert(!pVM->hwaccm.s.fNestedPaging);
1906 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
1907 break;
1908 case 4:
1909 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
1910 break;
1911 case 8:
1912 break;
1913 default:
1914 AssertFailed();
1915 }
1916 /* Check if a sync operation is pending. */
1917 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1918 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1919 {
1920 rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1921 AssertRC(rc);
1922
1923 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBCRxChange);
1924
1925 /* Must be set by PGMSyncCR3 */
1926 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || PGMGetGuestMode(pVCpu) <= PGMMODE_PROTECTED || pVCpu->hwaccm.s.fForceTLBFlush,
1927 ("rc=%Rrc mode=%d fForceTLBFlush=%RTbool\n", rc, PGMGetGuestMode(pVCpu), pVCpu->hwaccm.s.fForceTLBFlush));
1928 }
1929 if (rc == VINF_SUCCESS)
1930 {
1931 /* EIP has been updated already. */
1932
1933 /* Only resume if successful. */
1934 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1935 goto ResumeExecution;
1936 }
1937 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1938 break;
1939 }
1940
1941 case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1942 case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1943 case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1944 case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1945 {
1946 uint32_t cbSize;
1947
1948 Log2(("SVM: %RGv mov x, cr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
1949 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[exitCode - SVM_EXIT_READ_CR0]);
1950 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
1951 if (rc == VINF_SUCCESS)
1952 {
1953 /* EIP has been updated already. */
1954
1955 /* Only resume if successful. */
1956 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1957 goto ResumeExecution;
1958 }
1959 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1960 break;
1961 }
1962
1963 case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1964 case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1965 case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1966 case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1967 {
1968 uint32_t cbSize;
1969
1970 Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
1971 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
1972
1973 if (!DBGFIsStepping(pVCpu))
1974 {
1975 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
1976
1977 /* Disable drx move intercepts. */
1978 pVMCB->ctrl.u16InterceptRdDRx = 0;
1979 pVMCB->ctrl.u16InterceptWrDRx = 0;
1980
1981 /* Save the host and load the guest debug state. */
1982 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
1983 AssertRC(rc);
1984
1985 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1986 goto ResumeExecution;
1987 }
1988
1989 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
1990 if (rc == VINF_SUCCESS)
1991 {
1992 /* EIP has been updated already. */
1993 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
1994
1995 /* Only resume if successful. */
1996 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1997 goto ResumeExecution;
1998 }
1999 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2000 break;
2001 }
2002
2003 case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
2004 case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
2005 case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
2006 case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
2007 {
2008 uint32_t cbSize;
2009
2010 Log2(("SVM: %RGv mov x, dr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
2011 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
2012
2013 if (!DBGFIsStepping(pVCpu))
2014 {
2015 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2016
2017 /* Disable drx move intercepts. */
2018 pVMCB->ctrl.u16InterceptRdDRx = 0;
2019 pVMCB->ctrl.u16InterceptWrDRx = 0;
2020
2021 /* Save the host and load the guest debug state. */
2022 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2023 AssertRC(rc);
2024
2025 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2026 goto ResumeExecution;
2027 }
2028
2029 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2030 if (rc == VINF_SUCCESS)
2031 {
2032 /* EIP has been updated already. */
2033
2034 /* Only resume if successful. */
2035 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2036 goto ResumeExecution;
2037 }
2038 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2039 break;
2040 }
2041
2042 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2043 case SVM_EXIT_IOIO: /* I/O instruction. */
2044 {
2045 SVM_IOIO_EXIT IoExitInfo;
2046 uint32_t uIOSize, uAndVal;
2047
2048 IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
2049
2050 /** @todo could use a lookup table here */
2051 if (IoExitInfo.n.u1OP8)
2052 {
2053 uIOSize = 1;
2054 uAndVal = 0xff;
2055 }
2056 else
2057 if (IoExitInfo.n.u1OP16)
2058 {
2059 uIOSize = 2;
2060 uAndVal = 0xffff;
2061 }
2062 else
2063 if (IoExitInfo.n.u1OP32)
2064 {
2065 uIOSize = 4;
2066 uAndVal = 0xffffffff;
2067 }
2068 else
2069 {
2070 AssertFailed(); /* should be fatal. */
2071 rc = VINF_EM_RAW_EMULATE_INSTR;
2072 break;
2073 }
2074
2075 if (IoExitInfo.n.u1STR)
2076 {
2077 /* ins/outs */
2078 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2079
2080 /* Disassemble manually to deal with segment prefixes. */
2081 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL);
2082 if (rc == VINF_SUCCESS)
2083 {
2084 if (IoExitInfo.n.u1Type == 0)
2085 {
2086 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2087 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
2088 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize);
2089 }
2090 else
2091 {
2092 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2093 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
2094 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize);
2095 }
2096 }
2097 else
2098 rc = VINF_EM_RAW_EMULATE_INSTR;
2099 }
2100 else
2101 {
2102 /* normal in/out */
2103 Assert(!IoExitInfo.n.u1REP);
2104
2105 if (IoExitInfo.n.u1Type == 0)
2106 {
2107 Log2(("IOMIOPortWrite %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
2108 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
2109 rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
2110 }
2111 else
2112 {
2113 uint32_t u32Val = 0;
2114
2115 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
2116 rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
2117 if (IOM_SUCCESS(rc))
2118 {
2119 /* Write back to the EAX register. */
2120 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2121 Log2(("IOMIOPortRead %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
2122 }
2123 }
2124 }
2125 /*
2126 * Handled the I/O return codes.
2127 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2128 */
2129 if (IOM_SUCCESS(rc))
2130 {
2131 /* Update EIP and continue execution. */
2132 pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
2133 if (RT_LIKELY(rc == VINF_SUCCESS))
2134 {
2135 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
2136 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
2137 {
2138 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
2139 for (unsigned i=0;i<4;i++)
2140 {
2141 unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
2142
2143 if ( (IoExitInfo.n.u16Port >= pCtx->dr[i] && IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen)
2144 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
2145 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
2146 {
2147 SVM_EVENT Event;
2148
2149 Assert(CPUMIsGuestDebugStateActive(pVCpu));
2150
2151 /* Clear all breakpoint status flags and set the one we just hit. */
2152 pCtx->dr[6] &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
2153 pCtx->dr[6] |= (uint64_t)RT_BIT(i);
2154
2155 /* Note: AMD64 Architecture Programmer's Manual 13.1:
2156 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
2157 * the contents have been read.
2158 */
2159 pVMCB->guest.u64DR6 = pCtx->dr[6];
2160
2161 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2162 pCtx->dr[7] &= ~X86_DR7_GD;
2163
2164 /* Paranoia. */
2165 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2166 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2167 pCtx->dr[7] |= 0x400; /* must be one */
2168
2169 pVMCB->guest.u64DR7 = pCtx->dr[7];
2170
2171 /* Inject the exception. */
2172 Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
2173
2174 Event.au64[0] = 0;
2175 Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
2176 Event.n.u1Valid = 1;
2177 Event.n.u8Vector = X86_XCPT_DB;
2178
2179 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2180
2181 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2182 goto ResumeExecution;
2183 }
2184 }
2185 }
2186
2187 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2188 goto ResumeExecution;
2189 }
2190 Log2(("EM status from IO at %RGv %x size %d: %Rrc\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
2191 break;
2192 }
2193
2194#ifdef VBOX_STRICT
2195 if (rc == VINF_IOM_HC_IOPORT_READ)
2196 Assert(IoExitInfo.n.u1Type != 0);
2197 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2198 Assert(IoExitInfo.n.u1Type == 0);
2199 else
2200 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
2201#endif
2202 Log2(("Failed IO at %RGv %x size %d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2203 break;
2204 }
2205
2206 case SVM_EXIT_HLT:
2207 /** Check if external interrupts are pending; if so, don't switch back. */
2208 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
2209 pCtx->rip++; /* skip hlt */
2210 if ( pCtx->eflags.Bits.u1IF
2211 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
2212 goto ResumeExecution;
2213
2214 rc = VINF_EM_HALT;
2215 break;
2216
2217 case SVM_EXIT_MWAIT_UNCOND:
2218 Log2(("SVM: mwait\n"));
2219 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMwait);
2220 rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2221 if ( rc == VINF_EM_HALT
2222 || rc == VINF_SUCCESS)
2223 {
2224 /* Update EIP and continue execution. */
2225 pCtx->rip += 3; /* Note: hardcoded opcode size assumption! */
2226
2227 /** Check if external interrupts are pending; if so, don't switch back. */
2228 if ( rc == VINF_SUCCESS
2229 || ( rc == VINF_EM_HALT
2230 && pCtx->eflags.Bits.u1IF
2231 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
2232 )
2233 goto ResumeExecution;
2234 }
2235 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", rc));
2236 break;
2237
2238 case SVM_EXIT_RSM:
2239 case SVM_EXIT_INVLPGA:
2240 case SVM_EXIT_VMRUN:
2241 case SVM_EXIT_VMMCALL:
2242 case SVM_EXIT_VMLOAD:
2243 case SVM_EXIT_VMSAVE:
2244 case SVM_EXIT_STGI:
2245 case SVM_EXIT_CLGI:
2246 case SVM_EXIT_SKINIT:
2247 {
2248 /* Unsupported instructions. */
2249 SVM_EVENT Event;
2250
2251 Event.au64[0] = 0;
2252 Event.n.u3Type = SVM_EVENT_EXCEPTION;
2253 Event.n.u1Valid = 1;
2254 Event.n.u8Vector = X86_XCPT_UD;
2255
2256 Log(("Forced #UD trap at %RGv\n", (RTGCPTR)pCtx->rip));
2257 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2258
2259 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2260 goto ResumeExecution;
2261 }
2262
2263 /* Emulate in ring 3. */
2264 case SVM_EXIT_MSR:
2265 {
2266 uint32_t cbSize;
2267
2268 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2269 STAM_COUNTER_INC((pVMCB->ctrl.u64ExitInfo1 == 0) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
2270 Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
2271 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2272 if (rc == VINF_SUCCESS)
2273 {
2274 /* EIP has been updated already. */
2275
2276 /* Only resume if successful. */
2277 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2278 goto ResumeExecution;
2279 }
2280 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
2281 break;
2282 }
2283
2284 case SVM_EXIT_MONITOR:
2285 case SVM_EXIT_PAUSE:
2286 case SVM_EXIT_MWAIT_ARMED:
2287 case SVM_EXIT_TASK_SWITCH: /* can change CR3; emulate */
2288 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2289 break;
2290
2291 case SVM_EXIT_SHUTDOWN:
2292 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2293 break;
2294
2295 case SVM_EXIT_IDTR_READ:
2296 case SVM_EXIT_GDTR_READ:
2297 case SVM_EXIT_LDTR_READ:
2298 case SVM_EXIT_TR_READ:
2299 case SVM_EXIT_IDTR_WRITE:
2300 case SVM_EXIT_GDTR_WRITE:
2301 case SVM_EXIT_LDTR_WRITE:
2302 case SVM_EXIT_TR_WRITE:
2303 case SVM_EXIT_CR0_SEL_WRITE:
2304 default:
2305 /* Unexpected exit codes. */
2306 rc = VERR_EM_INTERNAL_ERROR;
2307 AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
2308 break;
2309 }
2310
2311end:
2312
2313 /* Signal changes for the recompiler. */
2314 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
2315
2316 /* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
2317 if (exitCode == SVM_EXIT_INTR)
2318 {
2319 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
2320 /* On the next entry we'll only sync the host context. */
2321 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
2322 }
2323 else
2324 {
2325 /* On the next entry we'll sync everything. */
2326 /** @todo we can do better than this */
2327 /* Not in the VINF_PGM_CHANGE_MODE though! */
2328 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2329 }
2330
2331 /* translate into a less severe return code */
2332 if (rc == VERR_EM_INTERPRETER)
2333 rc = VINF_EM_RAW_EMULATE_INSTR;
2334
2335 /* Just set the correct state here instead of trying to catch every goto above. */
2336 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
2337
2338#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2339 /* Restore interrupts if we exitted after disabling them. */
2340 if (uOldEFlags != ~(RTCCUINTREG)0)
2341 ASMSetFlags(uOldEFlags);
2342#endif
2343
2344 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2345 return rc;
2346}
2347
2348/**
2349 * Emulate simple mov tpr instruction
2350 *
2351 * @returns VBox status code.
2352 * @param pVCpu The VM CPU to operate on.
2353 * @param pDis Disassembly state
2354 * @param pCtx CPU context
2355 * @param cbOp Opcode size
2356 */
2357static int svmR0EmulateTprMov(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTX pCtx, unsigned cbOp)
2358{
2359 int rc;
2360
2361 if (pDis->param1.flags == USE_DISPLACEMENT32)
2362 {
2363 /* write */
2364 uint8_t u8Tpr;
2365
2366 /* Fetch the new TPR value */
2367 if (pDis->param2.flags == USE_REG_GEN32)
2368 {
2369 uint32_t val;
2370
2371 rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pDis->param2.base.reg_gen, &val);
2372 AssertRC(rc);
2373 u8Tpr = val;
2374 }
2375 else
2376 if (pDis->param2.flags == USE_IMMEDIATE32)
2377 {
2378 u8Tpr = (uint8_t)pDis->param2.parval;
2379 }
2380 else
2381 return VERR_EM_INTERPRETER;
2382
2383 rc = PDMApicSetTPR(pVCpu, u8Tpr);
2384 AssertRC(rc);
2385
2386 Log(("Emulated write successfully\n"));
2387 pCtx->rip += cbOp;
2388 return VINF_SUCCESS;
2389 }
2390 else
2391 if (pDis->param2.flags == USE_DISPLACEMENT32)
2392 {
2393 /* read */
2394 bool fPending;
2395 uint8_t u8Tpr;
2396
2397 /* TPR caching in CR8 */
2398 rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending);
2399 AssertRC(rc);
2400
2401 rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pDis->param1.base.reg_gen, u8Tpr);
2402 AssertRC(rc);
2403
2404 Log(("Emulated read successfully\n"));
2405 pCtx->rip += cbOp;
2406 return VINF_SUCCESS;
2407 }
2408 return VERR_EM_INTERPRETER;
2409}
2410
2411/**
2412 * Attempt to patch TPR mmio instructions
2413 *
2414 * @returns VBox status code.
2415 * @param pVM The VM to operate on.
2416 * @param pVCpu The VM CPU to operate on.
2417 * @param pCtx CPU context
2418 */
2419static int svmR0ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2420{
2421 RTGCPTR oldrip = pCtx->rip;
2422 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2423 unsigned cbOp;
2424
2425 Log(("Replace TPR access at %RGv\n", pCtx->rip));
2426
2427 int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
2428 AssertRC(rc);
2429 if ( rc == VINF_SUCCESS
2430 && pDis->pCurInstr->opcode == OP_MOV)
2431 {
2432#if 0
2433 uint8_t szInstr[15];
2434 if ( cbOp == 10
2435 && pDis->param1.flags == USE_DISPLACEMENT32
2436 && pDis->param2.flags == USE_IMMEDIATE32)
2437 {
2438 /* Found:
2439 * mov [fffe0080], immediate_dword (10 bytes)
2440 *
2441 * Replace with:
2442 * mov free_register, immediate_dword >> 4 (5 bytes)
2443 * mov cr8, free_register (4 bytes)
2444 * nop (1 byte)
2445 *
2446 */
2447 uint32_t u32tpr = (uint32_t)pDis->param2.parval;
2448
2449 u32tpr = (u32tpr >> 4) & 0xf;
2450
2451 /* Check if the next instruction overwrites a general purpose register. If
2452 * it does, then we can safely use it ourselves.
2453 */
2454 pCtx->rip += cbOp;
2455 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
2456 pCtx->rip = oldrip;
2457 if ( rc == VINF_SUCCESS
2458 && pDis->pCurInstr->opcode == OP_MOV
2459 && pDis->param1.flags == USE_REG_GEN32)
2460 {
2461 /* 0xB8, dword immediate = mov eax, dword immediate */
2462 szInstr[0] = 0xB8 + pDis->param1.base.reg_gen;
2463 szInstr[1] = (uint8_t)u32tpr;
2464 szInstr[2] = 0;
2465 szInstr[3] = 0;
2466 szInstr[4] = 0;
2467
2468 /* 0xF0, 0x0F, 0x22, 0xC0 = mov cr8, eax */
2469 szInstr[5] = 0xF0;
2470 szInstr[6] = 0x0F;
2471 szInstr[7] = 0x22;
2472 szInstr[8] = 0xC0 | pDis->param1.base.reg_gen;
2473 szInstr[9] = 0x90; /* nop */
2474
2475 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, 10);
2476 AssertRC(rc);
2477
2478 Log(("Acceptable write candidate!\n"));
2479 return VINF_SUCCESS;
2480 }
2481 }
2482 else
2483 {
2484 if ( pDis->param2.flags == USE_REG_GEN32
2485 && cbOp == 6)
2486 {
2487 RTGCPTR GCPtrTpr = (uint32_t)pDis->param1.disp32;
2488 uint32_t uMmioReg = pDis->param2.base.reg_gen;
2489
2490 /* Found:
2491 * mov dword [fffe0080], eax (6 bytes)
2492 * Check if next instruction is a TPR read:
2493 * mov ecx, dword [fffe0080] (5 bytes)
2494 */
2495 pCtx->rip += cbOp;
2496 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
2497 pCtx->rip = oldrip;
2498 if ( rc == VINF_SUCCESS
2499 && pDis->pCurInstr->opcode == OP_MOV
2500 && pDis->param1.flags == USE_REG_GEN32
2501 && pDis->param2.flags == USE_DISPLACEMENT32
2502 && pDis->param2.disp32 == (uint32_t)GCPtrTpr
2503 && cbOp == 5)
2504 {
2505 /* mov new_reg, uMmioReg */
2506 szInstr[0] = 0x89;
2507 szInstr[1] = MAKE_MODRM(3, uMmioReg, pDis->param1.base.reg_gen);
2508
2509 /* Let's hope the guest won't mind us trashing the source register...
2510 * shr uMmioReg, 4
2511 */
2512 szInstr[2] = 0xC1;
2513 szInstr[3] = 0xE8 | uMmioReg;
2514 szInstr[4] = 4;
2515
2516 /* 0xF0, 0x0F, 0x22, 0xC0 = mov cr8, eax */
2517 szInstr[5] = 0xF0;
2518 szInstr[6] = 0x0F;
2519 szInstr[7] = 0x22;
2520 szInstr[8] = 0xC0 | uMmioReg;
2521
2522 /* Two nop instructions */
2523 szInstr[9] = 0x90;
2524 szInstr[10] = 0x90;
2525
2526 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, 6+cbOp);
2527 AssertRC(rc);
2528
2529 Log(("Acceptable read/write candidate!\n"));
2530 return VINF_SUCCESS;
2531 }
2532 }
2533 else
2534 if ( pDis->param1.flags == USE_REG_GEN32
2535 && cbOp == 5)
2536 {
2537 uint32_t uMmioReg = pDis->param1.base.reg_gen;
2538
2539 /* Found:
2540 * mov eax, dword [fffe0080] (5 bytes)
2541 * Check if next instruction is:
2542 * shr eax, 4
2543 */
2544 pCtx->rip += cbOp;
2545 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
2546 pCtx->rip = oldrip;
2547 if ( rc == VINF_SUCCESS
2548 && pDis->pCurInstr->opcode == OP_SHR
2549 && pDis->param1.flags == USE_REG_GEN32
2550 && pDis->param1.base.reg_gen == uMmioReg
2551 && pDis->param2.flags == USE_IMMEDIATE8
2552 && pDis->param2.parval == 4)
2553 {
2554 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
2555 szInstr[0] = 0xF0;
2556 szInstr[1] = 0x0F;
2557 szInstr[2] = 0x20;
2558 szInstr[3] = 0xC0 | pDis->param1.base.reg_gen;
2559 for (unsigned i = 4; i < 5+cbOp; i++)
2560 szInstr[i] = 0x90; /* nop */
2561
2562 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, 5+cbOp);
2563 AssertRC(rc);
2564
2565 Log(("Acceptable read candidate!\n"));
2566 return VINF_SUCCESS;
2567 }
2568 }
2569 }
2570#endif
2571 rc = svmR0EmulateTprMov(pVCpu, pDis, pCtx, cbOp);
2572 if (rc != VINF_SUCCESS)
2573 return rc;
2574
2575 /* Emulated successfully, so continue. */
2576 return VINF_SUCCESS;
2577 }
2578 return VERR_ACCESS_DENIED;
2579}
2580
2581/**
2582 * Enters the AMD-V session
2583 *
2584 * @returns VBox status code.
2585 * @param pVM The VM to operate on.
2586 * @param pVCpu The VM CPU to operate on.
2587 * @param pCpu CPU info struct
2588 */
2589VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
2590{
2591 Assert(pVM->hwaccm.s.svm.fSupported);
2592
2593 LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVCpu->hwaccm.s.idLastCpu, pVCpu->hwaccm.s.uCurrentASID));
2594 pVCpu->hwaccm.s.fResumeVM = false;
2595
2596 /* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
2597 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_LDTR;
2598
2599 return VINF_SUCCESS;
2600}
2601
2602
2603/**
2604 * Leaves the AMD-V session
2605 *
2606 * @returns VBox status code.
2607 * @param pVM The VM to operate on.
2608 * @param pVCpu The VM CPU to operate on.
2609 * @param pCtx CPU context
2610 */
2611VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2612{
2613 SVM_VMCB *pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
2614
2615 Assert(pVM->hwaccm.s.svm.fSupported);
2616
2617 /* Save the guest debug state if necessary. */
2618 if (CPUMIsGuestDebugStateActive(pVCpu))
2619 {
2620 CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, false /* skip DR6 */);
2621
2622 /* Intercept all DRx reads and writes again. Changed later on. */
2623 pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
2624 pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
2625
2626 /* Resync the debug registers the next time. */
2627 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2628 }
2629 else
2630 Assert(pVMCB->ctrl.u16InterceptRdDRx == 0xFFFF && pVMCB->ctrl.u16InterceptWrDRx == 0xFFFF);
2631
2632 return VINF_SUCCESS;
2633}
2634
2635
2636static int svmR0InterpretInvlPg(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2637{
2638 OP_PARAMVAL param1;
2639 RTGCPTR addr;
2640
2641 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2642 if(RT_FAILURE(rc))
2643 return VERR_EM_INTERPRETER;
2644
2645 switch(param1.type)
2646 {
2647 case PARMTYPE_IMMEDIATE:
2648 case PARMTYPE_ADDRESS:
2649 if(!(param1.flags & (PARAM_VAL32|PARAM_VAL64)))
2650 return VERR_EM_INTERPRETER;
2651 addr = param1.val.val64;
2652 break;
2653
2654 default:
2655 return VERR_EM_INTERPRETER;
2656 }
2657
2658 /** @todo is addr always a flat linear address or ds based
2659 * (in absence of segment override prefixes)????
2660 */
2661 rc = PGMInvalidatePage(pVCpu, addr);
2662 if (RT_SUCCESS(rc))
2663 {
2664 /* Manually invalidate the page for the VM's TLB. */
2665 Log(("SVMR0InvlpgA %RGv ASID=%d\n", addr, uASID));
2666 SVMR0InvlpgA(addr, uASID);
2667 return VINF_SUCCESS;
2668 }
2669 AssertRC(rc);
2670 return rc;
2671}
2672
2673/**
2674 * Interprets INVLPG
2675 *
2676 * @returns VBox status code.
2677 * @retval VINF_* Scheduling instructions.
2678 * @retval VERR_EM_INTERPRETER Something we can't cope with.
2679 * @retval VERR_* Fatal errors.
2680 *
2681 * @param pVM The VM handle.
2682 * @param pRegFrame The register frame.
2683 * @param ASID Tagged TLB id for the guest
2684 *
2685 * Updates the EIP if an instruction was executed successfully.
2686 */
2687static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2688{
2689 /*
2690 * Only allow 32 & 64 bits code.
2691 */
2692 DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
2693 if (enmMode != CPUMODE_16BIT)
2694 {
2695 RTGCPTR pbCode;
2696 int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
2697 if (RT_SUCCESS(rc))
2698 {
2699 uint32_t cbOp;
2700 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2701
2702 pDis->mode = enmMode;
2703 rc = EMInterpretDisasOneEx(pVM, pVCpu, pbCode, pRegFrame, pDis, &cbOp);
2704 Assert(RT_FAILURE(rc) || pDis->pCurInstr->opcode == OP_INVLPG);
2705 if (RT_SUCCESS(rc) && pDis->pCurInstr->opcode == OP_INVLPG)
2706 {
2707 Assert(cbOp == pDis->opsize);
2708 rc = svmR0InterpretInvlPg(pVCpu, pDis, pRegFrame, uASID);
2709 if (RT_SUCCESS(rc))
2710 {
2711 pRegFrame->rip += cbOp; /* Move on to the next instruction. */
2712 }
2713 return rc;
2714 }
2715 }
2716 }
2717 return VERR_EM_INTERPRETER;
2718}
2719
2720
2721/**
2722 * Invalidates a guest page
2723 *
2724 * @returns VBox status code.
2725 * @param pVM The VM to operate on.
2726 * @param pVCpu The VM CPU to operate on.
2727 * @param GCVirt Page to invalidate
2728 */
2729VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
2730{
2731 bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB | pVCpu->hwaccm.s.fForceTLBFlush;
2732
2733 /* Skip it if a TLB flush is already pending. */
2734 if (!fFlushPending)
2735 {
2736 SVM_VMCB *pVMCB;
2737
2738 Log2(("SVMR0InvalidatePage %RGv\n", GCVirt));
2739 AssertReturn(pVM, VERR_INVALID_PARAMETER);
2740 Assert(pVM->hwaccm.s.svm.fSupported);
2741
2742 /* @todo SMP */
2743 pVMCB = (SVM_VMCB *)pVM->aCpus[0].hwaccm.s.svm.pVMCB;
2744 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2745
2746#if HC_ARCH_BITS == 32
2747 /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invlpga takes only 32 bits addresses. */
2748 if (CPUMIsGuestInLongMode(pVCpu))
2749 pVCpu->hwaccm.s.fForceTLBFlush = true;
2750 else
2751#endif
2752 SVMR0InvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2753 }
2754 return VINF_SUCCESS;
2755}
2756
2757
2758#if 0 /* obsolete, but left here for clarification. */
2759/**
2760 * Invalidates a guest page by physical address
2761 *
2762 * @returns VBox status code.
2763 * @param pVM The VM to operate on.
2764 * @param pVCpu The VM CPU to operate on.
2765 * @param GCPhys Page to invalidate
2766 */
2767VMMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
2768{
2769 Assert(pVM->hwaccm.s.fNestedPaging);
2770 /* invlpga only invalidates TLB entries for guest virtual addresses; we have no choice but to force a TLB flush here. */
2771 pVCpu->hwaccm.s.fForceTLBFlush = true;
2772 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBInvlpga);
2773 return VINF_SUCCESS;
2774}
2775#endif
2776
2777#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2778/**
2779 * Prepares for and executes VMRUN (64 bits guests from a 32 bits hosts).
2780 *
2781 * @returns VBox status code.
2782 * @param pVMCBHostPhys Physical address of host VMCB.
2783 * @param pVMCBPhys Physical address of the VMCB.
2784 * @param pCtx Guest context.
2785 * @param pVM The VM to operate on.
2786 * @param pVCpu The VMCPU to operate on.
2787 */
2788DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
2789{
2790 uint32_t aParam[4];
2791
2792 aParam[0] = (uint32_t)(pVMCBHostPhys); /* Param 1: pVMCBHostPhys - Lo. */
2793 aParam[1] = (uint32_t)(pVMCBHostPhys >> 32); /* Param 1: pVMCBHostPhys - Hi. */
2794 aParam[2] = (uint32_t)(pVMCBPhys); /* Param 2: pVMCBPhys - Lo. */
2795 aParam[3] = (uint32_t)(pVMCBPhys >> 32); /* Param 2: pVMCBPhys - Hi. */
2796
2797 return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSVMGCVMRun64, 4, &aParam[0]);
2798}
2799
2800/**
2801 * Executes the specified handler in 64 mode
2802 *
2803 * @returns VBox status code.
2804 * @param pVM The VM to operate on.
2805 * @param pVCpu The VMCPU to operate on.
2806 * @param pCtx Guest context
2807 * @param pfnHandler RC handler
2808 * @param cbParam Number of parameters
2809 * @param paParam Array of 32 bits parameters
2810 */
2811VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
2812{
2813 int rc;
2814 RTHCUINTREG uOldEFlags;
2815
2816 /* @todo This code is not guest SMP safe (hyper stack and switchers) */
2817 AssertReturn(pVM->cCPUs == 1, VERR_TOO_MANY_CPUS);
2818 Assert(pfnHandler);
2819
2820 uOldEFlags = ASMIntDisableFlags();
2821
2822 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVM));
2823 CPUMSetHyperEIP(pVCpu, pfnHandler);
2824 for (int i=(int)cbParam-1;i>=0;i--)
2825 CPUMPushHyper(pVCpu, paParam[i]);
2826
2827 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2828 /* Call switcher. */
2829 rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM);
2830 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2831
2832 ASMSetFlags(uOldEFlags);
2833 return rc;
2834}
2835
2836#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
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