HWSVMR0.cpp@ 2133

Last change on this file since 2133 was 2133, checked in by vboxsync, 18 years ago
Removed obsolete comment.
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1	/* $Id: HWSVMR0.cpp 2133 2007-04-17 13:29:50Z vboxsync $ */
2	/** @file
3	* HWACCM SVM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_svm.h>
32	#include <VBox/pgm.h>
33	#include <VBox/pdm.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <VBox/selm.h>
37	#include <VBox/iom.h>
38	#include <VBox/dis.h>
39	#include <VBox/disopcode.h>
40	#include <iprt/param.h>
41	#include <iprt/assert.h>
42	#include <iprt/asm.h>
43	#include "HWSVMR0.h"
44
45	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
46
47	/**
48	* Sets up and activates SVM
49	*
50	* @returns VBox status code.
51	* @param pVM The VM to operate on.
52	*/
53	HWACCMR0DECL(int) SVMR0Setup(PVM pVM)
54	{
55	int rc = VINF_SUCCESS;
56	SVM_VMCB *pVMCB;
57
58	if (pVM == NULL)
59	return VERR_INVALID_PARAMETER;
60
61	/* Setup AMD SVM. */
62	Assert(pVM->hwaccm.s.svm.fSupported);
63
64	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
65	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
66
67	/* Program the control fields. Most of them never have to be changed again. */
68	/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
69	/** @note CR0 & CR4 can be safely read when guest and shadow copies are identical. */
70	pVMCB->ctrl.u16InterceptRdCRx = BIT(0) \| BIT(3) \| BIT(4) \| BIT(8);
71
72	/*
73	* CR0/3/4 writes must be intercepted for obvious reasons.
74	*/
75	pVMCB->ctrl.u16InterceptWrCRx = BIT(0) \| BIT(3) \| BIT(4) \| BIT(8);
76
77	/* Intercept all DRx reads and writes. */
78	pVMCB->ctrl.u16InterceptRdDRx = BIT(0) \| BIT(1) \| BIT(2) \| BIT(3) \| BIT(4) \| BIT(5) \| BIT(6) \| BIT(7);
79	pVMCB->ctrl.u16InterceptWrDRx = BIT(0) \| BIT(1) \| BIT(2) \| BIT(3) \| BIT(4) \| BIT(5) \| BIT(6) \| BIT(7);
80
81	/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
82	* All breakpoints are automatically cleared when the VM exits.
83	*/
84
85	/** @todo nested paging */
86	/* Intercept #NM only; #PF is not relevant due to nested paging (we get a seperate exit code (SVM_EXIT_NPF) for
87	* pagefaults that need our attention).
88	*/
89	pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
90
91	pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
92	\| SVM_CTRL1_INTERCEPT_VINTR
93	\| SVM_CTRL1_INTERCEPT_NMI
94	\| SVM_CTRL1_INTERCEPT_SMI
95	\| SVM_CTRL1_INTERCEPT_INIT
96	\| SVM_CTRL1_INTERCEPT_CR0 /** @todo redundant? */
97	\| SVM_CTRL1_INTERCEPT_RDPMC
98	\| SVM_CTRL1_INTERCEPT_CPUID
99	\| SVM_CTRL1_INTERCEPT_RSM
100	\| SVM_CTRL1_INTERCEPT_HLT
101	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
102	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
103	\| SVM_CTRL1_INTERCEPT_INVLPG
104	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
105	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
106	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
107	;
108	pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
109	\| SVM_CTRL2_INTERCEPT_VMMCALL
110	\| SVM_CTRL2_INTERCEPT_VMLOAD
111	\| SVM_CTRL2_INTERCEPT_VMSAVE
112	\| SVM_CTRL2_INTERCEPT_STGI
113	\| SVM_CTRL2_INTERCEPT_CLGI
114	\| SVM_CTRL2_INTERCEPT_SKINIT
115	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
116	;
117	Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
118	Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
119	Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
120
121	/* Virtualize masking of INTR interrupts. */
122	pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
123
124	/* Set IO and MSR bitmap addresses. */
125	pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
126	pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
127
128	/* Enable nested paging. */
129	/** @todo how to detect support for this?? */
130	pVMCB->ctrl.u64NestedPaging = 0; /** @todo SVM_NESTED_PAGING_ENABLE; */
131
132	/* No LBR virtualization. */
133	pVMCB->ctrl.u64LBRVirt = 0;
134
135	return rc;
136	}
137
138
139	/**
140	* Injects an event (trap or external interrupt)
141	*
142	* @param pVM The VM to operate on.
143	* @param pVMCB SVM control block
144	* @param pCtx CPU Context
145	* @param pIntInfo SVM interrupt info
146	*/
147	inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx, SVM_EVENT* pEvent)
148	{
149	#ifdef VBOX_STRICT
150	if (pEvent->n.u8Vector == 0xE)
151	Log(("SVMR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
152	else
153	if (pEvent->n.u8Vector < 0x20)
154	Log(("SVMR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode));
155	else
156	{
157	Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->eip));
158	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
159	Assert(pCtx->eflags.u32 & X86_EFL_IF);
160	}
161	#endif
162
163	/* Set event injection state. */
164	pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
165	}
166
167
168	/**
169	* Checks for pending guest interrupts and injects them
170	*
171	* @returns VBox status code.
172	* @param pVM The VM to operate on.
173	* @param pVMCB SVM control block
174	* @param pCtx CPU Context
175	*/
176	static int SVMR0CheckPendingInterrupt(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx)
177	{
178	int rc;
179
180	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
181	if (pVM->hwaccm.s.Event.fPending)
182	{
183	SVM_EVENT Event;
184
185	Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
186	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
187	Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
188	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
189
190	pVM->hwaccm.s.Event.fPending = false;
191	return VINF_SUCCESS;
192	}
193
194	/* When external interrupts are pending, we should exit the VM when IF is set. */
195	if ( !TRPMHasTrap(pVM)
196	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
197	{
198	if (!(pCtx->eflags.u32 & X86_EFL_IF))
199	{
200	Log2(("Enable irq window exit!\n"));
201	/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
202	//// pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
203	//// AssertRC(rc);
204	}
205	else
206	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
207	{
208	uint8_t u8Interrupt;
209
210	rc = PDMGetInterrupt(pVM, &u8Interrupt);
211	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
212	if (VBOX_SUCCESS(rc))
213	{
214	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
215	AssertRC(rc);
216	}
217	else
218	{
219	/* can't happen... */
220	AssertFailed();
221	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
222	return VINF_EM_RAW_INTERRUPT_PENDING;
223	}
224	}
225	else
226	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
227	}
228
229	#ifdef VBOX_STRICT
230	if (TRPMHasTrap(pVM))
231	{
232	uint8_t u8Vector;
233	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
234	AssertRC(rc);
235	}
236	#endif
237
238	if ( pCtx->eflags.u32 & X86_EFL_IF
239	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
240	&& TRPMHasTrap(pVM)
241	)
242	{
243	uint8_t u8Vector;
244	int rc;
245	TRPMEVENT enmType;
246	SVM_EVENT Event;
247	uint32_t u32ErrorCode;
248
249	Event.au64[0] = 0;
250
251	/* If a new event is pending, then dispatch it now. */
252	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &u32ErrorCode, 0);
253	AssertRC(rc);
254	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
255	Assert(enmType != TRPM_SOFTWARE_INT);
256
257	/* Clear the pending trap. */
258	rc = TRPMResetTrap(pVM);
259	AssertRC(rc);
260
261	Event.n.u8Vector = u8Vector;
262	Event.n.u1Valid = 1;
263	Event.n.u32ErrorCode = u32ErrorCode;
264
265	if (enmType == TRPM_TRAP)
266	{
267	switch (u8Vector) {
268	case 8:
269	case 10:
270	case 11:
271	case 12:
272	case 13:
273	case 14:
274	case 17:
275	/* Valid error codes. */
276	Event.n.u1ErrorCodeValid = 1;
277	break;
278	default:
279	break;
280	}
281	if (u8Vector == X86_XCPT_NMI)
282	Event.n.u3Type = SVM_EVENT_NMI;
283	else
284	Event.n.u3Type = SVM_EVENT_EXCEPTION;
285	}
286	else
287	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
288
289	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
290	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
291	} /* if (interrupts can be dispatched) */
292
293	return VINF_SUCCESS;
294	}
295
296
297	/**
298	* Loads the guest state
299	*
300	* @returns VBox status code.
301	* @param pVM The VM to operate on.
302	* @param pCtx Guest context
303	*/
304	HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
305	{
306	int rc = VINF_SUCCESS;
307	RTGCUINTPTR val;
308	SVM_VMCB *pVMCB;
309
310	if (pVM == NULL)
311	return VERR_INVALID_PARAMETER;
312
313	/* Setup AMD SVM. */
314	Assert(pVM->hwaccm.s.svm.fSupported);
315
316	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
317	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
318
319	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
320	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
321	{
322	SVM_WRITE_SELREG(CS, cs);
323	SVM_WRITE_SELREG(SS, ss);
324	SVM_WRITE_SELREG(DS, ds);
325	SVM_WRITE_SELREG(ES, es);
326	SVM_WRITE_SELREG(FS, fs);
327	SVM_WRITE_SELREG(GS, gs);
328	}
329
330	/* Guest CPU context: LDTR. */
331	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
332	{
333	SVM_WRITE_SELREG(LDTR, ldtr);
334	}
335
336	/* Guest CPU context: TR. */
337	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
338	{
339	SVM_WRITE_SELREG(TR, tr);
340	}
341
342	/* Guest CPU context: GDTR. */
343	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
344	{
345	pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
346	pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
347	}
348
349	/* Guest CPU context: IDTR. */
350	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
351	{
352	pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
353	pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
354	}
355
356	/*
357	* Sysenter MSRs
358	*/
359	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
360	{
361	pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
362	pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
363	pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
364	}
365
366	/* Control registers */
367	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
368	{
369	val = pCtx->cr0;
370	if (CPUMIsGuestFPUStateActive(pVM) == false)
371	{
372	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
373	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
374	}
375	else
376	{
377	Assert(pVM->hwaccm.s.svm.fResumeVM == true);
378	/** @todo check if we support the old style mess correctly. */
379	if (!(val & X86_CR0_NE))
380	{
381	Log(("Forcing X86_CR0_NE!!!\n"));
382
383	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
384	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
385	{
386	pVMCB->ctrl.u32InterceptException \|= BIT(16);
387	pVM->hwaccm.s.fFPUOldStyleOverride = true;
388	}
389	}
390	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
391	}
392	if (!(val & X86_CR0_CD))
393	val &= ~X86_CR0_NW; /* Illegal when cache is turned on. */
394
395	val \|= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
396	pVMCB->guest.u64CR0 = val;
397	}
398	/* CR2 as well */
399	pVMCB->guest.u64CR2 = pCtx->cr2;
400
401	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
402	{
403	/* Save our shadow CR3 register. */
404	pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
405	}
406
407	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
408	{
409	val = pCtx->cr4;
410	switch(pVM->hwaccm.s.enmShadowMode)
411	{
412	case PGMMODE_REAL:
413	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
414	AssertFailed();
415	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
416
417	case PGMMODE_32_BIT: /* 32-bit paging. */
418	break;
419
420	case PGMMODE_PAE: /* PAE paging. */
421	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
422	/** @todo use normal 32 bits paging */
423	val \|= X86_CR4_PAE;
424	break;
425
426	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
427	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
428	AssertFailed();
429	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
430
431	default: /* shut up gcc */
432	AssertFailed();
433	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
434	}
435	pVMCB->guest.u64CR4 = val;
436	}
437
438	/* Debug registers. */
439	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
440	{
441	/** @todo DR0-6 */
442	val = pCtx->dr7;
443	val &= ~(BIT(11) \| BIT(12) \| BIT(14) \| BIT(15)); /* must be zero */
444	val \|= 0x400; /* must be one */
445	#ifdef VBOX_STRICT
446	val = 0x400;
447	#endif
448	pVMCB->guest.u64DR7 = val;
449
450	pVMCB->guest.u64DR6 = pCtx->dr6;
451	}
452
453	/* EIP, ESP and EFLAGS */
454	pVMCB->guest.u64RIP = pCtx->eip;
455	pVMCB->guest.u64RSP = pCtx->esp;
456	pVMCB->guest.u64RFlags = pCtx->eflags.u32;
457
458	/* Set CPL */
459	if (!(pCtx->cr0 & X86_CR0_PE))
460	pVMCB->guest.u8CPL = 0;
461	else
462	if (pCtx->eflags.Bits.u1VM)
463	pVMCB->guest.u8CPL = 3;
464	else
465	pVMCB->guest.u8CPL = (pCtx->ss & X86_SEL_RPL);
466
467	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
468	pVMCB->guest.u64RAX = pCtx->eax;
469
470	/* vmrun will fail otherwise. */
471	pVMCB->guest.u64EFER = MSR_K6_EFER_SVME;
472
473	/** @note We can do more complex things with tagged TLBs. */
474	pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
475
476	/** TSC offset. */
477	pVMCB->ctrl.u64TSCOffset = TMCpuTickGetOffset(pVM);
478
479	/** @todo 64 bits stuff (?):
480	* - STAR
481	* - LSTAR
482	* - CSTAR
483	* - SFMASK
484	* - KernelGSBase
485	*/
486
487	/* Done. */
488	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
489
490	return rc;
491	}
492
493
494	/**
495	* Runs guest code in an SVM VM.
496	*
497	* @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
498	*
499	* @returns VBox status code.
500	* @param pVM The VM to operate on.
501	* @param pCtx Guest context
502	*/
503	HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
504	{
505	int rc = VINF_SUCCESS;
506	uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
507	SVM_VMCB *pVMCB;
508	bool fForceTLBFlush = false;
509
510	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
511
512	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
513	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
514
515	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
516	*/
517	ResumeExecution:
518
519	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
520	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
521	{
522	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
523	if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
524	{
525	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
526	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
527	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
528	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
529	*/
530	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
531	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
532	pVMCB->ctrl.u64IntShadow = 0;
533	}
534	}
535	else
536	{
537	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
538	pVMCB->ctrl.u64IntShadow = 0;
539	}
540
541	/* Check for pending actions that force us to go back to ring 3. */
542	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
543	{
544	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
545	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
546	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
547	rc = VINF_EM_RAW_TO_R3;
548	goto end;
549	}
550	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
551	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
552	{
553	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
554	rc = VINF_EM_PENDING_REQUEST;
555	goto end;
556	}
557
558	/* When external interrupts are pending, we should exit the VM when IF is set. */
559	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
560	rc = SVMR0CheckPendingInterrupt(pVM, pVMCB, pCtx);
561	if (VBOX_FAILURE(rc))
562	{
563	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
564	goto end;
565	}
566
567	/* Load the guest state */
568	rc = SVMR0LoadGuestState(pVM, pCtx);
569	if (rc != VINF_SUCCESS)
570	{
571	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
572	goto end;
573	}
574
575	/* All done! Let's start VM execution. */
576	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
577
578	/** Erratum #170 -> must force a TLB flush */
579	/** @todo supposed to be fixed in future by AMD */
580	fForceTLBFlush = true;
581
582	if ( pVM->hwaccm.s.svm.fResumeVM == false
583	\|\| fForceTLBFlush)
584	{
585	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1;
586	}
587	else
588	{
589	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 0;
590	}
591	/* In case we execute a goto ResumeExecution later on. */
592	pVM->hwaccm.s.svm.fResumeVM = true;
593	fForceTLBFlush = false;
594
595	Assert(sizeof(pVM->hwaccm.s.svm.pVMCBPhys) == 8);
596	Assert(pVMCB->ctrl.u32InterceptCtrl1 == ( SVM_CTRL1_INTERCEPT_INTR
597	\| SVM_CTRL1_INTERCEPT_VINTR
598	\| SVM_CTRL1_INTERCEPT_NMI
599	\| SVM_CTRL1_INTERCEPT_SMI
600	\| SVM_CTRL1_INTERCEPT_INIT
601	\| SVM_CTRL1_INTERCEPT_CR0 /** @todo redundant? */
602	\| SVM_CTRL1_INTERCEPT_RDPMC
603	\| SVM_CTRL1_INTERCEPT_CPUID
604	\| SVM_CTRL1_INTERCEPT_RSM
605	\| SVM_CTRL1_INTERCEPT_HLT
606	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
607	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
608	\| SVM_CTRL1_INTERCEPT_INVLPG
609	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
610	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
611	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE /* Legacy FPU FERR handling. */
612	));
613	Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
614	\| SVM_CTRL2_INTERCEPT_VMMCALL
615	\| SVM_CTRL2_INTERCEPT_VMLOAD
616	\| SVM_CTRL2_INTERCEPT_VMSAVE
617	\| SVM_CTRL2_INTERCEPT_STGI
618	\| SVM_CTRL2_INTERCEPT_CLGI
619	\| SVM_CTRL2_INTERCEPT_SKINIT
620	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
621	));
622	Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
623	Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
624	Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
625	Assert(pVMCB->ctrl.u64NestedPaging == 0);
626	Assert(pVMCB->ctrl.u64LBRVirt == 0);
627
628	SVMVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);
629	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
630
631	/**
632	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
633	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
634	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
635	*/
636
637	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
638
639	/* Reason for the VM exit */
640	exitCode = pVMCB->ctrl.u64ExitCode;
641
642	if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
643	{
644	HWACCMDumpRegs(pCtx);
645	#ifdef DEBUG
646	Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
647	Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
648	Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
649	Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
650	Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
651	Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
652	Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
653	Log(("ctrl.u64IOPMPhysAddr %VX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
654	Log(("ctrl.u64MSRPMPhysAddr %VX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
655	Log(("ctrl.u64TSCOffset %VX64\n", pVMCB->ctrl.u64TSCOffset));
656
657	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
658	Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
659	Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
660	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
661
662	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
663	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
664	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
665	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
666	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
667	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
668	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
669	Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
670	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
671	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
672
673	Log(("ctrl.u64IntShadow %VX64\n", pVMCB->ctrl.u64IntShadow));
674	Log(("ctrl.u64ExitCode %VX64\n", pVMCB->ctrl.u64ExitCode));
675	Log(("ctrl.u64ExitInfo1 %VX64\n", pVMCB->ctrl.u64ExitInfo1));
676	Log(("ctrl.u64ExitInfo2 %VX64\n", pVMCB->ctrl.u64ExitInfo2));
677	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
678	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
679	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
680	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
681	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
682	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
683	Log(("ctrl.u64NestedPaging %VX64\n", pVMCB->ctrl.u64NestedPaging));
684	Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
685	Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
686	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
687	Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
688	Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
689	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
690
691	Log(("ctrl.u64HostCR3 %VX64\n", pVMCB->ctrl.u64HostCR3));
692	Log(("ctrl.u64LBRVirt %VX64\n", pVMCB->ctrl.u64LBRVirt));
693
694	Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
695	Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
696	Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
697	Log(("guest.CS.u64Base %VX64\n", pVMCB->guest.CS.u64Base));
698	Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
699	Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
700	Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
701	Log(("guest.DS.u64Base %VX64\n", pVMCB->guest.DS.u64Base));
702	Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
703	Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
704	Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
705	Log(("guest.ES.u64Base %VX64\n", pVMCB->guest.ES.u64Base));
706	Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
707	Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
708	Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
709	Log(("guest.FS.u64Base %VX64\n", pVMCB->guest.FS.u64Base));
710	Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
711	Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
712	Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
713	Log(("guest.GS.u64Base %VX64\n", pVMCB->guest.GS.u64Base));
714
715	Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
716	Log(("guest.GDTR.u64Base %VX64\n", pVMCB->guest.GDTR.u64Base));
717
718	Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
719	Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
720	Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
721	Log(("guest.LDTR.u64Base %VX64\n", pVMCB->guest.LDTR.u64Base));
722
723	Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
724	Log(("guest.IDTR.u64Base %VX64\n", pVMCB->guest.IDTR.u64Base));
725
726	Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
727	Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
728	Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
729	Log(("guest.TR.u64Base %VX64\n", pVMCB->guest.TR.u64Base));
730
731	Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
732	Log(("guest.u64CR0 %VX64\n", pVMCB->guest.u64CR0));
733	Log(("guest.u64CR2 %VX64\n", pVMCB->guest.u64CR2));
734	Log(("guest.u64CR3 %VX64\n", pVMCB->guest.u64CR3));
735	Log(("guest.u64CR4 %VX64\n", pVMCB->guest.u64CR4));
736	Log(("guest.u64DR6 %VX64\n", pVMCB->guest.u64DR6));
737	Log(("guest.u64DR7 %VX64\n", pVMCB->guest.u64DR7));
738
739	Log(("guest.u64RIP %VX64\n", pVMCB->guest.u64RIP));
740	Log(("guest.u64RSP %VX64\n", pVMCB->guest.u64RSP));
741	Log(("guest.u64RAX %VX64\n", pVMCB->guest.u64RAX));
742	Log(("guest.u64RFlags %VX64\n", pVMCB->guest.u64RFlags));
743
744	Log(("guest.u64SysEnterCS %VX64\n", pVMCB->guest.u64SysEnterCS));
745	Log(("guest.u64SysEnterEIP %VX64\n", pVMCB->guest.u64SysEnterEIP));
746	Log(("guest.u64SysEnterESP %VX64\n", pVMCB->guest.u64SysEnterESP));
747
748	Log(("guest.u64EFER %VX64\n", pVMCB->guest.u64EFER));
749	Log(("guest.u64STAR %VX64\n", pVMCB->guest.u64STAR));
750	Log(("guest.u64LSTAR %VX64\n", pVMCB->guest.u64LSTAR));
751	Log(("guest.u64CSTAR %VX64\n", pVMCB->guest.u64CSTAR));
752	Log(("guest.u64SFMASK %VX64\n", pVMCB->guest.u64SFMASK));
753	Log(("guest.u64KernelGSBase %VX64\n", pVMCB->guest.u64KernelGSBase));
754	Log(("guest.u64GPAT %VX64\n", pVMCB->guest.u64GPAT));
755	Log(("guest.u64DBGCTL %VX64\n", pVMCB->guest.u64DBGCTL));
756	Log(("guest.u64BR_FROM %VX64\n", pVMCB->guest.u64BR_FROM));
757	Log(("guest.u64BR_TO %VX64\n", pVMCB->guest.u64BR_TO));
758	Log(("guest.u64LASTEXCPFROM %VX64\n", pVMCB->guest.u64LASTEXCPFROM));
759	Log(("guest.u64LASTEXCPTO %VX64\n", pVMCB->guest.u64LASTEXCPTO));
760
761	#endif
762	rc = VERR_SVM_UNABLE_TO_START_VM;
763	goto end;
764	}
765
766	/* Let's first sync back eip, esp, and eflags. */
767	pCtx->eip = pVMCB->guest.u64RIP;
768	pCtx->esp = pVMCB->guest.u64RSP;
769	pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
770	/* eax is saved/restore across the vmrun instruction */
771	pCtx->eax = pVMCB->guest.u64RAX;
772
773	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
774	SVM_READ_SELREG(SS, ss);
775	SVM_READ_SELREG(CS, cs);
776	SVM_READ_SELREG(DS, ds);
777	SVM_READ_SELREG(ES, es);
778	SVM_READ_SELREG(FS, fs);
779	SVM_READ_SELREG(GS, gs);
780
781	/** @note no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
782
783	/** @note NOW IT'S SAFE FOR LOGGING! */
784
785	/* Take care of instruction fusing (sti, mov ss) */
786	if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
787	{
788	Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->eip));
789	EMSetInhibitInterruptsPC(pVM, pCtx->eip);
790	}
791	else
792	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
793
794	Log2(("exitCode = %x\n", exitCode));
795
796	/* Check if an injected event was interrupted prematurely. */
797	pVM->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
798	if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
799	&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
800	{
801	Log(("Pending inject %VX64 at %08x exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitCode));
802	pVM->hwaccm.s.Event.fPending = true;
803	/* Error code present? (redundant) */
804	if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
805	{
806	pVM->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
807	}
808	else
809	pVM->hwaccm.s.Event.errCode = 0;
810	}
811	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReason[exitCode & MASK_EXITREASON_STAT]);
812
813	/* Deal with the reason of the VM-exit. */
814	switch (exitCode)
815	{
816	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
817	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
818	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
819	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
820	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
821	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
822	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
823	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
824	{
825	/* Pending trap. */
826	SVM_EVENT Event;
827	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
828
829	Log2(("Hardware/software interrupt %d\n", vector));
830	switch (vector)
831	{
832	case X86_XCPT_NM:
833	{
834	uint32_t oldCR0;
835
836	Log(("#NM fault at %VGv\n", pCtx->eip));
837
838	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
839	oldCR0 = ASMGetCR0();
840	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
841	rc = CPUMHandleLazyFPU(pVM);
842	if (rc == VINF_SUCCESS)
843	{
844	Assert(CPUMIsGuestFPUStateActive(pVM));
845
846	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
847	ASMSetCR0(oldCR0);
848
849	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
850
851	/* Continue execution. */
852	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
853	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
854
855	goto ResumeExecution;
856	}
857
858	Log(("Forward #NM fault to the guest\n"));
859	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
860
861	Event.au64[0] = 0;
862	Event.n.u3Type = SVM_EVENT_EXCEPTION;
863	Event.n.u1Valid = 1;
864	Event.n.u8Vector = X86_XCPT_NM;
865
866	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
867	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
868	goto ResumeExecution;
869	}
870
871	case X86_XCPT_PF: /* Page fault */
872	{
873	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
874	RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
875
876	Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
877	/* Exit qualification contains the linear address of the page fault. */
878	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
879	TRPMSetErrorCode(pVM, errCode);
880	TRPMSetFaultAddress(pVM, uFaultAddress);
881
882	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
883	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
884	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
885	if (rc == VINF_SUCCESS)
886	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
887	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
888	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
889
890	TRPMResetTrap(pVM);
891
892	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
893	goto ResumeExecution;
894	}
895	else
896	if (rc == VINF_EM_RAW_GUEST_TRAP)
897	{ /* A genuine pagefault.
898	* Forward the trap to the guest by injecting the exception and resuming execution.
899	*/
900	Log2(("Forward page fault to the guest\n"));
901	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
902	/* The error code might have been changed. */
903	errCode = TRPMGetErrorCode(pVM);
904
905	TRPMResetTrap(pVM);
906
907	/* Now we must update CR2. */
908	pCtx->cr2 = uFaultAddress;
909
910	Event.au64[0] = 0;
911	Event.n.u3Type = SVM_EVENT_EXCEPTION;
912	Event.n.u1Valid = 1;
913	Event.n.u8Vector = X86_XCPT_PF;
914	Event.n.u1ErrorCodeValid = 1;
915	Event.n.u32ErrorCode = errCode;
916
917	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
918
919	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
920	goto ResumeExecution;
921	}
922	#ifdef VBOX_STRICT
923	if (rc != VINF_EM_RAW_EMULATE_INSTR)
924	Log(("PGMTrap0eHandler failed with %d\n", rc));
925	#endif
926	/* Need to go back to the recompiler to emulate the instruction. */
927	TRPMResetTrap(pVM);
928	break;
929	}
930
931	case X86_XCPT_MF: /* Floating point exception. */
932	{
933	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
934	if (!(pCtx->cr0 & X86_CR0_NE))
935	{
936	/* old style FPU error reporting needs some extra work. */
937	/** @todo don't fall back to the recompiler, but do it manually. */
938	rc = VINF_EM_RAW_EMULATE_INSTR;
939	break;
940	}
941	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
942
943	Event.au64[0] = 0;
944	Event.n.u3Type = SVM_EVENT_EXCEPTION;
945	Event.n.u1Valid = 1;
946	Event.n.u8Vector = X86_XCPT_MF;
947
948	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
949
950	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
951	goto ResumeExecution;
952	}
953
954	#ifdef VBOX_STRICT
955	case X86_XCPT_GP: /* General protection failure exception.*/
956	case X86_XCPT_UD: /* Unknown opcode exception. */
957	case X86_XCPT_DE: /* Debug exception. */
958	case X86_XCPT_SS: /* Stack segment exception. */
959	case X86_XCPT_NP: /* Segment not present exception. */
960	{
961	Event.au64[0] = 0;
962	Event.n.u3Type = SVM_EVENT_EXCEPTION;
963	Event.n.u1Valid = 1;
964	Event.n.u8Vector = vector;
965
966	switch(vector)
967	{
968	case X86_XCPT_GP:
969	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
970	Event.n.u1ErrorCodeValid = 1;
971	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
972	break;
973	case X86_XCPT_DE:
974	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
975	break;
976	case X86_XCPT_UD:
977	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
978	break;
979	case X86_XCPT_SS:
980	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
981	Event.n.u1ErrorCodeValid = 1;
982	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
983	break;
984	case X86_XCPT_NP:
985	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
986	Event.n.u1ErrorCodeValid = 1;
987	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
988	break;
989	}
990	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
991	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
992
993	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
994	goto ResumeExecution;
995	}
996	#endif
997	default:
998	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
999	rc = VERR_EM_INTERNAL_ERROR;
1000	break;
1001
1002	} /* switch (vector) */
1003	break;
1004	}
1005
1006	case SVM_EXIT_FERR_FREEZE:
1007	case SVM_EXIT_INTR:
1008	case SVM_EXIT_NMI:
1009	case SVM_EXIT_SMI:
1010	case SVM_EXIT_INIT:
1011	case SVM_EXIT_VINTR:
1012	/* External interrupt; leave to allow it to be dispatched again. */
1013	rc = VINF_EM_RAW_INTERRUPT;
1014	break;
1015
1016	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1017	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1018	/* Skip instruction and continue directly. */
1019	pCtx->eip += 2; /** @note hardcoded opcode size! */
1020	/* Continue execution.*/
1021	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1022	goto ResumeExecution;
1023
1024	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1025	{
1026	Log2(("SVM: Cpuid %x\n", pCtx->eax));
1027	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1028	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1029	if (rc == VINF_SUCCESS)
1030	{
1031	/* Update EIP and continue execution. */
1032	pCtx->eip += 2; /** @note hardcoded opcode size! */
1033	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1034	goto ResumeExecution;
1035	}
1036	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1037	rc = VINF_EM_RAW_EMULATE_INSTR;
1038	break;
1039	}
1040
1041	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1042	{
1043	Log2(("SVM: invlpg\n"));
1044	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1045
1046	/* Truly a pita. Why can't SVM give the same information as VMX? */
1047	rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1048	break;
1049	}
1050
1051	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1052	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1053	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1054	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1055	{
1056	uint32_t cbSize;
1057
1058	Log2(("SVM: %VGv mov cr%d, \n", pCtx->eip, exitCode - SVM_EXIT_WRITE_CR0));
1059	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1060	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1061
1062	switch (exitCode - SVM_EXIT_WRITE_CR0)
1063	{
1064	case 0:
1065	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1066	break;
1067	case 2:
1068	break;
1069	case 3:
1070	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1071	break;
1072	case 4:
1073	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1074	break;
1075	default:
1076	AssertFailed();
1077	}
1078	/* Check if a sync operation is pending. */
1079	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1080	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1081	{
1082	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1083	AssertRC(rc);
1084
1085	/** @note Force a TLB flush. SVM requires us to do it manually. */
1086	fForceTLBFlush = true;
1087	}
1088	if (rc == VINF_SUCCESS)
1089	{
1090	/* EIP has been updated already. */
1091
1092	/* Only resume if successful. */
1093	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1094	goto ResumeExecution;
1095	}
1096	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1097	if (rc == VERR_EM_INTERPRETER)
1098	rc = VINF_EM_RAW_EMULATE_INSTR;
1099	break;
1100	}
1101
1102	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1103	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1104	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1105	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1106	{
1107	uint32_t cbSize;
1108
1109	Log2(("SVM: %VGv mov x, cr%d\n", pCtx->eip, exitCode - SVM_EXIT_READ_CR0));
1110	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1111	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1112	if (rc == VINF_SUCCESS)
1113	{
1114	/* EIP has been updated already. */
1115
1116	/* Only resume if successful. */
1117	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1118	goto ResumeExecution;
1119	}
1120	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1121	if (rc == VERR_EM_INTERPRETER)
1122	rc = VINF_EM_RAW_EMULATE_INSTR;
1123	break;
1124	}
1125
1126	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1127	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1128	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1129	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1130	{
1131	uint32_t cbSize;
1132
1133	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_WRITE_DR0));
1134	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1135	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1136	if (rc == VINF_SUCCESS)
1137	{
1138	/* EIP has been updated already. */
1139
1140	/* Only resume if successful. */
1141	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1142	goto ResumeExecution;
1143	}
1144	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1145	if (rc == VERR_EM_INTERPRETER)
1146	rc = VINF_EM_RAW_EMULATE_INSTR;
1147	break;
1148	}
1149
1150	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1151	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1152	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1153	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1154	{
1155	uint32_t cbSize;
1156
1157	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_READ_DR0));
1158	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1159	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1160	if (rc == VINF_SUCCESS)
1161	{
1162	/* EIP has been updated already. */
1163
1164	/* Only resume if successful. */
1165	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1166	goto ResumeExecution;
1167	}
1168	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1169	if (rc == VERR_EM_INTERPRETER)
1170	rc = VINF_EM_RAW_EMULATE_INSTR;
1171	break;
1172	}
1173
1174	/** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1175	case SVM_EXIT_IOIO: /* I/O instruction. */
1176	{
1177	SVM_IOIO_EXIT IoExitInfo;
1178	uint32_t uIOSize, uAndVal;
1179
1180	IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1181
1182	/** @todo could use a lookup table here */
1183	if (IoExitInfo.n.u1OP8)
1184	{
1185	uIOSize = 1;
1186	uAndVal = 0xff;
1187	}
1188	else
1189	if (IoExitInfo.n.u1OP16)
1190	{
1191	uIOSize = 2;
1192	uAndVal = 0xffff;
1193	}
1194	else
1195	if (IoExitInfo.n.u1OP32)
1196	{
1197	uIOSize = 4;
1198	uAndVal = 0xffffffff;
1199	}
1200	else
1201	{
1202	AssertFailed(); /* should be fatal. */
1203	rc = VINF_EM_RAW_EMULATE_INSTR;
1204	break;
1205	}
1206
1207	/* First simple in and out instructions. */
1208	/** @todo str & rep */
1209	if ( !IoExitInfo.n.u1REP
1210	&& !IoExitInfo.n.u1STR
1211	)
1212	{
1213	if (IoExitInfo.n.u1Type == 0)
1214	{
1215	Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1216	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1217	rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1218	}
1219	else
1220	{
1221	uint32_t u32Val = 0;
1222
1223	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1224	rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1225	if (rc == VINF_SUCCESS)
1226	{
1227	/* Write back to the EAX register. */
1228	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1229	Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1230	}
1231	}
1232	if (rc == VINF_SUCCESS)
1233	{
1234	/* Update EIP and continue execution. */
1235	pCtx->eip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1236	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1237	goto ResumeExecution;
1238	}
1239	Assert(rc == VINF_IOM_HC_IOPORT_READ \|\| rc == VINF_IOM_HC_IOPORT_WRITE);
1240	rc = (IoExitInfo.n.u1Type == 0) ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1241	}
1242	else
1243	rc = VINF_IOM_HC_IOPORT_READWRITE;
1244
1245	Log2(("Failed IO at %VGv %x size %d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1246
1247	break;
1248	}
1249
1250	case SVM_EXIT_HLT:
1251	/** Check if external interrupts are pending; if so, don't switch back. */
1252	if (VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1253	{
1254	pCtx->eip++; /* skip hlt */
1255	goto ResumeExecution;
1256	}
1257
1258	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1259	break;
1260
1261	case SVM_EXIT_RDPMC:
1262	case SVM_EXIT_RSM:
1263	case SVM_EXIT_INVLPGA:
1264	case SVM_EXIT_VMRUN:
1265	case SVM_EXIT_VMMCALL:
1266	case SVM_EXIT_VMLOAD:
1267	case SVM_EXIT_VMSAVE:
1268	case SVM_EXIT_STGI:
1269	case SVM_EXIT_CLGI:
1270	case SVM_EXIT_SKINIT:
1271	case SVM_EXIT_RDTSCP:
1272	{
1273	/* Unsupported instructions. */
1274	SVM_EVENT Event;
1275
1276	Event.au64[0] = 0;
1277	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1278	Event.n.u1Valid = 1;
1279	Event.n.u8Vector = X86_XCPT_UD;
1280
1281	Log(("Forced #UD trap at %VGv\n", pCtx->eip));
1282	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1283
1284	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1285	goto ResumeExecution;
1286	}
1287
1288	/* Emulate RDMSR & WRMSR in ring 3. */
1289	case SVM_EXIT_MSR:
1290	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1291	break;
1292
1293	case SVM_EXIT_NPF:
1294	AssertFailed(); /* unexpected */
1295	break;
1296
1297	case SVM_EXIT_SHUTDOWN:
1298	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1299	break;
1300
1301	case SVM_EXIT_PAUSE:
1302	case SVM_EXIT_IDTR_READ:
1303	case SVM_EXIT_GDTR_READ:
1304	case SVM_EXIT_LDTR_READ:
1305	case SVM_EXIT_TR_READ:
1306	case SVM_EXIT_IDTR_WRITE:
1307	case SVM_EXIT_GDTR_WRITE:
1308	case SVM_EXIT_LDTR_WRITE:
1309	case SVM_EXIT_TR_WRITE:
1310	case SVM_EXIT_CR0_SEL_WRITE:
1311	default:
1312	/* Unexpected exit codes. */
1313	rc = VERR_EM_INTERNAL_ERROR;
1314	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
1315	break;
1316	}
1317
1318	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1319	SVM_READ_SELREG(LDTR, ldtr);
1320	SVM_READ_SELREG(TR, tr);
1321
1322	pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1323	pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1324
1325	pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1326	pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1327
1328	/*
1329	* System MSRs
1330	*/
1331	pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1332	pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1333	pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1334
1335	/* Signal changes for the recompiler. */
1336	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
1337
1338	end:
1339
1340	/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
1341	if (exitCode == SVM_EXIT_INTR)
1342	{
1343	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1344	/* On the next entry we'll only sync the host context. */
1345	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
1346	}
1347	else
1348	{
1349	/* On the next entry we'll sync everything. */
1350	/** @todo we can do better than this */
1351	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
1352	}
1353
1354	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1355	return rc;
1356	}
1357
1358	/**
1359	* Enable SVM
1360	*
1361	* @returns VBox status code.
1362	* @param pVM The VM to operate on.
1363	*/
1364	HWACCMR0DECL(int) SVMR0Enable(PVM pVM)
1365	{
1366	uint64_t val;
1367
1368	Assert(pVM->hwaccm.s.svm.fSupported);
1369
1370	/* We must turn on SVM and setup the host state physical address, as those MSRs are per-cpu/core. */
1371
1372	/* Turn on SVM in the EFER MSR. */
1373	val = ASMRdMsr(MSR_K6_EFER);
1374	if (!(val & MSR_K6_EFER_SVME))
1375	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
1376
1377	/* Write the physical page address where the CPU will store the host state while executing the VM. */
1378	ASMWrMsr(MSR_K8_VM_HSAVE_PA, pVM->hwaccm.s.svm.pHStatePhys);
1379
1380	/* Force a TLB flush on VM entry. */
1381	pVM->hwaccm.s.svm.fResumeVM = false;
1382
1383	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
1384	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_LDTR;
1385
1386	return VINF_SUCCESS;
1387	}
1388
1389
1390	/**
1391	* Disable SVM
1392	*
1393	* @returns VBox status code.
1394	* @param pVM The VM to operate on.
1395	*/
1396	HWACCMR0DECL(int) SVMR0Disable(PVM pVM)
1397	{
1398	/** @todo hopefully this is not very expensive. */
1399
1400	/* Turn off SVM in the EFER MSR. */
1401	uint64_t val = ASMRdMsr(MSR_K6_EFER);
1402	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
1403
1404	/* Invalidate host state physical address. */
1405	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
1406
1407	Assert(pVM->hwaccm.s.svm.fSupported);
1408	return VINF_SUCCESS;
1409	}
1410
1411
1412	static int svmInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1413	{
1414	OP_PARAMVAL param1;
1415	RTGCPTR addr;
1416
1417	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1418	if(VBOX_FAILURE(rc))
1419	return VERR_EM_INTERPRETER;
1420
1421	switch(param1.type)
1422	{
1423	case PARMTYPE_IMMEDIATE:
1424	case PARMTYPE_ADDRESS:
1425	if(!(param1.flags & PARAM_VAL32))
1426	return VERR_EM_INTERPRETER;
1427	addr = (RTGCPTR)param1.val.val32;
1428	break;
1429
1430	default:
1431	return VERR_EM_INTERPRETER;
1432	}
1433
1434	/** @todo is addr always a flat linear address or ds based
1435	* (in absence of segment override prefixes)????
1436	*/
1437	rc = PGMInvalidatePage(pVM, addr);
1438	if (VBOX_SUCCESS(rc))
1439	{
1440	/* Manually invalidate the page for the VM's TLB. */
1441	SVMInvlpgA(addr, uASID);
1442	return VINF_SUCCESS;
1443	}
1444	/** @todo r=bird: we shouldn't ignore returns codes like this... I'm 99% sure the error is fatal. */
1445	return VERR_EM_INTERPRETER;
1446	}
1447
1448	/**
1449	* Interprets INVLPG
1450	*
1451	* @returns VBox status code.
1452	* @retval VINF_* Scheduling instructions.
1453	* @retval VERR_EM_INTERPRETER Something we can't cope with.
1454	* @retval VERR_* Fatal errors.
1455	*
1456	* @param pVM The VM handle.
1457	* @param pRegFrame The register frame.
1458	* @param ASID Tagged TLB id for the guest
1459	*
1460	* Updates the EIP if an instruction was executed successfully.
1461	*/
1462	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1463	{
1464	/*
1465	* Only allow 32-bit code.
1466	*/
1467	if (SELMIsSelector32Bit(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid))
1468	{
1469	RTGCPTR pbCode;
1470	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pbCode);
1471	if (VBOX_SUCCESS(rc))
1472	{
1473	uint32_t cbOp;
1474	DISCPUSTATE Cpu;
1475
1476	Cpu.mode = CPUMODE_32BIT;
1477	rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
1478	Assert(VBOX_FAILURE(rc) \|\| Cpu.pCurInstr->opcode == OP_INVLPG);
1479	if (VBOX_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
1480	{
1481	Assert(cbOp == Cpu.opsize);
1482	rc = svmInterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
1483	if (VBOX_SUCCESS(rc))
1484	{
1485	pRegFrame->eip += cbOp; /* Move on to the next instruction. */
1486	}
1487	return rc;
1488	}
1489	}
1490	}
1491	return VERR_EM_INTERPRETER;
1492	}
1493

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 2133

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