HWSVMR0.cpp@ 2134

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1	/* $Id: HWSVMR0.cpp 2134 2007-04-17 14:52:36Z vboxsync $ */
2	/** @file
3	* HWACCM SVM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_svm.h>
32	#include <VBox/pgm.h>
33	#include <VBox/pdm.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <VBox/selm.h>
37	#include <VBox/iom.h>
38	#include <VBox/dis.h>
39	#include <VBox/disopcode.h>
40	#include <iprt/param.h>
41	#include <iprt/assert.h>
42	#include <iprt/asm.h>
43	#include "HWSVMR0.h"
44
45	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
46
47	/**
48	* Sets up and activates SVM
49	*
50	* @returns VBox status code.
51	* @param pVM The VM to operate on.
52	*/
53	HWACCMR0DECL(int) SVMR0Setup(PVM pVM)
54	{
55	int rc = VINF_SUCCESS;
56	SVM_VMCB *pVMCB;
57
58	if (pVM == NULL)
59	return VERR_INVALID_PARAMETER;
60
61	/* Setup AMD SVM. */
62	Assert(pVM->hwaccm.s.svm.fSupported);
63
64	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
65	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
66
67	/* Program the control fields. Most of them never have to be changed again. */
68	/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
69	/** @note CR0 & CR4 can be safely read when guest and shadow copies are identical. */
70	pVMCB->ctrl.u16InterceptRdCRx = BIT(0) \| BIT(3) \| BIT(4) \| BIT(8);
71
72	/*
73	* CR0/3/4 writes must be intercepted for obvious reasons.
74	*/
75	pVMCB->ctrl.u16InterceptWrCRx = BIT(0) \| BIT(3) \| BIT(4) \| BIT(8);
76
77	/* Intercept all DRx reads and writes. */
78	pVMCB->ctrl.u16InterceptRdDRx = BIT(0) \| BIT(1) \| BIT(2) \| BIT(3) \| BIT(4) \| BIT(5) \| BIT(6) \| BIT(7);
79	pVMCB->ctrl.u16InterceptWrDRx = BIT(0) \| BIT(1) \| BIT(2) \| BIT(3) \| BIT(4) \| BIT(5) \| BIT(6) \| BIT(7);
80
81	/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
82	* All breakpoints are automatically cleared when the VM exits.
83	*/
84
85	/** @todo nested paging */
86	/* Intercept #NM only; #PF is not relevant due to nested paging (we get a seperate exit code (SVM_EXIT_NPF) for
87	* pagefaults that need our attention).
88	*/
89	pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
90
91	pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
92	\| SVM_CTRL1_INTERCEPT_VINTR
93	\| SVM_CTRL1_INTERCEPT_NMI
94	\| SVM_CTRL1_INTERCEPT_SMI
95	\| SVM_CTRL1_INTERCEPT_INIT
96	\| SVM_CTRL1_INTERCEPT_CR0 /** @todo redundant? */
97	\| SVM_CTRL1_INTERCEPT_RDPMC
98	\| SVM_CTRL1_INTERCEPT_CPUID
99	\| SVM_CTRL1_INTERCEPT_RSM
100	\| SVM_CTRL1_INTERCEPT_HLT
101	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
102	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
103	\| SVM_CTRL1_INTERCEPT_INVLPG
104	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
105	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
106	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
107	;
108	pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
109	\| SVM_CTRL2_INTERCEPT_VMMCALL
110	\| SVM_CTRL2_INTERCEPT_VMLOAD
111	\| SVM_CTRL2_INTERCEPT_VMSAVE
112	\| SVM_CTRL2_INTERCEPT_STGI
113	\| SVM_CTRL2_INTERCEPT_CLGI
114	\| SVM_CTRL2_INTERCEPT_SKINIT
115	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
116	;
117	Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
118	Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
119	Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
120
121	/* Virtualize masking of INTR interrupts. */
122	pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
123
124	/* Set IO and MSR bitmap addresses. */
125	pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
126	pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
127
128	/* Enable nested paging. */
129	/** @todo how to detect support for this?? */
130	pVMCB->ctrl.u64NestedPaging = 0; /** @todo SVM_NESTED_PAGING_ENABLE; */
131
132	/* No LBR virtualization. */
133	pVMCB->ctrl.u64LBRVirt = 0;
134
135	return rc;
136	}
137
138
139	/**
140	* Injects an event (trap or external interrupt)
141	*
142	* @param pVM The VM to operate on.
143	* @param pVMCB SVM control block
144	* @param pCtx CPU Context
145	* @param pIntInfo SVM interrupt info
146	*/
147	inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx, SVM_EVENT* pEvent)
148	{
149	#ifdef VBOX_STRICT
150	if (pEvent->n.u8Vector == 0xE)
151	Log(("SVM: Inject int %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
152	else
153	if (pEvent->n.u8Vector < 0x20)
154	Log(("SVM: Inject int %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode));
155	else
156	{
157	Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->eip));
158	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
159	Assert(pCtx->eflags.u32 & X86_EFL_IF);
160	}
161	#endif
162
163	/* Set event injection state. */
164	pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
165	}
166
167
168	/**
169	* Checks for pending guest interrupts and injects them
170	*
171	* @returns VBox status code.
172	* @param pVM The VM to operate on.
173	* @param pVMCB SVM control block
174	* @param pCtx CPU Context
175	*/
176	static int SVMR0CheckPendingInterrupt(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx)
177	{
178	int rc;
179
180	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
181	if (pVM->hwaccm.s.Event.fPending)
182	{
183	SVM_EVENT Event;
184
185	Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
186	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
187	Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
188	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
189
190	pVM->hwaccm.s.Event.fPending = false;
191	return VINF_SUCCESS;
192	}
193
194	/* When external interrupts are pending, we should exit the VM when IF is set. */
195	if ( !TRPMHasTrap(pVM)
196	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
197	{
198	if (!(pCtx->eflags.u32 & X86_EFL_IF))
199	{
200	Log2(("Enable irq window exit!\n"));
201	/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
202	//// pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
203	//// AssertRC(rc);
204	}
205	else
206	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
207	{
208	uint8_t u8Interrupt;
209
210	rc = PDMGetInterrupt(pVM, &u8Interrupt);
211	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
212	if (VBOX_SUCCESS(rc))
213	{
214	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
215	AssertRC(rc);
216	}
217	else
218	{
219	/* can't happen... */
220	AssertFailed();
221	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
222	return VINF_EM_RAW_INTERRUPT_PENDING;
223	}
224	}
225	else
226	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
227	}
228
229	#ifdef VBOX_STRICT
230	if (TRPMHasTrap(pVM))
231	{
232	uint8_t u8Vector;
233	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
234	AssertRC(rc);
235	}
236	#endif
237
238	if ( pCtx->eflags.u32 & X86_EFL_IF
239	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
240	&& TRPMHasTrap(pVM)
241	)
242	{
243	uint8_t u8Vector;
244	int rc;
245	TRPMEVENT enmType;
246	SVM_EVENT Event;
247	uint32_t u32ErrorCode;
248
249	Event.au64[0] = 0;
250
251	/* If a new event is pending, then dispatch it now. */
252	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &u32ErrorCode, 0);
253	AssertRC(rc);
254	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
255	Assert(enmType != TRPM_SOFTWARE_INT);
256
257	/* Clear the pending trap. */
258	rc = TRPMResetTrap(pVM);
259	AssertRC(rc);
260
261	Event.n.u8Vector = u8Vector;
262	Event.n.u1Valid = 1;
263	Event.n.u32ErrorCode = u32ErrorCode;
264
265	if (enmType == TRPM_TRAP)
266	{
267	switch (u8Vector) {
268	case 8:
269	case 10:
270	case 11:
271	case 12:
272	case 13:
273	case 14:
274	case 17:
275	/* Valid error codes. */
276	Event.n.u1ErrorCodeValid = 1;
277	break;
278	default:
279	break;
280	}
281	if (u8Vector == X86_XCPT_NMI)
282	Event.n.u3Type = SVM_EVENT_NMI;
283	else
284	Event.n.u3Type = SVM_EVENT_EXCEPTION;
285	}
286	else
287	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
288
289	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
290	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
291	} /* if (interrupts can be dispatched) */
292
293	return VINF_SUCCESS;
294	}
295
296
297	/**
298	* Loads the guest state
299	*
300	* @returns VBox status code.
301	* @param pVM The VM to operate on.
302	* @param pCtx Guest context
303	*/
304	HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
305	{
306	RTGCUINTPTR val;
307	SVM_VMCB *pVMCB;
308
309	if (pVM == NULL)
310	return VERR_INVALID_PARAMETER;
311
312	/* Setup AMD SVM. */
313	Assert(pVM->hwaccm.s.svm.fSupported);
314
315	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
316	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
317
318	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
319	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
320	{
321	SVM_WRITE_SELREG(CS, cs);
322	SVM_WRITE_SELREG(SS, ss);
323	SVM_WRITE_SELREG(DS, ds);
324	SVM_WRITE_SELREG(ES, es);
325	SVM_WRITE_SELREG(FS, fs);
326	SVM_WRITE_SELREG(GS, gs);
327	}
328
329	/* Guest CPU context: LDTR. */
330	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
331	{
332	SVM_WRITE_SELREG(LDTR, ldtr);
333	}
334
335	/* Guest CPU context: TR. */
336	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
337	{
338	SVM_WRITE_SELREG(TR, tr);
339	}
340
341	/* Guest CPU context: GDTR. */
342	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
343	{
344	pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
345	pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
346	}
347
348	/* Guest CPU context: IDTR. */
349	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
350	{
351	pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
352	pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
353	}
354
355	/*
356	* Sysenter MSRs
357	*/
358	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
359	{
360	pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
361	pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
362	pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
363	}
364
365	/* Control registers */
366	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
367	{
368	val = pCtx->cr0;
369	if (CPUMIsGuestFPUStateActive(pVM) == false)
370	{
371	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
372	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
373	}
374	else
375	{
376	Assert(pVM->hwaccm.s.svm.fResumeVM == true);
377	/** @todo check if we support the old style mess correctly. */
378	if (!(val & X86_CR0_NE))
379	{
380	Log(("Forcing X86_CR0_NE!!!\n"));
381
382	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
383	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
384	{
385	pVMCB->ctrl.u32InterceptException \|= BIT(16);
386	pVM->hwaccm.s.fFPUOldStyleOverride = true;
387	}
388	}
389	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
390	}
391	if (!(val & X86_CR0_CD))
392	val &= ~X86_CR0_NW; /* Illegal when cache is turned on. */
393
394	val \|= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
395	pVMCB->guest.u64CR0 = val;
396	}
397	/* CR2 as well */
398	pVMCB->guest.u64CR2 = pCtx->cr2;
399
400	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
401	{
402	/* Save our shadow CR3 register. */
403	pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
404	}
405
406	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
407	{
408	val = pCtx->cr4;
409	switch(pVM->hwaccm.s.enmShadowMode)
410	{
411	case PGMMODE_REAL:
412	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
413	AssertFailed();
414	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
415
416	case PGMMODE_32_BIT: /* 32-bit paging. */
417	break;
418
419	case PGMMODE_PAE: /* PAE paging. */
420	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
421	/** @todo use normal 32 bits paging */
422	val \|= X86_CR4_PAE;
423	break;
424
425	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
426	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
427	AssertFailed();
428	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
429
430	default: /* shut up gcc */
431	AssertFailed();
432	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
433	}
434	pVMCB->guest.u64CR4 = val;
435	}
436
437	/* Debug registers. */
438	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
439	{
440	/** @todo DR0-6 */
441	val = pCtx->dr7;
442	val &= ~(BIT(11) \| BIT(12) \| BIT(14) \| BIT(15)); /* must be zero */
443	val \|= 0x400; /* must be one */
444	#ifdef VBOX_STRICT
445	val = 0x400;
446	#endif
447	pVMCB->guest.u64DR7 = val;
448
449	pVMCB->guest.u64DR6 = pCtx->dr6;
450	}
451
452	/* EIP, ESP and EFLAGS */
453	pVMCB->guest.u64RIP = pCtx->eip;
454	pVMCB->guest.u64RSP = pCtx->esp;
455	pVMCB->guest.u64RFlags = pCtx->eflags.u32;
456
457	/* Set CPL */
458	if (!(pCtx->cr0 & X86_CR0_PE))
459	pVMCB->guest.u8CPL = 0;
460	else
461	if (pCtx->eflags.Bits.u1VM)
462	pVMCB->guest.u8CPL = 3;
463	else
464	pVMCB->guest.u8CPL = (pCtx->ss & X86_SEL_RPL);
465
466	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
467	pVMCB->guest.u64RAX = pCtx->eax;
468
469	/* vmrun will fail otherwise. */
470	pVMCB->guest.u64EFER = MSR_K6_EFER_SVME;
471
472	/** @note We can do more complex things with tagged TLBs. */
473	pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
474
475	/** TSC offset. */
476	pVMCB->ctrl.u64TSCOffset = TMCpuTickGetOffset(pVM);
477
478	/** @todo 64 bits stuff (?):
479	* - STAR
480	* - LSTAR
481	* - CSTAR
482	* - SFMASK
483	* - KernelGSBase
484	*/
485
486	/* Done. */
487	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
488
489	return VINF_SUCCESS;
490	}
491
492
493	/**
494	* Runs guest code in an SVM VM.
495	*
496	* @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
497	*
498	* @returns VBox status code.
499	* @param pVM The VM to operate on.
500	* @param pCtx Guest context
501	*/
502	HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
503	{
504	int rc = VINF_SUCCESS;
505	uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
506	SVM_VMCB *pVMCB;
507	bool fForceTLBFlush = false;
508
509	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
510
511	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
512	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
513
514	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
515	*/
516	ResumeExecution:
517
518	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
519	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
520	{
521	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
522	if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
523	{
524	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
525	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
526	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
527	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
528	*/
529	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
530	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
531	pVMCB->ctrl.u64IntShadow = 0;
532	}
533	}
534	else
535	{
536	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
537	pVMCB->ctrl.u64IntShadow = 0;
538	}
539
540	/* Check for pending actions that force us to go back to ring 3. */
541	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
542	{
543	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
544	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
545	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
546	rc = VINF_EM_RAW_TO_R3;
547	goto end;
548	}
549	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
550	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
551	{
552	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
553	rc = VINF_EM_PENDING_REQUEST;
554	goto end;
555	}
556
557	/* When external interrupts are pending, we should exit the VM when IF is set. */
558	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
559	rc = SVMR0CheckPendingInterrupt(pVM, pVMCB, pCtx);
560	if (VBOX_FAILURE(rc))
561	{
562	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
563	goto end;
564	}
565
566	/* Load the guest state */
567	rc = SVMR0LoadGuestState(pVM, pCtx);
568	if (rc != VINF_SUCCESS)
569	{
570	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
571	goto end;
572	}
573
574	/* All done! Let's start VM execution. */
575	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
576
577	/** Erratum #170 -> must force a TLB flush */
578	/** @todo supposed to be fixed in future by AMD */
579	fForceTLBFlush = true;
580
581	if ( pVM->hwaccm.s.svm.fResumeVM == false
582	\|\| fForceTLBFlush)
583	{
584	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1;
585	}
586	else
587	{
588	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 0;
589	}
590	/* In case we execute a goto ResumeExecution later on. */
591	pVM->hwaccm.s.svm.fResumeVM = true;
592	fForceTLBFlush = false;
593
594	Assert(sizeof(pVM->hwaccm.s.svm.pVMCBPhys) == 8);
595	Assert(pVMCB->ctrl.u32InterceptCtrl1 == ( SVM_CTRL1_INTERCEPT_INTR
596	\| SVM_CTRL1_INTERCEPT_VINTR
597	\| SVM_CTRL1_INTERCEPT_NMI
598	\| SVM_CTRL1_INTERCEPT_SMI
599	\| SVM_CTRL1_INTERCEPT_INIT
600	\| SVM_CTRL1_INTERCEPT_CR0 /** @todo redundant? */
601	\| SVM_CTRL1_INTERCEPT_RDPMC
602	\| SVM_CTRL1_INTERCEPT_CPUID
603	\| SVM_CTRL1_INTERCEPT_RSM
604	\| SVM_CTRL1_INTERCEPT_HLT
605	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
606	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
607	\| SVM_CTRL1_INTERCEPT_INVLPG
608	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
609	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
610	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE /* Legacy FPU FERR handling. */
611	));
612	Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
613	\| SVM_CTRL2_INTERCEPT_VMMCALL
614	\| SVM_CTRL2_INTERCEPT_VMLOAD
615	\| SVM_CTRL2_INTERCEPT_VMSAVE
616	\| SVM_CTRL2_INTERCEPT_STGI
617	\| SVM_CTRL2_INTERCEPT_CLGI
618	\| SVM_CTRL2_INTERCEPT_SKINIT
619	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
620	));
621	Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
622	Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
623	Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
624	Assert(pVMCB->ctrl.u64NestedPaging == 0);
625	Assert(pVMCB->ctrl.u64LBRVirt == 0);
626
627	SVMVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);
628	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
629
630	/**
631	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
632	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
633	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
634	*/
635
636	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
637
638	/* Reason for the VM exit */
639	exitCode = pVMCB->ctrl.u64ExitCode;
640
641	if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
642	{
643	HWACCMDumpRegs(pCtx);
644	#ifdef DEBUG
645	Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
646	Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
647	Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
648	Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
649	Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
650	Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
651	Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
652	Log(("ctrl.u64IOPMPhysAddr %VX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
653	Log(("ctrl.u64MSRPMPhysAddr %VX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
654	Log(("ctrl.u64TSCOffset %VX64\n", pVMCB->ctrl.u64TSCOffset));
655
656	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
657	Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
658	Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
659	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
660
661	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
662	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
663	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
664	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
665	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
666	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
667	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
668	Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
669	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
670	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
671
672	Log(("ctrl.u64IntShadow %VX64\n", pVMCB->ctrl.u64IntShadow));
673	Log(("ctrl.u64ExitCode %VX64\n", pVMCB->ctrl.u64ExitCode));
674	Log(("ctrl.u64ExitInfo1 %VX64\n", pVMCB->ctrl.u64ExitInfo1));
675	Log(("ctrl.u64ExitInfo2 %VX64\n", pVMCB->ctrl.u64ExitInfo2));
676	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
677	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
678	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
679	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
680	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
681	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
682	Log(("ctrl.u64NestedPaging %VX64\n", pVMCB->ctrl.u64NestedPaging));
683	Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
684	Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
685	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
686	Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
687	Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
688	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
689
690	Log(("ctrl.u64HostCR3 %VX64\n", pVMCB->ctrl.u64HostCR3));
691	Log(("ctrl.u64LBRVirt %VX64\n", pVMCB->ctrl.u64LBRVirt));
692
693	Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
694	Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
695	Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
696	Log(("guest.CS.u64Base %VX64\n", pVMCB->guest.CS.u64Base));
697	Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
698	Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
699	Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
700	Log(("guest.DS.u64Base %VX64\n", pVMCB->guest.DS.u64Base));
701	Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
702	Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
703	Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
704	Log(("guest.ES.u64Base %VX64\n", pVMCB->guest.ES.u64Base));
705	Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
706	Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
707	Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
708	Log(("guest.FS.u64Base %VX64\n", pVMCB->guest.FS.u64Base));
709	Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
710	Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
711	Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
712	Log(("guest.GS.u64Base %VX64\n", pVMCB->guest.GS.u64Base));
713
714	Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
715	Log(("guest.GDTR.u64Base %VX64\n", pVMCB->guest.GDTR.u64Base));
716
717	Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
718	Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
719	Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
720	Log(("guest.LDTR.u64Base %VX64\n", pVMCB->guest.LDTR.u64Base));
721
722	Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
723	Log(("guest.IDTR.u64Base %VX64\n", pVMCB->guest.IDTR.u64Base));
724
725	Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
726	Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
727	Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
728	Log(("guest.TR.u64Base %VX64\n", pVMCB->guest.TR.u64Base));
729
730	Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
731	Log(("guest.u64CR0 %VX64\n", pVMCB->guest.u64CR0));
732	Log(("guest.u64CR2 %VX64\n", pVMCB->guest.u64CR2));
733	Log(("guest.u64CR3 %VX64\n", pVMCB->guest.u64CR3));
734	Log(("guest.u64CR4 %VX64\n", pVMCB->guest.u64CR4));
735	Log(("guest.u64DR6 %VX64\n", pVMCB->guest.u64DR6));
736	Log(("guest.u64DR7 %VX64\n", pVMCB->guest.u64DR7));
737
738	Log(("guest.u64RIP %VX64\n", pVMCB->guest.u64RIP));
739	Log(("guest.u64RSP %VX64\n", pVMCB->guest.u64RSP));
740	Log(("guest.u64RAX %VX64\n", pVMCB->guest.u64RAX));
741	Log(("guest.u64RFlags %VX64\n", pVMCB->guest.u64RFlags));
742
743	Log(("guest.u64SysEnterCS %VX64\n", pVMCB->guest.u64SysEnterCS));
744	Log(("guest.u64SysEnterEIP %VX64\n", pVMCB->guest.u64SysEnterEIP));
745	Log(("guest.u64SysEnterESP %VX64\n", pVMCB->guest.u64SysEnterESP));
746
747	Log(("guest.u64EFER %VX64\n", pVMCB->guest.u64EFER));
748	Log(("guest.u64STAR %VX64\n", pVMCB->guest.u64STAR));
749	Log(("guest.u64LSTAR %VX64\n", pVMCB->guest.u64LSTAR));
750	Log(("guest.u64CSTAR %VX64\n", pVMCB->guest.u64CSTAR));
751	Log(("guest.u64SFMASK %VX64\n", pVMCB->guest.u64SFMASK));
752	Log(("guest.u64KernelGSBase %VX64\n", pVMCB->guest.u64KernelGSBase));
753	Log(("guest.u64GPAT %VX64\n", pVMCB->guest.u64GPAT));
754	Log(("guest.u64DBGCTL %VX64\n", pVMCB->guest.u64DBGCTL));
755	Log(("guest.u64BR_FROM %VX64\n", pVMCB->guest.u64BR_FROM));
756	Log(("guest.u64BR_TO %VX64\n", pVMCB->guest.u64BR_TO));
757	Log(("guest.u64LASTEXCPFROM %VX64\n", pVMCB->guest.u64LASTEXCPFROM));
758	Log(("guest.u64LASTEXCPTO %VX64\n", pVMCB->guest.u64LASTEXCPTO));
759
760	#endif
761	rc = VERR_SVM_UNABLE_TO_START_VM;
762	goto end;
763	}
764
765	/* Let's first sync back eip, esp, and eflags. */
766	pCtx->eip = pVMCB->guest.u64RIP;
767	pCtx->esp = pVMCB->guest.u64RSP;
768	pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
769	/* eax is saved/restore across the vmrun instruction */
770	pCtx->eax = pVMCB->guest.u64RAX;
771
772	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
773	SVM_READ_SELREG(SS, ss);
774	SVM_READ_SELREG(CS, cs);
775	SVM_READ_SELREG(DS, ds);
776	SVM_READ_SELREG(ES, es);
777	SVM_READ_SELREG(FS, fs);
778	SVM_READ_SELREG(GS, gs);
779
780	/** @note no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
781
782	/** @note NOW IT'S SAFE FOR LOGGING! */
783
784	/* Take care of instruction fusing (sti, mov ss) */
785	if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
786	{
787	Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->eip));
788	EMSetInhibitInterruptsPC(pVM, pCtx->eip);
789	}
790	else
791	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
792
793	Log2(("exitCode = %x\n", exitCode));
794
795	/* Check if an injected event was interrupted prematurely. */
796	pVM->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
797	if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
798	&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
799	{
800	Log(("Pending inject %VX64 at %08x exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitCode));
801	pVM->hwaccm.s.Event.fPending = true;
802	/* Error code present? (redundant) */
803	if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
804	{
805	pVM->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
806	}
807	else
808	pVM->hwaccm.s.Event.errCode = 0;
809	}
810	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReason[exitCode & MASK_EXITREASON_STAT]);
811
812	/* Deal with the reason of the VM-exit. */
813	switch (exitCode)
814	{
815	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
816	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
817	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
818	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
819	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
820	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
821	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
822	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
823	{
824	/* Pending trap. */
825	SVM_EVENT Event;
826	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
827
828	Log2(("Hardware/software interrupt %d\n", vector));
829	switch (vector)
830	{
831	case X86_XCPT_NM:
832	{
833	uint32_t oldCR0;
834
835	Log(("#NM fault at %VGv\n", pCtx->eip));
836
837	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
838	oldCR0 = ASMGetCR0();
839	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
840	rc = CPUMHandleLazyFPU(pVM);
841	if (rc == VINF_SUCCESS)
842	{
843	Assert(CPUMIsGuestFPUStateActive(pVM));
844
845	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
846	ASMSetCR0(oldCR0);
847
848	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
849
850	/* Continue execution. */
851	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
852	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
853
854	goto ResumeExecution;
855	}
856
857	Log(("Forward #NM fault to the guest\n"));
858	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
859
860	Event.au64[0] = 0;
861	Event.n.u3Type = SVM_EVENT_EXCEPTION;
862	Event.n.u1Valid = 1;
863	Event.n.u8Vector = X86_XCPT_NM;
864
865	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
866	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
867	goto ResumeExecution;
868	}
869
870	case X86_XCPT_PF: /* Page fault */
871	{
872	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
873	RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
874
875	Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
876	/* Exit qualification contains the linear address of the page fault. */
877	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
878	TRPMSetErrorCode(pVM, errCode);
879	TRPMSetFaultAddress(pVM, uFaultAddress);
880
881	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
882	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
883	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
884	if (rc == VINF_SUCCESS)
885	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
886	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
887	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
888
889	TRPMResetTrap(pVM);
890
891	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
892	goto ResumeExecution;
893	}
894	else
895	if (rc == VINF_EM_RAW_GUEST_TRAP)
896	{ /* A genuine pagefault.
897	* Forward the trap to the guest by injecting the exception and resuming execution.
898	*/
899	Log2(("Forward page fault to the guest\n"));
900	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
901	/* The error code might have been changed. */
902	errCode = TRPMGetErrorCode(pVM);
903
904	TRPMResetTrap(pVM);
905
906	/* Now we must update CR2. */
907	pCtx->cr2 = uFaultAddress;
908
909	Event.au64[0] = 0;
910	Event.n.u3Type = SVM_EVENT_EXCEPTION;
911	Event.n.u1Valid = 1;
912	Event.n.u8Vector = X86_XCPT_PF;
913	Event.n.u1ErrorCodeValid = 1;
914	Event.n.u32ErrorCode = errCode;
915
916	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
917
918	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
919	goto ResumeExecution;
920	}
921	#ifdef VBOX_STRICT
922	if (rc != VINF_EM_RAW_EMULATE_INSTR)
923	Log(("PGMTrap0eHandler failed with %d\n", rc));
924	#endif
925	/* Need to go back to the recompiler to emulate the instruction. */
926	TRPMResetTrap(pVM);
927	break;
928	}
929
930	case X86_XCPT_MF: /* Floating point exception. */
931	{
932	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
933	if (!(pCtx->cr0 & X86_CR0_NE))
934	{
935	/* old style FPU error reporting needs some extra work. */
936	/** @todo don't fall back to the recompiler, but do it manually. */
937	rc = VINF_EM_RAW_EMULATE_INSTR;
938	break;
939	}
940	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
941
942	Event.au64[0] = 0;
943	Event.n.u3Type = SVM_EVENT_EXCEPTION;
944	Event.n.u1Valid = 1;
945	Event.n.u8Vector = X86_XCPT_MF;
946
947	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
948
949	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
950	goto ResumeExecution;
951	}
952
953	#ifdef VBOX_STRICT
954	case X86_XCPT_GP: /* General protection failure exception.*/
955	case X86_XCPT_UD: /* Unknown opcode exception. */
956	case X86_XCPT_DE: /* Debug exception. */
957	case X86_XCPT_SS: /* Stack segment exception. */
958	case X86_XCPT_NP: /* Segment not present exception. */
959	{
960	Event.au64[0] = 0;
961	Event.n.u3Type = SVM_EVENT_EXCEPTION;
962	Event.n.u1Valid = 1;
963	Event.n.u8Vector = vector;
964
965	switch(vector)
966	{
967	case X86_XCPT_GP:
968	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
969	Event.n.u1ErrorCodeValid = 1;
970	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
971	break;
972	case X86_XCPT_DE:
973	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
974	break;
975	case X86_XCPT_UD:
976	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
977	break;
978	case X86_XCPT_SS:
979	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
980	Event.n.u1ErrorCodeValid = 1;
981	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
982	break;
983	case X86_XCPT_NP:
984	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
985	Event.n.u1ErrorCodeValid = 1;
986	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
987	break;
988	}
989	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
990	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
991
992	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
993	goto ResumeExecution;
994	}
995	#endif
996	default:
997	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
998	rc = VERR_EM_INTERNAL_ERROR;
999	break;
1000
1001	} /* switch (vector) */
1002	break;
1003	}
1004
1005	case SVM_EXIT_FERR_FREEZE:
1006	case SVM_EXIT_INTR:
1007	case SVM_EXIT_NMI:
1008	case SVM_EXIT_SMI:
1009	case SVM_EXIT_INIT:
1010	case SVM_EXIT_VINTR:
1011	/* External interrupt; leave to allow it to be dispatched again. */
1012	rc = VINF_EM_RAW_INTERRUPT;
1013	break;
1014
1015	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1016	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1017	/* Skip instruction and continue directly. */
1018	pCtx->eip += 2; /** @note hardcoded opcode size! */
1019	/* Continue execution.*/
1020	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1021	goto ResumeExecution;
1022
1023	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1024	{
1025	Log2(("SVM: Cpuid %x\n", pCtx->eax));
1026	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1027	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1028	if (rc == VINF_SUCCESS)
1029	{
1030	/* Update EIP and continue execution. */
1031	pCtx->eip += 2; /** @note hardcoded opcode size! */
1032	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1033	goto ResumeExecution;
1034	}
1035	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1036	rc = VINF_EM_RAW_EMULATE_INSTR;
1037	break;
1038	}
1039
1040	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1041	{
1042	Log2(("SVM: invlpg\n"));
1043	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1044
1045	/* Truly a pita. Why can't SVM give the same information as VMX? */
1046	rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1047	break;
1048	}
1049
1050	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1051	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1052	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1053	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1054	{
1055	uint32_t cbSize;
1056
1057	Log2(("SVM: %VGv mov cr%d, \n", pCtx->eip, exitCode - SVM_EXIT_WRITE_CR0));
1058	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1059	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1060
1061	switch (exitCode - SVM_EXIT_WRITE_CR0)
1062	{
1063	case 0:
1064	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1065	break;
1066	case 2:
1067	break;
1068	case 3:
1069	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1070	break;
1071	case 4:
1072	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1073	break;
1074	default:
1075	AssertFailed();
1076	}
1077	/* Check if a sync operation is pending. */
1078	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1079	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1080	{
1081	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1082	AssertRC(rc);
1083
1084	/** @note Force a TLB flush. SVM requires us to do it manually. */
1085	fForceTLBFlush = true;
1086	}
1087	if (rc == VINF_SUCCESS)
1088	{
1089	/* EIP has been updated already. */
1090
1091	/* Only resume if successful. */
1092	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1093	goto ResumeExecution;
1094	}
1095	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1096	if (rc == VERR_EM_INTERPRETER)
1097	rc = VINF_EM_RAW_EMULATE_INSTR;
1098	break;
1099	}
1100
1101	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1102	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1103	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1104	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1105	{
1106	uint32_t cbSize;
1107
1108	Log2(("SVM: %VGv mov x, cr%d\n", pCtx->eip, exitCode - SVM_EXIT_READ_CR0));
1109	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1110	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1111	if (rc == VINF_SUCCESS)
1112	{
1113	/* EIP has been updated already. */
1114
1115	/* Only resume if successful. */
1116	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1117	goto ResumeExecution;
1118	}
1119	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1120	if (rc == VERR_EM_INTERPRETER)
1121	rc = VINF_EM_RAW_EMULATE_INSTR;
1122	break;
1123	}
1124
1125	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1126	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1127	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1128	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1129	{
1130	uint32_t cbSize;
1131
1132	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_WRITE_DR0));
1133	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1134	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1135	if (rc == VINF_SUCCESS)
1136	{
1137	/* EIP has been updated already. */
1138
1139	/* Only resume if successful. */
1140	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1141	goto ResumeExecution;
1142	}
1143	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1144	if (rc == VERR_EM_INTERPRETER)
1145	rc = VINF_EM_RAW_EMULATE_INSTR;
1146	break;
1147	}
1148
1149	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1150	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1151	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1152	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1153	{
1154	uint32_t cbSize;
1155
1156	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_READ_DR0));
1157	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1158	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1159	if (rc == VINF_SUCCESS)
1160	{
1161	/* EIP has been updated already. */
1162
1163	/* Only resume if successful. */
1164	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1165	goto ResumeExecution;
1166	}
1167	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1168	if (rc == VERR_EM_INTERPRETER)
1169	rc = VINF_EM_RAW_EMULATE_INSTR;
1170	break;
1171	}
1172
1173	/** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1174	case SVM_EXIT_IOIO: /* I/O instruction. */
1175	{
1176	SVM_IOIO_EXIT IoExitInfo;
1177	uint32_t uIOSize, uAndVal;
1178
1179	IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1180
1181	/** @todo could use a lookup table here */
1182	if (IoExitInfo.n.u1OP8)
1183	{
1184	uIOSize = 1;
1185	uAndVal = 0xff;
1186	}
1187	else
1188	if (IoExitInfo.n.u1OP16)
1189	{
1190	uIOSize = 2;
1191	uAndVal = 0xffff;
1192	}
1193	else
1194	if (IoExitInfo.n.u1OP32)
1195	{
1196	uIOSize = 4;
1197	uAndVal = 0xffffffff;
1198	}
1199	else
1200	{
1201	AssertFailed(); /* should be fatal. */
1202	rc = VINF_EM_RAW_EMULATE_INSTR;
1203	break;
1204	}
1205
1206	/* First simple in and out instructions. */
1207	/** @todo str & rep */
1208	if ( !IoExitInfo.n.u1REP
1209	&& !IoExitInfo.n.u1STR
1210	)
1211	{
1212	if (IoExitInfo.n.u1Type == 0)
1213	{
1214	Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1215	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1216	rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1217	}
1218	else
1219	{
1220	uint32_t u32Val = 0;
1221
1222	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1223	rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1224	if (rc == VINF_SUCCESS)
1225	{
1226	/* Write back to the EAX register. */
1227	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1228	Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1229	}
1230	}
1231	if (rc == VINF_SUCCESS)
1232	{
1233	/* Update EIP and continue execution. */
1234	pCtx->eip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1235	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1236	goto ResumeExecution;
1237	}
1238	Assert(rc == VINF_IOM_HC_IOPORT_READ \|\| rc == VINF_IOM_HC_IOPORT_WRITE);
1239	rc = (IoExitInfo.n.u1Type == 0) ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1240	}
1241	else
1242	rc = VINF_IOM_HC_IOPORT_READWRITE;
1243
1244	Log2(("Failed IO at %VGv %x size %d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1245
1246	break;
1247	}
1248
1249	case SVM_EXIT_HLT:
1250	/** Check if external interrupts are pending; if so, don't switch back. */
1251	if (VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1252	{
1253	pCtx->eip++; /* skip hlt */
1254	goto ResumeExecution;
1255	}
1256
1257	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1258	break;
1259
1260	case SVM_EXIT_RDPMC:
1261	case SVM_EXIT_RSM:
1262	case SVM_EXIT_INVLPGA:
1263	case SVM_EXIT_VMRUN:
1264	case SVM_EXIT_VMMCALL:
1265	case SVM_EXIT_VMLOAD:
1266	case SVM_EXIT_VMSAVE:
1267	case SVM_EXIT_STGI:
1268	case SVM_EXIT_CLGI:
1269	case SVM_EXIT_SKINIT:
1270	case SVM_EXIT_RDTSCP:
1271	{
1272	/* Unsupported instructions. */
1273	SVM_EVENT Event;
1274
1275	Event.au64[0] = 0;
1276	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1277	Event.n.u1Valid = 1;
1278	Event.n.u8Vector = X86_XCPT_UD;
1279
1280	Log(("Forced #UD trap at %VGv\n", pCtx->eip));
1281	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1282
1283	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1284	goto ResumeExecution;
1285	}
1286
1287	/* Emulate RDMSR & WRMSR in ring 3. */
1288	case SVM_EXIT_MSR:
1289	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1290	break;
1291
1292	case SVM_EXIT_NPF:
1293	AssertFailed(); /* unexpected */
1294	break;
1295
1296	case SVM_EXIT_SHUTDOWN:
1297	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1298	break;
1299
1300	case SVM_EXIT_PAUSE:
1301	case SVM_EXIT_IDTR_READ:
1302	case SVM_EXIT_GDTR_READ:
1303	case SVM_EXIT_LDTR_READ:
1304	case SVM_EXIT_TR_READ:
1305	case SVM_EXIT_IDTR_WRITE:
1306	case SVM_EXIT_GDTR_WRITE:
1307	case SVM_EXIT_LDTR_WRITE:
1308	case SVM_EXIT_TR_WRITE:
1309	case SVM_EXIT_CR0_SEL_WRITE:
1310	default:
1311	/* Unexpected exit codes. */
1312	rc = VERR_EM_INTERNAL_ERROR;
1313	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
1314	break;
1315	}
1316
1317	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1318	SVM_READ_SELREG(LDTR, ldtr);
1319	SVM_READ_SELREG(TR, tr);
1320
1321	pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1322	pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1323
1324	pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1325	pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1326
1327	/*
1328	* System MSRs
1329	*/
1330	pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1331	pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1332	pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1333
1334	/* Signal changes for the recompiler. */
1335	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
1336
1337	end:
1338
1339	/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
1340	if (exitCode == SVM_EXIT_INTR)
1341	{
1342	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1343	/* On the next entry we'll only sync the host context. */
1344	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
1345	}
1346	else
1347	{
1348	/* On the next entry we'll sync everything. */
1349	/** @todo we can do better than this */
1350	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
1351	}
1352
1353	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1354	return rc;
1355	}
1356
1357	/**
1358	* Enable SVM
1359	*
1360	* @returns VBox status code.
1361	* @param pVM The VM to operate on.
1362	*/
1363	HWACCMR0DECL(int) SVMR0Enable(PVM pVM)
1364	{
1365	uint64_t val;
1366
1367	Assert(pVM->hwaccm.s.svm.fSupported);
1368
1369	/* We must turn on SVM and setup the host state physical address, as those MSRs are per-cpu/core. */
1370
1371	/* Turn on SVM in the EFER MSR. */
1372	val = ASMRdMsr(MSR_K6_EFER);
1373	if (!(val & MSR_K6_EFER_SVME))
1374	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
1375
1376	/* Write the physical page address where the CPU will store the host state while executing the VM. */
1377	ASMWrMsr(MSR_K8_VM_HSAVE_PA, pVM->hwaccm.s.svm.pHStatePhys);
1378
1379	/* Force a TLB flush on VM entry. */
1380	pVM->hwaccm.s.svm.fResumeVM = false;
1381
1382	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
1383	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_LDTR;
1384
1385	return VINF_SUCCESS;
1386	}
1387
1388
1389	/**
1390	* Disable SVM
1391	*
1392	* @returns VBox status code.
1393	* @param pVM The VM to operate on.
1394	*/
1395	HWACCMR0DECL(int) SVMR0Disable(PVM pVM)
1396	{
1397	/** @todo hopefully this is not very expensive. */
1398
1399	/* Turn off SVM in the EFER MSR. */
1400	uint64_t val = ASMRdMsr(MSR_K6_EFER);
1401	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
1402
1403	/* Invalidate host state physical address. */
1404	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
1405
1406	Assert(pVM->hwaccm.s.svm.fSupported);
1407	return VINF_SUCCESS;
1408	}
1409
1410
1411	static int svmInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1412	{
1413	OP_PARAMVAL param1;
1414	RTGCPTR addr;
1415
1416	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1417	if(VBOX_FAILURE(rc))
1418	return VERR_EM_INTERPRETER;
1419
1420	switch(param1.type)
1421	{
1422	case PARMTYPE_IMMEDIATE:
1423	case PARMTYPE_ADDRESS:
1424	if(!(param1.flags & PARAM_VAL32))
1425	return VERR_EM_INTERPRETER;
1426	addr = (RTGCPTR)param1.val.val32;
1427	break;
1428
1429	default:
1430	return VERR_EM_INTERPRETER;
1431	}
1432
1433	/** @todo is addr always a flat linear address or ds based
1434	* (in absence of segment override prefixes)????
1435	*/
1436	rc = PGMInvalidatePage(pVM, addr);
1437	if (VBOX_SUCCESS(rc))
1438	{
1439	/* Manually invalidate the page for the VM's TLB. */
1440	SVMInvlpgA(addr, uASID);
1441	return VINF_SUCCESS;
1442	}
1443	/** @todo r=bird: we shouldn't ignore returns codes like this... I'm 99% sure the error is fatal. */
1444	return VERR_EM_INTERPRETER;
1445	}
1446
1447	/**
1448	* Interprets INVLPG
1449	*
1450	* @returns VBox status code.
1451	* @retval VINF_* Scheduling instructions.
1452	* @retval VERR_EM_INTERPRETER Something we can't cope with.
1453	* @retval VERR_* Fatal errors.
1454	*
1455	* @param pVM The VM handle.
1456	* @param pRegFrame The register frame.
1457	* @param ASID Tagged TLB id for the guest
1458	*
1459	* Updates the EIP if an instruction was executed successfully.
1460	*/
1461	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1462	{
1463	/*
1464	* Only allow 32-bit code.
1465	*/
1466	if (SELMIsSelector32Bit(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid))
1467	{
1468	RTGCPTR pbCode;
1469	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pbCode);
1470	if (VBOX_SUCCESS(rc))
1471	{
1472	uint32_t cbOp;
1473	DISCPUSTATE Cpu;
1474
1475	Cpu.mode = CPUMODE_32BIT;
1476	rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
1477	Assert(VBOX_FAILURE(rc) \|\| Cpu.pCurInstr->opcode == OP_INVLPG);
1478	if (VBOX_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
1479	{
1480	Assert(cbOp == Cpu.opsize);
1481	rc = svmInterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
1482	if (VBOX_SUCCESS(rc))
1483	{
1484	pRegFrame->eip += cbOp; /* Move on to the next instruction. */
1485	}
1486	return rc;
1487	}
1488	}
1489	}
1490	return VERR_EM_INTERPRETER;
1491	}
1492

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 2134

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