VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 21620

Last change on this file since 21620 was 21620, checked in by vboxsync, 16 years ago

TPR access optimization experiments (disabled).
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1/* $Id: HWSVMR0.cpp 21620 2009-07-15 15:59:30Z vboxsync $ */
2/** @file
3 * HWACCM SVM - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/hwacc_svm.h>
32#include <VBox/pgm.h>
33#include <VBox/pdm.h>
34#include <VBox/err.h>
35#include <VBox/log.h>
36#include <VBox/selm.h>
37#include <VBox/iom.h>
38#include <VBox/dis.h>
39#include <VBox/dbgf.h>
40#include <VBox/disopcode.h>
41#include <iprt/param.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/cpuset.h>
45#include <iprt/mp.h>
46#include <iprt/time.h>
47#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
48# include <iprt/thread.h>
49#endif
50#include "HWSVMR0.h"
51
52/*******************************************************************************
53* Internal Functions *
54*******************************************************************************/
55static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID);
56static int svmR0ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
57static int svmR0EmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
58
59/*******************************************************************************
60* Global Variables *
61*******************************************************************************/
62/* IO operation lookup arrays. */
63static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
64
65/**
66 * Sets up and activates AMD-V on the current CPU
67 *
68 * @returns VBox status code.
69 * @param pCpu CPU info struct
70 * @param pVM The VM to operate on. (can be NULL after a resume!!)
71 * @param pvPageCpu Pointer to the global cpu page
72 * @param pPageCpuPhys Physical address of the global cpu page
73 */
74VMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
75{
76 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
77 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
78
79 /* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
80
81#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
82 SUPR0Printf("SVMR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
83#endif
84
85 /* Turn on AMD-V in the EFER MSR. */
86 uint64_t val = ASMRdMsr(MSR_K6_EFER);
87 if (!(val & MSR_K6_EFER_SVME))
88 ASMWrMsr(MSR_K6_EFER, val | MSR_K6_EFER_SVME);
89
90 /* Write the physical page address where the CPU will store the host state while executing the VM. */
91 ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
92
93 return VINF_SUCCESS;
94}
95
96/**
97 * Deactivates AMD-V on the current CPU
98 *
99 * @returns VBox status code.
100 * @param pCpu CPU info struct
101 * @param pvPageCpu Pointer to the global cpu page
102 * @param pPageCpuPhys Physical address of the global cpu page
103 */
104VMMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
105{
106 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
107 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
108
109#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
110 SUPR0Printf("SVMR0DisableCpu cpu %d\n", pCpu->idCpu);
111#endif
112
113 /* Turn off AMD-V in the EFER MSR. */
114 uint64_t val = ASMRdMsr(MSR_K6_EFER);
115 ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
116
117 /* Invalidate host state physical address. */
118 ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
119
120 return VINF_SUCCESS;
121}
122
123/**
124 * Does Ring-0 per VM AMD-V init.
125 *
126 * @returns VBox status code.
127 * @param pVM The VM to operate on.
128 */
129VMMR0DECL(int) SVMR0InitVM(PVM pVM)
130{
131 int rc;
132
133 pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
134 pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
135
136 /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
137 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
138 if (RT_FAILURE(rc))
139 return rc;
140
141 pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
142 pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
143 /* Set all bits to intercept all IO accesses. */
144 ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
145
146 /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
147 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
148 if (RT_FAILURE(rc))
149 return rc;
150
151 pVM->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
152 pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
153 /* Set all bits to intercept all MSR accesses. */
154 ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
155
156 /* Erratum 170 which requires a forced TLB flush for each world switch:
157 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
158 *
159 * All BH-G1/2 and DH-G1/2 models include a fix:
160 * Athlon X2: 0x6b 1/2
161 * 0x68 1/2
162 * Athlon 64: 0x7f 1
163 * 0x6f 2
164 * Sempron: 0x7f 1/2
165 * 0x6f 2
166 * 0x6c 2
167 * 0x7c 2
168 * Turion 64: 0x68 2
169 *
170 */
171 uint32_t u32Dummy;
172 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
173 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
174 u32BaseFamily= (u32Version >> 8) & 0xf;
175 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
176 u32Model = ((u32Version >> 4) & 0xf);
177 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
178 u32Stepping = u32Version & 0xf;
179 if ( u32Family == 0xf
180 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
181 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
182 {
183 Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
184 pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
185 }
186
187 /* Allocate VMCBs for all guest CPUs. */
188 for (unsigned i=0;i<pVM->cCPUs;i++)
189 {
190 PVMCPU pVCpu = &pVM->aCpus[i];
191
192 pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
193 pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
194
195 /* Allocate one page for the host context */
196 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
197 if (RT_FAILURE(rc))
198 return rc;
199
200 pVCpu->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCBHost);
201 pVCpu->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 0);
202 ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCBHost);
203
204 /* Allocate one page for the VM control block (VMCB). */
205 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
206 if (RT_FAILURE(rc))
207 return rc;
208
209 pVCpu->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCB);
210 pVCpu->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCB, 0);
211 ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCB);
212 }
213
214 return VINF_SUCCESS;
215}
216
217/**
218 * Does Ring-0 per VM AMD-V termination.
219 *
220 * @returns VBox status code.
221 * @param pVM The VM to operate on.
222 */
223VMMR0DECL(int) SVMR0TermVM(PVM pVM)
224{
225 for (unsigned i=0;i<pVM->cCPUs;i++)
226 {
227 PVMCPU pVCpu = &pVM->aCpus[i];
228
229 if (pVCpu->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ)
230 {
231 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, false);
232 pVCpu->hwaccm.s.svm.pVMCBHost = 0;
233 pVCpu->hwaccm.s.svm.pVMCBHostPhys = 0;
234 pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
235 }
236
237 if (pVCpu->hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)
238 {
239 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCB, false);
240 pVCpu->hwaccm.s.svm.pVMCB = 0;
241 pVCpu->hwaccm.s.svm.pVMCBPhys = 0;
242 pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
243 }
244 }
245 if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)
246 {
247 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
248 pVM->hwaccm.s.svm.pIOBitmap = 0;
249 pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
250 pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
251 }
252 if (pVM->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
253 {
254 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
255 pVM->hwaccm.s.svm.pMSRBitmap = 0;
256 pVM->hwaccm.s.svm.pMSRBitmapPhys = 0;
257 pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
258 }
259 return VINF_SUCCESS;
260}
261
262/**
263 * Sets up AMD-V for the specified VM
264 *
265 * @returns VBox status code.
266 * @param pVM The VM to operate on.
267 */
268VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
269{
270 int rc = VINF_SUCCESS;
271 SVM_VMCB *pVMCB;
272
273 AssertReturn(pVM, VERR_INVALID_PARAMETER);
274
275 Assert(pVM->hwaccm.s.svm.fSupported);
276
277 for (unsigned i=0;i<pVM->cCPUs;i++)
278 {
279 pVMCB = (SVM_VMCB *)pVM->aCpus[i].hwaccm.s.svm.pVMCB;
280 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
281
282 /* Program the control fields. Most of them never have to be changed again. */
283 /* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
284 /* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical. */
285 if (!pVM->hwaccm.s.fNestedPaging)
286 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
287 else
288 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(4);
289
290 /*
291 * CR0/3/4 writes must be intercepted for obvious reasons.
292 */
293 if (!pVM->hwaccm.s.fNestedPaging)
294 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
295 else
296 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(4) | RT_BIT(8);
297
298 /* Intercept all DRx reads and writes by default. Changed later on. */
299 pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
300 pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
301
302 /* Currently we don't care about DRx reads or writes. DRx registers are trashed.
303 * All breakpoints are automatically cleared when the VM exits.
304 */
305
306 pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
307#ifndef DEBUG
308 if (pVM->hwaccm.s.fNestedPaging)
309 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
310#endif
311
312 pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
313 | SVM_CTRL1_INTERCEPT_VINTR
314 | SVM_CTRL1_INTERCEPT_NMI
315 | SVM_CTRL1_INTERCEPT_SMI
316 | SVM_CTRL1_INTERCEPT_INIT
317 | SVM_CTRL1_INTERCEPT_RDPMC
318 | SVM_CTRL1_INTERCEPT_CPUID
319 | SVM_CTRL1_INTERCEPT_RSM
320 | SVM_CTRL1_INTERCEPT_HLT
321 | SVM_CTRL1_INTERCEPT_INOUT_BITMAP
322 | SVM_CTRL1_INTERCEPT_MSR_SHADOW
323 | SVM_CTRL1_INTERCEPT_INVLPG
324 | SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
325 | SVM_CTRL1_INTERCEPT_TASK_SWITCH
326 | SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
327 | SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
328 ;
329 /* With nested paging we don't care about invlpg anymore. */
330 if (pVM->hwaccm.s.fNestedPaging)
331 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
332
333 pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
334 | SVM_CTRL2_INTERCEPT_VMMCALL
335 | SVM_CTRL2_INTERCEPT_VMLOAD
336 | SVM_CTRL2_INTERCEPT_VMSAVE
337 | SVM_CTRL2_INTERCEPT_STGI
338 | SVM_CTRL2_INTERCEPT_CLGI
339 | SVM_CTRL2_INTERCEPT_SKINIT
340 | SVM_CTRL2_INTERCEPT_WBINVD
341 | SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
342 ;
343 Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
344 Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
345 Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
346
347 /* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
348 pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
349 /* Ignore the priority in the TPR; just deliver it when we tell it to. */
350 pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
351
352 /* Set IO and MSR bitmap addresses. */
353 pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
354 pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
355
356 /* No LBR virtualization. */
357 pVMCB->ctrl.u64LBRVirt = 0;
358
359 /** The ASID must start at 1; the host uses 0. */
360 pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
361
362 /** Setup the PAT msr (nested paging only) */
363 pVMCB->guest.u64GPAT = 0x0007040600070406ULL;
364 }
365 return rc;
366}
367
368
369/**
370 * Injects an event (trap or external interrupt)
371 *
372 * @param pVCpu The VMCPU to operate on.
373 * @param pVMCB SVM control block
374 * @param pCtx CPU Context
375 * @param pIntInfo SVM interrupt info
376 */
377inline void SVMR0InjectEvent(PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx, SVM_EVENT* pEvent)
378{
379#ifdef VBOX_WITH_STATISTICS
380 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
381#endif
382
383#ifdef VBOX_STRICT
384 if (pEvent->n.u8Vector == 0xE)
385 Log(("SVM: Inject int %d at %RGv error code=%02x CR2=%RGv intInfo=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode, (RTGCPTR)pCtx->cr2, pEvent->au64[0]));
386 else
387 if (pEvent->n.u8Vector < 0x20)
388 Log(("SVM: Inject int %d at %RGv error code=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode));
389 else
390 {
391 Log(("INJ-EI: %x at %RGv\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip));
392 Assert(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
393 Assert(pCtx->eflags.u32 & X86_EFL_IF);
394 }
395#endif
396
397 /* Set event injection state. */
398 pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
399}
400
401
402/**
403 * Checks for pending guest interrupts and injects them
404 *
405 * @returns VBox status code.
406 * @param pVM The VM to operate on.
407 * @param pVCpu The VM CPU to operate on.
408 * @param pVMCB SVM control block
409 * @param pCtx CPU Context
410 */
411static int SVMR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx)
412{
413 int rc;
414
415 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
416 if (pVCpu->hwaccm.s.Event.fPending)
417 {
418 SVM_EVENT Event;
419
420 Log(("Reinjecting event %08x %08x at %RGv\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip));
421 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
422 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
423 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
424
425 pVCpu->hwaccm.s.Event.fPending = false;
426 return VINF_SUCCESS;
427 }
428
429 /* If an active trap is already pending, then we must forward it first! */
430 if (!TRPMHasTrap(pVCpu))
431 {
432 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI))
433 {
434 SVM_EVENT Event;
435
436 Log(("CPU%d: injecting #NMI\n", pVCpu->idCpu));
437 Event.n.u8Vector = X86_XCPT_NMI;
438 Event.n.u1Valid = 1;
439 Event.n.u32ErrorCode = 0;
440 Event.n.u3Type = SVM_EVENT_NMI;
441
442 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
443 return VINF_SUCCESS;
444 }
445
446 /* @todo SMI interrupts. */
447
448 /* When external interrupts are pending, we should exit the VM when IF is set. */
449 if (VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
450 {
451 if ( !(pCtx->eflags.u32 & X86_EFL_IF)
452 || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
453 {
454 if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
455 {
456 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
457 LogFlow(("Enable irq window exit!\n"));
458 else
459 Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", (RTGCPTR)pCtx->rip));
460
461 /** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
462 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_VINTR;
463 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
464 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
465 }
466 }
467 else
468 {
469 uint8_t u8Interrupt;
470
471 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
472 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
473 if (RT_SUCCESS(rc))
474 {
475 rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
476 AssertRC(rc);
477 }
478 else
479 {
480 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
481 Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)));
482 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
483 /* Just continue */
484 }
485 }
486 }
487 }
488
489#ifdef VBOX_STRICT
490 if (TRPMHasTrap(pVCpu))
491 {
492 uint8_t u8Vector;
493 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
494 AssertRC(rc);
495 }
496#endif
497
498 if ( (pCtx->eflags.u32 & X86_EFL_IF)
499 && (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
500 && TRPMHasTrap(pVCpu)
501 )
502 {
503 uint8_t u8Vector;
504 int rc;
505 TRPMEVENT enmType;
506 SVM_EVENT Event;
507 RTGCUINT u32ErrorCode;
508
509 Event.au64[0] = 0;
510
511 /* If a new event is pending, then dispatch it now. */
512 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &u32ErrorCode, 0);
513 AssertRC(rc);
514 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
515 Assert(enmType != TRPM_SOFTWARE_INT);
516
517 /* Clear the pending trap. */
518 rc = TRPMResetTrap(pVCpu);
519 AssertRC(rc);
520
521 Event.n.u8Vector = u8Vector;
522 Event.n.u1Valid = 1;
523 Event.n.u32ErrorCode = u32ErrorCode;
524
525 if (enmType == TRPM_TRAP)
526 {
527 switch (u8Vector) {
528 case 8:
529 case 10:
530 case 11:
531 case 12:
532 case 13:
533 case 14:
534 case 17:
535 /* Valid error codes. */
536 Event.n.u1ErrorCodeValid = 1;
537 break;
538 default:
539 break;
540 }
541 if (u8Vector == X86_XCPT_NMI)
542 Event.n.u3Type = SVM_EVENT_NMI;
543 else
544 Event.n.u3Type = SVM_EVENT_EXCEPTION;
545 }
546 else
547 Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
548
549 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
550 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
551 } /* if (interrupts can be dispatched) */
552
553 return VINF_SUCCESS;
554}
555
556/**
557 * Save the host state
558 *
559 * @returns VBox status code.
560 * @param pVM The VM to operate on.
561 * @param pVCpu The VM CPU to operate on.
562 */
563VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
564{
565 NOREF(pVM);
566 NOREF(pVCpu);
567 /* Nothing to do here. */
568 return VINF_SUCCESS;
569}
570
571/**
572 * Loads the guest state
573 *
574 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
575 *
576 * @returns VBox status code.
577 * @param pVM The VM to operate on.
578 * @param pVCpu The VM CPU to operate on.
579 * @param pCtx Guest context
580 */
581VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
582{
583 RTGCUINTPTR val;
584 SVM_VMCB *pVMCB;
585
586 if (pVM == NULL)
587 return VERR_INVALID_PARAMETER;
588
589 /* Setup AMD SVM. */
590 Assert(pVM->hwaccm.s.svm.fSupported);
591
592 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
593 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
594
595 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
596 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
597 {
598 SVM_WRITE_SELREG(CS, cs);
599 SVM_WRITE_SELREG(SS, ss);
600 SVM_WRITE_SELREG(DS, ds);
601 SVM_WRITE_SELREG(ES, es);
602 SVM_WRITE_SELREG(FS, fs);
603 SVM_WRITE_SELREG(GS, gs);
604 }
605
606 /* Guest CPU context: LDTR. */
607 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
608 {
609 SVM_WRITE_SELREG(LDTR, ldtr);
610 }
611
612 /* Guest CPU context: TR. */
613 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
614 {
615 SVM_WRITE_SELREG(TR, tr);
616 }
617
618 /* Guest CPU context: GDTR. */
619 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
620 {
621 pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
622 pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
623 }
624
625 /* Guest CPU context: IDTR. */
626 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
627 {
628 pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
629 pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
630 }
631
632 /*
633 * Sysenter MSRs (unconditional)
634 */
635 pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
636 pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
637 pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
638
639 /* Control registers */
640 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
641 {
642 val = pCtx->cr0;
643 if (!CPUMIsGuestFPUStateActive(pVCpu))
644 {
645 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
646 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
647 }
648 else
649 {
650 /** @todo check if we support the old style mess correctly. */
651 if (!(val & X86_CR0_NE))
652 {
653 Log(("Forcing X86_CR0_NE!!!\n"));
654
655 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
656 if (!pVCpu->hwaccm.s.fFPUOldStyleOverride)
657 {
658 pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_MF);
659 pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
660 }
661 }
662 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
663 }
664 /* Always enable caching. */
665 val &= ~(X86_CR0_CD|X86_CR0_NW);
666
667 /* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
668 /* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
669 if (!pVM->hwaccm.s.fNestedPaging)
670 {
671 val |= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
672 val |= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
673 }
674 pVMCB->guest.u64CR0 = val;
675 }
676 /* CR2 as well */
677 pVMCB->guest.u64CR2 = pCtx->cr2;
678
679 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
680 {
681 /* Save our shadow CR3 register. */
682 if (pVM->hwaccm.s.fNestedPaging)
683 {
684 PGMMODE enmShwPagingMode;
685
686#if HC_ARCH_BITS == 32
687 if (CPUMIsGuestInLongModeEx(pCtx))
688 enmShwPagingMode = PGMMODE_AMD64_NX;
689 else
690#endif
691 enmShwPagingMode = PGMGetHostMode(pVM);
692
693 pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
694 Assert(pVMCB->ctrl.u64NestedPagingCR3);
695 pVMCB->guest.u64CR3 = pCtx->cr3;
696 }
697 else
698 {
699 pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
700 Assert(pVMCB->guest.u64CR3 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
701 }
702 }
703
704 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
705 {
706 val = pCtx->cr4;
707 if (!pVM->hwaccm.s.fNestedPaging)
708 {
709 switch(pVCpu->hwaccm.s.enmShadowMode)
710 {
711 case PGMMODE_REAL:
712 case PGMMODE_PROTECTED: /* Protected mode, no paging. */
713 AssertFailed();
714 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
715
716 case PGMMODE_32_BIT: /* 32-bit paging. */
717 val &= ~X86_CR4_PAE;
718 break;
719
720 case PGMMODE_PAE: /* PAE paging. */
721 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
722 /** @todo use normal 32 bits paging */
723 val |= X86_CR4_PAE;
724 break;
725
726 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
727 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
728#ifdef VBOX_ENABLE_64_BITS_GUESTS
729 break;
730#else
731 AssertFailed();
732 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
733#endif
734
735 default: /* shut up gcc */
736 AssertFailed();
737 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
738 }
739 }
740 pVMCB->guest.u64CR4 = val;
741 }
742
743 /* Debug registers. */
744 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
745 {
746 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
747 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
748
749 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
750 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
751 pCtx->dr[7] |= 0x400; /* must be one */
752
753 pVMCB->guest.u64DR7 = pCtx->dr[7];
754 pVMCB->guest.u64DR6 = pCtx->dr[6];
755
756#ifdef DEBUG
757 /* Sync the hypervisor debug state now if any breakpoint is armed. */
758 if ( CPUMGetHyperDR7(pVCpu) & (X86_DR7_ENABLED_MASK|X86_DR7_GD)
759 && !CPUMIsHyperDebugStateActive(pVCpu)
760 && !DBGFIsStepping(pVCpu))
761 {
762 /* Save the host and load the hypervisor debug state. */
763 int rc = CPUMR0LoadHyperDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
764 AssertRC(rc);
765
766 /* DRx intercepts remain enabled. */
767
768 /* Override dr6 & dr7 with the hypervisor values. */
769 pVMCB->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
770 pVMCB->guest.u64DR6 = CPUMGetHyperDR6(pVCpu);
771 }
772 else
773#endif
774 /* Sync the debug state now if any breakpoint is armed. */
775 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
776 && !CPUMIsGuestDebugStateActive(pVCpu)
777 && !DBGFIsStepping(pVCpu))
778 {
779 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
780
781 /* Disable drx move intercepts. */
782 pVMCB->ctrl.u16InterceptRdDRx = 0;
783 pVMCB->ctrl.u16InterceptWrDRx = 0;
784
785 /* Save the host and load the guest debug state. */
786 int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
787 AssertRC(rc);
788 }
789 }
790
791 /* EIP, ESP and EFLAGS */
792 pVMCB->guest.u64RIP = pCtx->rip;
793 pVMCB->guest.u64RSP = pCtx->rsp;
794 pVMCB->guest.u64RFlags = pCtx->eflags.u32;
795
796 /* Set CPL */
797 pVMCB->guest.u8CPL = pCtx->csHid.Attr.n.u2Dpl;
798
799 /* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
800 pVMCB->guest.u64RAX = pCtx->rax;
801
802 /* vmrun will fail without MSR_K6_EFER_SVME. */
803 pVMCB->guest.u64EFER = pCtx->msrEFER | MSR_K6_EFER_SVME;
804
805 /* 64 bits guest mode? */
806 if (CPUMIsGuestInLongModeEx(pCtx))
807 {
808#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
809 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
810#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
811 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
812#else
813# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
814 if (!pVM->hwaccm.s.fAllow64BitGuests)
815 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
816# endif
817 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun64;
818#endif
819 /* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
820 pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
821 pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
822 }
823 else
824 {
825 /* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
826 pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
827
828 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun;
829 }
830
831 /* TSC offset. */
832 if (TMCpuTickCanUseRealTSC(pVCpu, &pVMCB->ctrl.u64TSCOffset))
833 {
834 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
835 pVMCB->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
836 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
837 }
838 else
839 {
840 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
841 pVMCB->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;
842 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
843 }
844
845 /* Sync the various msrs for 64 bits mode. */
846 pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
847 pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
848 pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
849 pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
850 pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
851
852#ifdef DEBUG
853 /* Intercept X86_XCPT_DB if stepping is enabled */
854 if ( DBGFIsStepping(pVCpu)
855 || CPUMIsHyperDebugStateActive(pVCpu))
856 pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_DB);
857 else
858 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_DB);
859#endif
860
861 /* Done. */
862 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
863
864 return VINF_SUCCESS;
865}
866
867
868/**
869 * Runs guest code in an AMD-V VM.
870 *
871 * @returns VBox status code.
872 * @param pVM The VM to operate on.
873 * @param pVCpu The VM CPU to operate on.
874 * @param pCtx Guest context
875 */
876VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
877{
878 int rc = VINF_SUCCESS;
879 uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
880 SVM_VMCB *pVMCB;
881 bool fSyncTPR = false;
882 unsigned cResume = 0;
883 uint8_t u8LastTPR;
884 PHWACCM_CPUINFO pCpu = 0;
885 RTCCUINTREG uOldEFlags = ~(RTCCUINTREG)0;
886#ifdef VBOX_STRICT
887 RTCPUID idCpuCheck;
888#endif
889#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
890 uint64_t u64LastTime = RTTimeMilliTS();
891#endif
892
893 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
894
895 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
896 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
897
898 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
899 */
900ResumeExecution:
901 Assert(!HWACCMR0SuspendPending());
902
903 /* Safety precaution; looping for too long here can have a very bad effect on the host */
904 if (RT_UNLIKELY(++cResume > pVM->hwaccm.s.cMaxResumeLoops))
905 {
906 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
907 rc = VINF_EM_RAW_INTERRUPT;
908 goto end;
909 }
910
911 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
912 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
913 {
914 Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
915 if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
916 {
917 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
918 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
919 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
920 * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
921 */
922 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
923 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
924 pVMCB->ctrl.u64IntShadow = 0;
925 }
926 }
927 else
928 {
929 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
930 pVMCB->ctrl.u64IntShadow = 0;
931 }
932
933#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
934 if (RT_UNLIKELY(cResume & 0xf) == 0)
935 {
936 uint64_t u64CurTime = RTTimeMilliTS();
937
938 if (RT_UNLIKELY(u64CurTime > u64LastTime))
939 {
940 u64LastTime = u64CurTime;
941 TMTimerPollVoid(pVM, pVCpu);
942 }
943 }
944#endif
945
946 /* Check for pending actions that force us to go back to ring 3. */
947#ifdef DEBUG
948 /* Intercept X86_XCPT_DB if stepping is enabled */
949 if (!DBGFIsStepping(pVCpu))
950#endif
951 {
952 if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK)
953 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
954 {
955 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
956 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
957 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
958 rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
959 goto end;
960 }
961 }
962
963 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
964 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
965 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
966 {
967 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
968 rc = VINF_EM_PENDING_REQUEST;
969 goto end;
970 }
971
972#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
973 /*
974 * Exit to ring-3 preemption/work is pending.
975 *
976 * Interrupts are disabled before the call to make sure we don't miss any interrupt
977 * that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
978 * further down, but SVMR0CheckPendingInterrupt makes that impossible.)
979 *
980 * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
981 * shootdowns rely on this.
982 */
983 uOldEFlags = ASMIntDisableFlags();
984 if (RTThreadPreemptIsPending(NIL_RTTHREAD))
985 {
986 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);
987 rc = VINF_EM_RAW_INTERRUPT;
988 goto end;
989 }
990 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
991#endif
992
993 /* When external interrupts are pending, we should exit the VM when IF is set. */
994 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
995 rc = SVMR0CheckPendingInterrupt(pVM, pVCpu, pVMCB, pCtx);
996 if (RT_FAILURE(rc))
997 {
998 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
999 goto end;
1000 }
1001
1002 /* TPR caching using CR8 is only available in 64 bits mode or with 32 bits guests when X86_CPUID_AMD_FEATURE_ECX_CR8L is supported. */
1003 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!!
1004 * @todo query and update the TPR only when it could have been changed (mmio access)
1005 */
1006 if (pVM->hwaccm.s.fHasIoApic)
1007 {
1008 bool fPending;
1009
1010 /* TPR caching in CR8 */
1011 int rc = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);
1012 AssertRC(rc);
1013 pVMCB->ctrl.IntCtrl.n.u8VTPR = (u8LastTPR >> 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1014
1015 if (fPending)
1016 {
1017 /* A TPR change could activate a pending interrupt, so catch cr8 writes. */
1018 pVMCB->ctrl.u16InterceptWrCRx |= RT_BIT(8);
1019 }
1020 else
1021 /* No interrupts are pending, so we don't need to be explicitely notified.
1022 * There are enough world switches for detecting pending interrupts.
1023 */
1024 pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1025
1026 fSyncTPR = !fPending;
1027 }
1028
1029 /* All done! Let's start VM execution. */
1030 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, x);
1031
1032 /* Enable nested paging if necessary (disabled each time after #VMEXIT). */
1033 pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
1034
1035#ifdef LOG_ENABLED
1036 pCpu = HWACCMR0GetCurrentCpu();
1037 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1038 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1039 {
1040 if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
1041 Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
1042 else
1043 Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1044 }
1045 if (pCpu->fFlushTLB)
1046 Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
1047#endif
1048
1049 /*
1050 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1051 * (until the actual world switch)
1052 */
1053#ifdef VBOX_STRICT
1054 idCpuCheck = RTMpCpuId();
1055#endif
1056 VMMR0LogFlushDisable(pVCpu);
1057
1058 /* Load the guest state; *must* be here as it sets up the shadow cr0 for lazy fpu syncing! */
1059 rc = SVMR0LoadGuestState(pVM, pVCpu, pCtx);
1060 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1061 {
1062 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1063 VMMR0LogFlushEnable(pVCpu);
1064 goto end;
1065 }
1066
1067#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1068 /* Disable interrupts to make sure a poke will interrupt execution.
1069 * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
1070 */
1071 uOldEFlags = ASMIntDisableFlags();
1072 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1073#endif
1074
1075 pCpu = HWACCMR0GetCurrentCpu();
1076 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1077 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1078 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1079 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1080 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1081 {
1082 /* Force a TLB flush on VM entry. */
1083 pVCpu->hwaccm.s.fForceTLBFlush = true;
1084 }
1085 else
1086 Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1087
1088 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1089
1090 /* Check for tlb shootdown flushes. */
1091 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1092 pVCpu->hwaccm.s.fForceTLBFlush = true;
1093
1094 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1095 if ( pVCpu->hwaccm.s.fForceTLBFlush
1096 && !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
1097 {
1098 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1099 || pCpu->fFlushTLB)
1100 {
1101 pCpu->fFlushTLB = false;
1102 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1103 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
1104 pCpu->cTLBFlushes++;
1105 }
1106 else
1107 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1108
1109 pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1110 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1111 }
1112 else
1113 {
1114 Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1115
1116 /* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
1117 if (!pCpu->uCurrentASID || !pVCpu->hwaccm.s.uCurrentASID)
1118 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
1119
1120 Assert(!pVM->hwaccm.s.svm.fAlwaysFlushTLB || pVCpu->hwaccm.s.fForceTLBFlush);
1121 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVCpu->hwaccm.s.fForceTLBFlush;
1122
1123 if ( !pVM->hwaccm.s.svm.fAlwaysFlushTLB
1124 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1125 {
1126 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1127 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1128 for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1129 SVMR0InvlpgA(pVCpu->hwaccm.s.TlbShootdown.aPages[i], pVMCB->ctrl.TLBCtrl.n.u32ASID);
1130 }
1131 }
1132 pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1133 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1134
1135 AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1136 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1137 AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1138 pVMCB->ctrl.TLBCtrl.n.u32ASID = pVCpu->hwaccm.s.uCurrentASID;
1139
1140#ifdef VBOX_WITH_STATISTICS
1141 if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
1142 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1143 else
1144 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1145#endif
1146
1147 /* In case we execute a goto ResumeExecution later on. */
1148 pVCpu->hwaccm.s.fResumeVM = true;
1149 pVCpu->hwaccm.s.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
1150
1151 Assert(sizeof(pVCpu->hwaccm.s.svm.pVMCBPhys) == 8);
1152 Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
1153 Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
1154 Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
1155 Assert(pVMCB->ctrl.u64LBRVirt == 0);
1156
1157#ifdef VBOX_STRICT
1158 Assert(idCpuCheck == RTMpCpuId());
1159#endif
1160 TMNotifyStartOfExecution(pVCpu);
1161#ifdef VBOX_WITH_KERNEL_USING_XMM
1162 hwaccmR0SVMRunWrapXMM(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu, pVCpu->hwaccm.s.svm.pfnVMRun);
1163#else
1164 pVCpu->hwaccm.s.svm.pfnVMRun(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu);
1165#endif
1166 TMNotifyEndOfExecution(pVCpu);
1167 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
1168 ASMSetFlags(uOldEFlags);
1169#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1170 uOldEFlags = ~(RTCCUINTREG)0;
1171#endif
1172 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, x);
1173
1174 /*
1175 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1176 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1177 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1178 */
1179
1180 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, x);
1181
1182 /* Reason for the VM exit */
1183 exitCode = pVMCB->ctrl.u64ExitCode;
1184
1185 if (RT_UNLIKELY(exitCode == (uint64_t)SVM_EXIT_INVALID)) /* Invalid guest state. */
1186 {
1187 HWACCMDumpRegs(pVM, pVCpu, pCtx);
1188#ifdef DEBUG
1189 Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
1190 Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
1191 Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
1192 Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
1193 Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
1194 Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
1195 Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
1196 Log(("ctrl.u64IOPMPhysAddr %RX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
1197 Log(("ctrl.u64MSRPMPhysAddr %RX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
1198 Log(("ctrl.u64TSCOffset %RX64\n", pVMCB->ctrl.u64TSCOffset));
1199
1200 Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
1201 Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
1202 Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
1203 Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
1204
1205 Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
1206 Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
1207 Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
1208 Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
1209 Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
1210 Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
1211 Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
1212 Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
1213 Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
1214 Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
1215
1216 Log(("ctrl.u64IntShadow %RX64\n", pVMCB->ctrl.u64IntShadow));
1217 Log(("ctrl.u64ExitCode %RX64\n", pVMCB->ctrl.u64ExitCode));
1218 Log(("ctrl.u64ExitInfo1 %RX64\n", pVMCB->ctrl.u64ExitInfo1));
1219 Log(("ctrl.u64ExitInfo2 %RX64\n", pVMCB->ctrl.u64ExitInfo2));
1220 Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
1221 Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
1222 Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
1223 Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
1224 Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
1225 Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
1226 Log(("ctrl.NestedPaging %RX64\n", pVMCB->ctrl.NestedPaging.au64));
1227 Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
1228 Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
1229 Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
1230 Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
1231 Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
1232 Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
1233
1234 Log(("ctrl.u64NestedPagingCR3 %RX64\n", pVMCB->ctrl.u64NestedPagingCR3));
1235 Log(("ctrl.u64LBRVirt %RX64\n", pVMCB->ctrl.u64LBRVirt));
1236
1237 Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
1238 Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1239 Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1240 Log(("guest.CS.u64Base %RX64\n", pVMCB->guest.CS.u64Base));
1241 Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1242 Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1243 Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1244 Log(("guest.DS.u64Base %RX64\n", pVMCB->guest.DS.u64Base));
1245 Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1246 Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1247 Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1248 Log(("guest.ES.u64Base %RX64\n", pVMCB->guest.ES.u64Base));
1249 Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1250 Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1251 Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1252 Log(("guest.FS.u64Base %RX64\n", pVMCB->guest.FS.u64Base));
1253 Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1254 Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1255 Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1256 Log(("guest.GS.u64Base %RX64\n", pVMCB->guest.GS.u64Base));
1257
1258 Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1259 Log(("guest.GDTR.u64Base %RX64\n", pVMCB->guest.GDTR.u64Base));
1260
1261 Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1262 Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1263 Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1264 Log(("guest.LDTR.u64Base %RX64\n", pVMCB->guest.LDTR.u64Base));
1265
1266 Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1267 Log(("guest.IDTR.u64Base %RX64\n", pVMCB->guest.IDTR.u64Base));
1268
1269 Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1270 Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1271 Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1272 Log(("guest.TR.u64Base %RX64\n", pVMCB->guest.TR.u64Base));
1273
1274 Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1275 Log(("guest.u64CR0 %RX64\n", pVMCB->guest.u64CR0));
1276 Log(("guest.u64CR2 %RX64\n", pVMCB->guest.u64CR2));
1277 Log(("guest.u64CR3 %RX64\n", pVMCB->guest.u64CR3));
1278 Log(("guest.u64CR4 %RX64\n", pVMCB->guest.u64CR4));
1279 Log(("guest.u64DR6 %RX64\n", pVMCB->guest.u64DR6));
1280 Log(("guest.u64DR7 %RX64\n", pVMCB->guest.u64DR7));
1281
1282 Log(("guest.u64RIP %RX64\n", pVMCB->guest.u64RIP));
1283 Log(("guest.u64RSP %RX64\n", pVMCB->guest.u64RSP));
1284 Log(("guest.u64RAX %RX64\n", pVMCB->guest.u64RAX));
1285 Log(("guest.u64RFlags %RX64\n", pVMCB->guest.u64RFlags));
1286
1287 Log(("guest.u64SysEnterCS %RX64\n", pVMCB->guest.u64SysEnterCS));
1288 Log(("guest.u64SysEnterEIP %RX64\n", pVMCB->guest.u64SysEnterEIP));
1289 Log(("guest.u64SysEnterESP %RX64\n", pVMCB->guest.u64SysEnterESP));
1290
1291 Log(("guest.u64EFER %RX64\n", pVMCB->guest.u64EFER));
1292 Log(("guest.u64STAR %RX64\n", pVMCB->guest.u64STAR));
1293 Log(("guest.u64LSTAR %RX64\n", pVMCB->guest.u64LSTAR));
1294 Log(("guest.u64CSTAR %RX64\n", pVMCB->guest.u64CSTAR));
1295 Log(("guest.u64SFMASK %RX64\n", pVMCB->guest.u64SFMASK));
1296 Log(("guest.u64KernelGSBase %RX64\n", pVMCB->guest.u64KernelGSBase));
1297 Log(("guest.u64GPAT %RX64\n", pVMCB->guest.u64GPAT));
1298 Log(("guest.u64DBGCTL %RX64\n", pVMCB->guest.u64DBGCTL));
1299 Log(("guest.u64BR_FROM %RX64\n", pVMCB->guest.u64BR_FROM));
1300 Log(("guest.u64BR_TO %RX64\n", pVMCB->guest.u64BR_TO));
1301 Log(("guest.u64LASTEXCPFROM %RX64\n", pVMCB->guest.u64LASTEXCPFROM));
1302 Log(("guest.u64LASTEXCPTO %RX64\n", pVMCB->guest.u64LASTEXCPTO));
1303
1304#endif
1305 rc = VERR_SVM_UNABLE_TO_START_VM;
1306 VMMR0LogFlushEnable(pVCpu);
1307 goto end;
1308 }
1309
1310 /* Let's first sync back eip, esp, and eflags. */
1311 pCtx->rip = pVMCB->guest.u64RIP;
1312 pCtx->rsp = pVMCB->guest.u64RSP;
1313 pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1314 /* eax is saved/restore across the vmrun instruction */
1315 pCtx->rax = pVMCB->guest.u64RAX;
1316
1317 pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
1318
1319 /* Can be updated behind our back in the nested paging case. */
1320 pCtx->cr2 = pVMCB->guest.u64CR2;
1321
1322 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1323 SVM_READ_SELREG(SS, ss);
1324 SVM_READ_SELREG(CS, cs);
1325 SVM_READ_SELREG(DS, ds);
1326 SVM_READ_SELREG(ES, es);
1327 SVM_READ_SELREG(FS, fs);
1328 SVM_READ_SELREG(GS, gs);
1329
1330 /*
1331 * System MSRs
1332 */
1333 pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1334 pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1335 pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1336
1337 /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1338 SVM_READ_SELREG(LDTR, ldtr);
1339 SVM_READ_SELREG(TR, tr);
1340
1341 pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1342 pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1343
1344 pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1345 pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1346
1347 /* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1348 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1349 if ( pVM->hwaccm.s.fNestedPaging
1350 && pCtx->cr3 != pVMCB->guest.u64CR3)
1351 {
1352 CPUMSetGuestCR3(pVCpu, pVMCB->guest.u64CR3);
1353 PGMUpdateCR3(pVCpu, pVMCB->guest.u64CR3);
1354 }
1355
1356 /* Note! NOW IT'S SAFE FOR LOGGING! */
1357 VMMR0LogFlushEnable(pVCpu);
1358
1359 /* Take care of instruction fusing (sti, mov ss) (see 15.20.5 Interrupt Shadows) */
1360 if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1361 {
1362 Log(("uInterruptState %x rip=%RGv\n", pVMCB->ctrl.u64IntShadow, (RTGCPTR)pCtx->rip));
1363 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
1364 }
1365 else
1366 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1367
1368 Log2(("exitCode = %x\n", exitCode));
1369
1370 /* Sync back DR6 as it could have been changed by hitting breakpoints. */
1371 pCtx->dr[6] = pVMCB->guest.u64DR6;
1372 /* DR7.GD can be cleared by debug exceptions, so sync it back as well. */
1373 pCtx->dr[7] = pVMCB->guest.u64DR7;
1374
1375 /* Check if an injected event was interrupted prematurely. */
1376 pVCpu->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1377 if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1378 && pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1379 {
1380 Log(("Pending inject %RX64 at %RGv exit=%08x\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitCode));
1381
1382#ifdef LOG_ENABLED
1383 SVM_EVENT Event;
1384 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
1385
1386 if ( exitCode == SVM_EXIT_EXCEPTION_E
1387 && Event.n.u8Vector == 0xE)
1388 {
1389 Log(("Double fault!\n"));
1390 }
1391#endif
1392
1393 pVCpu->hwaccm.s.Event.fPending = true;
1394 /* Error code present? (redundant) */
1395 if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1396 pVCpu->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1397 else
1398 pVCpu->hwaccm.s.Event.errCode = 0;
1399 }
1400#ifdef VBOX_WITH_STATISTICS
1401 if (exitCode == SVM_EXIT_NPF)
1402 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
1403 else
1404 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1405#endif
1406
1407 /* Sync back the TPR if it was changed. */
1408 if ( fSyncTPR
1409 && (u8LastTPR >> 4) != pVMCB->ctrl.IntCtrl.n.u8VTPR)
1410 {
1411 rc = PDMApicSetTPR(pVCpu, pVMCB->ctrl.IntCtrl.n.u8VTPR << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1412 AssertRC(rc);
1413 }
1414
1415 /* Deal with the reason of the VM-exit. */
1416 switch (exitCode)
1417 {
1418 case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1419 case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1420 case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1421 case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1422 case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1423 case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1424 case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1425 case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1426 {
1427 /* Pending trap. */
1428 SVM_EVENT Event;
1429 uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1430
1431 Log2(("Hardware/software interrupt %d\n", vector));
1432 switch (vector)
1433 {
1434 case X86_XCPT_DB:
1435 {
1436 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
1437
1438 /* Note that we don't support guest and host-initiated debugging at the same time. */
1439 Assert(DBGFIsStepping(pVCpu) || CPUMIsHyperDebugStateActive(pVCpu));
1440
1441 rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
1442 if (rc == VINF_EM_RAW_GUEST_TRAP)
1443 {
1444 Log(("Trap %x (debug) at %016RX64\n", vector, pCtx->rip));
1445
1446 /* Reinject the exception. */
1447 Event.au64[0] = 0;
1448 Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
1449 Event.n.u1Valid = 1;
1450 Event.n.u8Vector = X86_XCPT_DB;
1451
1452 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1453
1454 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1455 goto ResumeExecution;
1456 }
1457 /* Return to ring 3 to deal with the debug exit code. */
1458 Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, rc));
1459 break;
1460 }
1461
1462 case X86_XCPT_NM:
1463 {
1464 Log(("#NM fault at %RGv\n", (RTGCPTR)pCtx->rip));
1465
1466 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1467 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1468 rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
1469 if (rc == VINF_SUCCESS)
1470 {
1471 Assert(CPUMIsGuestFPUStateActive(pVCpu));
1472 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
1473
1474 /* Continue execution. */
1475 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1476 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1477
1478 goto ResumeExecution;
1479 }
1480
1481 Log(("Forward #NM fault to the guest\n"));
1482 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
1483
1484 Event.au64[0] = 0;
1485 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1486 Event.n.u1Valid = 1;
1487 Event.n.u8Vector = X86_XCPT_NM;
1488
1489 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1490 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1491 goto ResumeExecution;
1492 }
1493
1494 case X86_XCPT_PF: /* Page fault */
1495 {
1496 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1497 RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1498
1499#ifdef DEBUG
1500 if (pVM->hwaccm.s.fNestedPaging)
1501 { /* A genuine pagefault.
1502 * Forward the trap to the guest by injecting the exception and resuming execution.
1503 */
1504 Log(("Guest page fault at %04X:%RGv cr2=%RGv error code %x rsp=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
1505 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1506
1507 /* Now we must update CR2. */
1508 pCtx->cr2 = uFaultAddress;
1509
1510 Event.au64[0] = 0;
1511 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1512 Event.n.u1Valid = 1;
1513 Event.n.u8Vector = X86_XCPT_PF;
1514 Event.n.u1ErrorCodeValid = 1;
1515 Event.n.u32ErrorCode = errCode;
1516
1517 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1518
1519 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1520 goto ResumeExecution;
1521 }
1522#endif
1523 Assert(!pVM->hwaccm.s.fNestedPaging);
1524
1525#if 0
1526 /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1527 if ( (uFaultAddress & 0xfff) == 0x080
1528 && pVM->hwaccm.s.fHasIoApic
1529 && !(errCode & X86_TRAP_PF_P) /* not present */
1530 && !CPUMIsGuestInLongModeEx(pCtx))
1531 {
1532 RTGCPHYS GCPhysApicBase, GCPhys;
1533 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1534 GCPhysApicBase &= PAGE_BASE_GC_MASK;
1535
1536 rc = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL, &GCPhys);
1537 if ( rc == VINF_SUCCESS
1538 && GCPhys == GCPhysApicBase)
1539 {
1540 Log(("Replace TPR access at %RGv\n", pCtx->rip));
1541
1542 DISCPUSTATE Cpu;
1543 unsigned cbOp;
1544 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);
1545 AssertRC(rc);
1546 if ( rc == VINF_SUCCESS
1547 && Cpu.pCurInstr->opcode == OP_MOV
1548 && (cbOp == 5 || cbOp == 6))
1549 {
1550 uint8_t szInstr[15];
1551 if ( (errCode & X86_TRAP_PF_RW)
1552 && Cpu.param1.disp32 == (uint32_t)uFaultAddress
1553 && Cpu.param2.flags == USE_REG_GEN32)
1554 {
1555 /* 0xF0, 0x0F, 0x22, 0xC0 = mov cr8, eax */
1556 szInstr[0] = 0xF0;
1557 szInstr[1] = 0x0F;
1558 szInstr[2] = 0x22;
1559 szInstr[3] = 0xC0 | Cpu.param2.base.reg_gen;
1560 for (unsigned i = 4; i < cbOp; i++)
1561 szInstr[i] = 0x90; /* nop */
1562
1563 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, cbOp);
1564 AssertRC(rc);
1565
1566 Log(("Acceptable write candidate!\n"));
1567 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1568 goto ResumeExecution;
1569 }
1570 else
1571 if ( Cpu.param2.disp32 == (uint32_t)uFaultAddress
1572 && Cpu.param1.flags == USE_REG_GEN32)
1573 {
1574 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1575 szInstr[0] = 0xF0;
1576 szInstr[1] = 0x0F;
1577 szInstr[2] = 0x20;
1578 szInstr[3] = 0xC0 | Cpu.param1.base.reg_gen;
1579 for (unsigned i = 4; i < cbOp; i++)
1580 szInstr[i] = 0x90; /* nop */
1581
1582 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, cbOp);
1583 AssertRC(rc);
1584
1585 Log(("Acceptable read candidate!\n"));
1586 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1587 goto ResumeExecution;
1588 }
1589 }
1590 }
1591 }
1592#endif
1593
1594 Log2(("Page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1595 /* Exit qualification contains the linear address of the page fault. */
1596 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1597 TRPMSetErrorCode(pVCpu, errCode);
1598 TRPMSetFaultAddress(pVCpu, uFaultAddress);
1599
1600 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1601 rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1602 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1603 if (rc == VINF_SUCCESS)
1604 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1605 Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1606 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1607
1608 TRPMResetTrap(pVCpu);
1609
1610 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1611 goto ResumeExecution;
1612 }
1613 else
1614 if (rc == VINF_EM_RAW_GUEST_TRAP)
1615 { /* A genuine pagefault.
1616 * Forward the trap to the guest by injecting the exception and resuming execution.
1617 */
1618 Log2(("Forward page fault to the guest\n"));
1619 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1620 /* The error code might have been changed. */
1621 errCode = TRPMGetErrorCode(pVCpu);
1622
1623 TRPMResetTrap(pVCpu);
1624
1625 /* Now we must update CR2. */
1626 pCtx->cr2 = uFaultAddress;
1627
1628 Event.au64[0] = 0;
1629 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1630 Event.n.u1Valid = 1;
1631 Event.n.u8Vector = X86_XCPT_PF;
1632 Event.n.u1ErrorCodeValid = 1;
1633 Event.n.u32ErrorCode = errCode;
1634
1635 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1636
1637 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1638 goto ResumeExecution;
1639 }
1640#ifdef VBOX_STRICT
1641 if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
1642 LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
1643#endif
1644 /* Need to go back to the recompiler to emulate the instruction. */
1645 TRPMResetTrap(pVCpu);
1646 break;
1647 }
1648
1649 case X86_XCPT_MF: /* Floating point exception. */
1650 {
1651 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
1652 if (!(pCtx->cr0 & X86_CR0_NE))
1653 {
1654 /* old style FPU error reporting needs some extra work. */
1655 /** @todo don't fall back to the recompiler, but do it manually. */
1656 rc = VINF_EM_RAW_EMULATE_INSTR;
1657 break;
1658 }
1659 Log(("Trap %x at %RGv\n", vector, (RTGCPTR)pCtx->rip));
1660
1661 Event.au64[0] = 0;
1662 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1663 Event.n.u1Valid = 1;
1664 Event.n.u8Vector = X86_XCPT_MF;
1665
1666 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1667
1668 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1669 goto ResumeExecution;
1670 }
1671
1672#ifdef VBOX_STRICT
1673 case X86_XCPT_GP: /* General protection failure exception.*/
1674 case X86_XCPT_UD: /* Unknown opcode exception. */
1675 case X86_XCPT_DE: /* Divide error. */
1676 case X86_XCPT_SS: /* Stack segment exception. */
1677 case X86_XCPT_NP: /* Segment not present exception. */
1678 {
1679 Event.au64[0] = 0;
1680 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1681 Event.n.u1Valid = 1;
1682 Event.n.u8Vector = vector;
1683
1684 switch(vector)
1685 {
1686 case X86_XCPT_GP:
1687 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
1688 Event.n.u1ErrorCodeValid = 1;
1689 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1690 break;
1691 case X86_XCPT_DE:
1692 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
1693 break;
1694 case X86_XCPT_UD:
1695 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
1696 break;
1697 case X86_XCPT_SS:
1698 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
1699 Event.n.u1ErrorCodeValid = 1;
1700 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1701 break;
1702 case X86_XCPT_NP:
1703 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
1704 Event.n.u1ErrorCodeValid = 1;
1705 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1706 break;
1707 }
1708 Log(("Trap %x at %04x:%RGv esi=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->esi));
1709 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1710
1711 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1712 goto ResumeExecution;
1713 }
1714#endif
1715 default:
1716 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1717 rc = VERR_EM_INTERNAL_ERROR;
1718 break;
1719
1720 } /* switch (vector) */
1721 break;
1722 }
1723
1724 case SVM_EXIT_NPF:
1725 {
1726 /* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1727 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1728 RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1729 PGMMODE enmShwPagingMode;
1730
1731 Assert(pVM->hwaccm.s.fNestedPaging);
1732 LogFlow(("Nested page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1733
1734#if 0
1735 /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1736 if ( (uFaultAddress & 0xfff) == 0x080
1737 && pVM->hwaccm.s.fHasIoApic
1738 && !(errCode & X86_TRAP_PF_P) /* not present */
1739 && CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
1740 && !CPUMIsGuestInLongModeEx(pCtx))
1741 {
1742 RTGCPHYS GCPhysApicBase;
1743 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1744 GCPhysApicBase &= PAGE_BASE_GC_MASK;
1745
1746 if (uFaultAddress == GCPhysApicBase + 0x80)
1747 {
1748 rc = svmR0ReplaceTprInstr(pVM, pVCpu, pCtx);
1749 if (rc == VINF_SUCCESS)
1750 {
1751 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1752 goto ResumeExecution;
1753 }
1754
1755 rc = IOMMMIOPhysHandler(pVM, errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1756 if (rc == VINF_SUCCESS)
1757 {
1758 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1759 goto ResumeExecution; /* rip already updated */
1760 }
1761 }
1762 }
1763#endif
1764
1765 /* Exit qualification contains the linear address of the page fault. */
1766 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1767 TRPMSetErrorCode(pVCpu, errCode);
1768 TRPMSetFaultAddress(pVCpu, uFaultAddress);
1769
1770 /* Handle the pagefault trap for the nested shadow table. */
1771#if HC_ARCH_BITS == 32
1772 if (CPUMIsGuestInLongModeEx(pCtx))
1773 enmShwPagingMode = PGMMODE_AMD64_NX;
1774 else
1775#endif
1776 enmShwPagingMode = PGMGetHostMode(pVM);
1777
1778 rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmShwPagingMode, errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1779 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1780 if (rc == VINF_SUCCESS)
1781 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1782 Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1783 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1784
1785 TRPMResetTrap(pVCpu);
1786
1787 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1788 goto ResumeExecution;
1789 }
1790
1791#ifdef VBOX_STRICT
1792 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1793 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
1794#endif
1795 /* Need to go back to the recompiler to emulate the instruction. */
1796 TRPMResetTrap(pVCpu);
1797 break;
1798 }
1799
1800 case SVM_EXIT_VINTR:
1801 /* A virtual interrupt is about to be delivered, which means IF=1. */
1802 Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1803 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1804 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1805 goto ResumeExecution;
1806
1807 case SVM_EXIT_FERR_FREEZE:
1808 case SVM_EXIT_INTR:
1809 case SVM_EXIT_NMI:
1810 case SVM_EXIT_SMI:
1811 case SVM_EXIT_INIT:
1812 /* External interrupt; leave to allow it to be dispatched again. */
1813 rc = VINF_EM_RAW_INTERRUPT;
1814 break;
1815
1816 case SVM_EXIT_WBINVD:
1817 case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1818 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
1819 /* Skip instruction and continue directly. */
1820 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1821 /* Continue execution.*/
1822 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1823 goto ResumeExecution;
1824
1825 case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1826 {
1827 Log2(("SVM: Cpuid at %RGv for %x\n", (RTGCPTR)pCtx->rip, pCtx->eax));
1828 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
1829 rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1830 if (rc == VINF_SUCCESS)
1831 {
1832 /* Update EIP and continue execution. */
1833 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1834 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1835 goto ResumeExecution;
1836 }
1837 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
1838 rc = VINF_EM_RAW_EMULATE_INSTR;
1839 break;
1840 }
1841
1842 case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1843 {
1844 Log2(("SVM: Rdtsc\n"));
1845 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1846 rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1847 if (rc == VINF_SUCCESS)
1848 {
1849 /* Update EIP and continue execution. */
1850 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1851 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1852 goto ResumeExecution;
1853 }
1854 rc = VINF_EM_RAW_EMULATE_INSTR;
1855 break;
1856 }
1857
1858 case SVM_EXIT_RDPMC: /* Guest software attempted to execute RDPMC. */
1859 {
1860 Log2(("SVM: Rdpmc %x\n", pCtx->ecx));
1861 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdpmc);
1862 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1863 if (rc == VINF_SUCCESS)
1864 {
1865 /* Update EIP and continue execution. */
1866 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1867 goto ResumeExecution;
1868 }
1869 rc = VINF_EM_RAW_EMULATE_INSTR;
1870 break;
1871 }
1872
1873 case SVM_EXIT_RDTSCP: /* Guest software attempted to execute RDTSCP. */
1874 {
1875 Log2(("SVM: Rdtscp\n"));
1876 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1877 rc = EMInterpretRdtscp(pVM, pVCpu, pCtx);
1878 if (rc == VINF_SUCCESS)
1879 {
1880 /* Update EIP and continue execution. */
1881 pCtx->rip += 3; /* Note! hardcoded opcode size! */
1882 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1883 goto ResumeExecution;
1884 }
1885 AssertMsgFailed(("EMU: rdtscp failed with %Rrc\n", rc));
1886 rc = VINF_EM_RAW_EMULATE_INSTR;
1887 break;
1888 }
1889
1890 case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1891 {
1892 Log2(("SVM: invlpg\n"));
1893 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
1894
1895 Assert(!pVM->hwaccm.s.fNestedPaging);
1896
1897 /* Truly a pita. Why can't SVM give the same information as VT-x? */
1898 rc = svmR0InterpretInvpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1899 if (rc == VINF_SUCCESS)
1900 {
1901 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushPageInvlpg);
1902 goto ResumeExecution; /* eip already updated */
1903 }
1904 break;
1905 }
1906
1907 case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1908 case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1909 case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1910 case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1911 {
1912 uint32_t cbSize;
1913
1914 Log2(("SVM: %RGv mov cr%d, \n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
1915 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[exitCode - SVM_EXIT_WRITE_CR0]);
1916 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
1917
1918 switch (exitCode - SVM_EXIT_WRITE_CR0)
1919 {
1920 case 0:
1921 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1922 break;
1923 case 2:
1924 break;
1925 case 3:
1926 Assert(!pVM->hwaccm.s.fNestedPaging);
1927 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
1928 break;
1929 case 4:
1930 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
1931 break;
1932 case 8:
1933 break;
1934 default:
1935 AssertFailed();
1936 }
1937 /* Check if a sync operation is pending. */
1938 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1939 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1940 {
1941 rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1942 AssertRC(rc);
1943
1944 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBCRxChange);
1945
1946 /* Must be set by PGMSyncCR3 */
1947 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || PGMGetGuestMode(pVCpu) <= PGMMODE_PROTECTED || pVCpu->hwaccm.s.fForceTLBFlush,
1948 ("rc=%Rrc mode=%d fForceTLBFlush=%RTbool\n", rc, PGMGetGuestMode(pVCpu), pVCpu->hwaccm.s.fForceTLBFlush));
1949 }
1950 if (rc == VINF_SUCCESS)
1951 {
1952 /* EIP has been updated already. */
1953
1954 /* Only resume if successful. */
1955 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1956 goto ResumeExecution;
1957 }
1958 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1959 break;
1960 }
1961
1962 case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1963 case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1964 case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1965 case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1966 {
1967 uint32_t cbSize;
1968
1969 Log2(("SVM: %RGv mov x, cr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
1970 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[exitCode - SVM_EXIT_READ_CR0]);
1971 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
1972 if (rc == VINF_SUCCESS)
1973 {
1974 /* EIP has been updated already. */
1975
1976 /* Only resume if successful. */
1977 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1978 goto ResumeExecution;
1979 }
1980 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1981 break;
1982 }
1983
1984 case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1985 case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1986 case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1987 case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1988 {
1989 uint32_t cbSize;
1990
1991 Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
1992 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
1993
1994 if ( !DBGFIsStepping(pVCpu)
1995 && !CPUMIsHyperDebugStateActive(pVCpu))
1996 {
1997 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
1998
1999 /* Disable drx move intercepts. */
2000 pVMCB->ctrl.u16InterceptRdDRx = 0;
2001 pVMCB->ctrl.u16InterceptWrDRx = 0;
2002
2003 /* Save the host and load the guest debug state. */
2004 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2005 AssertRC(rc);
2006
2007 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2008 goto ResumeExecution;
2009 }
2010
2011 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2012 if (rc == VINF_SUCCESS)
2013 {
2014 /* EIP has been updated already. */
2015 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2016
2017 /* Only resume if successful. */
2018 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2019 goto ResumeExecution;
2020 }
2021 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2022 break;
2023 }
2024
2025 case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
2026 case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
2027 case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
2028 case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
2029 {
2030 uint32_t cbSize;
2031
2032 Log2(("SVM: %RGv mov x, dr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
2033 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
2034
2035 if (!DBGFIsStepping(pVCpu))
2036 {
2037 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2038
2039 /* Disable drx move intercepts. */
2040 pVMCB->ctrl.u16InterceptRdDRx = 0;
2041 pVMCB->ctrl.u16InterceptWrDRx = 0;
2042
2043 /* Save the host and load the guest debug state. */
2044 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2045 AssertRC(rc);
2046
2047 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2048 goto ResumeExecution;
2049 }
2050
2051 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2052 if (rc == VINF_SUCCESS)
2053 {
2054 /* EIP has been updated already. */
2055
2056 /* Only resume if successful. */
2057 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2058 goto ResumeExecution;
2059 }
2060 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2061 break;
2062 }
2063
2064 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2065 case SVM_EXIT_IOIO: /* I/O instruction. */
2066 {
2067 SVM_IOIO_EXIT IoExitInfo;
2068 uint32_t uIOSize, uAndVal;
2069
2070 IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
2071
2072 /** @todo could use a lookup table here */
2073 if (IoExitInfo.n.u1OP8)
2074 {
2075 uIOSize = 1;
2076 uAndVal = 0xff;
2077 }
2078 else
2079 if (IoExitInfo.n.u1OP16)
2080 {
2081 uIOSize = 2;
2082 uAndVal = 0xffff;
2083 }
2084 else
2085 if (IoExitInfo.n.u1OP32)
2086 {
2087 uIOSize = 4;
2088 uAndVal = 0xffffffff;
2089 }
2090 else
2091 {
2092 AssertFailed(); /* should be fatal. */
2093 rc = VINF_EM_RAW_EMULATE_INSTR;
2094 break;
2095 }
2096
2097 if (IoExitInfo.n.u1STR)
2098 {
2099 /* ins/outs */
2100 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2101
2102 /* Disassemble manually to deal with segment prefixes. */
2103 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL);
2104 if (rc == VINF_SUCCESS)
2105 {
2106 if (IoExitInfo.n.u1Type == 0)
2107 {
2108 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2109 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
2110 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize);
2111 }
2112 else
2113 {
2114 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2115 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
2116 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize);
2117 }
2118 }
2119 else
2120 rc = VINF_EM_RAW_EMULATE_INSTR;
2121 }
2122 else
2123 {
2124 /* normal in/out */
2125 Assert(!IoExitInfo.n.u1REP);
2126
2127 if (IoExitInfo.n.u1Type == 0)
2128 {
2129 Log2(("IOMIOPortWrite %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
2130 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
2131 rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
2132 if (rc == VINF_IOM_HC_IOPORT_WRITE)
2133 HWACCMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
2134 }
2135 else
2136 {
2137 uint32_t u32Val = 0;
2138
2139 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
2140 rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
2141 if (IOM_SUCCESS(rc))
2142 {
2143 /* Write back to the EAX register. */
2144 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2145 Log2(("IOMIOPortRead %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
2146 }
2147 else
2148 if (rc == VINF_IOM_HC_IOPORT_READ)
2149 HWACCMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
2150 }
2151 }
2152 /*
2153 * Handled the I/O return codes.
2154 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2155 */
2156 if (IOM_SUCCESS(rc))
2157 {
2158 /* Update EIP and continue execution. */
2159 pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
2160 if (RT_LIKELY(rc == VINF_SUCCESS))
2161 {
2162 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
2163 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
2164 {
2165 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
2166 for (unsigned i=0;i<4;i++)
2167 {
2168 unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
2169
2170 if ( (IoExitInfo.n.u16Port >= pCtx->dr[i] && IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen)
2171 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
2172 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
2173 {
2174 SVM_EVENT Event;
2175
2176 Assert(CPUMIsGuestDebugStateActive(pVCpu));
2177
2178 /* Clear all breakpoint status flags and set the one we just hit. */
2179 pCtx->dr[6] &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
2180 pCtx->dr[6] |= (uint64_t)RT_BIT(i);
2181
2182 /* Note: AMD64 Architecture Programmer's Manual 13.1:
2183 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
2184 * the contents have been read.
2185 */
2186 pVMCB->guest.u64DR6 = pCtx->dr[6];
2187
2188 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2189 pCtx->dr[7] &= ~X86_DR7_GD;
2190
2191 /* Paranoia. */
2192 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2193 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2194 pCtx->dr[7] |= 0x400; /* must be one */
2195
2196 pVMCB->guest.u64DR7 = pCtx->dr[7];
2197
2198 /* Inject the exception. */
2199 Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
2200
2201 Event.au64[0] = 0;
2202 Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
2203 Event.n.u1Valid = 1;
2204 Event.n.u8Vector = X86_XCPT_DB;
2205
2206 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2207
2208 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2209 goto ResumeExecution;
2210 }
2211 }
2212 }
2213
2214 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2215 goto ResumeExecution;
2216 }
2217 Log2(("EM status from IO at %RGv %x size %d: %Rrc\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
2218 break;
2219 }
2220
2221#ifdef VBOX_STRICT
2222 if (rc == VINF_IOM_HC_IOPORT_READ)
2223 Assert(IoExitInfo.n.u1Type != 0);
2224 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2225 Assert(IoExitInfo.n.u1Type == 0);
2226 else
2227 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
2228#endif
2229 Log2(("Failed IO at %RGv %x size %d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2230 break;
2231 }
2232
2233 case SVM_EXIT_HLT:
2234 /** Check if external interrupts are pending; if so, don't switch back. */
2235 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
2236 pCtx->rip++; /* skip hlt */
2237 if ( pCtx->eflags.Bits.u1IF
2238 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
2239 goto ResumeExecution;
2240
2241 rc = VINF_EM_HALT;
2242 break;
2243
2244 case SVM_EXIT_MWAIT_UNCOND:
2245 Log2(("SVM: mwait\n"));
2246 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMwait);
2247 rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2248 if ( rc == VINF_EM_HALT
2249 || rc == VINF_SUCCESS)
2250 {
2251 /* Update EIP and continue execution. */
2252 pCtx->rip += 3; /* Note: hardcoded opcode size assumption! */
2253
2254 /** Check if external interrupts are pending; if so, don't switch back. */
2255 if ( rc == VINF_SUCCESS
2256 || ( rc == VINF_EM_HALT
2257 && pCtx->eflags.Bits.u1IF
2258 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
2259 )
2260 goto ResumeExecution;
2261 }
2262 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", rc));
2263 break;
2264
2265 case SVM_EXIT_VMMCALL:
2266 rc = svmR0EmulateTprVMMCall(pVM, pVCpu, pCtx);
2267 if (rc == VINF_SUCCESS)
2268 {
2269 goto ResumeExecution; /* rip already updated. */
2270 }
2271 /* no break */
2272
2273 case SVM_EXIT_RSM:
2274 case SVM_EXIT_INVLPGA:
2275 case SVM_EXIT_VMRUN:
2276 case SVM_EXIT_VMLOAD:
2277 case SVM_EXIT_VMSAVE:
2278 case SVM_EXIT_STGI:
2279 case SVM_EXIT_CLGI:
2280 case SVM_EXIT_SKINIT:
2281 {
2282 /* Unsupported instructions. */
2283 SVM_EVENT Event;
2284
2285 Event.au64[0] = 0;
2286 Event.n.u3Type = SVM_EVENT_EXCEPTION;
2287 Event.n.u1Valid = 1;
2288 Event.n.u8Vector = X86_XCPT_UD;
2289
2290 Log(("Forced #UD trap at %RGv\n", (RTGCPTR)pCtx->rip));
2291 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2292
2293 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2294 goto ResumeExecution;
2295 }
2296
2297 /* Emulate in ring 3. */
2298 case SVM_EXIT_MSR:
2299 {
2300 uint32_t cbSize;
2301
2302 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2303 STAM_COUNTER_INC((pVMCB->ctrl.u64ExitInfo1 == 0) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
2304 Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
2305 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2306 if (rc == VINF_SUCCESS)
2307 {
2308 /* EIP has been updated already. */
2309
2310 /* Only resume if successful. */
2311 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2312 goto ResumeExecution;
2313 }
2314 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
2315 break;
2316 }
2317
2318 case SVM_EXIT_MONITOR:
2319 case SVM_EXIT_PAUSE:
2320 case SVM_EXIT_MWAIT_ARMED:
2321 case SVM_EXIT_TASK_SWITCH: /* can change CR3; emulate */
2322 rc = VERR_EM_INTERPRETER;
2323 break;
2324
2325 case SVM_EXIT_SHUTDOWN:
2326 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2327 break;
2328
2329 case SVM_EXIT_IDTR_READ:
2330 case SVM_EXIT_GDTR_READ:
2331 case SVM_EXIT_LDTR_READ:
2332 case SVM_EXIT_TR_READ:
2333 case SVM_EXIT_IDTR_WRITE:
2334 case SVM_EXIT_GDTR_WRITE:
2335 case SVM_EXIT_LDTR_WRITE:
2336 case SVM_EXIT_TR_WRITE:
2337 case SVM_EXIT_CR0_SEL_WRITE:
2338 default:
2339 /* Unexpected exit codes. */
2340 rc = VERR_EM_INTERNAL_ERROR;
2341 AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
2342 break;
2343 }
2344
2345end:
2346
2347 /* Signal changes for the recompiler. */
2348 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
2349
2350 /* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
2351 if (exitCode == SVM_EXIT_INTR)
2352 {
2353 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
2354 /* On the next entry we'll only sync the host context. */
2355 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
2356 }
2357 else
2358 {
2359 /* On the next entry we'll sync everything. */
2360 /** @todo we can do better than this */
2361 /* Not in the VINF_PGM_CHANGE_MODE though! */
2362 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2363 }
2364
2365 /* translate into a less severe return code */
2366 if (rc == VERR_EM_INTERPRETER)
2367 rc = VINF_EM_RAW_EMULATE_INSTR;
2368
2369 /* Just set the correct state here instead of trying to catch every goto above. */
2370 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
2371
2372#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2373 /* Restore interrupts if we exitted after disabling them. */
2374 if (uOldEFlags != ~(RTCCUINTREG)0)
2375 ASMSetFlags(uOldEFlags);
2376#endif
2377
2378 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2379 return rc;
2380}
2381
2382/**
2383 * Emulate simple mov tpr instruction
2384 *
2385 * @returns VBox status code.
2386 * @param pVCpu The VM CPU to operate on.
2387 * @param pDis Disassembly state
2388 * @param pCtx CPU context
2389 * @param cbOp Opcode size
2390 */
2391static int svmR0EmulateTprMov(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTX pCtx, unsigned cbOp)
2392{
2393 int rc;
2394
2395 if (pDis->param1.flags == USE_DISPLACEMENT32)
2396 {
2397 /* write */
2398 uint8_t u8Tpr;
2399
2400 /* Fetch the new TPR value */
2401 if (pDis->param2.flags == USE_REG_GEN32)
2402 {
2403 uint32_t val;
2404
2405 rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pDis->param2.base.reg_gen, &val);
2406 AssertRC(rc);
2407 u8Tpr = val;
2408 }
2409 else
2410 if (pDis->param2.flags == USE_IMMEDIATE32)
2411 {
2412 u8Tpr = (uint8_t)pDis->param2.parval;
2413 }
2414 else
2415 return VERR_EM_INTERPRETER;
2416
2417 rc = PDMApicSetTPR(pVCpu, u8Tpr);
2418 AssertRC(rc);
2419
2420 Log(("Emulated write successfully\n"));
2421 pCtx->rip += cbOp;
2422 return VINF_SUCCESS;
2423 }
2424 else
2425 if (pDis->param2.flags == USE_DISPLACEMENT32)
2426 {
2427 /* read */
2428 bool fPending;
2429 uint8_t u8Tpr;
2430
2431 /* TPR caching in CR8 */
2432 rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending);
2433 AssertRC(rc);
2434
2435 rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pDis->param1.base.reg_gen, u8Tpr);
2436 AssertRC(rc);
2437
2438 Log(("Emulated read successfully\n"));
2439 pCtx->rip += cbOp;
2440 return VINF_SUCCESS;
2441 }
2442 return VERR_EM_INTERPRETER;
2443}
2444
2445/**
2446 * Emulate simple mov tpr instruction
2447 *
2448 * @returns VBox status code.
2449 * @param pVM The VM to operate on.
2450 * @param pVCpu The VM CPU to operate on.
2451 * @param pCtx CPU context
2452 */
2453static int svmR0EmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2454{
2455 int rc;
2456
2457 Log(("Emulated VMMCall TPR access replacement at %RGv\n", pCtx->rip));
2458
2459 while (true)
2460 {
2461 bool fPending;
2462 uint8_t u8Tpr;
2463
2464 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.svm.PatchTree, (AVLOU32KEY)pCtx->eip);
2465 if (!pPatch)
2466 break;
2467
2468 switch(pPatch->enmType)
2469 {
2470 case HWACCMTPRINSTR_READ:
2471 /* TPR caching in CR8 */
2472 rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending);
2473 AssertRC(rc);
2474
2475 rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
2476 AssertRC(rc);
2477
2478 Log(("Emulated read successfully\n"));
2479 pCtx->rip += pPatch->cbOp;
2480 break;
2481
2482 case HWACCMTPRINSTR_WRITE_REG:
2483 case HWACCMTPRINSTR_WRITE_IMM:
2484 /* Fetch the new TPR value */
2485 if (pPatch->enmType == HWACCMTPRINSTR_WRITE_REG)
2486 {
2487 uint32_t val;
2488
2489 rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &val);
2490 AssertRC(rc);
2491 u8Tpr = val;
2492 }
2493 else
2494 u8Tpr = (uint8_t)pPatch->uSrcOperand;
2495
2496 rc = PDMApicSetTPR(pVCpu, u8Tpr);
2497 AssertRC(rc);
2498 Log(("Emulated write successfully\n"));
2499 pCtx->rip += pPatch->cbOp;
2500 break;
2501 }
2502 }
2503 return VINF_SUCCESS;
2504}
2505
2506/**
2507 * Attempt to patch TPR mmio instructions
2508 *
2509 * @returns VBox status code.
2510 * @param pVM The VM to operate on.
2511 * @param pVCpu The VM CPU to operate on.
2512 * @param pCtx CPU context
2513 */
2514static int svmR0ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2515{
2516 RTGCPTR oldrip = pCtx->rip;
2517 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2518 unsigned cbOp;
2519
2520 Log(("Replace TPR access at %RGv\n", pCtx->rip));
2521
2522 int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
2523 AssertRC(rc);
2524 if ( rc == VINF_SUCCESS
2525 && pDis->pCurInstr->opcode == OP_MOV)
2526 {
2527 if (pVM->hwaccm.s.svm.cPatches < RT_ELEMENTS(pVM->hwaccm.s.svm.aPatches))
2528 {
2529 uint8_t aVMMCall[3] = { 0xf, 0x1, 0xd9};
2530 uint32_t idx = pVM->hwaccm.s.svm.cPatches;
2531 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[idx];
2532
2533 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2534 AssertRC(rc);
2535
2536 pPatch->cbOp = cbOp;
2537
2538 if (pDis->param1.flags == USE_DISPLACEMENT32)
2539 {
2540 /* write. */
2541 if (pDis->param2.flags == USE_REG_GEN32)
2542 {
2543 pPatch->enmType = HWACCMTPRINSTR_WRITE_REG;
2544 pPatch->uSrcOperand = pDis->param2.base.reg_gen;
2545 }
2546 else
2547 {
2548 Assert(pDis->param2.flags == USE_IMMEDIATE32);
2549 pPatch->enmType = HWACCMTPRINSTR_WRITE_IMM;
2550 pPatch->uSrcOperand = pDis->param2.parval;
2551 }
2552 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
2553 AssertRC(rc);
2554 }
2555 else
2556 {
2557 RTGCPTR oldrip = pCtx->rip;
2558 uint32_t oldcbOp = cbOp;
2559 uint32_t uMmioReg = pDis->param1.base.reg_gen;
2560
2561 /* read */
2562 Assert(pDis->param1.flags == USE_REG_GEN32);
2563
2564 /* Found:
2565 * mov eax, dword [fffe0080] (5 bytes)
2566 * Check if next instruction is:
2567 * shr eax, 4
2568 */
2569 pCtx->rip += cbOp;
2570 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
2571 pCtx->rip = oldrip;
2572 if ( rc == VINF_SUCCESS
2573 && pDis->pCurInstr->opcode == OP_SHR
2574 && pDis->param1.flags == USE_REG_GEN32
2575 && pDis->param1.base.reg_gen == uMmioReg
2576 && pDis->param2.flags == USE_IMMEDIATE8
2577 && pDis->param2.parval == 4
2578 && oldcbOp + cbOp < sizeof(pVM->hwaccm.s.svm.aPatches[idx]))
2579 {
2580 uint8_t szInstr[15];
2581
2582 /* Replacing two instructions now. */
2583 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, oldcbOp + cbOp);
2584 AssertRC(rc);
2585
2586 pPatch->cbOp = oldcbOp + cbOp;
2587
2588 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
2589 szInstr[0] = 0xF0;
2590 szInstr[1] = 0x0F;
2591 szInstr[2] = 0x20;
2592 szInstr[3] = 0xC0 | pDis->param1.base.reg_gen;
2593 for (unsigned i = 4; i < 5+cbOp; i++)
2594 szInstr[i] = 0x90; /* nop */
2595
2596 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, 5+cbOp);
2597 AssertRC(rc);
2598
2599 Log(("Acceptable read/shr candidate!\n"));
2600 pPatch->enmType = HWACCMTPRINSTR_READ_SHR4;
2601 }
2602 else
2603 {
2604 pPatch->enmType = HWACCMTPRINSTR_READ;
2605 pPatch->uDstOperand = pDis->param1.base.reg_gen;
2606
2607 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
2608 AssertRC(rc);
2609 }
2610 }
2611
2612 pPatch->Core.Key = pCtx->eip;
2613 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
2614 AssertRC(rc);
2615
2616 pVM->hwaccm.s.svm.cPatches++;
2617 return VINF_SUCCESS;
2618 }
2619 return svmR0EmulateTprMov(pVCpu, pDis, pCtx, cbOp);
2620 }
2621 return VERR_ACCESS_DENIED;
2622}
2623
2624/**
2625 * Enters the AMD-V session
2626 *
2627 * @returns VBox status code.
2628 * @param pVM The VM to operate on.
2629 * @param pVCpu The VM CPU to operate on.
2630 * @param pCpu CPU info struct
2631 */
2632VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
2633{
2634 Assert(pVM->hwaccm.s.svm.fSupported);
2635
2636 LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVCpu->hwaccm.s.idLastCpu, pVCpu->hwaccm.s.uCurrentASID));
2637 pVCpu->hwaccm.s.fResumeVM = false;
2638
2639 /* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
2640 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_LDTR;
2641
2642 return VINF_SUCCESS;
2643}
2644
2645
2646/**
2647 * Leaves the AMD-V session
2648 *
2649 * @returns VBox status code.
2650 * @param pVM The VM to operate on.
2651 * @param pVCpu The VM CPU to operate on.
2652 * @param pCtx CPU context
2653 */
2654VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2655{
2656 SVM_VMCB *pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
2657
2658 Assert(pVM->hwaccm.s.svm.fSupported);
2659
2660#ifdef DEBUG
2661 if (CPUMIsHyperDebugStateActive(pVCpu))
2662 {
2663 CPUMR0LoadHostDebugState(pVM, pVCpu);
2664 }
2665 else
2666#endif
2667 /* Save the guest debug state if necessary. */
2668 if (CPUMIsGuestDebugStateActive(pVCpu))
2669 {
2670 CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, false /* skip DR6 */);
2671
2672 /* Intercept all DRx reads and writes again. Changed later on. */
2673 pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
2674 pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
2675
2676 /* Resync the debug registers the next time. */
2677 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2678 }
2679 else
2680 Assert(pVMCB->ctrl.u16InterceptRdDRx == 0xFFFF && pVMCB->ctrl.u16InterceptWrDRx == 0xFFFF);
2681
2682 return VINF_SUCCESS;
2683}
2684
2685
2686static int svmR0InterpretInvlPg(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2687{
2688 OP_PARAMVAL param1;
2689 RTGCPTR addr;
2690
2691 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2692 if(RT_FAILURE(rc))
2693 return VERR_EM_INTERPRETER;
2694
2695 switch(param1.type)
2696 {
2697 case PARMTYPE_IMMEDIATE:
2698 case PARMTYPE_ADDRESS:
2699 if(!(param1.flags & (PARAM_VAL32|PARAM_VAL64)))
2700 return VERR_EM_INTERPRETER;
2701 addr = param1.val.val64;
2702 break;
2703
2704 default:
2705 return VERR_EM_INTERPRETER;
2706 }
2707
2708 /** @todo is addr always a flat linear address or ds based
2709 * (in absence of segment override prefixes)????
2710 */
2711 rc = PGMInvalidatePage(pVCpu, addr);
2712 if (RT_SUCCESS(rc))
2713 {
2714 /* Manually invalidate the page for the VM's TLB. */
2715 Log(("SVMR0InvlpgA %RGv ASID=%d\n", addr, uASID));
2716 SVMR0InvlpgA(addr, uASID);
2717 return VINF_SUCCESS;
2718 }
2719 AssertRC(rc);
2720 return rc;
2721}
2722
2723/**
2724 * Interprets INVLPG
2725 *
2726 * @returns VBox status code.
2727 * @retval VINF_* Scheduling instructions.
2728 * @retval VERR_EM_INTERPRETER Something we can't cope with.
2729 * @retval VERR_* Fatal errors.
2730 *
2731 * @param pVM The VM handle.
2732 * @param pRegFrame The register frame.
2733 * @param ASID Tagged TLB id for the guest
2734 *
2735 * Updates the EIP if an instruction was executed successfully.
2736 */
2737static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2738{
2739 /*
2740 * Only allow 32 & 64 bits code.
2741 */
2742 DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
2743 if (enmMode != CPUMODE_16BIT)
2744 {
2745 RTGCPTR pbCode;
2746 int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
2747 if (RT_SUCCESS(rc))
2748 {
2749 uint32_t cbOp;
2750 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2751
2752 pDis->mode = enmMode;
2753 rc = EMInterpretDisasOneEx(pVM, pVCpu, pbCode, pRegFrame, pDis, &cbOp);
2754 Assert(RT_FAILURE(rc) || pDis->pCurInstr->opcode == OP_INVLPG);
2755 if (RT_SUCCESS(rc) && pDis->pCurInstr->opcode == OP_INVLPG)
2756 {
2757 Assert(cbOp == pDis->opsize);
2758 rc = svmR0InterpretInvlPg(pVCpu, pDis, pRegFrame, uASID);
2759 if (RT_SUCCESS(rc))
2760 {
2761 pRegFrame->rip += cbOp; /* Move on to the next instruction. */
2762 }
2763 return rc;
2764 }
2765 }
2766 }
2767 return VERR_EM_INTERPRETER;
2768}
2769
2770
2771/**
2772 * Invalidates a guest page
2773 *
2774 * @returns VBox status code.
2775 * @param pVM The VM to operate on.
2776 * @param pVCpu The VM CPU to operate on.
2777 * @param GCVirt Page to invalidate
2778 */
2779VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
2780{
2781 bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB | VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH);
2782
2783 /* Skip it if a TLB flush is already pending. */
2784 if (!fFlushPending)
2785 {
2786 SVM_VMCB *pVMCB;
2787
2788 Log2(("SVMR0InvalidatePage %RGv\n", GCVirt));
2789 AssertReturn(pVM, VERR_INVALID_PARAMETER);
2790 Assert(pVM->hwaccm.s.svm.fSupported);
2791
2792 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
2793 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2794
2795#if HC_ARCH_BITS == 32
2796 /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invlpga takes only 32 bits addresses. */
2797 if (CPUMIsGuestInLongMode(pVCpu))
2798 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2799 else
2800#endif
2801 SVMR0InvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2802 }
2803 return VINF_SUCCESS;
2804}
2805
2806
2807#if 0 /* obsolete, but left here for clarification. */
2808/**
2809 * Invalidates a guest page by physical address
2810 *
2811 * @returns VBox status code.
2812 * @param pVM The VM to operate on.
2813 * @param pVCpu The VM CPU to operate on.
2814 * @param GCPhys Page to invalidate
2815 */
2816VMMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
2817{
2818 Assert(pVM->hwaccm.s.fNestedPaging);
2819 /* invlpga only invalidates TLB entries for guest virtual addresses; we have no choice but to force a TLB flush here. */
2820 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2821 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBInvlpga);
2822 return VINF_SUCCESS;
2823}
2824#endif
2825
2826#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2827/**
2828 * Prepares for and executes VMRUN (64 bits guests from a 32 bits hosts).
2829 *
2830 * @returns VBox status code.
2831 * @param pVMCBHostPhys Physical address of host VMCB.
2832 * @param pVMCBPhys Physical address of the VMCB.
2833 * @param pCtx Guest context.
2834 * @param pVM The VM to operate on.
2835 * @param pVCpu The VMCPU to operate on.
2836 */
2837DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
2838{
2839 uint32_t aParam[4];
2840
2841 aParam[0] = (uint32_t)(pVMCBHostPhys); /* Param 1: pVMCBHostPhys - Lo. */
2842 aParam[1] = (uint32_t)(pVMCBHostPhys >> 32); /* Param 1: pVMCBHostPhys - Hi. */
2843 aParam[2] = (uint32_t)(pVMCBPhys); /* Param 2: pVMCBPhys - Lo. */
2844 aParam[3] = (uint32_t)(pVMCBPhys >> 32); /* Param 2: pVMCBPhys - Hi. */
2845
2846 return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSVMGCVMRun64, 4, &aParam[0]);
2847}
2848
2849/**
2850 * Executes the specified handler in 64 mode
2851 *
2852 * @returns VBox status code.
2853 * @param pVM The VM to operate on.
2854 * @param pVCpu The VMCPU to operate on.
2855 * @param pCtx Guest context
2856 * @param pfnHandler RC handler
2857 * @param cbParam Number of parameters
2858 * @param paParam Array of 32 bits parameters
2859 */
2860VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
2861{
2862 int rc;
2863 RTHCUINTREG uOldEFlags;
2864
2865 /* @todo This code is not guest SMP safe (hyper stack and switchers) */
2866 AssertReturn(pVM->cCPUs == 1, VERR_TOO_MANY_CPUS);
2867 Assert(pfnHandler);
2868
2869 uOldEFlags = ASMIntDisableFlags();
2870
2871 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVM));
2872 CPUMSetHyperEIP(pVCpu, pfnHandler);
2873 for (int i=(int)cbParam-1;i>=0;i--)
2874 CPUMPushHyper(pVCpu, paParam[i]);
2875
2876 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2877 /* Call switcher. */
2878 rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM);
2879 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2880
2881 ASMSetFlags(uOldEFlags);
2882 return rc;
2883}
2884
2885#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
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