HWSVMR0.cpp@ 2166

Last change on this file since 2166 was 2166, checked in by vboxsync, 18 years ago
Single stepping support added (as a debug feature)
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1	/* $Id: HWSVMR0.cpp 2166 2007-04-18 12:42:08Z vboxsync $ */
2	/** @file
3	* HWACCM SVM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_svm.h>
32	#include <VBox/pgm.h>
33	#include <VBox/pdm.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <VBox/selm.h>
37	#include <VBox/iom.h>
38	#include <VBox/dis.h>
39	#include <VBox/dbgf.h>
40	#include <VBox/disopcode.h>
41	#include <iprt/param.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm.h>
44	#include "HWSVMR0.h"
45
46	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
47
48	/**
49	* Sets up and activates SVM
50	*
51	* @returns VBox status code.
52	* @param pVM The VM to operate on.
53	*/
54	HWACCMR0DECL(int) SVMR0Setup(PVM pVM)
55	{
56	int rc = VINF_SUCCESS;
57	SVM_VMCB *pVMCB;
58
59	if (pVM == NULL)
60	return VERR_INVALID_PARAMETER;
61
62	/* Setup AMD SVM. */
63	Assert(pVM->hwaccm.s.svm.fSupported);
64
65	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
66	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
67
68	/* Program the control fields. Most of them never have to be changed again. */
69	/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
70	/** @note CR0 & CR4 can be safely read when guest and shadow copies are identical. */
71	pVMCB->ctrl.u16InterceptRdCRx = BIT(0) \| BIT(3) \| BIT(4) \| BIT(8);
72
73	/*
74	* CR0/3/4 writes must be intercepted for obvious reasons.
75	*/
76	pVMCB->ctrl.u16InterceptWrCRx = BIT(0) \| BIT(3) \| BIT(4) \| BIT(8);
77
78	/* Intercept all DRx reads and writes. */
79	pVMCB->ctrl.u16InterceptRdDRx = BIT(0) \| BIT(1) \| BIT(2) \| BIT(3) \| BIT(4) \| BIT(5) \| BIT(6) \| BIT(7);
80	pVMCB->ctrl.u16InterceptWrDRx = BIT(0) \| BIT(1) \| BIT(2) \| BIT(3) \| BIT(4) \| BIT(5) \| BIT(6) \| BIT(7);
81
82	/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
83	* All breakpoints are automatically cleared when the VM exits.
84	*/
85
86	/** @todo nested paging */
87	/* Intercept #NM only; #PF is not relevant due to nested paging (we get a seperate exit code (SVM_EXIT_NPF) for
88	* pagefaults that need our attention).
89	*/
90	pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
91
92	pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
93	\| SVM_CTRL1_INTERCEPT_VINTR
94	\| SVM_CTRL1_INTERCEPT_NMI
95	\| SVM_CTRL1_INTERCEPT_SMI
96	\| SVM_CTRL1_INTERCEPT_INIT
97	\| SVM_CTRL1_INTERCEPT_CR0 /** @todo redundant? */
98	\| SVM_CTRL1_INTERCEPT_RDPMC
99	\| SVM_CTRL1_INTERCEPT_CPUID
100	\| SVM_CTRL1_INTERCEPT_RSM
101	\| SVM_CTRL1_INTERCEPT_HLT
102	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
103	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
104	\| SVM_CTRL1_INTERCEPT_INVLPG
105	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
106	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
107	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
108	;
109	pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
110	\| SVM_CTRL2_INTERCEPT_VMMCALL
111	\| SVM_CTRL2_INTERCEPT_VMLOAD
112	\| SVM_CTRL2_INTERCEPT_VMSAVE
113	\| SVM_CTRL2_INTERCEPT_STGI
114	\| SVM_CTRL2_INTERCEPT_CLGI
115	\| SVM_CTRL2_INTERCEPT_SKINIT
116	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
117	;
118	Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
119	Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
120	Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
121
122	/* Virtualize masking of INTR interrupts. */
123	pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
124
125	/* Set IO and MSR bitmap addresses. */
126	pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
127	pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
128
129	/* Enable nested paging. */
130	/** @todo how to detect support for this?? */
131	pVMCB->ctrl.u64NestedPaging = 0; /** @todo SVM_NESTED_PAGING_ENABLE; */
132
133	/* No LBR virtualization. */
134	pVMCB->ctrl.u64LBRVirt = 0;
135
136	return rc;
137	}
138
139
140	/**
141	* Injects an event (trap or external interrupt)
142	*
143	* @param pVM The VM to operate on.
144	* @param pVMCB SVM control block
145	* @param pCtx CPU Context
146	* @param pIntInfo SVM interrupt info
147	*/
148	inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx, SVM_EVENT* pEvent)
149	{
150	#ifdef VBOX_STRICT
151	if (pEvent->n.u8Vector == 0xE)
152	Log(("SVM: Inject int %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
153	else
154	if (pEvent->n.u8Vector < 0x20)
155	Log(("SVM: Inject int %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode));
156	else
157	{
158	Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->eip));
159	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
160	Assert(pCtx->eflags.u32 & X86_EFL_IF);
161	}
162	#endif
163
164	/* Set event injection state. */
165	pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
166	}
167
168
169	/**
170	* Checks for pending guest interrupts and injects them
171	*
172	* @returns VBox status code.
173	* @param pVM The VM to operate on.
174	* @param pVMCB SVM control block
175	* @param pCtx CPU Context
176	*/
177	static int SVMR0CheckPendingInterrupt(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx)
178	{
179	int rc;
180
181	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
182	if (pVM->hwaccm.s.Event.fPending)
183	{
184	SVM_EVENT Event;
185
186	Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
187	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
188	Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
189	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
190
191	pVM->hwaccm.s.Event.fPending = false;
192	return VINF_SUCCESS;
193	}
194
195	/* When external interrupts are pending, we should exit the VM when IF is set. */
196	if ( !TRPMHasTrap(pVM)
197	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
198	{
199	if (!(pCtx->eflags.u32 & X86_EFL_IF))
200	{
201	Log2(("Enable irq window exit!\n"));
202	/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
203	//// pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
204	//// AssertRC(rc);
205	}
206	else
207	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
208	{
209	uint8_t u8Interrupt;
210
211	rc = PDMGetInterrupt(pVM, &u8Interrupt);
212	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
213	if (VBOX_SUCCESS(rc))
214	{
215	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
216	AssertRC(rc);
217	}
218	else
219	{
220	/* can't happen... */
221	AssertFailed();
222	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
223	return VINF_EM_RAW_INTERRUPT_PENDING;
224	}
225	}
226	else
227	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
228	}
229
230	#ifdef VBOX_STRICT
231	if (TRPMHasTrap(pVM))
232	{
233	uint8_t u8Vector;
234	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
235	AssertRC(rc);
236	}
237	#endif
238
239	if ( pCtx->eflags.u32 & X86_EFL_IF
240	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
241	&& TRPMHasTrap(pVM)
242	)
243	{
244	uint8_t u8Vector;
245	int rc;
246	TRPMEVENT enmType;
247	SVM_EVENT Event;
248	uint32_t u32ErrorCode;
249
250	Event.au64[0] = 0;
251
252	/* If a new event is pending, then dispatch it now. */
253	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &u32ErrorCode, 0);
254	AssertRC(rc);
255	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
256	Assert(enmType != TRPM_SOFTWARE_INT);
257
258	/* Clear the pending trap. */
259	rc = TRPMResetTrap(pVM);
260	AssertRC(rc);
261
262	Event.n.u8Vector = u8Vector;
263	Event.n.u1Valid = 1;
264	Event.n.u32ErrorCode = u32ErrorCode;
265
266	if (enmType == TRPM_TRAP)
267	{
268	switch (u8Vector) {
269	case 8:
270	case 10:
271	case 11:
272	case 12:
273	case 13:
274	case 14:
275	case 17:
276	/* Valid error codes. */
277	Event.n.u1ErrorCodeValid = 1;
278	break;
279	default:
280	break;
281	}
282	if (u8Vector == X86_XCPT_NMI)
283	Event.n.u3Type = SVM_EVENT_NMI;
284	else
285	Event.n.u3Type = SVM_EVENT_EXCEPTION;
286	}
287	else
288	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
289
290	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
291	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
292	} /* if (interrupts can be dispatched) */
293
294	return VINF_SUCCESS;
295	}
296
297
298	/**
299	* Loads the guest state
300	*
301	* @returns VBox status code.
302	* @param pVM The VM to operate on.
303	* @param pCtx Guest context
304	*/
305	HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
306	{
307	RTGCUINTPTR val;
308	SVM_VMCB *pVMCB;
309
310	if (pVM == NULL)
311	return VERR_INVALID_PARAMETER;
312
313	/* Setup AMD SVM. */
314	Assert(pVM->hwaccm.s.svm.fSupported);
315
316	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
317	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
318
319	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
320	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
321	{
322	SVM_WRITE_SELREG(CS, cs);
323	SVM_WRITE_SELREG(SS, ss);
324	SVM_WRITE_SELREG(DS, ds);
325	SVM_WRITE_SELREG(ES, es);
326	SVM_WRITE_SELREG(FS, fs);
327	SVM_WRITE_SELREG(GS, gs);
328	}
329
330	/* Guest CPU context: LDTR. */
331	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
332	{
333	SVM_WRITE_SELREG(LDTR, ldtr);
334	}
335
336	/* Guest CPU context: TR. */
337	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
338	{
339	SVM_WRITE_SELREG(TR, tr);
340	}
341
342	/* Guest CPU context: GDTR. */
343	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
344	{
345	pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
346	pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
347	}
348
349	/* Guest CPU context: IDTR. */
350	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
351	{
352	pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
353	pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
354	}
355
356	/*
357	* Sysenter MSRs
358	*/
359	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
360	{
361	pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
362	pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
363	pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
364	}
365
366	/* Control registers */
367	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
368	{
369	val = pCtx->cr0;
370	if (CPUMIsGuestFPUStateActive(pVM) == false)
371	{
372	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
373	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
374	}
375	else
376	{
377	Assert(pVM->hwaccm.s.svm.fResumeVM == true);
378	/** @todo check if we support the old style mess correctly. */
379	if (!(val & X86_CR0_NE))
380	{
381	Log(("Forcing X86_CR0_NE!!!\n"));
382
383	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
384	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
385	{
386	pVMCB->ctrl.u32InterceptException \|= BIT(16);
387	pVM->hwaccm.s.fFPUOldStyleOverride = true;
388	}
389	}
390	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
391	}
392	if (!(val & X86_CR0_CD))
393	val &= ~X86_CR0_NW; /* Illegal when cache is turned on. */
394
395	val \|= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
396	pVMCB->guest.u64CR0 = val;
397	}
398	/* CR2 as well */
399	pVMCB->guest.u64CR2 = pCtx->cr2;
400
401	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
402	{
403	/* Save our shadow CR3 register. */
404	pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
405	}
406
407	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
408	{
409	val = pCtx->cr4;
410	switch(pVM->hwaccm.s.enmShadowMode)
411	{
412	case PGMMODE_REAL:
413	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
414	AssertFailed();
415	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
416
417	case PGMMODE_32_BIT: /* 32-bit paging. */
418	break;
419
420	case PGMMODE_PAE: /* PAE paging. */
421	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
422	/** @todo use normal 32 bits paging */
423	val \|= X86_CR4_PAE;
424	break;
425
426	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
427	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
428	AssertFailed();
429	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
430
431	default: /* shut up gcc */
432	AssertFailed();
433	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
434	}
435	pVMCB->guest.u64CR4 = val;
436	}
437
438	/* Debug registers. */
439	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
440	{
441	/** @todo DR0-6 */
442	val = pCtx->dr7;
443	val &= ~(BIT(11) \| BIT(12) \| BIT(14) \| BIT(15)); /* must be zero */
444	val \|= 0x400; /* must be one */
445	#ifdef VBOX_STRICT
446	val = 0x400;
447	#endif
448	pVMCB->guest.u64DR7 = val;
449
450	pVMCB->guest.u64DR6 = pCtx->dr6;
451	}
452
453	/* EIP, ESP and EFLAGS */
454	pVMCB->guest.u64RIP = pCtx->eip;
455	pVMCB->guest.u64RSP = pCtx->esp;
456	pVMCB->guest.u64RFlags = pCtx->eflags.u32;
457
458	/* Set CPL */
459	pVMCB->guest.u8CPL = pCtx->ssHid.Attr.n.u2Dpl;
460
461	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
462	pVMCB->guest.u64RAX = pCtx->eax;
463
464	/* vmrun will fail otherwise. */
465	pVMCB->guest.u64EFER = MSR_K6_EFER_SVME;
466
467	/** @note We can do more complex things with tagged TLBs. */
468	pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
469
470	/** TSC offset. */
471	pVMCB->ctrl.u64TSCOffset = TMCpuTickGetOffset(pVM);
472
473	/** @todo 64 bits stuff (?):
474	* - STAR
475	* - LSTAR
476	* - CSTAR
477	* - SFMASK
478	* - KernelGSBase
479	*/
480
481	/* Done. */
482	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
483
484	return VINF_SUCCESS;
485	}
486
487
488	/**
489	* Runs guest code in an SVM VM.
490	*
491	* @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
492	*
493	* @returns VBox status code.
494	* @param pVM The VM to operate on.
495	* @param pCtx Guest context
496	*/
497	HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
498	{
499	int rc = VINF_SUCCESS;
500	uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
501	SVM_VMCB *pVMCB;
502	bool fForceTLBFlush = false;
503
504	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
505
506	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
507	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
508
509	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
510	*/
511	ResumeExecution:
512
513	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
514	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
515	{
516	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
517	if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
518	{
519	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
520	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
521	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
522	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
523	*/
524	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
525	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
526	pVMCB->ctrl.u64IntShadow = 0;
527	}
528	}
529	else
530	{
531	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
532	pVMCB->ctrl.u64IntShadow = 0;
533	}
534
535	/* Check for pending actions that force us to go back to ring 3. */
536	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
537	{
538	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
539	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
540	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
541	rc = VINF_EM_RAW_TO_R3;
542	goto end;
543	}
544	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
545	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
546	{
547	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
548	rc = VINF_EM_PENDING_REQUEST;
549	goto end;
550	}
551
552	/* When external interrupts are pending, we should exit the VM when IF is set. */
553	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
554	rc = SVMR0CheckPendingInterrupt(pVM, pVMCB, pCtx);
555	if (VBOX_FAILURE(rc))
556	{
557	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
558	goto end;
559	}
560
561	/* Load the guest state */
562	rc = SVMR0LoadGuestState(pVM, pCtx);
563	if (rc != VINF_SUCCESS)
564	{
565	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
566	goto end;
567	}
568
569	/* All done! Let's start VM execution. */
570	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
571
572	/** Erratum #170 -> must force a TLB flush */
573	/** @todo supposed to be fixed in future by AMD */
574	fForceTLBFlush = true;
575
576	if ( pVM->hwaccm.s.svm.fResumeVM == false
577	\|\| fForceTLBFlush)
578	{
579	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1;
580	}
581	else
582	{
583	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 0;
584	}
585	/* In case we execute a goto ResumeExecution later on. */
586	pVM->hwaccm.s.svm.fResumeVM = true;
587	fForceTLBFlush = false;
588
589	Assert(sizeof(pVM->hwaccm.s.svm.pVMCBPhys) == 8);
590	Assert(pVMCB->ctrl.u32InterceptCtrl1 == ( SVM_CTRL1_INTERCEPT_INTR
591	\| SVM_CTRL1_INTERCEPT_VINTR
592	\| SVM_CTRL1_INTERCEPT_NMI
593	\| SVM_CTRL1_INTERCEPT_SMI
594	\| SVM_CTRL1_INTERCEPT_INIT
595	\| SVM_CTRL1_INTERCEPT_CR0 /** @todo redundant? */
596	\| SVM_CTRL1_INTERCEPT_RDPMC
597	\| SVM_CTRL1_INTERCEPT_CPUID
598	\| SVM_CTRL1_INTERCEPT_RSM
599	\| SVM_CTRL1_INTERCEPT_HLT
600	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
601	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
602	\| SVM_CTRL1_INTERCEPT_INVLPG
603	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
604	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
605	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE /* Legacy FPU FERR handling. */
606	));
607	Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
608	\| SVM_CTRL2_INTERCEPT_VMMCALL
609	\| SVM_CTRL2_INTERCEPT_VMLOAD
610	\| SVM_CTRL2_INTERCEPT_VMSAVE
611	\| SVM_CTRL2_INTERCEPT_STGI
612	\| SVM_CTRL2_INTERCEPT_CLGI
613	\| SVM_CTRL2_INTERCEPT_SKINIT
614	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
615	));
616	Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
617	Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
618	Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
619	Assert(pVMCB->ctrl.u64NestedPaging == 0);
620	Assert(pVMCB->ctrl.u64LBRVirt == 0);
621
622	SVMVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);
623	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
624
625	/**
626	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
627	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
628	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
629	*/
630
631	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
632
633	/* Reason for the VM exit */
634	exitCode = pVMCB->ctrl.u64ExitCode;
635
636	if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
637	{
638	HWACCMDumpRegs(pCtx);
639	#ifdef DEBUG
640	Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
641	Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
642	Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
643	Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
644	Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
645	Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
646	Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
647	Log(("ctrl.u64IOPMPhysAddr %VX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
648	Log(("ctrl.u64MSRPMPhysAddr %VX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
649	Log(("ctrl.u64TSCOffset %VX64\n", pVMCB->ctrl.u64TSCOffset));
650
651	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
652	Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
653	Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
654	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
655
656	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
657	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
658	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
659	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
660	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
661	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
662	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
663	Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
664	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
665	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
666
667	Log(("ctrl.u64IntShadow %VX64\n", pVMCB->ctrl.u64IntShadow));
668	Log(("ctrl.u64ExitCode %VX64\n", pVMCB->ctrl.u64ExitCode));
669	Log(("ctrl.u64ExitInfo1 %VX64\n", pVMCB->ctrl.u64ExitInfo1));
670	Log(("ctrl.u64ExitInfo2 %VX64\n", pVMCB->ctrl.u64ExitInfo2));
671	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
672	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
673	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
674	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
675	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
676	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
677	Log(("ctrl.u64NestedPaging %VX64\n", pVMCB->ctrl.u64NestedPaging));
678	Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
679	Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
680	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
681	Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
682	Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
683	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
684
685	Log(("ctrl.u64HostCR3 %VX64\n", pVMCB->ctrl.u64HostCR3));
686	Log(("ctrl.u64LBRVirt %VX64\n", pVMCB->ctrl.u64LBRVirt));
687
688	Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
689	Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
690	Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
691	Log(("guest.CS.u64Base %VX64\n", pVMCB->guest.CS.u64Base));
692	Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
693	Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
694	Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
695	Log(("guest.DS.u64Base %VX64\n", pVMCB->guest.DS.u64Base));
696	Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
697	Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
698	Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
699	Log(("guest.ES.u64Base %VX64\n", pVMCB->guest.ES.u64Base));
700	Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
701	Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
702	Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
703	Log(("guest.FS.u64Base %VX64\n", pVMCB->guest.FS.u64Base));
704	Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
705	Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
706	Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
707	Log(("guest.GS.u64Base %VX64\n", pVMCB->guest.GS.u64Base));
708
709	Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
710	Log(("guest.GDTR.u64Base %VX64\n", pVMCB->guest.GDTR.u64Base));
711
712	Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
713	Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
714	Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
715	Log(("guest.LDTR.u64Base %VX64\n", pVMCB->guest.LDTR.u64Base));
716
717	Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
718	Log(("guest.IDTR.u64Base %VX64\n", pVMCB->guest.IDTR.u64Base));
719
720	Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
721	Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
722	Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
723	Log(("guest.TR.u64Base %VX64\n", pVMCB->guest.TR.u64Base));
724
725	Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
726	Log(("guest.u64CR0 %VX64\n", pVMCB->guest.u64CR0));
727	Log(("guest.u64CR2 %VX64\n", pVMCB->guest.u64CR2));
728	Log(("guest.u64CR3 %VX64\n", pVMCB->guest.u64CR3));
729	Log(("guest.u64CR4 %VX64\n", pVMCB->guest.u64CR4));
730	Log(("guest.u64DR6 %VX64\n", pVMCB->guest.u64DR6));
731	Log(("guest.u64DR7 %VX64\n", pVMCB->guest.u64DR7));
732
733	Log(("guest.u64RIP %VX64\n", pVMCB->guest.u64RIP));
734	Log(("guest.u64RSP %VX64\n", pVMCB->guest.u64RSP));
735	Log(("guest.u64RAX %VX64\n", pVMCB->guest.u64RAX));
736	Log(("guest.u64RFlags %VX64\n", pVMCB->guest.u64RFlags));
737
738	Log(("guest.u64SysEnterCS %VX64\n", pVMCB->guest.u64SysEnterCS));
739	Log(("guest.u64SysEnterEIP %VX64\n", pVMCB->guest.u64SysEnterEIP));
740	Log(("guest.u64SysEnterESP %VX64\n", pVMCB->guest.u64SysEnterESP));
741
742	Log(("guest.u64EFER %VX64\n", pVMCB->guest.u64EFER));
743	Log(("guest.u64STAR %VX64\n", pVMCB->guest.u64STAR));
744	Log(("guest.u64LSTAR %VX64\n", pVMCB->guest.u64LSTAR));
745	Log(("guest.u64CSTAR %VX64\n", pVMCB->guest.u64CSTAR));
746	Log(("guest.u64SFMASK %VX64\n", pVMCB->guest.u64SFMASK));
747	Log(("guest.u64KernelGSBase %VX64\n", pVMCB->guest.u64KernelGSBase));
748	Log(("guest.u64GPAT %VX64\n", pVMCB->guest.u64GPAT));
749	Log(("guest.u64DBGCTL %VX64\n", pVMCB->guest.u64DBGCTL));
750	Log(("guest.u64BR_FROM %VX64\n", pVMCB->guest.u64BR_FROM));
751	Log(("guest.u64BR_TO %VX64\n", pVMCB->guest.u64BR_TO));
752	Log(("guest.u64LASTEXCPFROM %VX64\n", pVMCB->guest.u64LASTEXCPFROM));
753	Log(("guest.u64LASTEXCPTO %VX64\n", pVMCB->guest.u64LASTEXCPTO));
754
755	#endif
756	rc = VERR_SVM_UNABLE_TO_START_VM;
757	goto end;
758	}
759
760	/* Let's first sync back eip, esp, and eflags. */
761	pCtx->eip = pVMCB->guest.u64RIP;
762	pCtx->esp = pVMCB->guest.u64RSP;
763	pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
764	/* eax is saved/restore across the vmrun instruction */
765	pCtx->eax = pVMCB->guest.u64RAX;
766
767	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
768	SVM_READ_SELREG(SS, ss);
769	SVM_READ_SELREG(CS, cs);
770	SVM_READ_SELREG(DS, ds);
771	SVM_READ_SELREG(ES, es);
772	SVM_READ_SELREG(FS, fs);
773	SVM_READ_SELREG(GS, gs);
774
775	/** @note no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
776
777	/** @note NOW IT'S SAFE FOR LOGGING! */
778
779	/* Take care of instruction fusing (sti, mov ss) */
780	if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
781	{
782	Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->eip));
783	EMSetInhibitInterruptsPC(pVM, pCtx->eip);
784	}
785	else
786	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
787
788	Log2(("exitCode = %x\n", exitCode));
789
790	/* Check if an injected event was interrupted prematurely. */
791	pVM->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
792	if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
793	&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
794	{
795	Log(("Pending inject %VX64 at %08x exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitCode));
796	pVM->hwaccm.s.Event.fPending = true;
797	/* Error code present? (redundant) */
798	if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
799	{
800	pVM->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
801	}
802	else
803	pVM->hwaccm.s.Event.errCode = 0;
804	}
805	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReason[exitCode & MASK_EXITREASON_STAT]);
806
807	/* Deal with the reason of the VM-exit. */
808	switch (exitCode)
809	{
810	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
811	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
812	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
813	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
814	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
815	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
816	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
817	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
818	{
819	/* Pending trap. */
820	SVM_EVENT Event;
821	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
822
823	Log2(("Hardware/software interrupt %d\n", vector));
824	switch (vector)
825	{
826	#ifdef DEBUG
827	case X86_XCPT_DB:
828	rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), pCtx->dr6);
829	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
830	break;
831	#endif
832
833	case X86_XCPT_NM:
834	{
835	uint32_t oldCR0;
836
837	Log(("#NM fault at %VGv\n", pCtx->eip));
838
839	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
840	oldCR0 = ASMGetCR0();
841	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
842	rc = CPUMHandleLazyFPU(pVM);
843	if (rc == VINF_SUCCESS)
844	{
845	Assert(CPUMIsGuestFPUStateActive(pVM));
846
847	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
848	ASMSetCR0(oldCR0);
849
850	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
851
852	/* Continue execution. */
853	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
854	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
855
856	goto ResumeExecution;
857	}
858
859	Log(("Forward #NM fault to the guest\n"));
860	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
861
862	Event.au64[0] = 0;
863	Event.n.u3Type = SVM_EVENT_EXCEPTION;
864	Event.n.u1Valid = 1;
865	Event.n.u8Vector = X86_XCPT_NM;
866
867	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
868	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
869	goto ResumeExecution;
870	}
871
872	case X86_XCPT_PF: /* Page fault */
873	{
874	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
875	RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
876
877	Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
878	/* Exit qualification contains the linear address of the page fault. */
879	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
880	TRPMSetErrorCode(pVM, errCode);
881	TRPMSetFaultAddress(pVM, uFaultAddress);
882
883	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
884	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
885	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
886	if (rc == VINF_SUCCESS)
887	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
888	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
889	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
890
891	TRPMResetTrap(pVM);
892
893	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
894	goto ResumeExecution;
895	}
896	else
897	if (rc == VINF_EM_RAW_GUEST_TRAP)
898	{ /* A genuine pagefault.
899	* Forward the trap to the guest by injecting the exception and resuming execution.
900	*/
901	Log2(("Forward page fault to the guest\n"));
902	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
903	/* The error code might have been changed. */
904	errCode = TRPMGetErrorCode(pVM);
905
906	TRPMResetTrap(pVM);
907
908	/* Now we must update CR2. */
909	pCtx->cr2 = uFaultAddress;
910
911	Event.au64[0] = 0;
912	Event.n.u3Type = SVM_EVENT_EXCEPTION;
913	Event.n.u1Valid = 1;
914	Event.n.u8Vector = X86_XCPT_PF;
915	Event.n.u1ErrorCodeValid = 1;
916	Event.n.u32ErrorCode = errCode;
917
918	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
919
920	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
921	goto ResumeExecution;
922	}
923	#ifdef VBOX_STRICT
924	if (rc != VINF_EM_RAW_EMULATE_INSTR)
925	Log(("PGMTrap0eHandler failed with %d\n", rc));
926	#endif
927	/* Need to go back to the recompiler to emulate the instruction. */
928	TRPMResetTrap(pVM);
929	break;
930	}
931
932	case X86_XCPT_MF: /* Floating point exception. */
933	{
934	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
935	if (!(pCtx->cr0 & X86_CR0_NE))
936	{
937	/* old style FPU error reporting needs some extra work. */
938	/** @todo don't fall back to the recompiler, but do it manually. */
939	rc = VINF_EM_RAW_EMULATE_INSTR;
940	break;
941	}
942	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
943
944	Event.au64[0] = 0;
945	Event.n.u3Type = SVM_EVENT_EXCEPTION;
946	Event.n.u1Valid = 1;
947	Event.n.u8Vector = X86_XCPT_MF;
948
949	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
950
951	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
952	goto ResumeExecution;
953	}
954
955	#ifdef VBOX_STRICT
956	case X86_XCPT_GP: /* General protection failure exception.*/
957	case X86_XCPT_UD: /* Unknown opcode exception. */
958	case X86_XCPT_DE: /* Debug exception. */
959	case X86_XCPT_SS: /* Stack segment exception. */
960	case X86_XCPT_NP: /* Segment not present exception. */
961	{
962	Event.au64[0] = 0;
963	Event.n.u3Type = SVM_EVENT_EXCEPTION;
964	Event.n.u1Valid = 1;
965	Event.n.u8Vector = vector;
966
967	switch(vector)
968	{
969	case X86_XCPT_GP:
970	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
971	Event.n.u1ErrorCodeValid = 1;
972	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
973	break;
974	case X86_XCPT_DE:
975	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
976	break;
977	case X86_XCPT_UD:
978	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
979	break;
980	case X86_XCPT_SS:
981	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
982	Event.n.u1ErrorCodeValid = 1;
983	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
984	break;
985	case X86_XCPT_NP:
986	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
987	Event.n.u1ErrorCodeValid = 1;
988	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
989	break;
990	}
991	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
992	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
993
994	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
995	goto ResumeExecution;
996	}
997	#endif
998	default:
999	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1000	rc = VERR_EM_INTERNAL_ERROR;
1001	break;
1002
1003	} /* switch (vector) */
1004	break;
1005	}
1006
1007	case SVM_EXIT_FERR_FREEZE:
1008	case SVM_EXIT_INTR:
1009	case SVM_EXIT_NMI:
1010	case SVM_EXIT_SMI:
1011	case SVM_EXIT_INIT:
1012	case SVM_EXIT_VINTR:
1013	/* External interrupt; leave to allow it to be dispatched again. */
1014	rc = VINF_EM_RAW_INTERRUPT;
1015	break;
1016
1017	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1018	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1019	/* Skip instruction and continue directly. */
1020	pCtx->eip += 2; /** @note hardcoded opcode size! */
1021	/* Continue execution.*/
1022	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1023	goto ResumeExecution;
1024
1025	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1026	{
1027	Log2(("SVM: Cpuid %x\n", pCtx->eax));
1028	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1029	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1030	if (rc == VINF_SUCCESS)
1031	{
1032	/* Update EIP and continue execution. */
1033	pCtx->eip += 2; /** @note hardcoded opcode size! */
1034	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1035	goto ResumeExecution;
1036	}
1037	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1038	rc = VINF_EM_RAW_EMULATE_INSTR;
1039	break;
1040	}
1041
1042	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1043	{
1044	Log2(("SVM: invlpg\n"));
1045	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1046
1047	/* Truly a pita. Why can't SVM give the same information as VMX? */
1048	rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1049	break;
1050	}
1051
1052	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1053	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1054	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1055	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1056	{
1057	uint32_t cbSize;
1058
1059	Log2(("SVM: %VGv mov cr%d, \n", pCtx->eip, exitCode - SVM_EXIT_WRITE_CR0));
1060	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1061	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1062
1063	switch (exitCode - SVM_EXIT_WRITE_CR0)
1064	{
1065	case 0:
1066	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1067	break;
1068	case 2:
1069	break;
1070	case 3:
1071	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1072	break;
1073	case 4:
1074	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1075	break;
1076	default:
1077	AssertFailed();
1078	}
1079	/* Check if a sync operation is pending. */
1080	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1081	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1082	{
1083	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1084	AssertRC(rc);
1085
1086	/** @note Force a TLB flush. SVM requires us to do it manually. */
1087	fForceTLBFlush = true;
1088	}
1089	if (rc == VINF_SUCCESS)
1090	{
1091	/* EIP has been updated already. */
1092
1093	/* Only resume if successful. */
1094	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1095	goto ResumeExecution;
1096	}
1097	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1098	if (rc == VERR_EM_INTERPRETER)
1099	rc = VINF_EM_RAW_EMULATE_INSTR;
1100	break;
1101	}
1102
1103	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1104	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1105	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1106	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1107	{
1108	uint32_t cbSize;
1109
1110	Log2(("SVM: %VGv mov x, cr%d\n", pCtx->eip, exitCode - SVM_EXIT_READ_CR0));
1111	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1112	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1113	if (rc == VINF_SUCCESS)
1114	{
1115	/* EIP has been updated already. */
1116
1117	/* Only resume if successful. */
1118	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1119	goto ResumeExecution;
1120	}
1121	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1122	if (rc == VERR_EM_INTERPRETER)
1123	rc = VINF_EM_RAW_EMULATE_INSTR;
1124	break;
1125	}
1126
1127	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1128	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1129	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1130	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1131	{
1132	uint32_t cbSize;
1133
1134	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_WRITE_DR0));
1135	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1136	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1137	if (rc == VINF_SUCCESS)
1138	{
1139	/* EIP has been updated already. */
1140
1141	/* Only resume if successful. */
1142	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1143	goto ResumeExecution;
1144	}
1145	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1146	if (rc == VERR_EM_INTERPRETER)
1147	rc = VINF_EM_RAW_EMULATE_INSTR;
1148	break;
1149	}
1150
1151	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1152	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1153	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1154	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1155	{
1156	uint32_t cbSize;
1157
1158	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_READ_DR0));
1159	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1160	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1161	if (rc == VINF_SUCCESS)
1162	{
1163	/* EIP has been updated already. */
1164
1165	/* Only resume if successful. */
1166	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1167	goto ResumeExecution;
1168	}
1169	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1170	if (rc == VERR_EM_INTERPRETER)
1171	rc = VINF_EM_RAW_EMULATE_INSTR;
1172	break;
1173	}
1174
1175	/** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1176	case SVM_EXIT_IOIO: /* I/O instruction. */
1177	{
1178	SVM_IOIO_EXIT IoExitInfo;
1179	uint32_t uIOSize, uAndVal;
1180
1181	IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1182
1183	/** @todo could use a lookup table here */
1184	if (IoExitInfo.n.u1OP8)
1185	{
1186	uIOSize = 1;
1187	uAndVal = 0xff;
1188	}
1189	else
1190	if (IoExitInfo.n.u1OP16)
1191	{
1192	uIOSize = 2;
1193	uAndVal = 0xffff;
1194	}
1195	else
1196	if (IoExitInfo.n.u1OP32)
1197	{
1198	uIOSize = 4;
1199	uAndVal = 0xffffffff;
1200	}
1201	else
1202	{
1203	AssertFailed(); /* should be fatal. */
1204	rc = VINF_EM_RAW_EMULATE_INSTR;
1205	break;
1206	}
1207
1208	/* First simple in and out instructions. */
1209	/** @todo str & rep */
1210	if ( !IoExitInfo.n.u1REP
1211	&& !IoExitInfo.n.u1STR
1212	)
1213	{
1214	if (IoExitInfo.n.u1Type == 0)
1215	{
1216	Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1217	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1218	rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1219	}
1220	else
1221	{
1222	uint32_t u32Val = 0;
1223
1224	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1225	rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1226	if (rc == VINF_SUCCESS)
1227	{
1228	/* Write back to the EAX register. */
1229	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1230	Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1231	}
1232	}
1233	if (rc == VINF_SUCCESS)
1234	{
1235	/* Update EIP and continue execution. */
1236	pCtx->eip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1237	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1238	goto ResumeExecution;
1239	}
1240	Assert(rc == VINF_IOM_HC_IOPORT_READ \|\| rc == VINF_IOM_HC_IOPORT_WRITE);
1241	rc = (IoExitInfo.n.u1Type == 0) ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1242	}
1243	else
1244	rc = VINF_IOM_HC_IOPORT_READWRITE;
1245
1246	Log2(("Failed IO at %VGv %x size %d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1247
1248	break;
1249	}
1250
1251	case SVM_EXIT_HLT:
1252	/** Check if external interrupts are pending; if so, don't switch back. */
1253	if (VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1254	{
1255	pCtx->eip++; /* skip hlt */
1256	goto ResumeExecution;
1257	}
1258
1259	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1260	break;
1261
1262	case SVM_EXIT_RDPMC:
1263	case SVM_EXIT_RSM:
1264	case SVM_EXIT_INVLPGA:
1265	case SVM_EXIT_VMRUN:
1266	case SVM_EXIT_VMMCALL:
1267	case SVM_EXIT_VMLOAD:
1268	case SVM_EXIT_VMSAVE:
1269	case SVM_EXIT_STGI:
1270	case SVM_EXIT_CLGI:
1271	case SVM_EXIT_SKINIT:
1272	case SVM_EXIT_RDTSCP:
1273	{
1274	/* Unsupported instructions. */
1275	SVM_EVENT Event;
1276
1277	Event.au64[0] = 0;
1278	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1279	Event.n.u1Valid = 1;
1280	Event.n.u8Vector = X86_XCPT_UD;
1281
1282	Log(("Forced #UD trap at %VGv\n", pCtx->eip));
1283	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1284
1285	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1286	goto ResumeExecution;
1287	}
1288
1289	/* Emulate RDMSR & WRMSR in ring 3. */
1290	case SVM_EXIT_MSR:
1291	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1292	break;
1293
1294	case SVM_EXIT_NPF:
1295	AssertFailed(); /* unexpected */
1296	break;
1297
1298	case SVM_EXIT_SHUTDOWN:
1299	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1300	break;
1301
1302	case SVM_EXIT_PAUSE:
1303	case SVM_EXIT_IDTR_READ:
1304	case SVM_EXIT_GDTR_READ:
1305	case SVM_EXIT_LDTR_READ:
1306	case SVM_EXIT_TR_READ:
1307	case SVM_EXIT_IDTR_WRITE:
1308	case SVM_EXIT_GDTR_WRITE:
1309	case SVM_EXIT_LDTR_WRITE:
1310	case SVM_EXIT_TR_WRITE:
1311	case SVM_EXIT_CR0_SEL_WRITE:
1312	default:
1313	/* Unexpected exit codes. */
1314	rc = VERR_EM_INTERNAL_ERROR;
1315	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
1316	break;
1317	}
1318
1319	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1320	SVM_READ_SELREG(LDTR, ldtr);
1321	SVM_READ_SELREG(TR, tr);
1322
1323	pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1324	pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1325
1326	pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1327	pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1328
1329	/*
1330	* System MSRs
1331	*/
1332	pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1333	pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1334	pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1335
1336	/* Signal changes for the recompiler. */
1337	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
1338
1339	end:
1340
1341	/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
1342	if (exitCode == SVM_EXIT_INTR)
1343	{
1344	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1345	/* On the next entry we'll only sync the host context. */
1346	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
1347	}
1348	else
1349	{
1350	/* On the next entry we'll sync everything. */
1351	/** @todo we can do better than this */
1352	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
1353	}
1354
1355	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1356	return rc;
1357	}
1358
1359	/**
1360	* Enable SVM
1361	*
1362	* @returns VBox status code.
1363	* @param pVM The VM to operate on.
1364	*/
1365	HWACCMR0DECL(int) SVMR0Enable(PVM pVM)
1366	{
1367	uint64_t val;
1368
1369	Assert(pVM->hwaccm.s.svm.fSupported);
1370
1371	/* We must turn on SVM and setup the host state physical address, as those MSRs are per-cpu/core. */
1372
1373	/* Turn on SVM in the EFER MSR. */
1374	val = ASMRdMsr(MSR_K6_EFER);
1375	if (!(val & MSR_K6_EFER_SVME))
1376	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
1377
1378	/* Write the physical page address where the CPU will store the host state while executing the VM. */
1379	ASMWrMsr(MSR_K8_VM_HSAVE_PA, pVM->hwaccm.s.svm.pHStatePhys);
1380
1381	/* Force a TLB flush on VM entry. */
1382	pVM->hwaccm.s.svm.fResumeVM = false;
1383
1384	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
1385	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_LDTR;
1386
1387	return VINF_SUCCESS;
1388	}
1389
1390
1391	/**
1392	* Disable SVM
1393	*
1394	* @returns VBox status code.
1395	* @param pVM The VM to operate on.
1396	*/
1397	HWACCMR0DECL(int) SVMR0Disable(PVM pVM)
1398	{
1399	/** @todo hopefully this is not very expensive. */
1400
1401	/* Turn off SVM in the EFER MSR. */
1402	uint64_t val = ASMRdMsr(MSR_K6_EFER);
1403	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
1404
1405	/* Invalidate host state physical address. */
1406	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
1407
1408	Assert(pVM->hwaccm.s.svm.fSupported);
1409	return VINF_SUCCESS;
1410	}
1411
1412
1413	static int svmInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1414	{
1415	OP_PARAMVAL param1;
1416	RTGCPTR addr;
1417
1418	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1419	if(VBOX_FAILURE(rc))
1420	return VERR_EM_INTERPRETER;
1421
1422	switch(param1.type)
1423	{
1424	case PARMTYPE_IMMEDIATE:
1425	case PARMTYPE_ADDRESS:
1426	if(!(param1.flags & PARAM_VAL32))
1427	return VERR_EM_INTERPRETER;
1428	addr = (RTGCPTR)param1.val.val32;
1429	break;
1430
1431	default:
1432	return VERR_EM_INTERPRETER;
1433	}
1434
1435	/** @todo is addr always a flat linear address or ds based
1436	* (in absence of segment override prefixes)????
1437	*/
1438	rc = PGMInvalidatePage(pVM, addr);
1439	if (VBOX_SUCCESS(rc))
1440	{
1441	/* Manually invalidate the page for the VM's TLB. */
1442	SVMInvlpgA(addr, uASID);
1443	return VINF_SUCCESS;
1444	}
1445	/** @todo r=bird: we shouldn't ignore returns codes like this... I'm 99% sure the error is fatal. */
1446	return VERR_EM_INTERPRETER;
1447	}
1448
1449	/**
1450	* Interprets INVLPG
1451	*
1452	* @returns VBox status code.
1453	* @retval VINF_* Scheduling instructions.
1454	* @retval VERR_EM_INTERPRETER Something we can't cope with.
1455	* @retval VERR_* Fatal errors.
1456	*
1457	* @param pVM The VM handle.
1458	* @param pRegFrame The register frame.
1459	* @param ASID Tagged TLB id for the guest
1460	*
1461	* Updates the EIP if an instruction was executed successfully.
1462	*/
1463	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1464	{
1465	/*
1466	* Only allow 32-bit code.
1467	*/
1468	if (SELMIsSelector32Bit(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid))
1469	{
1470	RTGCPTR pbCode;
1471	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pbCode);
1472	if (VBOX_SUCCESS(rc))
1473	{
1474	uint32_t cbOp;
1475	DISCPUSTATE Cpu;
1476
1477	Cpu.mode = CPUMODE_32BIT;
1478	rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
1479	Assert(VBOX_FAILURE(rc) \|\| Cpu.pCurInstr->opcode == OP_INVLPG);
1480	if (VBOX_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
1481	{
1482	Assert(cbOp == Cpu.opsize);
1483	rc = svmInterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
1484	if (VBOX_SUCCESS(rc))
1485	{
1486	pRegFrame->eip += cbOp; /* Move on to the next instruction. */
1487	}
1488	return rc;
1489	}
1490	}
1491	}
1492	return VERR_EM_INTERPRETER;
1493	}
1494

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 2166

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