VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 25931

Last change on this file since 25931 was 25931, checked in by vboxsync, 15 years ago

Added VBOX_HWVIRTEX_IGNORE_SVM_IN_USE environment variable check to enable hack for disregarding VERR_SVM_IN_USE errors (quite a few BIOSes around that incorrectly set EFER.SVME).
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 114.2 KB
Line 
1/* $Id: HWSVMR0.cpp 25931 2010-01-20 14:05:01Z vboxsync $ */
2/** @file
3 * HWACCM SVM - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/hwacc_svm.h>
32#include <VBox/pgm.h>
33#include <VBox/pdm.h>
34#include <VBox/err.h>
35#include <VBox/log.h>
36#include <VBox/selm.h>
37#include <VBox/iom.h>
38#include <VBox/dis.h>
39#include <VBox/dbgf.h>
40#include <VBox/disopcode.h>
41#include <iprt/param.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/cpuset.h>
45#include <iprt/mp.h>
46#include <iprt/time.h>
47#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
48# include <iprt/thread.h>
49#endif
50#include "HWSVMR0.h"
51
52/*******************************************************************************
53* Internal Functions *
54*******************************************************************************/
55static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID);
56static int svmR0EmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
57static void svmR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite);
58
59/*******************************************************************************
60* Global Variables *
61*******************************************************************************/
62
63/**
64 * Sets up and activates AMD-V on the current CPU
65 *
66 * @returns VBox status code.
67 * @param pCpu CPU info struct
68 * @param pVM The VM to operate on. (can be NULL after a resume!!)
69 * @param pvPageCpu Pointer to the global cpu page
70 * @param pPageCpuPhys Physical address of the global cpu page
71 */
72VMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
73{
74 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
75 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
76
77 /* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
78 uint64_t val = ASMRdMsr(MSR_K6_EFER);
79 if (val & MSR_K6_EFER_SVME)
80 {
81 /* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active, then we blindly use AMD-V. */
82 if ( pVM
83 && pVM->hwaccm.s.svm.fIgnoreInUseError)
84 {
85 pCpu->fIgnoreAMDVInUseError = true;
86 }
87
88 if (!pCpu->fIgnoreAMDVInUseError)
89 return VERR_SVM_IN_USE;
90 }
91
92 /* Turn on AMD-V in the EFER MSR. */
93 ASMWrMsr(MSR_K6_EFER, val | MSR_K6_EFER_SVME);
94
95 /* Write the physical page address where the CPU will store the host state while executing the VM. */
96 ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
97
98 return VINF_SUCCESS;
99}
100
101/**
102 * Deactivates AMD-V on the current CPU
103 *
104 * @returns VBox status code.
105 * @param pCpu CPU info struct
106 * @param pvPageCpu Pointer to the global cpu page
107 * @param pPageCpuPhys Physical address of the global cpu page
108 */
109VMMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
110{
111 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
112 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
113
114 /* Turn off AMD-V in the EFER MSR. */
115 uint64_t val = ASMRdMsr(MSR_K6_EFER);
116 ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
117
118 /* Invalidate host state physical address. */
119 ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
120
121 return VINF_SUCCESS;
122}
123
124/**
125 * Does Ring-0 per VM AMD-V init.
126 *
127 * @returns VBox status code.
128 * @param pVM The VM to operate on.
129 */
130VMMR0DECL(int) SVMR0InitVM(PVM pVM)
131{
132 int rc;
133
134 pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
135
136 /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
137 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
138 if (RT_FAILURE(rc))
139 return rc;
140
141 pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
142 pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
143 /* Set all bits to intercept all IO accesses. */
144 ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
145
146 /* Erratum 170 which requires a forced TLB flush for each world switch:
147 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
148 *
149 * All BH-G1/2 and DH-G1/2 models include a fix:
150 * Athlon X2: 0x6b 1/2
151 * 0x68 1/2
152 * Athlon 64: 0x7f 1
153 * 0x6f 2
154 * Sempron: 0x7f 1/2
155 * 0x6f 2
156 * 0x6c 2
157 * 0x7c 2
158 * Turion 64: 0x68 2
159 *
160 */
161 uint32_t u32Dummy;
162 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
163 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
164 u32BaseFamily= (u32Version >> 8) & 0xf;
165 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
166 u32Model = ((u32Version >> 4) & 0xf);
167 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
168 u32Stepping = u32Version & 0xf;
169 if ( u32Family == 0xf
170 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
171 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
172 {
173 Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
174 pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
175 }
176
177 /* Allocate VMCBs for all guest CPUs. */
178 for (VMCPUID i = 0; i < pVM->cCpus; i++)
179 {
180 PVMCPU pVCpu = &pVM->aCpus[i];
181
182 pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
183 pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
184 pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
185
186 /* Allocate one page for the host context */
187 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
188 if (RT_FAILURE(rc))
189 return rc;
190
191 pVCpu->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCBHost);
192 pVCpu->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 0);
193 Assert(pVCpu->hwaccm.s.svm.pVMCBHostPhys < _4G);
194 ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCBHost);
195
196 /* Allocate one page for the VM control block (VMCB). */
197 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
198 if (RT_FAILURE(rc))
199 return rc;
200
201 pVCpu->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCB);
202 pVCpu->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCB, 0);
203 Assert(pVCpu->hwaccm.s.svm.pVMCBPhys < _4G);
204 ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCB);
205
206 /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
207 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
208 if (RT_FAILURE(rc))
209 return rc;
210
211 pVCpu->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap);
212 pVCpu->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 0);
213 /* Set all bits to intercept all MSR accesses. */
214 ASMMemFill32(pVCpu->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
215 }
216
217 return VINF_SUCCESS;
218}
219
220/**
221 * Does Ring-0 per VM AMD-V termination.
222 *
223 * @returns VBox status code.
224 * @param pVM The VM to operate on.
225 */
226VMMR0DECL(int) SVMR0TermVM(PVM pVM)
227{
228 for (VMCPUID i = 0; i < pVM->cCpus; i++)
229 {
230 PVMCPU pVCpu = &pVM->aCpus[i];
231
232 if (pVCpu->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ)
233 {
234 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, false);
235 pVCpu->hwaccm.s.svm.pVMCBHost = 0;
236 pVCpu->hwaccm.s.svm.pVMCBHostPhys = 0;
237 pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
238 }
239
240 if (pVCpu->hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)
241 {
242 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCB, false);
243 pVCpu->hwaccm.s.svm.pVMCB = 0;
244 pVCpu->hwaccm.s.svm.pVMCBPhys = 0;
245 pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
246 }
247 if (pVCpu->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
248 {
249 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, false);
250 pVCpu->hwaccm.s.svm.pMSRBitmap = 0;
251 pVCpu->hwaccm.s.svm.pMSRBitmapPhys = 0;
252 pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
253 }
254 }
255 if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)
256 {
257 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
258 pVM->hwaccm.s.svm.pIOBitmap = 0;
259 pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
260 pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
261 }
262 return VINF_SUCCESS;
263}
264
265/**
266 * Sets up AMD-V for the specified VM
267 *
268 * @returns VBox status code.
269 * @param pVM The VM to operate on.
270 */
271VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
272{
273 int rc = VINF_SUCCESS;
274
275 AssertReturn(pVM, VERR_INVALID_PARAMETER);
276
277 Assert(pVM->hwaccm.s.svm.fSupported);
278
279 for (VMCPUID i = 0; i < pVM->cCpus; i++)
280 {
281 PVMCPU pVCpu = &pVM->aCpus[i];
282 SVM_VMCB *pVMCB = (SVM_VMCB *)pVM->aCpus[i].hwaccm.s.svm.pVMCB;
283
284 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
285
286 /* Program the control fields. Most of them never have to be changed again. */
287 /* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
288 /* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical. */
289 if (!pVM->hwaccm.s.fNestedPaging)
290 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
291 else
292 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(4);
293
294 /*
295 * CR0/3/4 writes must be intercepted for obvious reasons.
296 */
297 if (!pVM->hwaccm.s.fNestedPaging)
298 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
299 else
300 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(4) | RT_BIT(8);
301
302 /* Intercept all DRx reads and writes by default. Changed later on. */
303 pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
304 pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
305
306 /* Currently we don't care about DRx reads or writes. DRx registers are trashed.
307 * All breakpoints are automatically cleared when the VM exits.
308 */
309
310 pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
311#ifndef DEBUG
312 if (pVM->hwaccm.s.fNestedPaging)
313 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
314#endif
315
316 pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
317 | SVM_CTRL1_INTERCEPT_VINTR
318 | SVM_CTRL1_INTERCEPT_NMI
319 | SVM_CTRL1_INTERCEPT_SMI
320 | SVM_CTRL1_INTERCEPT_INIT
321 | SVM_CTRL1_INTERCEPT_RDPMC
322 | SVM_CTRL1_INTERCEPT_CPUID
323 | SVM_CTRL1_INTERCEPT_RSM
324 | SVM_CTRL1_INTERCEPT_HLT
325 | SVM_CTRL1_INTERCEPT_INOUT_BITMAP
326 | SVM_CTRL1_INTERCEPT_MSR_SHADOW
327 | SVM_CTRL1_INTERCEPT_INVLPG
328 | SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
329 | SVM_CTRL1_INTERCEPT_TASK_SWITCH
330 | SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
331 | SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
332 ;
333 /* With nested paging we don't care about invlpg anymore. */
334 if (pVM->hwaccm.s.fNestedPaging)
335 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
336
337 pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
338 | SVM_CTRL2_INTERCEPT_VMMCALL
339 | SVM_CTRL2_INTERCEPT_VMLOAD
340 | SVM_CTRL2_INTERCEPT_VMSAVE
341 | SVM_CTRL2_INTERCEPT_STGI
342 | SVM_CTRL2_INTERCEPT_CLGI
343 | SVM_CTRL2_INTERCEPT_SKINIT
344 | SVM_CTRL2_INTERCEPT_WBINVD
345 | SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
346 ;
347 Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
348 Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
349 Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
350
351 /* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
352 pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
353 /* Ignore the priority in the TPR; just deliver it when we tell it to. */
354 pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
355
356 /* Set IO and MSR bitmap addresses. */
357 pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
358 pVMCB->ctrl.u64MSRPMPhysAddr = pVCpu->hwaccm.s.svm.pMSRBitmapPhys;
359
360 /* No LBR virtualization. */
361 pVMCB->ctrl.u64LBRVirt = 0;
362
363 /** The ASID must start at 1; the host uses 0. */
364 pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
365
366 /** Setup the PAT msr (nested paging only) */
367 pVMCB->guest.u64GPAT = 0x0007040600070406ULL;
368
369 /* The following MSRs are saved automatically by vmload/vmsave, so we allow the guest
370 * to modify them directly.
371 */
372 svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
373 svmR0SetMSRPermission(pVCpu, MSR_K8_CSTAR, true, true);
374 svmR0SetMSRPermission(pVCpu, MSR_K6_STAR, true, true);
375 svmR0SetMSRPermission(pVCpu, MSR_K8_SF_MASK, true, true);
376 svmR0SetMSRPermission(pVCpu, MSR_K8_FS_BASE, true, true);
377 svmR0SetMSRPermission(pVCpu, MSR_K8_GS_BASE, true, true);
378 svmR0SetMSRPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, true, true);
379 svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_CS, true, true);
380 svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_ESP, true, true);
381 svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_EIP, true, true);
382 }
383
384 return rc;
385}
386
387
388/**
389 * Sets the permission bits for the specified MSR
390 *
391 * @param pVCpu The VMCPU to operate on.
392 * @param ulMSR MSR value
393 * @param fRead Reading allowed/disallowed
394 * @param fWrite Writing allowed/disallowed
395 */
396static void svmR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite)
397{
398 unsigned ulBit;
399 uint8_t *pMSRBitmap = (uint8_t *)pVCpu->hwaccm.s.svm.pMSRBitmap;
400
401 if (ulMSR <= 0x00001FFF)
402 {
403 /* Pentium-compatible MSRs */
404 ulBit = ulMSR * 2;
405 }
406 else
407 if ( ulMSR >= 0xC0000000
408 && ulMSR <= 0xC0001FFF)
409 {
410 /* AMD Sixth Generation x86 Processor MSRs and SYSCALL */
411 ulBit = (ulMSR - 0xC0000000) * 2;
412 pMSRBitmap += 0x800;
413 }
414 else
415 if ( ulMSR >= 0xC0010000
416 && ulMSR <= 0xC0011FFF)
417 {
418 /* AMD Seventh and Eighth Generation Processor MSRs */
419 ulBit = (ulMSR - 0xC0001000) * 2;
420 pMSRBitmap += 0x1000;
421 }
422 else
423 {
424 AssertFailed();
425 return;
426 }
427 Assert(ulBit < 16 * 1024 - 1);
428 if (fRead)
429 ASMBitClear(pMSRBitmap, ulBit);
430 else
431 ASMBitSet(pMSRBitmap, ulBit);
432
433 if (fWrite)
434 ASMBitClear(pMSRBitmap, ulBit + 1);
435 else
436 ASMBitSet(pMSRBitmap, ulBit + 1);
437}
438
439/**
440 * Injects an event (trap or external interrupt)
441 *
442 * @param pVCpu The VMCPU to operate on.
443 * @param pVMCB SVM control block
444 * @param pCtx CPU Context
445 * @param pIntInfo SVM interrupt info
446 */
447inline void SVMR0InjectEvent(PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx, SVM_EVENT* pEvent)
448{
449#ifdef VBOX_WITH_STATISTICS
450 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
451#endif
452
453#ifdef VBOX_STRICT
454 if (pEvent->n.u8Vector == 0xE)
455 Log(("SVM: Inject int %d at %RGv error code=%02x CR2=%RGv intInfo=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode, (RTGCPTR)pCtx->cr2, pEvent->au64[0]));
456 else
457 if (pEvent->n.u8Vector < 0x20)
458 Log(("SVM: Inject int %d at %RGv error code=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode));
459 else
460 {
461 Log(("INJ-EI: %x at %RGv\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip));
462 Assert(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
463 Assert(pCtx->eflags.u32 & X86_EFL_IF);
464 }
465#endif
466
467 /* Set event injection state. */
468 pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
469}
470
471
472/**
473 * Checks for pending guest interrupts and injects them
474 *
475 * @returns VBox status code.
476 * @param pVM The VM to operate on.
477 * @param pVCpu The VM CPU to operate on.
478 * @param pVMCB SVM control block
479 * @param pCtx CPU Context
480 */
481static int SVMR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx)
482{
483 int rc;
484
485 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
486 if (pVCpu->hwaccm.s.Event.fPending)
487 {
488 SVM_EVENT Event;
489
490 Log(("Reinjecting event %08x %08x at %RGv\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip));
491 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
492 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
493 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
494
495 pVCpu->hwaccm.s.Event.fPending = false;
496 return VINF_SUCCESS;
497 }
498
499 /* If an active trap is already pending, then we must forward it first! */
500 if (!TRPMHasTrap(pVCpu))
501 {
502 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI))
503 {
504 SVM_EVENT Event;
505
506 Log(("CPU%d: injecting #NMI\n", pVCpu->idCpu));
507 Event.n.u8Vector = X86_XCPT_NMI;
508 Event.n.u1Valid = 1;
509 Event.n.u32ErrorCode = 0;
510 Event.n.u3Type = SVM_EVENT_NMI;
511
512 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
513 return VINF_SUCCESS;
514 }
515
516 /* @todo SMI interrupts. */
517
518 /* When external interrupts are pending, we should exit the VM when IF is set. */
519 if (VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
520 {
521 if ( !(pCtx->eflags.u32 & X86_EFL_IF)
522 || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
523 {
524 if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
525 {
526 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
527 LogFlow(("Enable irq window exit!\n"));
528 else
529 Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", (RTGCPTR)pCtx->rip));
530
531 /** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
532 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_VINTR;
533 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
534 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
535 }
536 }
537 else
538 {
539 uint8_t u8Interrupt;
540
541 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
542 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
543 if (RT_SUCCESS(rc))
544 {
545 rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
546 AssertRC(rc);
547 }
548 else
549 {
550 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
551 Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)));
552 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
553 /* Just continue */
554 }
555 }
556 }
557 }
558
559#ifdef VBOX_STRICT
560 if (TRPMHasTrap(pVCpu))
561 {
562 uint8_t u8Vector;
563 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
564 AssertRC(rc);
565 }
566#endif
567
568 if ( (pCtx->eflags.u32 & X86_EFL_IF)
569 && (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
570 && TRPMHasTrap(pVCpu)
571 )
572 {
573 uint8_t u8Vector;
574 int rc;
575 TRPMEVENT enmType;
576 SVM_EVENT Event;
577 RTGCUINT u32ErrorCode;
578
579 Event.au64[0] = 0;
580
581 /* If a new event is pending, then dispatch it now. */
582 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &u32ErrorCode, 0);
583 AssertRC(rc);
584 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
585 Assert(enmType != TRPM_SOFTWARE_INT);
586
587 /* Clear the pending trap. */
588 rc = TRPMResetTrap(pVCpu);
589 AssertRC(rc);
590
591 Event.n.u8Vector = u8Vector;
592 Event.n.u1Valid = 1;
593 Event.n.u32ErrorCode = u32ErrorCode;
594
595 if (enmType == TRPM_TRAP)
596 {
597 switch (u8Vector) {
598 case 8:
599 case 10:
600 case 11:
601 case 12:
602 case 13:
603 case 14:
604 case 17:
605 /* Valid error codes. */
606 Event.n.u1ErrorCodeValid = 1;
607 break;
608 default:
609 break;
610 }
611 if (u8Vector == X86_XCPT_NMI)
612 Event.n.u3Type = SVM_EVENT_NMI;
613 else
614 Event.n.u3Type = SVM_EVENT_EXCEPTION;
615 }
616 else
617 Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
618
619 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
620 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
621 } /* if (interrupts can be dispatched) */
622
623 return VINF_SUCCESS;
624}
625
626/**
627 * Save the host state
628 *
629 * @returns VBox status code.
630 * @param pVM The VM to operate on.
631 * @param pVCpu The VM CPU to operate on.
632 */
633VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
634{
635 NOREF(pVM);
636 NOREF(pVCpu);
637 /* Nothing to do here. */
638 return VINF_SUCCESS;
639}
640
641/**
642 * Loads the guest state
643 *
644 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
645 *
646 * @returns VBox status code.
647 * @param pVM The VM to operate on.
648 * @param pVCpu The VM CPU to operate on.
649 * @param pCtx Guest context
650 */
651VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
652{
653 RTGCUINTPTR val;
654 SVM_VMCB *pVMCB;
655
656 if (pVM == NULL)
657 return VERR_INVALID_PARAMETER;
658
659 /* Setup AMD SVM. */
660 Assert(pVM->hwaccm.s.svm.fSupported);
661
662 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
663 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
664
665 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
666 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
667 {
668 SVM_WRITE_SELREG(CS, cs);
669 SVM_WRITE_SELREG(SS, ss);
670 SVM_WRITE_SELREG(DS, ds);
671 SVM_WRITE_SELREG(ES, es);
672 SVM_WRITE_SELREG(FS, fs);
673 SVM_WRITE_SELREG(GS, gs);
674 }
675
676 /* Guest CPU context: LDTR. */
677 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
678 {
679 SVM_WRITE_SELREG(LDTR, ldtr);
680 }
681
682 /* Guest CPU context: TR. */
683 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
684 {
685 SVM_WRITE_SELREG(TR, tr);
686 }
687
688 /* Guest CPU context: GDTR. */
689 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
690 {
691 pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
692 pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
693 }
694
695 /* Guest CPU context: IDTR. */
696 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
697 {
698 pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
699 pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
700 }
701
702 /*
703 * Sysenter MSRs (unconditional)
704 */
705 pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
706 pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
707 pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
708
709 /* Control registers */
710 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
711 {
712 val = pCtx->cr0;
713 if (!CPUMIsGuestFPUStateActive(pVCpu))
714 {
715 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
716 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
717 }
718 else
719 {
720 /** @todo check if we support the old style mess correctly. */
721 if (!(val & X86_CR0_NE))
722 {
723 Log(("Forcing X86_CR0_NE!!!\n"));
724
725 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
726 if (!pVCpu->hwaccm.s.fFPUOldStyleOverride)
727 {
728 pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_MF);
729 pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
730 }
731 }
732 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
733 }
734 /* Always enable caching. */
735 val &= ~(X86_CR0_CD|X86_CR0_NW);
736
737 /* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
738 /* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
739 if (!pVM->hwaccm.s.fNestedPaging)
740 {
741 val |= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
742 val |= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
743 }
744 pVMCB->guest.u64CR0 = val;
745 }
746 /* CR2 as well */
747 pVMCB->guest.u64CR2 = pCtx->cr2;
748
749 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
750 {
751 /* Save our shadow CR3 register. */
752 if (pVM->hwaccm.s.fNestedPaging)
753 {
754 PGMMODE enmShwPagingMode;
755
756#if HC_ARCH_BITS == 32
757 if (CPUMIsGuestInLongModeEx(pCtx))
758 enmShwPagingMode = PGMMODE_AMD64_NX;
759 else
760#endif
761 enmShwPagingMode = PGMGetHostMode(pVM);
762
763 pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
764 Assert(pVMCB->ctrl.u64NestedPagingCR3);
765 pVMCB->guest.u64CR3 = pCtx->cr3;
766 }
767 else
768 {
769 pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
770 Assert(pVMCB->guest.u64CR3 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
771 }
772 }
773
774 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
775 {
776 val = pCtx->cr4;
777 if (!pVM->hwaccm.s.fNestedPaging)
778 {
779 switch(pVCpu->hwaccm.s.enmShadowMode)
780 {
781 case PGMMODE_REAL:
782 case PGMMODE_PROTECTED: /* Protected mode, no paging. */
783 AssertFailed();
784 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
785
786 case PGMMODE_32_BIT: /* 32-bit paging. */
787 val &= ~X86_CR4_PAE;
788 break;
789
790 case PGMMODE_PAE: /* PAE paging. */
791 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
792 /** @todo use normal 32 bits paging */
793 val |= X86_CR4_PAE;
794 break;
795
796 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
797 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
798#ifdef VBOX_ENABLE_64_BITS_GUESTS
799 break;
800#else
801 AssertFailed();
802 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
803#endif
804
805 default: /* shut up gcc */
806 AssertFailed();
807 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
808 }
809 }
810 pVMCB->guest.u64CR4 = val;
811 }
812
813 /* Debug registers. */
814 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
815 {
816 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
817 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
818
819 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
820 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
821 pCtx->dr[7] |= 0x400; /* must be one */
822
823 pVMCB->guest.u64DR7 = pCtx->dr[7];
824 pVMCB->guest.u64DR6 = pCtx->dr[6];
825
826#ifdef DEBUG
827 /* Sync the hypervisor debug state now if any breakpoint is armed. */
828 if ( CPUMGetHyperDR7(pVCpu) & (X86_DR7_ENABLED_MASK|X86_DR7_GD)
829 && !CPUMIsHyperDebugStateActive(pVCpu)
830 && !DBGFIsStepping(pVCpu))
831 {
832 /* Save the host and load the hypervisor debug state. */
833 int rc = CPUMR0LoadHyperDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
834 AssertRC(rc);
835
836 /* DRx intercepts remain enabled. */
837
838 /* Override dr6 & dr7 with the hypervisor values. */
839 pVMCB->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
840 pVMCB->guest.u64DR6 = CPUMGetHyperDR6(pVCpu);
841 }
842 else
843#endif
844 /* Sync the debug state now if any breakpoint is armed. */
845 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
846 && !CPUMIsGuestDebugStateActive(pVCpu)
847 && !DBGFIsStepping(pVCpu))
848 {
849 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
850
851 /* Disable drx move intercepts. */
852 pVMCB->ctrl.u16InterceptRdDRx = 0;
853 pVMCB->ctrl.u16InterceptWrDRx = 0;
854
855 /* Save the host and load the guest debug state. */
856 int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
857 AssertRC(rc);
858 }
859 }
860
861 /* EIP, ESP and EFLAGS */
862 pVMCB->guest.u64RIP = pCtx->rip;
863 pVMCB->guest.u64RSP = pCtx->rsp;
864 pVMCB->guest.u64RFlags = pCtx->eflags.u32;
865
866 /* Set CPL */
867 pVMCB->guest.u8CPL = pCtx->csHid.Attr.n.u2Dpl;
868
869 /* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
870 pVMCB->guest.u64RAX = pCtx->rax;
871
872 /* vmrun will fail without MSR_K6_EFER_SVME. */
873 pVMCB->guest.u64EFER = pCtx->msrEFER | MSR_K6_EFER_SVME;
874
875 /* 64 bits guest mode? */
876 if (CPUMIsGuestInLongModeEx(pCtx))
877 {
878#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
879 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
880#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
881 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
882#else
883# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
884 if (!pVM->hwaccm.s.fAllow64BitGuests)
885 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
886# endif
887 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun64;
888#endif
889 /* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
890 pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
891 pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
892 }
893 else
894 {
895 /* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
896 pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
897
898 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun;
899 }
900
901 /* TSC offset. */
902 if (TMCpuTickCanUseRealTSC(pVCpu, &pVMCB->ctrl.u64TSCOffset))
903 {
904 uint64_t u64CurTSC = ASMReadTSC();
905 if (u64CurTSC + pVMCB->ctrl.u64TSCOffset >= TMCpuTickGetLastSeen(pVCpu))
906 {
907 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
908 pVMCB->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
909 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
910 }
911 else
912 {
913 /* Fall back to rdtsc emulation as we would otherwise pass decreasing tsc values to the guest. */
914 LogFlow(("TSC %RX64 offset %RX64 time=%RX64 last=%RX64 (diff=%RX64, virt_tsc=%RX64)\n", u64CurTSC, pVMCB->ctrl.u64TSCOffset, u64CurTSC + pVMCB->ctrl.u64TSCOffset, TMCpuTickGetLastSeen(pVCpu), TMCpuTickGetLastSeen(pVCpu) - u64CurTSC - pVMCB->ctrl.u64TSCOffset, TMCpuTickGet(pVCpu)));
915 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
916 pVMCB->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;
917 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow);
918 }
919 }
920 else
921 {
922 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
923 pVMCB->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;
924 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
925 }
926
927 /* Sync the various msrs for 64 bits mode. */
928 pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
929 pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
930 pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
931 pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
932 pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
933
934#ifdef DEBUG
935 /* Intercept X86_XCPT_DB if stepping is enabled */
936 if ( DBGFIsStepping(pVCpu)
937 || CPUMIsHyperDebugStateActive(pVCpu))
938 pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_DB);
939 else
940 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_DB);
941#endif
942
943 /* Done. */
944 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
945
946 return VINF_SUCCESS;
947}
948
949
950/**
951 * Runs guest code in an AMD-V VM.
952 *
953 * @returns VBox status code.
954 * @param pVM The VM to operate on.
955 * @param pVCpu The VM CPU to operate on.
956 * @param pCtx Guest context
957 */
958VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
959{
960 int rc = VINF_SUCCESS;
961 uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
962 SVM_VMCB *pVMCB;
963 bool fSyncTPR = false;
964 unsigned cResume = 0;
965 uint8_t u8LastTPR;
966 PHWACCM_CPUINFO pCpu = 0;
967 RTCCUINTREG uOldEFlags = ~(RTCCUINTREG)0;
968#ifdef VBOX_STRICT
969 RTCPUID idCpuCheck;
970#endif
971#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
972 uint64_t u64LastTime = RTTimeMilliTS();
973#endif
974
975 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
976
977 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
978 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
979
980 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
981 */
982ResumeExecution:
983 Assert(!HWACCMR0SuspendPending());
984
985 /* Safety precaution; looping for too long here can have a very bad effect on the host */
986 if (RT_UNLIKELY(++cResume > pVM->hwaccm.s.cMaxResumeLoops))
987 {
988 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
989 rc = VINF_EM_RAW_INTERRUPT;
990 goto end;
991 }
992
993 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
994 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
995 {
996 Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
997 if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
998 {
999 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1000 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1001 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1002 * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
1003 */
1004 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1005 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
1006 pVMCB->ctrl.u64IntShadow = 0;
1007 }
1008 }
1009 else
1010 {
1011 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
1012 pVMCB->ctrl.u64IntShadow = 0;
1013 }
1014
1015#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
1016 if (RT_UNLIKELY(cResume & 0xf) == 0)
1017 {
1018 uint64_t u64CurTime = RTTimeMilliTS();
1019
1020 if (RT_UNLIKELY(u64CurTime > u64LastTime))
1021 {
1022 u64LastTime = u64CurTime;
1023 TMTimerPollVoid(pVM, pVCpu);
1024 }
1025 }
1026#endif
1027
1028 /* Check for pending actions that force us to go back to ring 3. */
1029#ifdef DEBUG
1030 /* Intercept X86_XCPT_DB if stepping is enabled */
1031 if (!DBGFIsStepping(pVCpu))
1032#endif
1033 {
1034 if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK)
1035 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
1036 {
1037 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
1038 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
1039 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1040 rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
1041 goto end;
1042 }
1043 }
1044
1045 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1046 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
1047 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
1048 {
1049 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1050 rc = VINF_EM_PENDING_REQUEST;
1051 goto end;
1052 }
1053
1054#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1055 /*
1056 * Exit to ring-3 preemption/work is pending.
1057 *
1058 * Interrupts are disabled before the call to make sure we don't miss any interrupt
1059 * that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
1060 * further down, but SVMR0CheckPendingInterrupt makes that impossible.)
1061 *
1062 * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
1063 * shootdowns rely on this.
1064 */
1065 uOldEFlags = ASMIntDisableFlags();
1066 if (RTThreadPreemptIsPending(NIL_RTTHREAD))
1067 {
1068 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);
1069 rc = VINF_EM_RAW_INTERRUPT;
1070 goto end;
1071 }
1072 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1073#endif
1074
1075 /* When external interrupts are pending, we should exit the VM when IF is set. */
1076 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
1077 rc = SVMR0CheckPendingInterrupt(pVM, pVCpu, pVMCB, pCtx);
1078 if (RT_FAILURE(rc))
1079 {
1080 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1081 goto end;
1082 }
1083
1084 /* TPR caching using CR8 is only available in 64 bits mode or with 32 bits guests when X86_CPUID_AMD_FEATURE_ECX_CR8L is supported. */
1085 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! (no longer true)
1086 * @todo query and update the TPR only when it could have been changed (mmio access)
1087 */
1088 if (pVM->hwaccm.s.fHasIoApic)
1089 {
1090 bool fPending;
1091
1092 /* TPR caching in CR8 */
1093 int rc = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);
1094 AssertRC(rc);
1095
1096 if (pVM->hwaccm.s.fTPRPatchingActive)
1097 {
1098 /* Our patch code uses LSTAR for TPR caching. */
1099 pCtx->msrLSTAR = u8LastTPR;
1100
1101 if (fPending)
1102 {
1103 /* A TPR change could activate a pending interrupt, so catch lstar writes. */
1104 svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, false);
1105 }
1106 else
1107 /* No interrupts are pending, so we don't need to be explicitely notified.
1108 * There are enough world switches for detecting pending interrupts.
1109 */
1110 svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
1111 }
1112 else
1113 {
1114 pVMCB->ctrl.IntCtrl.n.u8VTPR = (u8LastTPR >> 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1115
1116 if (fPending)
1117 {
1118 /* A TPR change could activate a pending interrupt, so catch cr8 writes. */
1119 pVMCB->ctrl.u16InterceptWrCRx |= RT_BIT(8);
1120 }
1121 else
1122 /* No interrupts are pending, so we don't need to be explicitely notified.
1123 * There are enough world switches for detecting pending interrupts.
1124 */
1125 pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1126 }
1127 fSyncTPR = !fPending;
1128 }
1129
1130 /* All done! Let's start VM execution. */
1131 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, x);
1132
1133 /* Enable nested paging if necessary (disabled each time after #VMEXIT). */
1134 pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
1135
1136#ifdef LOG_ENABLED
1137 pCpu = HWACCMR0GetCurrentCpu();
1138 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1139 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1140 {
1141 if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
1142 LogFlow(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
1143 else
1144 LogFlow(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1145 }
1146 if (pCpu->fFlushTLB)
1147 LogFlow(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
1148#endif
1149
1150 /*
1151 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1152 * (until the actual world switch)
1153 */
1154#ifdef VBOX_STRICT
1155 idCpuCheck = RTMpCpuId();
1156#endif
1157 VMMR0LogFlushDisable(pVCpu);
1158
1159 /* Load the guest state; *must* be here as it sets up the shadow cr0 for lazy fpu syncing! */
1160 rc = SVMR0LoadGuestState(pVM, pVCpu, pCtx);
1161 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1162 {
1163 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1164 VMMR0LogFlushEnable(pVCpu);
1165 goto end;
1166 }
1167
1168#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1169 /* Disable interrupts to make sure a poke will interrupt execution.
1170 * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
1171 */
1172 uOldEFlags = ASMIntDisableFlags();
1173 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1174#endif
1175
1176 pCpu = HWACCMR0GetCurrentCpu();
1177 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1178 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1179 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1180 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1181 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1182 {
1183 /* Force a TLB flush on VM entry. */
1184 pVCpu->hwaccm.s.fForceTLBFlush = true;
1185 }
1186 else
1187 Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1188
1189 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1190
1191 /** Set TLB flush state as checked until we return from the world switch. */
1192 ASMAtomicWriteU8(&pVCpu->hwaccm.s.fCheckedTLBFlush, true);
1193
1194 /* Check for tlb shootdown flushes. */
1195 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1196 pVCpu->hwaccm.s.fForceTLBFlush = true;
1197
1198 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1199 if ( pVCpu->hwaccm.s.fForceTLBFlush
1200 && !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
1201 {
1202 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1203 || pCpu->fFlushTLB)
1204 {
1205 pCpu->fFlushTLB = false;
1206 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1207 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
1208 pCpu->cTLBFlushes++;
1209 }
1210 else
1211 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1212
1213 pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1214 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1215 }
1216 else
1217 {
1218 Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1219
1220 /* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
1221 if (!pCpu->uCurrentASID || !pVCpu->hwaccm.s.uCurrentASID)
1222 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
1223
1224 Assert(!pVM->hwaccm.s.svm.fAlwaysFlushTLB || pVCpu->hwaccm.s.fForceTLBFlush);
1225 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVCpu->hwaccm.s.fForceTLBFlush;
1226
1227 if ( !pVM->hwaccm.s.svm.fAlwaysFlushTLB
1228 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1229 {
1230 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1231 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1232 for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1233 SVMR0InvlpgA(pVCpu->hwaccm.s.TlbShootdown.aPages[i], pVMCB->ctrl.TLBCtrl.n.u32ASID);
1234 }
1235 }
1236 pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1237 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1238
1239 AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1240 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1241 AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1242 pVMCB->ctrl.TLBCtrl.n.u32ASID = pVCpu->hwaccm.s.uCurrentASID;
1243
1244#ifdef VBOX_WITH_STATISTICS
1245 if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
1246 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1247 else
1248 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1249#endif
1250
1251 /* In case we execute a goto ResumeExecution later on. */
1252 pVCpu->hwaccm.s.fResumeVM = true;
1253 pVCpu->hwaccm.s.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
1254
1255 Assert(sizeof(pVCpu->hwaccm.s.svm.pVMCBPhys) == 8);
1256 Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
1257 Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
1258 Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVCpu->hwaccm.s.svm.pMSRBitmapPhys);
1259 Assert(pVMCB->ctrl.u64LBRVirt == 0);
1260
1261#ifdef VBOX_STRICT
1262 Assert(idCpuCheck == RTMpCpuId());
1263#endif
1264 TMNotifyStartOfExecution(pVCpu);
1265#ifdef VBOX_WITH_KERNEL_USING_XMM
1266 hwaccmR0SVMRunWrapXMM(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu, pVCpu->hwaccm.s.svm.pfnVMRun);
1267#else
1268 pVCpu->hwaccm.s.svm.pfnVMRun(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu);
1269#endif
1270 ASMAtomicWriteU8(&pVCpu->hwaccm.s.fCheckedTLBFlush, false);
1271 ASMAtomicIncU32(&pVCpu->hwaccm.s.cWorldSwitchExit);
1272 /* Possibly the last TSC value seen by the guest (too high) (only when we're in tsc offset mode). */
1273 if (!(pVMCB->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
1274 TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVMCB->ctrl.u64TSCOffset - 0x400 /* guestimate of world switch overhead in clock ticks */);
1275 TMNotifyEndOfExecution(pVCpu);
1276 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
1277 ASMSetFlags(uOldEFlags);
1278#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1279 uOldEFlags = ~(RTCCUINTREG)0;
1280#endif
1281 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, x);
1282
1283 /*
1284 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1285 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1286 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1287 */
1288
1289 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, x);
1290
1291 /* Reason for the VM exit */
1292 exitCode = pVMCB->ctrl.u64ExitCode;
1293
1294 if (RT_UNLIKELY(exitCode == (uint64_t)SVM_EXIT_INVALID)) /* Invalid guest state. */
1295 {
1296 HWACCMDumpRegs(pVM, pVCpu, pCtx);
1297#ifdef DEBUG
1298 Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
1299 Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
1300 Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
1301 Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
1302 Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
1303 Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
1304 Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
1305 Log(("ctrl.u64IOPMPhysAddr %RX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
1306 Log(("ctrl.u64MSRPMPhysAddr %RX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
1307 Log(("ctrl.u64TSCOffset %RX64\n", pVMCB->ctrl.u64TSCOffset));
1308
1309 Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
1310 Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
1311 Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
1312 Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
1313
1314 Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
1315 Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
1316 Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
1317 Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
1318 Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
1319 Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
1320 Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
1321 Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
1322 Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
1323 Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
1324
1325 Log(("ctrl.u64IntShadow %RX64\n", pVMCB->ctrl.u64IntShadow));
1326 Log(("ctrl.u64ExitCode %RX64\n", pVMCB->ctrl.u64ExitCode));
1327 Log(("ctrl.u64ExitInfo1 %RX64\n", pVMCB->ctrl.u64ExitInfo1));
1328 Log(("ctrl.u64ExitInfo2 %RX64\n", pVMCB->ctrl.u64ExitInfo2));
1329 Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
1330 Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
1331 Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
1332 Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
1333 Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
1334 Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
1335 Log(("ctrl.NestedPaging %RX64\n", pVMCB->ctrl.NestedPaging.au64));
1336 Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
1337 Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
1338 Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
1339 Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
1340 Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
1341 Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
1342
1343 Log(("ctrl.u64NestedPagingCR3 %RX64\n", pVMCB->ctrl.u64NestedPagingCR3));
1344 Log(("ctrl.u64LBRVirt %RX64\n", pVMCB->ctrl.u64LBRVirt));
1345
1346 Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
1347 Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1348 Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1349 Log(("guest.CS.u64Base %RX64\n", pVMCB->guest.CS.u64Base));
1350 Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1351 Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1352 Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1353 Log(("guest.DS.u64Base %RX64\n", pVMCB->guest.DS.u64Base));
1354 Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1355 Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1356 Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1357 Log(("guest.ES.u64Base %RX64\n", pVMCB->guest.ES.u64Base));
1358 Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1359 Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1360 Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1361 Log(("guest.FS.u64Base %RX64\n", pVMCB->guest.FS.u64Base));
1362 Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1363 Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1364 Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1365 Log(("guest.GS.u64Base %RX64\n", pVMCB->guest.GS.u64Base));
1366
1367 Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1368 Log(("guest.GDTR.u64Base %RX64\n", pVMCB->guest.GDTR.u64Base));
1369
1370 Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1371 Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1372 Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1373 Log(("guest.LDTR.u64Base %RX64\n", pVMCB->guest.LDTR.u64Base));
1374
1375 Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1376 Log(("guest.IDTR.u64Base %RX64\n", pVMCB->guest.IDTR.u64Base));
1377
1378 Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1379 Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1380 Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1381 Log(("guest.TR.u64Base %RX64\n", pVMCB->guest.TR.u64Base));
1382
1383 Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1384 Log(("guest.u64CR0 %RX64\n", pVMCB->guest.u64CR0));
1385 Log(("guest.u64CR2 %RX64\n", pVMCB->guest.u64CR2));
1386 Log(("guest.u64CR3 %RX64\n", pVMCB->guest.u64CR3));
1387 Log(("guest.u64CR4 %RX64\n", pVMCB->guest.u64CR4));
1388 Log(("guest.u64DR6 %RX64\n", pVMCB->guest.u64DR6));
1389 Log(("guest.u64DR7 %RX64\n", pVMCB->guest.u64DR7));
1390
1391 Log(("guest.u64RIP %RX64\n", pVMCB->guest.u64RIP));
1392 Log(("guest.u64RSP %RX64\n", pVMCB->guest.u64RSP));
1393 Log(("guest.u64RAX %RX64\n", pVMCB->guest.u64RAX));
1394 Log(("guest.u64RFlags %RX64\n", pVMCB->guest.u64RFlags));
1395
1396 Log(("guest.u64SysEnterCS %RX64\n", pVMCB->guest.u64SysEnterCS));
1397 Log(("guest.u64SysEnterEIP %RX64\n", pVMCB->guest.u64SysEnterEIP));
1398 Log(("guest.u64SysEnterESP %RX64\n", pVMCB->guest.u64SysEnterESP));
1399
1400 Log(("guest.u64EFER %RX64\n", pVMCB->guest.u64EFER));
1401 Log(("guest.u64STAR %RX64\n", pVMCB->guest.u64STAR));
1402 Log(("guest.u64LSTAR %RX64\n", pVMCB->guest.u64LSTAR));
1403 Log(("guest.u64CSTAR %RX64\n", pVMCB->guest.u64CSTAR));
1404 Log(("guest.u64SFMASK %RX64\n", pVMCB->guest.u64SFMASK));
1405 Log(("guest.u64KernelGSBase %RX64\n", pVMCB->guest.u64KernelGSBase));
1406 Log(("guest.u64GPAT %RX64\n", pVMCB->guest.u64GPAT));
1407 Log(("guest.u64DBGCTL %RX64\n", pVMCB->guest.u64DBGCTL));
1408 Log(("guest.u64BR_FROM %RX64\n", pVMCB->guest.u64BR_FROM));
1409 Log(("guest.u64BR_TO %RX64\n", pVMCB->guest.u64BR_TO));
1410 Log(("guest.u64LASTEXCPFROM %RX64\n", pVMCB->guest.u64LASTEXCPFROM));
1411 Log(("guest.u64LASTEXCPTO %RX64\n", pVMCB->guest.u64LASTEXCPTO));
1412
1413#endif
1414 rc = VERR_SVM_UNABLE_TO_START_VM;
1415 VMMR0LogFlushEnable(pVCpu);
1416 goto end;
1417 }
1418
1419 /* Let's first sync back eip, esp, and eflags. */
1420 pCtx->rip = pVMCB->guest.u64RIP;
1421 pCtx->rsp = pVMCB->guest.u64RSP;
1422 pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1423 /* eax is saved/restore across the vmrun instruction */
1424 pCtx->rax = pVMCB->guest.u64RAX;
1425
1426 /* Save all the MSRs that can be changed by the guest without causing a world switch. (fs & gs base are saved with SVM_READ_SELREG) */
1427 pCtx->msrSTAR = pVMCB->guest.u64STAR; /* legacy syscall eip, cs & ss */
1428 pCtx->msrLSTAR = pVMCB->guest.u64LSTAR; /* 64 bits mode syscall rip */
1429 pCtx->msrCSTAR = pVMCB->guest.u64CSTAR; /* compatibility mode syscall rip */
1430 pCtx->msrSFMASK = pVMCB->guest.u64SFMASK; /* syscall flag mask */
1431 pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
1432 pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1433 pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1434 pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1435
1436 /* Can be updated behind our back in the nested paging case. */
1437 pCtx->cr2 = pVMCB->guest.u64CR2;
1438
1439 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1440 SVM_READ_SELREG(SS, ss);
1441 SVM_READ_SELREG(CS, cs);
1442 SVM_READ_SELREG(DS, ds);
1443 SVM_READ_SELREG(ES, es);
1444 SVM_READ_SELREG(FS, fs);
1445 SVM_READ_SELREG(GS, gs);
1446
1447 /* Correct the hidden CS granularity flag. Haven't seen it being wrong in
1448 any other register (yet). */
1449 if ( !pCtx->csHid.Attr.n.u1Granularity
1450 && pCtx->csHid.Attr.n.u1Present
1451 && pCtx->csHid.u32Limit > UINT32_C(0xfffff))
1452 {
1453 Assert((pCtx->csHid.u32Limit & 0xfff) == 0xfff);
1454 pCtx->csHid.Attr.n.u1Granularity = 1;
1455 }
1456#define SVM_ASSERT_SEL_GRANULARITY(reg) \
1457 AssertMsg( !pCtx->reg##Hid.Attr.n.u1Present \
1458 || ( pCtx->reg##Hid.Attr.n.u1Granularity \
1459 ? (pCtx->reg##Hid.u32Limit & 0xfff) == 0xfff \
1460 : pCtx->reg##Hid.u32Limit <= 0xfffff), \
1461 ("%#x %#x %#llx\n", pCtx->reg##Hid.u32Limit, pCtx->reg##Hid.Attr.u, pCtx->reg##Hid.u64Base))
1462 SVM_ASSERT_SEL_GRANULARITY(ss);
1463 SVM_ASSERT_SEL_GRANULARITY(cs);
1464 SVM_ASSERT_SEL_GRANULARITY(ds);
1465 SVM_ASSERT_SEL_GRANULARITY(es);
1466 SVM_ASSERT_SEL_GRANULARITY(fs);
1467 SVM_ASSERT_SEL_GRANULARITY(gs);
1468#undef SVM_ASSERT_SEL_GRANULARITY
1469
1470 /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1471 SVM_READ_SELREG(LDTR, ldtr);
1472 SVM_READ_SELREG(TR, tr);
1473
1474 pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1475 pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1476
1477 pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1478 pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1479
1480 /* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1481 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1482 if ( pVM->hwaccm.s.fNestedPaging
1483 && pCtx->cr3 != pVMCB->guest.u64CR3)
1484 {
1485 CPUMSetGuestCR3(pVCpu, pVMCB->guest.u64CR3);
1486 PGMUpdateCR3(pVCpu, pVMCB->guest.u64CR3);
1487 }
1488
1489 /* Note! NOW IT'S SAFE FOR LOGGING! */
1490 VMMR0LogFlushEnable(pVCpu);
1491
1492 /* Take care of instruction fusing (sti, mov ss) (see 15.20.5 Interrupt Shadows) */
1493 if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1494 {
1495 Log(("uInterruptState %x rip=%RGv\n", pVMCB->ctrl.u64IntShadow, (RTGCPTR)pCtx->rip));
1496 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
1497 }
1498 else
1499 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1500
1501 Log2(("exitCode = %x\n", exitCode));
1502
1503 /* Sync back DR6 as it could have been changed by hitting breakpoints. */
1504 pCtx->dr[6] = pVMCB->guest.u64DR6;
1505 /* DR7.GD can be cleared by debug exceptions, so sync it back as well. */
1506 pCtx->dr[7] = pVMCB->guest.u64DR7;
1507
1508 /* Check if an injected event was interrupted prematurely. */
1509 pVCpu->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1510 if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1511 && pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1512 {
1513 Log(("Pending inject %RX64 at %RGv exit=%08x\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitCode));
1514
1515#ifdef LOG_ENABLED
1516 SVM_EVENT Event;
1517 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
1518
1519 if ( exitCode == SVM_EXIT_EXCEPTION_E
1520 && Event.n.u8Vector == 0xE)
1521 {
1522 Log(("Double fault!\n"));
1523 }
1524#endif
1525
1526 pVCpu->hwaccm.s.Event.fPending = true;
1527 /* Error code present? (redundant) */
1528 if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1529 pVCpu->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1530 else
1531 pVCpu->hwaccm.s.Event.errCode = 0;
1532 }
1533#ifdef VBOX_WITH_STATISTICS
1534 if (exitCode == SVM_EXIT_NPF)
1535 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
1536 else
1537 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1538#endif
1539
1540 /* Sync back the TPR if it was changed. */
1541 if (fSyncTPR)
1542 {
1543 if (pVM->hwaccm.s.fTPRPatchingActive)
1544 {
1545 if ((pCtx->msrLSTAR & 0xff) != u8LastTPR)
1546 {
1547 /* Our patch code uses LSTAR for TPR caching. */
1548 rc = PDMApicSetTPR(pVCpu, pCtx->msrLSTAR & 0xff);
1549 AssertRC(rc);
1550 }
1551 }
1552 else
1553 {
1554 if ((u8LastTPR >> 4) != pVMCB->ctrl.IntCtrl.n.u8VTPR)
1555 {
1556 rc = PDMApicSetTPR(pVCpu, pVMCB->ctrl.IntCtrl.n.u8VTPR << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1557 AssertRC(rc);
1558 }
1559 }
1560 }
1561
1562 /* Deal with the reason of the VM-exit. */
1563 switch (exitCode)
1564 {
1565 case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1566 case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1567 case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1568 case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1569 case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1570 case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1571 case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1572 case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1573 {
1574 /* Pending trap. */
1575 SVM_EVENT Event;
1576 uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1577
1578 Log2(("Hardware/software interrupt %d\n", vector));
1579 switch (vector)
1580 {
1581 case X86_XCPT_DB:
1582 {
1583 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
1584
1585 /* Note that we don't support guest and host-initiated debugging at the same time. */
1586 Assert(DBGFIsStepping(pVCpu) || CPUMIsHyperDebugStateActive(pVCpu));
1587
1588 rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
1589 if (rc == VINF_EM_RAW_GUEST_TRAP)
1590 {
1591 Log(("Trap %x (debug) at %016RX64\n", vector, pCtx->rip));
1592
1593 /* Reinject the exception. */
1594 Event.au64[0] = 0;
1595 Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
1596 Event.n.u1Valid = 1;
1597 Event.n.u8Vector = X86_XCPT_DB;
1598
1599 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1600
1601 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1602 goto ResumeExecution;
1603 }
1604 /* Return to ring 3 to deal with the debug exit code. */
1605 Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, rc));
1606 break;
1607 }
1608
1609 case X86_XCPT_NM:
1610 {
1611 Log(("#NM fault at %RGv\n", (RTGCPTR)pCtx->rip));
1612
1613 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1614 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1615 rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
1616 if (rc == VINF_SUCCESS)
1617 {
1618 Assert(CPUMIsGuestFPUStateActive(pVCpu));
1619 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
1620
1621 /* Continue execution. */
1622 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1623 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1624
1625 goto ResumeExecution;
1626 }
1627
1628 Log(("Forward #NM fault to the guest\n"));
1629 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
1630
1631 Event.au64[0] = 0;
1632 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1633 Event.n.u1Valid = 1;
1634 Event.n.u8Vector = X86_XCPT_NM;
1635
1636 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1637 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1638 goto ResumeExecution;
1639 }
1640
1641 case X86_XCPT_PF: /* Page fault */
1642 {
1643 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1644 RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1645
1646#ifdef DEBUG
1647 if (pVM->hwaccm.s.fNestedPaging)
1648 { /* A genuine pagefault.
1649 * Forward the trap to the guest by injecting the exception and resuming execution.
1650 */
1651 Log(("Guest page fault at %04X:%RGv cr2=%RGv error code %x rsp=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
1652 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1653
1654 /* Now we must update CR2. */
1655 pCtx->cr2 = uFaultAddress;
1656
1657 Event.au64[0] = 0;
1658 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1659 Event.n.u1Valid = 1;
1660 Event.n.u8Vector = X86_XCPT_PF;
1661 Event.n.u1ErrorCodeValid = 1;
1662 Event.n.u32ErrorCode = errCode;
1663
1664 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1665
1666 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1667 goto ResumeExecution;
1668 }
1669#endif
1670 Assert(!pVM->hwaccm.s.fNestedPaging);
1671
1672#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
1673 /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1674 if ( pVM->hwaccm.s.fTRPPatchingAllowed
1675 && (uFaultAddress & 0xfff) == 0x080
1676 && !(errCode & X86_TRAP_PF_P) /* not present */
1677 && CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
1678 && !CPUMIsGuestInLongModeEx(pCtx)
1679 && pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches))
1680 {
1681 RTGCPHYS GCPhysApicBase, GCPhys;
1682 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1683 GCPhysApicBase &= PAGE_BASE_GC_MASK;
1684
1685 rc = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL, &GCPhys);
1686 if ( rc == VINF_SUCCESS
1687 && GCPhys == GCPhysApicBase)
1688 {
1689 /* Only attempt to patch the instruction once. */
1690 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1691 if (!pPatch)
1692 {
1693 rc = VINF_EM_HWACCM_PATCH_TPR_INSTR;
1694 break;
1695 }
1696 }
1697 }
1698#endif
1699
1700 Log2(("Page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1701 /* Exit qualification contains the linear address of the page fault. */
1702 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1703 TRPMSetErrorCode(pVCpu, errCode);
1704 TRPMSetFaultAddress(pVCpu, uFaultAddress);
1705
1706 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1707 rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1708 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1709 if (rc == VINF_SUCCESS)
1710 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1711 Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1712 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1713
1714 TRPMResetTrap(pVCpu);
1715
1716 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1717 goto ResumeExecution;
1718 }
1719 else
1720 if (rc == VINF_EM_RAW_GUEST_TRAP)
1721 { /* A genuine pagefault.
1722 * Forward the trap to the guest by injecting the exception and resuming execution.
1723 */
1724 Log2(("Forward page fault to the guest\n"));
1725 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1726 /* The error code might have been changed. */
1727 errCode = TRPMGetErrorCode(pVCpu);
1728
1729 TRPMResetTrap(pVCpu);
1730
1731 /* Now we must update CR2. */
1732 pCtx->cr2 = uFaultAddress;
1733
1734 Event.au64[0] = 0;
1735 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1736 Event.n.u1Valid = 1;
1737 Event.n.u8Vector = X86_XCPT_PF;
1738 Event.n.u1ErrorCodeValid = 1;
1739 Event.n.u32ErrorCode = errCode;
1740
1741 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1742
1743 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1744 goto ResumeExecution;
1745 }
1746#ifdef VBOX_STRICT
1747 if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
1748 LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
1749#endif
1750 /* Need to go back to the recompiler to emulate the instruction. */
1751 TRPMResetTrap(pVCpu);
1752 break;
1753 }
1754
1755 case X86_XCPT_MF: /* Floating point exception. */
1756 {
1757 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
1758 if (!(pCtx->cr0 & X86_CR0_NE))
1759 {
1760 /* old style FPU error reporting needs some extra work. */
1761 /** @todo don't fall back to the recompiler, but do it manually. */
1762 rc = VINF_EM_RAW_EMULATE_INSTR;
1763 break;
1764 }
1765 Log(("Trap %x at %RGv\n", vector, (RTGCPTR)pCtx->rip));
1766
1767 Event.au64[0] = 0;
1768 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1769 Event.n.u1Valid = 1;
1770 Event.n.u8Vector = X86_XCPT_MF;
1771
1772 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1773
1774 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1775 goto ResumeExecution;
1776 }
1777
1778#ifdef VBOX_STRICT
1779 case X86_XCPT_GP: /* General protection failure exception.*/
1780 case X86_XCPT_UD: /* Unknown opcode exception. */
1781 case X86_XCPT_DE: /* Divide error. */
1782 case X86_XCPT_SS: /* Stack segment exception. */
1783 case X86_XCPT_NP: /* Segment not present exception. */
1784 {
1785 Event.au64[0] = 0;
1786 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1787 Event.n.u1Valid = 1;
1788 Event.n.u8Vector = vector;
1789
1790 switch(vector)
1791 {
1792 case X86_XCPT_GP:
1793 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
1794 Event.n.u1ErrorCodeValid = 1;
1795 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1796 break;
1797 case X86_XCPT_DE:
1798 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
1799 break;
1800 case X86_XCPT_UD:
1801 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
1802 break;
1803 case X86_XCPT_SS:
1804 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
1805 Event.n.u1ErrorCodeValid = 1;
1806 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1807 break;
1808 case X86_XCPT_NP:
1809 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
1810 Event.n.u1ErrorCodeValid = 1;
1811 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1812 break;
1813 }
1814 Log(("Trap %x at %04x:%RGv esi=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->esi));
1815 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1816
1817 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1818 goto ResumeExecution;
1819 }
1820#endif
1821 default:
1822 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1823 rc = VERR_EM_INTERNAL_ERROR;
1824 break;
1825
1826 } /* switch (vector) */
1827 break;
1828 }
1829
1830 case SVM_EXIT_NPF:
1831 {
1832 /* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1833 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1834 RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1835 PGMMODE enmShwPagingMode;
1836
1837 Assert(pVM->hwaccm.s.fNestedPaging);
1838 LogFlow(("Nested page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1839
1840#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
1841 /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1842 if ( pVM->hwaccm.s.fTRPPatchingAllowed
1843 && (uFaultAddress & 0xfff) == 0x080
1844 && !(errCode & X86_TRAP_PF_P) /* not present */
1845 && CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
1846 && !CPUMIsGuestInLongModeEx(pCtx)
1847 && pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches))
1848 {
1849 RTGCPHYS GCPhysApicBase;
1850 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1851 GCPhysApicBase &= PAGE_BASE_GC_MASK;
1852
1853 if (uFaultAddress == GCPhysApicBase + 0x80)
1854 {
1855 /* Only attempt to patch the instruction once. */
1856 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1857 if (!pPatch)
1858 {
1859 rc = VINF_EM_HWACCM_PATCH_TPR_INSTR;
1860 break;
1861 }
1862 }
1863 }
1864#endif
1865
1866 /* Exit qualification contains the linear address of the page fault. */
1867 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1868 TRPMSetErrorCode(pVCpu, errCode);
1869 TRPMSetFaultAddress(pVCpu, uFaultAddress);
1870
1871 /* Handle the pagefault trap for the nested shadow table. */
1872#if HC_ARCH_BITS == 32
1873 if (CPUMIsGuestInLongModeEx(pCtx))
1874 enmShwPagingMode = PGMMODE_AMD64_NX;
1875 else
1876#endif
1877 enmShwPagingMode = PGMGetHostMode(pVM);
1878
1879 rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmShwPagingMode, errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1880 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1881 if (rc == VINF_SUCCESS)
1882 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1883 Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1884 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1885
1886 TRPMResetTrap(pVCpu);
1887
1888 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1889 goto ResumeExecution;
1890 }
1891
1892#ifdef VBOX_STRICT
1893 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1894 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
1895#endif
1896 /* Need to go back to the recompiler to emulate the instruction. */
1897 TRPMResetTrap(pVCpu);
1898 break;
1899 }
1900
1901 case SVM_EXIT_VINTR:
1902 /* A virtual interrupt is about to be delivered, which means IF=1. */
1903 Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1904 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1905 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1906 goto ResumeExecution;
1907
1908 case SVM_EXIT_FERR_FREEZE:
1909 case SVM_EXIT_INTR:
1910 case SVM_EXIT_NMI:
1911 case SVM_EXIT_SMI:
1912 case SVM_EXIT_INIT:
1913 /* External interrupt; leave to allow it to be dispatched again. */
1914 rc = VINF_EM_RAW_INTERRUPT;
1915 break;
1916
1917 case SVM_EXIT_WBINVD:
1918 case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1919 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
1920 /* Skip instruction and continue directly. */
1921 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1922 /* Continue execution.*/
1923 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1924 goto ResumeExecution;
1925
1926 case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1927 {
1928 Log2(("SVM: Cpuid at %RGv for %x\n", (RTGCPTR)pCtx->rip, pCtx->eax));
1929 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
1930 rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1931 if (rc == VINF_SUCCESS)
1932 {
1933 /* Update EIP and continue execution. */
1934 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1935 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1936 goto ResumeExecution;
1937 }
1938 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
1939 rc = VINF_EM_RAW_EMULATE_INSTR;
1940 break;
1941 }
1942
1943 case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1944 {
1945 Log2(("SVM: Rdtsc\n"));
1946 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1947 rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1948 if (rc == VINF_SUCCESS)
1949 {
1950 /* Update EIP and continue execution. */
1951 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1952 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1953 goto ResumeExecution;
1954 }
1955 rc = VINF_EM_RAW_EMULATE_INSTR;
1956 break;
1957 }
1958
1959 case SVM_EXIT_RDPMC: /* Guest software attempted to execute RDPMC. */
1960 {
1961 Log2(("SVM: Rdpmc %x\n", pCtx->ecx));
1962 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdpmc);
1963 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1964 if (rc == VINF_SUCCESS)
1965 {
1966 /* Update EIP and continue execution. */
1967 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1968 goto ResumeExecution;
1969 }
1970 rc = VINF_EM_RAW_EMULATE_INSTR;
1971 break;
1972 }
1973
1974 case SVM_EXIT_RDTSCP: /* Guest software attempted to execute RDTSCP. */
1975 {
1976 Log2(("SVM: Rdtscp\n"));
1977 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1978 rc = EMInterpretRdtscp(pVM, pVCpu, pCtx);
1979 if (rc == VINF_SUCCESS)
1980 {
1981 /* Update EIP and continue execution. */
1982 pCtx->rip += 3; /* Note! hardcoded opcode size! */
1983 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1984 goto ResumeExecution;
1985 }
1986 AssertMsgFailed(("EMU: rdtscp failed with %Rrc\n", rc));
1987 rc = VINF_EM_RAW_EMULATE_INSTR;
1988 break;
1989 }
1990
1991 case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1992 {
1993 Log2(("SVM: invlpg\n"));
1994 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
1995
1996 Assert(!pVM->hwaccm.s.fNestedPaging);
1997
1998 /* Truly a pita. Why can't SVM give the same information as VT-x? */
1999 rc = svmR0InterpretInvpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
2000 if (rc == VINF_SUCCESS)
2001 {
2002 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushPageInvlpg);
2003 goto ResumeExecution; /* eip already updated */
2004 }
2005 break;
2006 }
2007
2008 case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
2009 case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
2010 case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
2011 case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
2012 {
2013 uint32_t cbSize;
2014
2015 Log2(("SVM: %RGv mov cr%d, \n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
2016 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[exitCode - SVM_EXIT_WRITE_CR0]);
2017 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2018
2019 switch (exitCode - SVM_EXIT_WRITE_CR0)
2020 {
2021 case 0:
2022 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2023 break;
2024 case 2:
2025 break;
2026 case 3:
2027 Assert(!pVM->hwaccm.s.fNestedPaging);
2028 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
2029 break;
2030 case 4:
2031 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
2032 break;
2033 case 8:
2034 break;
2035 default:
2036 AssertFailed();
2037 }
2038 /* Check if a sync operation is pending. */
2039 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
2040 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
2041 {
2042 rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2043 AssertRC(rc);
2044
2045 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBCRxChange);
2046
2047 /* Must be set by PGMSyncCR3 */
2048 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || PGMGetGuestMode(pVCpu) <= PGMMODE_PROTECTED || pVCpu->hwaccm.s.fForceTLBFlush,
2049 ("rc=%Rrc mode=%d fForceTLBFlush=%RTbool\n", rc, PGMGetGuestMode(pVCpu), pVCpu->hwaccm.s.fForceTLBFlush));
2050 }
2051 if (rc == VINF_SUCCESS)
2052 {
2053 /* EIP has been updated already. */
2054
2055 /* Only resume if successful. */
2056 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2057 goto ResumeExecution;
2058 }
2059 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2060 break;
2061 }
2062
2063 case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
2064 case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
2065 case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
2066 case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
2067 {
2068 uint32_t cbSize;
2069
2070 Log2(("SVM: %RGv mov x, cr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
2071 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[exitCode - SVM_EXIT_READ_CR0]);
2072 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2073 if (rc == VINF_SUCCESS)
2074 {
2075 /* EIP has been updated already. */
2076
2077 /* Only resume if successful. */
2078 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2079 goto ResumeExecution;
2080 }
2081 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2082 break;
2083 }
2084
2085 case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
2086 case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
2087 case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
2088 case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
2089 {
2090 uint32_t cbSize;
2091
2092 Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
2093 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
2094
2095 if ( !DBGFIsStepping(pVCpu)
2096 && !CPUMIsHyperDebugStateActive(pVCpu))
2097 {
2098 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2099
2100 /* Disable drx move intercepts. */
2101 pVMCB->ctrl.u16InterceptRdDRx = 0;
2102 pVMCB->ctrl.u16InterceptWrDRx = 0;
2103
2104 /* Save the host and load the guest debug state. */
2105 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2106 AssertRC(rc);
2107
2108 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2109 goto ResumeExecution;
2110 }
2111
2112 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2113 if (rc == VINF_SUCCESS)
2114 {
2115 /* EIP has been updated already. */
2116 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2117
2118 /* Only resume if successful. */
2119 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2120 goto ResumeExecution;
2121 }
2122 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2123 break;
2124 }
2125
2126 case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
2127 case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
2128 case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
2129 case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
2130 {
2131 uint32_t cbSize;
2132
2133 Log2(("SVM: %RGv mov x, dr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
2134 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
2135
2136 if (!DBGFIsStepping(pVCpu))
2137 {
2138 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2139
2140 /* Disable drx move intercepts. */
2141 pVMCB->ctrl.u16InterceptRdDRx = 0;
2142 pVMCB->ctrl.u16InterceptWrDRx = 0;
2143
2144 /* Save the host and load the guest debug state. */
2145 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2146 AssertRC(rc);
2147
2148 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2149 goto ResumeExecution;
2150 }
2151
2152 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2153 if (rc == VINF_SUCCESS)
2154 {
2155 /* EIP has been updated already. */
2156
2157 /* Only resume if successful. */
2158 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2159 goto ResumeExecution;
2160 }
2161 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2162 break;
2163 }
2164
2165 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2166 case SVM_EXIT_IOIO: /* I/O instruction. */
2167 {
2168 SVM_IOIO_EXIT IoExitInfo;
2169 uint32_t uIOSize, uAndVal;
2170
2171 IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
2172
2173 /** @todo could use a lookup table here */
2174 if (IoExitInfo.n.u1OP8)
2175 {
2176 uIOSize = 1;
2177 uAndVal = 0xff;
2178 }
2179 else
2180 if (IoExitInfo.n.u1OP16)
2181 {
2182 uIOSize = 2;
2183 uAndVal = 0xffff;
2184 }
2185 else
2186 if (IoExitInfo.n.u1OP32)
2187 {
2188 uIOSize = 4;
2189 uAndVal = 0xffffffff;
2190 }
2191 else
2192 {
2193 AssertFailed(); /* should be fatal. */
2194 rc = VINF_EM_RAW_EMULATE_INSTR;
2195 break;
2196 }
2197
2198 if (IoExitInfo.n.u1STR)
2199 {
2200 /* ins/outs */
2201 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2202
2203 /* Disassemble manually to deal with segment prefixes. */
2204 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL);
2205 if (rc == VINF_SUCCESS)
2206 {
2207 if (IoExitInfo.n.u1Type == 0)
2208 {
2209 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2210 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
2211 rc = VBOXSTRICTRC_TODO(IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize));
2212 }
2213 else
2214 {
2215 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2216 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
2217 rc = VBOXSTRICTRC_TODO(IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize));
2218 }
2219 }
2220 else
2221 rc = VINF_EM_RAW_EMULATE_INSTR;
2222 }
2223 else
2224 {
2225 /* normal in/out */
2226 Assert(!IoExitInfo.n.u1REP);
2227
2228 if (IoExitInfo.n.u1Type == 0)
2229 {
2230 Log2(("IOMIOPortWrite %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
2231 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
2232 rc = VBOXSTRICTRC_TODO(IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
2233 if (rc == VINF_IOM_HC_IOPORT_WRITE)
2234 HWACCMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
2235 }
2236 else
2237 {
2238 uint32_t u32Val = 0;
2239
2240 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
2241 rc = VBOXSTRICTRC_TODO(IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize));
2242 if (IOM_SUCCESS(rc))
2243 {
2244 /* Write back to the EAX register. */
2245 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2246 Log2(("IOMIOPortRead %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
2247 }
2248 else
2249 if (rc == VINF_IOM_HC_IOPORT_READ)
2250 HWACCMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
2251 }
2252 }
2253 /*
2254 * Handled the I/O return codes.
2255 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2256 */
2257 if (IOM_SUCCESS(rc))
2258 {
2259 /* Update EIP and continue execution. */
2260 pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
2261 if (RT_LIKELY(rc == VINF_SUCCESS))
2262 {
2263 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
2264 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
2265 {
2266 /* IO operation lookup arrays. */
2267 static uint32_t const aIOSize[4] = {1, 2, 0, 4};
2268
2269 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
2270 for (unsigned i=0;i<4;i++)
2271 {
2272 unsigned uBPLen = aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
2273
2274 if ( (IoExitInfo.n.u16Port >= pCtx->dr[i] && IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen)
2275 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
2276 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
2277 {
2278 SVM_EVENT Event;
2279
2280 Assert(CPUMIsGuestDebugStateActive(pVCpu));
2281
2282 /* Clear all breakpoint status flags and set the one we just hit. */
2283 pCtx->dr[6] &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
2284 pCtx->dr[6] |= (uint64_t)RT_BIT(i);
2285
2286 /* Note: AMD64 Architecture Programmer's Manual 13.1:
2287 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
2288 * the contents have been read.
2289 */
2290 pVMCB->guest.u64DR6 = pCtx->dr[6];
2291
2292 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2293 pCtx->dr[7] &= ~X86_DR7_GD;
2294
2295 /* Paranoia. */
2296 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2297 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2298 pCtx->dr[7] |= 0x400; /* must be one */
2299
2300 pVMCB->guest.u64DR7 = pCtx->dr[7];
2301
2302 /* Inject the exception. */
2303 Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
2304
2305 Event.au64[0] = 0;
2306 Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
2307 Event.n.u1Valid = 1;
2308 Event.n.u8Vector = X86_XCPT_DB;
2309
2310 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2311
2312 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2313 goto ResumeExecution;
2314 }
2315 }
2316 }
2317
2318 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2319 goto ResumeExecution;
2320 }
2321 Log2(("EM status from IO at %RGv %x size %d: %Rrc\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
2322 break;
2323 }
2324
2325#ifdef VBOX_STRICT
2326 if (rc == VINF_IOM_HC_IOPORT_READ)
2327 Assert(IoExitInfo.n.u1Type != 0);
2328 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2329 Assert(IoExitInfo.n.u1Type == 0);
2330 else
2331 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
2332#endif
2333 Log2(("Failed IO at %RGv %x size %d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2334 break;
2335 }
2336
2337 case SVM_EXIT_HLT:
2338 /** Check if external interrupts are pending; if so, don't switch back. */
2339 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
2340 pCtx->rip++; /* skip hlt */
2341 if ( pCtx->eflags.Bits.u1IF
2342 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
2343 goto ResumeExecution;
2344
2345 rc = VINF_EM_HALT;
2346 break;
2347
2348 case SVM_EXIT_MWAIT_UNCOND:
2349 Log2(("SVM: mwait\n"));
2350 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMwait);
2351 rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2352 if ( rc == VINF_EM_HALT
2353 || rc == VINF_SUCCESS)
2354 {
2355 /* Update EIP and continue execution. */
2356 pCtx->rip += 3; /* Note: hardcoded opcode size assumption! */
2357
2358 /** Check if external interrupts are pending; if so, don't switch back. */
2359 if ( rc == VINF_SUCCESS
2360 || ( rc == VINF_EM_HALT
2361 && pCtx->eflags.Bits.u1IF
2362 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
2363 )
2364 goto ResumeExecution;
2365 }
2366 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", rc));
2367 break;
2368
2369 case SVM_EXIT_VMMCALL:
2370 rc = svmR0EmulateTprVMMCall(pVM, pVCpu, pCtx);
2371 if (rc == VINF_SUCCESS)
2372 {
2373 goto ResumeExecution; /* rip already updated. */
2374 }
2375 /* no break */
2376
2377 case SVM_EXIT_RSM:
2378 case SVM_EXIT_INVLPGA:
2379 case SVM_EXIT_VMRUN:
2380 case SVM_EXIT_VMLOAD:
2381 case SVM_EXIT_VMSAVE:
2382 case SVM_EXIT_STGI:
2383 case SVM_EXIT_CLGI:
2384 case SVM_EXIT_SKINIT:
2385 {
2386 /* Unsupported instructions. */
2387 SVM_EVENT Event;
2388
2389 Event.au64[0] = 0;
2390 Event.n.u3Type = SVM_EVENT_EXCEPTION;
2391 Event.n.u1Valid = 1;
2392 Event.n.u8Vector = X86_XCPT_UD;
2393
2394 Log(("Forced #UD trap at %RGv\n", (RTGCPTR)pCtx->rip));
2395 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2396
2397 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2398 goto ResumeExecution;
2399 }
2400
2401 /* Emulate in ring 3. */
2402 case SVM_EXIT_MSR:
2403 {
2404 uint32_t cbSize;
2405
2406 /* When an interrupt is pending, we'll let MSR_K8_LSTAR writes fault in our TPR patch code. */
2407 if ( pVM->hwaccm.s.fTPRPatchingActive
2408 && pCtx->ecx == MSR_K8_LSTAR
2409 && pVMCB->ctrl.u64ExitInfo1 == 1 /* wrmsr */)
2410 {
2411 if ((pCtx->eax & 0xff) != u8LastTPR)
2412 {
2413 Log(("SVM: Faulting MSR_K8_LSTAR write with new TPR value %x\n", pCtx->eax & 0xff));
2414
2415 /* Our patch code uses LSTAR for TPR caching. */
2416 rc = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
2417 AssertRC(rc);
2418 }
2419
2420 /* Skip the instruction and continue. */
2421 pCtx->rip += 2; /* wrmsr = [0F 30] */
2422
2423 /* Only resume if successful. */
2424 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2425 goto ResumeExecution;
2426 }
2427
2428 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2429 STAM_COUNTER_INC((pVMCB->ctrl.u64ExitInfo1 == 0) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
2430 Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
2431 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2432 if (rc == VINF_SUCCESS)
2433 {
2434 /* EIP has been updated already. */
2435
2436 /* Only resume if successful. */
2437 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2438 goto ResumeExecution;
2439 }
2440 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
2441 break;
2442 }
2443
2444 case SVM_EXIT_TASK_SWITCH: /* too complicated to emulate, so fall back to the recompiler*/
2445 Log(("SVM_EXIT_TASK_SWITCH: exit2=%RX64\n", pVMCB->ctrl.u64ExitInfo2));
2446 if ( !(pVMCB->ctrl.u64ExitInfo2 & (SVM_EXIT2_TASK_SWITCH_IRET | SVM_EXIT2_TASK_SWITCH_JMP))
2447 && pVCpu->hwaccm.s.Event.fPending)
2448 {
2449 SVM_EVENT Event;
2450
2451 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
2452
2453 /* Caused by an injected interrupt. */
2454 pVCpu->hwaccm.s.Event.fPending = false;
2455
2456 switch (Event.n.u3Type)
2457 {
2458 case SVM_EVENT_EXTERNAL_IRQ:
2459 case SVM_EVENT_NMI:
2460 Log(("SVM_EXIT_TASK_SWITCH: reassert trap %d\n", Event.n.u8Vector));
2461 Assert(!Event.n.u1ErrorCodeValid);
2462 rc = TRPMAssertTrap(pVCpu, Event.n.u8Vector, TRPM_HARDWARE_INT);
2463 AssertRC(rc);
2464 break;
2465
2466 default:
2467 /* Exceptions and software interrupts can just be restarted. */
2468 break;
2469 }
2470 }
2471 rc = VERR_EM_INTERPRETER;
2472 break;
2473
2474 case SVM_EXIT_MONITOR:
2475 case SVM_EXIT_PAUSE:
2476 case SVM_EXIT_MWAIT_ARMED:
2477 rc = VERR_EM_INTERPRETER;
2478 break;
2479
2480 case SVM_EXIT_SHUTDOWN:
2481 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2482 break;
2483
2484 case SVM_EXIT_IDTR_READ:
2485 case SVM_EXIT_GDTR_READ:
2486 case SVM_EXIT_LDTR_READ:
2487 case SVM_EXIT_TR_READ:
2488 case SVM_EXIT_IDTR_WRITE:
2489 case SVM_EXIT_GDTR_WRITE:
2490 case SVM_EXIT_LDTR_WRITE:
2491 case SVM_EXIT_TR_WRITE:
2492 case SVM_EXIT_CR0_SEL_WRITE:
2493 default:
2494 /* Unexpected exit codes. */
2495 rc = VERR_EM_INTERNAL_ERROR;
2496 AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
2497 break;
2498 }
2499
2500end:
2501
2502 /* Signal changes for the recompiler. */
2503 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
2504
2505 /* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
2506 if (exitCode == SVM_EXIT_INTR)
2507 {
2508 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
2509 /* On the next entry we'll only sync the host context. */
2510 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
2511 }
2512 else
2513 {
2514 /* On the next entry we'll sync everything. */
2515 /** @todo we can do better than this */
2516 /* Not in the VINF_PGM_CHANGE_MODE though! */
2517 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2518 }
2519
2520 /* translate into a less severe return code */
2521 if (rc == VERR_EM_INTERPRETER)
2522 rc = VINF_EM_RAW_EMULATE_INSTR;
2523
2524 /* Just set the correct state here instead of trying to catch every goto above. */
2525 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
2526
2527#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2528 /* Restore interrupts if we exitted after disabling them. */
2529 if (uOldEFlags != ~(RTCCUINTREG)0)
2530 ASMSetFlags(uOldEFlags);
2531#endif
2532
2533 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2534 return rc;
2535}
2536
2537/**
2538 * Emulate simple mov tpr instruction
2539 *
2540 * @returns VBox status code.
2541 * @param pVM The VM to operate on.
2542 * @param pVCpu The VM CPU to operate on.
2543 * @param pCtx CPU context
2544 */
2545static int svmR0EmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2546{
2547 int rc;
2548
2549 LogFlow(("Emulated VMMCall TPR access replacement at %RGv\n", pCtx->rip));
2550
2551 while (true)
2552 {
2553 bool fPending;
2554 uint8_t u8Tpr;
2555
2556 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2557 if (!pPatch)
2558 break;
2559
2560 switch(pPatch->enmType)
2561 {
2562 case HWACCMTPRINSTR_READ:
2563 /* TPR caching in CR8 */
2564 rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending);
2565 AssertRC(rc);
2566
2567 rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
2568 AssertRC(rc);
2569
2570 LogFlow(("Emulated read successfully\n"));
2571 pCtx->rip += pPatch->cbOp;
2572 break;
2573
2574 case HWACCMTPRINSTR_WRITE_REG:
2575 case HWACCMTPRINSTR_WRITE_IMM:
2576 /* Fetch the new TPR value */
2577 if (pPatch->enmType == HWACCMTPRINSTR_WRITE_REG)
2578 {
2579 uint32_t val;
2580
2581 rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &val);
2582 AssertRC(rc);
2583 u8Tpr = val;
2584 }
2585 else
2586 u8Tpr = (uint8_t)pPatch->uSrcOperand;
2587
2588 rc = PDMApicSetTPR(pVCpu, u8Tpr);
2589 AssertRC(rc);
2590 LogFlow(("Emulated write successfully\n"));
2591 pCtx->rip += pPatch->cbOp;
2592 break;
2593 default:
2594 AssertMsgFailedReturn(("Unexpected type %d\n", pPatch->enmType), VERR_INTERNAL_ERROR);
2595 }
2596 }
2597 return VINF_SUCCESS;
2598}
2599
2600
2601/**
2602 * Enters the AMD-V session
2603 *
2604 * @returns VBox status code.
2605 * @param pVM The VM to operate on.
2606 * @param pVCpu The VM CPU to operate on.
2607 * @param pCpu CPU info struct
2608 */
2609VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
2610{
2611 Assert(pVM->hwaccm.s.svm.fSupported);
2612
2613 LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVCpu->hwaccm.s.idLastCpu, pVCpu->hwaccm.s.uCurrentASID));
2614 pVCpu->hwaccm.s.fResumeVM = false;
2615
2616 /* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
2617 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_LDTR;
2618
2619 return VINF_SUCCESS;
2620}
2621
2622
2623/**
2624 * Leaves the AMD-V session
2625 *
2626 * @returns VBox status code.
2627 * @param pVM The VM to operate on.
2628 * @param pVCpu The VM CPU to operate on.
2629 * @param pCtx CPU context
2630 */
2631VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2632{
2633 SVM_VMCB *pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
2634
2635 Assert(pVM->hwaccm.s.svm.fSupported);
2636
2637#ifdef DEBUG
2638 if (CPUMIsHyperDebugStateActive(pVCpu))
2639 {
2640 CPUMR0LoadHostDebugState(pVM, pVCpu);
2641 }
2642 else
2643#endif
2644 /* Save the guest debug state if necessary. */
2645 if (CPUMIsGuestDebugStateActive(pVCpu))
2646 {
2647 CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, false /* skip DR6 */);
2648
2649 /* Intercept all DRx reads and writes again. Changed later on. */
2650 pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
2651 pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
2652
2653 /* Resync the debug registers the next time. */
2654 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2655 }
2656 else
2657 Assert(pVMCB->ctrl.u16InterceptRdDRx == 0xFFFF && pVMCB->ctrl.u16InterceptWrDRx == 0xFFFF);
2658
2659 return VINF_SUCCESS;
2660}
2661
2662
2663static int svmR0InterpretInvlPg(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2664{
2665 OP_PARAMVAL param1;
2666 RTGCPTR addr;
2667
2668 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2669 if(RT_FAILURE(rc))
2670 return VERR_EM_INTERPRETER;
2671
2672 switch(param1.type)
2673 {
2674 case PARMTYPE_IMMEDIATE:
2675 case PARMTYPE_ADDRESS:
2676 if(!(param1.flags & (PARAM_VAL32|PARAM_VAL64)))
2677 return VERR_EM_INTERPRETER;
2678 addr = param1.val.val64;
2679 break;
2680
2681 default:
2682 return VERR_EM_INTERPRETER;
2683 }
2684
2685 /** @todo is addr always a flat linear address or ds based
2686 * (in absence of segment override prefixes)????
2687 */
2688 rc = PGMInvalidatePage(pVCpu, addr);
2689 if (RT_SUCCESS(rc))
2690 return VINF_SUCCESS;
2691
2692 AssertRC(rc);
2693 return rc;
2694}
2695
2696/**
2697 * Interprets INVLPG
2698 *
2699 * @returns VBox status code.
2700 * @retval VINF_* Scheduling instructions.
2701 * @retval VERR_EM_INTERPRETER Something we can't cope with.
2702 * @retval VERR_* Fatal errors.
2703 *
2704 * @param pVM The VM handle.
2705 * @param pRegFrame The register frame.
2706 * @param ASID Tagged TLB id for the guest
2707 *
2708 * Updates the EIP if an instruction was executed successfully.
2709 */
2710static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2711{
2712 /*
2713 * Only allow 32 & 64 bits code.
2714 */
2715 DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
2716 if (enmMode != CPUMODE_16BIT)
2717 {
2718 RTGCPTR pbCode;
2719 int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
2720 if (RT_SUCCESS(rc))
2721 {
2722 uint32_t cbOp;
2723 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2724
2725 pDis->mode = enmMode;
2726 rc = EMInterpretDisasOneEx(pVM, pVCpu, pbCode, pRegFrame, pDis, &cbOp);
2727 Assert(RT_FAILURE(rc) || pDis->pCurInstr->opcode == OP_INVLPG);
2728 if (RT_SUCCESS(rc) && pDis->pCurInstr->opcode == OP_INVLPG)
2729 {
2730 Assert(cbOp == pDis->opsize);
2731 rc = svmR0InterpretInvlPg(pVCpu, pDis, pRegFrame, uASID);
2732 if (RT_SUCCESS(rc))
2733 pRegFrame->rip += cbOp; /* Move on to the next instruction. */
2734
2735 return rc;
2736 }
2737 }
2738 }
2739 return VERR_EM_INTERPRETER;
2740}
2741
2742
2743/**
2744 * Invalidates a guest page
2745 *
2746 * @returns VBox status code.
2747 * @param pVM The VM to operate on.
2748 * @param pVCpu The VM CPU to operate on.
2749 * @param GCVirt Page to invalidate
2750 */
2751VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
2752{
2753 bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB | VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH);
2754
2755 /* Skip it if a TLB flush is already pending. */
2756 if (!fFlushPending)
2757 {
2758 SVM_VMCB *pVMCB;
2759
2760 Log2(("SVMR0InvalidatePage %RGv\n", GCVirt));
2761 AssertReturn(pVM, VERR_INVALID_PARAMETER);
2762 Assert(pVM->hwaccm.s.svm.fSupported);
2763
2764 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
2765 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2766
2767#if HC_ARCH_BITS == 32
2768 /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invlpga takes only 32 bits addresses. */
2769 if (CPUMIsGuestInLongMode(pVCpu))
2770 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2771 else
2772#endif
2773 SVMR0InvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2774 }
2775 return VINF_SUCCESS;
2776}
2777
2778
2779#if 0 /* obsolete, but left here for clarification. */
2780/**
2781 * Invalidates a guest page by physical address
2782 *
2783 * @returns VBox status code.
2784 * @param pVM The VM to operate on.
2785 * @param pVCpu The VM CPU to operate on.
2786 * @param GCPhys Page to invalidate
2787 */
2788VMMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
2789{
2790 Assert(pVM->hwaccm.s.fNestedPaging);
2791 /* invlpga only invalidates TLB entries for guest virtual addresses; we have no choice but to force a TLB flush here. */
2792 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2793 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBInvlpga);
2794 return VINF_SUCCESS;
2795}
2796#endif
2797
2798#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2799/**
2800 * Prepares for and executes VMRUN (64 bits guests from a 32 bits hosts).
2801 *
2802 * @returns VBox status code.
2803 * @param pVMCBHostPhys Physical address of host VMCB.
2804 * @param pVMCBPhys Physical address of the VMCB.
2805 * @param pCtx Guest context.
2806 * @param pVM The VM to operate on.
2807 * @param pVCpu The VMCPU to operate on.
2808 */
2809DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
2810{
2811 uint32_t aParam[4];
2812
2813 aParam[0] = (uint32_t)(pVMCBHostPhys); /* Param 1: pVMCBHostPhys - Lo. */
2814 aParam[1] = (uint32_t)(pVMCBHostPhys >> 32); /* Param 1: pVMCBHostPhys - Hi. */
2815 aParam[2] = (uint32_t)(pVMCBPhys); /* Param 2: pVMCBPhys - Lo. */
2816 aParam[3] = (uint32_t)(pVMCBPhys >> 32); /* Param 2: pVMCBPhys - Hi. */
2817
2818 return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSVMGCVMRun64, 4, &aParam[0]);
2819}
2820
2821/**
2822 * Executes the specified handler in 64 mode
2823 *
2824 * @returns VBox status code.
2825 * @param pVM The VM to operate on.
2826 * @param pVCpu The VMCPU to operate on.
2827 * @param pCtx Guest context
2828 * @param pfnHandler RC handler
2829 * @param cbParam Number of parameters
2830 * @param paParam Array of 32 bits parameters
2831 */
2832VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
2833{
2834 int rc;
2835 RTHCUINTREG uOldEFlags;
2836
2837 /* @todo This code is not guest SMP safe (hyper stack and switchers) */
2838 AssertReturn(pVM->cCpus == 1, VERR_TOO_MANY_CPUS);
2839 Assert(pfnHandler);
2840
2841 /* Disable interrupts. */
2842 uOldEFlags = ASMIntDisableFlags();
2843
2844 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVM));
2845 CPUMSetHyperEIP(pVCpu, pfnHandler);
2846 for (int i=(int)cbParam-1;i>=0;i--)
2847 CPUMPushHyper(pVCpu, paParam[i]);
2848
2849 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2850 /* Call switcher. */
2851 rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM);
2852 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2853
2854 ASMSetFlags(uOldEFlags);
2855 return rc;
2856}
2857
2858#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette